Method for correcting double patterning imaging of line and space pattern and photolithography method

Abstract

The disclosure provides a correction method for double patterning imaging of a line grid pattern and a photolithography method, the correction method comprising: S1, splitting a target line grid pattern into a first mask pattern for one-time photolithography and a second mask pattern for two-time photolithography; S2, respectively performing optimization to obtain first mask data and second mask data; S3, respectively calculating first light field intensity distribution and second light field intensity distribution, and adjusting the second light field intensity distribution; S4, superimposing the light field intensity distributions to obtain an actual photoresist imaging superposition pattern; S5, calculating edge distance errors of the actual photoresist imaging superposition pattern and the target line grid pattern; S6, judging whether the edge distance errors are less than a preset threshold value or whether a current cumulative iteration number is greater than a preset iteration number value; if not, adjusting the second light field intensity distribution and repeating S4-S6 until the conditions are met; if yes, the current light field intensity distribution is an optimized light field parameter, and the correction process is completed.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and specifically to a method, system, electronic device, computer-readable storage medium, program product, and surface plasmon super-resolution lithography method for correcting dual pattern imaging of wire grid patterns. Background Technology

[0002] In modern integrated circuit manufacturing, photolithography is a crucial step, so improvements in photolithography technology are of great significance to the development of integrated circuits. Before conducting photolithography, the pattern of the integrated circuit needs to be designed as a pattern on a mask and transferred to the mask using specific equipment. Then, photolithography is used to transfer the pattern from the mask to the chip. Due to the diffraction limit, projection lithography technology needs to reduce the wavelength to improve resolution; however, as the wavelength decreases, the technical complexity increases. Super-resolution lithography using surface plasmoic polaritons (SPP) utilizes nanoscale metal imaging film structures such as superlenses to enhance evanescent waves carrying high-frequency spatial information of the object through coupling effects. By leveraging negative refraction imaging effects, the mask pattern can be transferred to the photoresist space, thus enabling super-resolution imaging lithography to overcome the resolution limitations faced by traditional projection lithography technology.

[0003] Wire grid patterns are a crucial element in integrated circuit chip layouts. They are line patterns formed by transistor gates, where the spacing between lines is typically an integer multiple of the minimum period, the critical dimension (CD) of the lines is generally equal, but the line lengths may vary. When using super-resolution lithography to lithographically pattern wire grids, the polarization selectivity of SPP waves (which can only be excited by TM polarization fields) can lead to blurring at the edges, especially at corners and cuts, where distortion may occur. In severe cases, adhesion may even occur, resulting in defects in the lithographic final product and reducing chip yield.

[0004] Therefore, there is an urgent need in the field for a method to perform lithography on line grid patterns under super-resolution lithography to overcome the above problems, thereby improving the fidelity of the lithography results of line grid patterns under super-resolution lithography. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the aforementioned issues, this disclosure provides a method, system, electronic device, computer-readable storage medium, program product, and surface plasmon super-resolution lithography method for correcting dual-pattern imaging of wire grid patterns, thereby solving technical problems such as the generation of dead pixels and reduced chip yield caused by traditional methods.

[0007] (II) Technical Solution

[0008] The first aspect of this disclosure provides a method for correcting dual-pattern imaging of a wire grating pattern, comprising: S1, splitting the target wire grating pattern into a first mask pattern for a first photolithography step and a second mask pattern for a second photolithography step; wherein the ideal photoresist imaging superimposed pattern of the first mask pattern and the second mask pattern is the same as the target wire grating pattern; S2, optimizing the first mask pattern and the second mask pattern respectively to obtain first mask data and second mask data; S3, calculating the first light field intensity distribution and the second light field intensity distribution in the photoresist based on the first mask data and the second mask data respectively, and according to... The first light field intensity distribution is adjusted to the second light field intensity distribution; S4, the first light field intensity distribution and the adjusted second light field intensity distribution are superimposed, and the actual photoresist imaging superimposed pattern is calculated; S5, the edge distance error between the actual photoresist imaging superimposed pattern and the target line grid pattern is calculated; S6, it is determined whether the edge distance error is less than a preset threshold or whether the current cumulative iteration number is greater than a preset iteration number; if not, the second light field intensity distribution is adjusted and S4 to S6 are repeated until the condition for stopping iteration is met; if yes, the current light field intensity distribution is the optimized light field parameter, and the correction process is completed.

[0009] According to an embodiment of this disclosure, in S1, the first mask pattern is a dense line pattern, the period of the first mask pattern is the same as the period of the target line grid pattern, and the feature size of the first mask pattern is the difference between the period and the feature size of the target line grid pattern; in S1, the second mask pattern is a cropped pattern that can be obtained by cropping the imaging result of the first mask pattern from the first photolithography through secondary photolithography.

[0010] According to an embodiment of this disclosure, S2 includes: optimizing the first mask pattern using a genetic algorithm so that the line widths in the photoresist imaging pattern of the first mask pattern are close to the initial line widths in the first mask pattern, thereby obtaining first mask data; and optimizing the second mask pattern using an optical proximity correction algorithm so that the photoresist imaging pattern of the second mask pattern is close to the second mask pattern, thereby obtaining second mask data.

[0011] According to embodiments of this disclosure, the genetic algorithm is represented as follows:

[0012] W o =F(W r )

[0013] Among them, W o W represents the line widths in the photoresist imaging pattern of the first mask pattern. r represents the line widths in the first mask pattern, and F represents the lithography model;

[0014] The evaluation function in the genetic algorithm is:

[0015]

[0016] Among them, W m Let n be the line width of the first mask pattern, and n be the number of lines in the first mask pattern.

[0017] According to embodiments of this disclosure, the optical proximity effect correction algorithm includes any one of rule-based optical proximity effect correction algorithm, model-based optical proximity effect correction algorithm, and reverse lithography.

[0018] According to an embodiment of this disclosure, S3 includes: performing a first photolithography simulation calculation based on the photoresist model and the first mask data to obtain a first light field intensity distribution; performing a second photolithography simulation calculation based on the photoresist model and the second mask data to obtain a second light field intensity distribution; wherein the simulation calculation method includes any one of the following: finite-difference time-domain method, rigorous coupled-wave analysis, and finite element method; the photoresist model includes a structure of a mask, an air spacer layer, a metal transmission layer, photoresist, a metal reflection layer, and a substrate; or includes a structure of a mask, an air spacer layer, a metal transmission layer, photoresist, and a substrate; or includes a structure of a mask, an air spacer layer, photoresist, a metal reflection layer, and a substrate.

[0019] According to an embodiment of this disclosure, S3 includes: adjusting the intensity distribution of the second light field using the following formula:

[0020]

[0021] Wherein, R1 is the peak intensity of the imaging light field of the first mask pattern; R2 is the peak intensity of the imaging light field of the second mask pattern; and R2′ is the adjusted peak intensity of the imaging light field of the second mask pattern.

[0022] According to an embodiment of this disclosure, S5 includes: calculating the edge distance error EDE using the following formula:

[0023]

[0024] Among them, I out This represents the result of taking the spatial light field intensity distribution of the current actual photoresist imaging overlay pattern in binary form. I0 represents the target line grid pattern in binary form, ||·||2 represents the L-2 norm, and L represents the perimeter of the target line grid pattern.

[0025] The second aspect of this disclosure provides a surface plasmon super-resolution lithography method, comprising: obtaining optimized optical field parameters according to the above-described correction method for dual pattern imaging of a wire grating pattern; processing a first mask and a second mask according to the optimized first mask pattern and second mask pattern respectively; performing a first lithography and a second lithography sequentially using the first mask and the second mask according to the optimized optical field parameters; wherein the first lithography and the second lithography are surface plasmon super-resolution lithography.

[0026] A third aspect of this disclosure provides a correction system for dual-pattern imaging of a wire grating pattern, comprising: a splitting module for splitting a target wire grating pattern into a first mask pattern for a first photolithography step and a second mask pattern for a second photolithography step; wherein the ideal photoresist imaging superimposed pattern of the first mask pattern and the second mask pattern is identical to the target wire grating pattern; an optimization module for optimizing the first mask pattern and the second mask pattern respectively to obtain first mask data and second mask data; and a first calculation module for calculating a first light field intensity distribution and a second light field intensity distribution in the photoresist based on the first mask data and the second mask data, and calculating the first light field intensity distribution and the second light field intensity distribution in the photoresist based on the first mask data and the second mask data, respectively. The first light field intensity distribution is used to adjust the second light field intensity distribution; the superposition module is used to superimpose the first light field intensity distribution and the adjusted second light field intensity distribution, and calculate the actual photoresist imaging superimposed pattern; the second calculation module is used to calculate the edge distance error between the actual photoresist imaging superimposed pattern and the target line grid pattern; the judgment module is used to determine whether the condition for stopping iteration is met based on the edge distance error and the current cumulative iteration number; if not, the second light field intensity distribution is adjusted and the superposition and subsequent steps are repeated until the condition for stopping iteration is met; if yes, the current light field intensity distribution is the optimized light field parameter, and the correction process is completed.

[0027] A fourth aspect of this disclosure provides an electronic device, including: a processor; and a memory storing a computer-executable program that, when executed by the processor, causes the processor to perform the correction method for dual-pattern imaging of a line grid pattern as described above.

[0028] The fifth aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the correction method for dual-pattern imaging of a line grid pattern as described above.

[0029] The sixth aspect of this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the correction method for dual-pattern imaging of a wire grating pattern as described above.

[0030] (III) Beneficial Effects

[0031] This disclosure provides a method, system, electronic device, computer-readable storage medium, program product, and surface plasmon super-resolution lithography method for correcting dual-pattern imaging of wire grating patterns. The method employs dual-patterning technology to split a complex target pattern on a mask, optimizes each split mask pattern, adjusts the optical field parameters corresponding to the second mask pattern, and then superimposes them to obtain the target pattern. This method can reduce problems such as blurring, distortion, and dead pixels in lithography results caused by polarization selectivity when lithographically imaging wire grating patterns under super-resolution lithography, providing a better mask pattern and lithography scheme, and achieving better lithography result fidelity and product yield. Attached Figure Description

[0032] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 A flowchart illustrating a method for correcting dual-pattern imaging of a wire grid pattern according to an embodiment of the present disclosure is shown schematically.

[0034] Figure 2 The illustration shows a schematic diagram of an application scenario of a method for correcting dual-pattern imaging of a wire grid pattern according to an embodiment of the present disclosure;

[0035] Figure 3 A target wire grid pattern is schematically shown according to an embodiment of the present disclosure;

[0036] Figure 4 A schematic diagram illustrating the splitting rules of a second mask pattern according to an embodiment of the present disclosure is shown.

[0037] Figure 5 The illustration schematically shows a target wire grid pattern being split into a first mask pattern and a second mask pattern according to an embodiment of the present disclosure;

[0038] Figure 6 This schematic diagram illustrates the optimization results on photoresist after imaging a first mask pattern using a genetic algorithm according to an embodiment of the present disclosure.

[0039] Figure 7 This schematic diagram illustrates the result of optimizing the second mask pattern using an optical proximity correction algorithm according to an embodiment of the present disclosure.

[0040] Figure 8 This schematic diagram illustrates the result of superimposing the first light field intensity distribution and the adjusted second light field intensity distribution according to an embodiment of the present disclosure.

[0041] Figure 9 A block diagram schematically illustrates a correction system for dual pattern imaging of a wire grid pattern according to an embodiment of the present disclosure;

[0042] Figure 10 A block diagram schematically illustrates an electronic device suitable for implementing the methods described above, according to embodiments of the present disclosure. Detailed Implementation

[0043] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0045] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0046] The accompanying drawings illustrate several block diagrams and / or flowcharts. It should be understood that some blocks, or combinations thereof, in the block diagrams and / or flowcharts can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that, when executed by the processor, these instructions can create means for implementing the functions / operations described in these block diagrams and / or flowcharts. The technology of this disclosure can be implemented in hardware and / or software (including firmware, microcode, etc.). Alternatively, the technology of this disclosure can take the form of a computer program product stored on a computer-readable storage medium, which is available for use by or in conjunction with an instruction execution system.

[0047] In this disclosure, for ease of explanation, only the target grid pattern, the first mask pattern, the second mask pattern, the photoresist imaging pattern, and the photoresist imaging superimposed pattern are referred to as patterns, while the calculation process and the results obtained in the imaging process are referred to as data. It is understood that the data in the process can all be output as corresponding patterns.

[0048] Figure 1A flowchart illustrating a method for correcting dual-pattern imaging of a wire grid pattern according to an embodiment of the present disclosure is shown schematically.

[0049] like Figure 1 As shown, the correction method for dual-pattern imaging of wire grating patterns includes:

[0050] S1, the target line grid pattern is split into a first mask pattern for a first photolithography and a second mask pattern for a second photolithography; wherein, the ideal photoresist imaging superimposed pattern of the first mask pattern and the second mask pattern is the same as the target line grid pattern;

[0051] S2, optimize the first mask pattern and the second mask pattern respectively to obtain the first mask data and the second mask data;

[0052] S3, calculate the first light field intensity distribution and the second light field intensity distribution in the photoresist based on the first mask data and the second mask data respectively, and adjust the second light field intensity distribution based on the first light field intensity distribution;

[0053] S4, superimpose the first light field intensity distribution and the adjusted second light field intensity distribution, and calculate the actual photoresist imaging superimposed pattern;

[0054] S5, calculate the edge distance error between the actual photoresist imaging overlay pattern and the target wire grid pattern;

[0055] S6, determine whether the edge distance error is less than the preset threshold or whether the current cumulative iteration count is greater than the preset iteration count; if not, adjust the second light field intensity distribution and repeat S4 to S6 until the condition for stopping iteration is met; if yes, the current light field intensity distribution is the optimized light field parameter, and the correction process is completed.

[0056] This disclosure first decomposes the target grating pattern to obtain a first mask pattern for primary lithography and a second mask pattern for secondary lithography. Then, the first and second mask patterns are optimized respectively. Finally, the corresponding light fields are calculated for the two optimized mask patterns. The intensity distribution of the second light field is adjusted and superimposed with the intensity distribution of the first light field to obtain the actual photoresist imaging overlay pattern. The edge distance error between the actual photoresist imaging overlay pattern and the target grating pattern is used as a criterion. When the iteration stops, the optimized light field parameters are obtained, completing the correction process. This method can reduce problems such as blurring, distortion, and dead pixels in lithography results caused by polarization selectivity when lithographically processing grating patterns under super-resolution lithography, providing better mask patterns and lithography schemes, and achieving better lithography result fidelity and product yield.

[0057] Based on the above embodiments, in S1, the first mask pattern is a dense line pattern, the period of the first mask pattern is the same as the period of the target line grid pattern, and the feature size of the first mask pattern is the difference between the period and the feature size of the target line grid pattern; in S1, the second mask pattern is a cropped pattern that can be obtained by cropping the imaging result of the first mask pattern in one photolithography step by two photolithography steps to obtain the target line grid pattern.

[0058] The target line grid pattern is split into a first mask pattern and a second mask pattern. Dual patterning is a technique that splits a single mask pattern into two different mask patterns for photolithography. Because dual patterning involves two different mask patterns being lithographically processed within the same photolithographic structure, and the results of the two lithography processes are superimposed to produce the desired target pattern, it is necessary to split the mask into a first mask pattern and a second mask pattern based on the target pattern; that is, a dense line mask pattern and a clipped pattern. The purpose of the clipped pattern is to crop the imaging result of the first mask pattern to obtain the target line grid pattern.

[0059] Based on the above embodiments, S2 includes: optimizing the first mask pattern using a genetic algorithm so that the width of each line in the photoresist imaging pattern of the first mask pattern is close to the initial width of each line in the first mask pattern, thereby obtaining first mask data; and optimizing the second mask pattern using an optical proximity correction (OPC) algorithm so that the photoresist imaging pattern of the second mask pattern is close to the second mask pattern, thereby obtaining second mask data.

[0060] The first and second mask patterns, after being split in step S1, are optimized respectively. Due to the optical proximity effect, the photoresist contour corresponding to the mask pattern may be distorted. The purpose of optimization is to make the photoresist contour of the mask pattern closer to the mask pattern.

[0061] In this step, a genetic algorithm is used to optimize the first mask pattern. By optimizing the width of each line in the dense line pattern, the width of each line in its photoresist outline is made closer to the initial line width of the first mask pattern obtained by splitting.

[0062] In this step, the second mask pattern is optimized using an optical proximity correction algorithm. By correcting the cropped pattern, its photoresist outline is made closer to the split second mask pattern.

[0063] Based on the above embodiments, the genetic algorithm is expressed as follows:

[0064] W o =F(W r )

[0065] Among them, Wo W represents the line widths in the photoresist imaging pattern of the first mask pattern. r represents the line widths in the first mask pattern, and F represents the lithography model;

[0066] The evaluation function in the genetic algorithm is:

[0067]

[0068] Among them, W m Let n be the line width of the first mask pattern, and n be the number of lines in the first mask pattern.

[0069] Based on the above embodiments, the optical proximity effect correction algorithm includes any one of the following: rule-based optical proximity effect correction algorithm, model-based optical proximity effect correction algorithm, and reverse lithography technology.

[0070] The corresponding second mask data is obtained by using the optical proximity effect correction method described above, so that the corresponding photoresist contour is closer to the second mask pattern.

[0071] Based on the above embodiments, S3 includes: performing a first lithography simulation calculation based on the photoresist model and the first mask data to obtain a first light field intensity distribution; performing a second lithography simulation calculation based on the photoresist model and the second mask data to obtain a second light field intensity distribution; wherein, the simulation calculation method includes any one of the following: Finite-Difference Time Domain (FDTD), Rigorous Coupled-Wave Analysis (RCWA), and Finite Element Method (FEM); the photoresist model includes a structure of a mask, an air spacer layer, a metal transmission layer, photoresist, a metal reflection layer, and a substrate; or includes a structure of a mask, an air spacer layer, a metal transmission layer, photoresist, and a substrate; or includes a structure of a mask, an air spacer layer, photoresist, a metal reflection layer, and a substrate.

[0072] The first and second mask data are substituted into the photoresist model for simulation calculation to obtain the light field intensity distribution within the photoresist. The light field intensity distribution is then converted into a binary image using the photoresist model. The photoresist model can be a constant threshold model or other models, where the photoresist threshold is determined by fitting experimental results. Various numerical calculation methods, such as FDTD, FEM, or RCWA, can be used to simulate the light field intensity distribution within the photoresist in this step. The photoresist thresholds used for the simulation calculation of the first and second mask data in this step can be different.

[0073] Based on the above embodiments, S3 includes: adjusting the intensity distribution of the second light field using the following formula:

[0074]

[0075] Wherein, R1 is the peak intensity of the imaging light field of the first mask pattern; R2 is the peak intensity of the imaging light field of the second mask pattern; R2′ is the adjusted peak intensity of the imaging light field of the second mask pattern; that is, the light field parameter of the second mask pattern is R1 / R2, and the light field parameter of the first mask pattern is 1.0.

[0076] Based on the optimization results obtained in step S2, the light field intensity distribution within the photoresist of the optimized second mask pattern (the second light field intensity distribution) is adjusted. Since the first and second light field intensity distributions may differ significantly, resulting in a large difference in photoresist thresholds, and the photoresist parameters used in actual photolithography are the same, the second light field intensity distribution needs to be adjusted to produce a photoresist profile closer to the optimized profile in step S2 during actual photolithography. A common adjustment method is to multiply it by the light field parameters. This step corresponds to adjusting the exposure dose of the second mask pattern in actual photolithography.

[0077] Further, S4 includes: superimposing the adjusted imaging light field (adjusted second light field intensity distribution) corresponding to the optimized second mask pattern in S3 with the imaging light field (first light field intensity distribution) of the optimized first mask pattern and calculating the actual photoresist superimposed imaging pattern.

[0078] Based on the above embodiments, S5 includes: calculating the edge distance error EDE using the following formula:

[0079]

[0080] Among them, I out This represents the result of taking the spatial light field intensity distribution of the current actual photoresist imaging overlay pattern in binary form. I0 represents the target line grid pattern in binary form, ||·||2 represents the L-2 norm, and L represents the perimeter of the target line grid pattern.

[0081] The calculated actual photoresist imaging overlay pattern is compared with the target grating pattern, and it is determined whether the EDE is less than the set threshold. If the EDE value is less than the preset threshold or the current cumulative iteration number is greater than the preset iteration number, then the requirements are met; otherwise, the second light field intensity distribution is adjusted and steps S4 to S6 are repeated until the requirements are met.

[0082] This disclosure applies dual-patterning technology to the photolithography of wire grating patterns. The wire grating pattern, originally on one mask, is split onto two masks, imaged separately, and then superimposed to obtain the target wire grating pattern. This method can significantly reduce distortion and dead pixels in the wire grating pattern photolithography results, thereby improving the photolithography quality of the system.

[0083] This disclosure also provides a surface plasmon super-resolution lithography method, comprising: obtaining optimized optical field parameters according to the above-described correction method for dual pattern imaging of wire grating patterns; processing a first mask and a second mask according to the optimized first mask pattern and second mask pattern respectively; performing a first lithography and a second lithography sequentially using the first mask and the second mask according to the optimized optical field parameters; wherein the first lithography and the second lithography are surface plasmon super-resolution lithography.

[0084] Photolithography is performed based on the first and second mask patterns and their corresponding optical field parameters. After determining compliance in step S6, the optimized first and second mask patterns are processed to obtain the first and second masks. Photolithography is then performed on the first and second masks respectively based on the optimized optical field parameters obtained in step S6. During the photolithography process, the exposure dose of the second mask needs to be adjusted according to the optical field parameters of the second mask pattern. When the exposure dose of the first mask is the reference exposure dose, the ratio of the exposure dose of the second mask to the reference exposure dose is the optical field parameter of the second mask pattern.

[0085] This method employs a dual-patterning technique for super-resolution lithography of wire grating patterns. First, the target wire grating pattern is decomposed into a first mask pattern and a second mask pattern. The first mask pattern is then optimized to make the line widths in its photoresist contour approximate the initial line widths of the first mask pattern. Optical proximity correction is applied to the second mask pattern to make its photoresist contour approximate the second mask pattern. Finally, the corresponding light fields are calculated for each of the two optimized mask patterns, adjusted, and superimposed. The desired target wire grating pattern is then obtained through lithography based on the optimized mask pattern and the adjusted light field parameters. In other words, optimized light field parameters are obtained based on the aforementioned dual-patterning imaging correction method for wire grating patterns, and lithography is performed using these optimized light field parameters. The specific processes of operations S1 to S6 are not detailed here.

[0086] The present disclosure will be further described below through specific embodiments. The following embodiments specifically illustrate the above-described method for correcting dual-pattern imaging of wire grating patterns and the photolithography method. However, the following embodiments are merely illustrative of the present disclosure, and the scope of the present disclosure is not limited thereto.

[0087] Specifically, such as Figure 1 As shown, the method in this embodiment includes the following steps:

[0088] Step S01: Design a splitting scheme to split the target line grid pattern into a first mask pattern for primary lithography and a second mask pattern for secondary lithography. The resulting first mask pattern is the dense line pattern; the resulting second mask pattern is the trimmed pattern, which is mainly trimmed according to the target line grid pattern to make it closer to the target line grid pattern by selecting the trimming area. Generally, the center position of each trimmed mask is set to be the same as the center position of the area to be trimmed in the first mask pattern, its length is the length of the area to be trimmed in the first mask pattern, and its width is set to w = a + CD; where a is the width of the area to be trimmed in the first mask pattern, CD is the line width of the dense line mask, and w is generally an integer multiple of the target pattern period. This is equivalent to the aforementioned operation S1.

[0089] Step S02: Optimize the first and second mask patterns obtained from the splitting in step S01. For the first mask pattern, a genetic algorithm is used to optimize the line widths of each line, making the line widths in the photoresist contour obtained after passing through the photoresist model closer to the initial line widths of the first mask pattern. For the second mask pattern, an optical proximity correction algorithm is used for optimization, correcting the cropped pattern to make its photoresist contour closer to the second mask pattern. This is equivalent to the aforementioned operation S2.

[0090] Step S03: Based on the optimization results obtained in step S02, adjust the light field intensity distribution within the photoresist of the optimized second mask pattern. A common adjustment method is to multiply by a light field parameter. This step corresponds to adjusting the exposure dose of the second mask pattern in actual photolithography. The peak intensities of the imaging light fields of the first and second mask patterns are used as references to ensure that their peak intensities are close after light field adjustment. This is equivalent to the aforementioned step S3.

[0091] Step S04: The actual photoresist imaging overlay pattern is calculated by superimposing the imaging light field of the adjusted second mask pattern and the optimized first mask pattern in S03. This is equivalent to the aforementioned operation S4.

[0092] Step S05: Compare the calculated actual photoresist imaging overlay pattern with the target line grid pattern and determine whether the EDE is less than a preset threshold or whether the current cumulative iteration count is greater than a preset iteration count. If yes, the requirements are met; if not, adjust the light field parameters of the second mask pattern to 0.9 times the previous light field parameters, and repeat steps S04 and S05 until the requirements are met. This is equivalent to the aforementioned operations S5 to S6.

[0093] Step S06: Perform photolithography based on the first mask pattern, the second mask pattern, and the corresponding optical field parameters. After determining that the requirements are met in S05, process the optimized first mask pattern and the second mask pattern to obtain the first mask and the second mask. Perform photolithography on the first mask and the second mask respectively based on the optical field parameters obtained in S05.

[0094] Based on steps S01 to S06 above, a specific embodiment is provided below. The following is a description of the specific embodiment.

[0095] Example 1:

[0096] like Figure 2 As shown, the structure 201 of the super-resolution lithography imaging model in this embodiment includes a mask (SiO2+Cr), an air spacer layer (Air), an upper metal layer (Ag), a photoresist (Pr), a lower metal layer (Ag), and a substrate (SiO2). In this embodiment, the mask thickness is 40nm, the air spacer layer thickness is 40nm, the upper metal layer thickness is 12nm, the lower metal layer thickness is 40nm, and the photoresist thickness is 28nm.

[0097] Figure 3 The target wireline pattern used in this example is shown. It has a period of 105 nm, a CD of 65 nm, and a length of 1000 nm.

[0098] Figure 4 A schematic diagram of the splitting rules for the second mask pattern is shown. Here, 401 represents the region in the first mask pattern that needs to be clipped, and its center coordinates are... 402 is the corresponding clipping mask, and its center coordinates should be the same as 401. The length is the same as 401, L, and the width is w = a + CD. Where a is the width of the clipping region in 401, CD is the line width of the dense line mask, and w is generally an integer multiple of the period of the target graphic.

[0099] Figure 5 The diagram shows the target line grid pattern ( Figure 3 The diagram shows the two mask patterns obtained from the splitting process. 501 is the first mask pattern obtained from the splitting, i.e., the dense line mask pattern, with a CD of 40nm. White areas represent light-transmitting regions, and black areas represent light-blocking regions. Under positive development, the white areas are removed, and the black areas are retained to form lines. 502 is the second mask pattern, i.e., the cropped pattern, where white areas represent light-transmitting regions, and black areas represent light-blocking regions. Under positive development, the white areas are removed, and the black areas are retained. The lines remaining in the light field obtained after superimposing the images from the two masks constitute the desired target wire grating pattern.

[0100] Figure 6This diagram illustrates the optimization results of imaged first mask patterns onto photoresist using a genetic algorithm. By altering the line widths of each line in the dense line mask pattern, the line widths in the resulting photoresist contour after passing through the photoresist model are made closest to the initial line widths of the first mask pattern. In the diagram, 601 shows the light field distribution before optimization, 602 shows the center-section distribution of the light field before optimization, 603 shows the light field distribution after optimization, 604 shows the center-section distribution of the light field after optimization, and 605 shows the iterative curve of the evaluation function.

[0101] In the genetic algorithm optimization, the maximum linewidth of the image was set to 80nm, the minimum to 20nm, and the photoresist threshold to 0.7. The final value of the resulting iterative curve was 2.245. Before optimization, the contrast of the dense lines was 0.5752 and the peak variance was 0.0751. After optimization, the contrast was 0.5820 and the peak variance was 0.0411. The comparison shows that the contrast and peak variance of the dense lines in the first mask image were improved after optimization, resulting in improved imaging performance.

[0102] Figure 7 The diagram shows the result of the second mask pattern after OPC. 701, 702, and 703 are the mask pattern, light field pattern, and photoresist imaging pattern before OPC; 704, 705, and 706 are the mask pattern, light field pattern, and photoresist imaging pattern after OPC; 707 and 708 are contour comparison diagrams and EDE iteration curves. It can be seen that the EDE decreases, and the imaging effect of the cropped pattern is improved. Figure 7 The final iteration result of EDE is 8.2996nm.

[0103] Figure 8 This diagram illustrates the result of superimposing and optimizing two light fields after adjusting the light field intensity distribution within the photoresist. 801 shows the superimposed light field image before optimization, while 802 and 803 show the comparison between the optimized superimposed photoresist image and its contour. Since the peak light field intensity of the first mask image and the second mask image are 0.7 and 0.25 respectively, the light field parameter is set to 2.8. The light field obtained from the first mask image is superimposed with the light field obtained from the second mask image (2.8 times the value), and the photoresist contour is calculated and compared with the target image. In this embodiment, the EDE threshold is set to 10nm, and the EDE of the photoresist contour after light field superposition is 9.64nm, which is less than the preset threshold and meets the requirements. Subsequently, the optimized first and second mask images are processed. The resulting first and second masks are then used to lithographically etch the grid pattern during the photolithography process at the corresponding set exposure doses.

[0104] This disclosure introduces a dual-patterning technique in super-resolution lithography, which obtains the required grating pattern through two lithography processes. This method can reduce the probability of problems such as adhesion and bad spots in the lithography results of the grating pattern in super-resolution lithography, and improve the fidelity of the lithography results.

[0105] Figure 9 A block diagram schematically illustrates a correction system for dual-pattern imaging of a line grid pattern according to an embodiment of the present disclosure.

[0106] like Figure 9 As shown, the correction system 900 includes: a splitting module 910, an optimization module 920, a first calculation module 930, an overlay module 940, a second calculation module 950, and a judgment module 960.

[0107] The splitting module 910 is used to split the target line grid pattern into a first mask pattern for a first photolithography step and a second mask pattern for a second photolithography step; wherein the ideal photoresist imaging superimposed pattern of the first mask pattern and the second mask pattern is the same as the target line grid pattern. According to embodiments of this disclosure, the splitting module 910 can be used, for example, to perform the above-described references. Figure 1 The S1 step described herein will not be repeated here.

[0108] The optimization module 920 is used to optimize the first mask pattern and the second mask pattern respectively to obtain first mask data and second mask data. According to embodiments of this disclosure, the optimization module 920 can, for example, be used to perform the above-mentioned... Figure 1 The S2 steps described herein will not be repeated here.

[0109] The first calculation module 930 is configured to calculate a first light field intensity distribution and a second light field intensity distribution in the photoresist based on the first mask data and the second mask data, respectively, and adjust the second light field intensity distribution based on the first light field intensity distribution. According to embodiments of this disclosure, the first calculation module 930 can, for example, be used to perform the functions described above. Figure 1 The S3 steps described herein will not be repeated here.

[0110] The overlay module 940 is used to overlay the first light field intensity distribution and the adjusted second light field intensity distribution, and calculate the actual photoresist imaging overlay pattern. According to embodiments of this disclosure, the overlay module 940 can, for example, be used to perform the functions described above. Figure 1 The S4 steps described herein will not be repeated here.

[0111] The second calculation module 950 is used to calculate the edge distance error between the actual photoresist imaging overlay pattern and the target line grid pattern. According to embodiments of this disclosure, the second calculation module 950 can, for example, be used to perform the above-mentioned... Figure 1The S5 steps described herein will not be repeated here.

[0112] The judgment module 960 is used to determine whether the condition for stopping iteration is met based on the edge distance error and the current cumulative iteration count. If not, the second light field intensity distribution is adjusted and the superposition and subsequent steps are repeated until the condition for stopping iteration is met. If yes, the current light field intensity distribution is the optimized light field parameters, and the correction process is completed. According to embodiments of this disclosure, the judgment module 960 can, for example, be used to perform the above-mentioned references. Figure 1 The S6 steps described herein will not be repeated here.

[0113] It should be noted that any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of this disclosure, or at least part of the functions of any one or more of them, can be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of this disclosure can be divided into multiple modules for implementation. Any one or more of the modules, sub-modules, units, and sub-units according to the embodiments of this disclosure can be at least partially implemented as hardware circuits, such as field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems-on-a-chip, systems-on-a-substrate, systems-on-package, application-specific integrated circuits (ASICs), or implemented in hardware or firmware by any other reasonable means of integrating or packaging circuits, or implemented in software, hardware, and firmware, or in any appropriate combination of any of these three implementation methods. Alternatively, one or more of the modules, sub-modules, units, and sub-units according to the embodiments of this disclosure can be at least partially implemented as computer program modules, which, when run, can perform corresponding functions.

[0114] For example, any multiple of the splitting module 910, optimization module 920, first calculation module 930, superposition module 940, second calculation module 950, and judgment module 960 can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules can be combined with at least part of the functionality of other modules and implemented in one module. According to embodiments of this disclosure, at least one of the splitting module 910, optimization module 920, first calculation module 930, superposition module 940, second calculation module 950, and judgment module 960 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), programmable logic array (PLA), system-on-a-chip, system-on-a-substrate, system-on-package, application-specific integrated circuit (ASIC), or implemented in hardware or firmware by any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the splitting module 910, optimization module 920, first calculation module 930, superposition module 940, second calculation module 950 and judgment module 960 can be at least partially implemented as a computer program module, which can perform corresponding functions when the computer program module is run.

[0115] Figure 10 A block diagram schematically illustrates an electronic device suitable for implementing the methods described above, according to embodiments of the present disclosure. Figure 10 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0116] like Figure 10 As shown, the electronic device 1000 described in this embodiment includes a processor 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage portion 1008 into a random access memory (RAM) 1003. The processor 1001 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1001 may also include onboard memory for caching purposes. The processor 1001 may include a single processing unit or multiple processing units for performing different actions of the method flow according to embodiments of this disclosure.

[0117] RAM 1003 stores various programs and data required for the operation of system 1000. Processor 1001, ROM 1002, and RAM 1003 are interconnected via bus 1004. Processor 1001 executes various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 1002 and / or RAM 1003. It should be noted that programs may also be stored in one or more memories other than ROM 1002 and RAM 1003. Processor 1001 may also execute various operations of the method flow according to embodiments of the present disclosure by executing programs stored in one or more memories.

[0118] According to embodiments of this disclosure, the electronic device 1000 may further include an input / output (I / O) interface 1005, which is also connected to a bus 1004. The system 1000 may also include one or more of the following components connected to the I / O interface 1005: an input section 1006 including a keyboard, mouse, etc.; an output section 1007 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN card, modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 1010 as needed so that computer programs read from it can be installed into the storage section 1008 as needed.

[0119] According to embodiments of this disclosure, the method flow according to embodiments of this disclosure can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the methods shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1009, and / or installed from removable medium 1011. When the computer program is executed by processor 1001, it performs the functions defined in the system of embodiments of this disclosure. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0120] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the correction method for dual-pattern imaging of a wireframe pattern according to embodiments of this disclosure.

[0121] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this disclosure, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 1002 and / or RAM 1003 and / or one or more memories other than ROM 1002 and RAM 1003 described above.

[0122] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code enables the computer system to implement the correction method for dual-pattern imaging of line grid patterns provided in embodiments of this disclosure.

[0123] When the computer program is executed by the processor 1001, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0124] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 1009, and / or installed from a removable medium 1011. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0125] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 1009, and / or installed from removable medium 1011. When the computer program is executed by processor 1001, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0126] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0127] It should be noted that the functional modules in the various embodiments of this disclosure can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules can be implemented in hardware or as software functional modules. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0128] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0129] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0130] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A method for correcting dual-pattern imaging of a wire grating pattern, characterized in that, include: S1, the target line grid pattern is split into a first mask pattern for a first photolithography and a second mask pattern for a second photolithography; wherein, the ideal photoresist imaging superimposed pattern of the first mask pattern and the second mask pattern is the same as the target line grid pattern. S2, optimize the first mask pattern and the second mask pattern respectively to obtain the first mask data and the second mask data; S3, calculate the first light field intensity distribution and the second light field intensity distribution in the photoresist based on the first mask data and the second mask data respectively, and adjust the second light field intensity distribution based on the first light field intensity distribution; S4, superimpose the first light field intensity distribution and the adjusted second light field intensity distribution, and calculate the actual photoresist imaging superimposed pattern; S5, calculate the edge distance error between the actual photoresist imaging overlay pattern and the target wire grid pattern; S6, determine whether the edge distance error is less than a preset threshold or whether the current cumulative iteration count is greater than a preset iteration count; if not, adjust the second light field intensity distribution and repeat S4~S6 until the condition for stopping iteration is met; if yes, the first light field intensity distribution and the adjusted second light field intensity distribution are the optimized light field parameters, and the correction process is completed. S2 includes: optimizing the first mask pattern using a genetic algorithm so that the line widths in the photoresist imaging pattern of the first mask pattern are close to the initial line widths in the first mask pattern, thereby obtaining first mask data; and optimizing the second mask pattern using an optical proximity correction algorithm so that the photoresist imaging pattern of the second mask pattern is close to the second mask pattern, thereby obtaining second mask data. S3 includes: adjusting the intensity distribution of the second light field using the following formula: in, The peak intensity of the imaging light field of the first mask pattern; The peak intensity of the imaging light field of the second mask pattern; The peak intensity of the imaging light field of the adjusted second mask pattern.

2. The method for correcting dual-pattern imaging of a wire grating pattern according to claim 1, characterized in that, In S1, the first mask pattern is a dense line pattern, the period of the first mask pattern is the same as the period of the target line grid pattern, and the feature size of the first mask pattern is the difference between the period and the feature size of the target line grid pattern. In S1, the second mask pattern is a cropped pattern that can be obtained by cropping the imaging result of the first mask pattern from the first photolithography through secondary photolithography to obtain the target wire grid pattern.

3. The method for correcting dual-pattern imaging of a line grid pattern according to claim 1, characterized in that, The genetic algorithm is expressed as follows: Among them, W o W represents the line widths in the photoresist imaging pattern of the first mask pattern. r Where is the width of each line in the first mask pattern, and F is the lithography model; The evaluation function in the genetic algorithm is: Among them, W m Let n be the line width of the first mask pattern, and n be the number of lines in the first mask pattern.

4. The method for correcting dual-pattern imaging of a wire grating pattern according to claim 1, characterized in that, The optical proximity effect correction algorithm includes any one of the following: rule-based optical proximity effect correction algorithm, model-based optical proximity effect correction algorithm, and reverse lithography technology.

5. The method for correcting dual-pattern imaging of a wire grating pattern according to claim 1, characterized in that, S3 includes: A photolithography simulation calculation is performed based on the photoresist model and the first mask data to obtain the first light field intensity distribution; Based on the photoresist model and the second mask data, a simulation calculation of secondary photolithography is performed to obtain the second light field intensity distribution; The simulation calculation method includes any one of the following: finite-difference time-domain method, rigorous coupled-wave analysis, and finite element method. The photoresist model includes a structure comprising a mask, an air gap layer, a metal transmission layer, photoresist, a metal reflection layer, and a substrate; or a structure comprising a mask, an air gap layer, a metal transmission layer, photoresist, and a substrate; or a structure comprising a mask, an air gap layer, photoresist, a metal reflection layer, and a substrate.

6. The method for correcting dual-pattern imaging of a wire grating pattern according to claim 1, characterized in that, S5 includes: The edge distance error EDE is calculated using the following formula: in, This represents the result of taking the spatial light field intensity distribution of the actual photoresist imaging overlay pattern in binary form. Represents the target line grid pattern in binary form. This represents the L-2 norm, where L represents the perimeter of the target wire mesh pattern.

7. A surface plasmon super-resolution lithography method, characterized in that, include: The method for correcting dual-pattern imaging of a wire grating pattern according to any one of claims 1 to 6 yields optimized optical field parameters; The first mask and the second mask are obtained by processing the optimized first mask pattern and the second mask pattern respectively; Based on the optimized light field parameters, photolithography is performed sequentially using the first mask and the second mask, followed by a second photolithography step. The first and second photolithography are surface plasmon super-resolution photolithography.

8. A correction system for dual-pattern imaging of line grid patterns, characterized in that, include: The splitting module is used to split the target line grid pattern into a first mask pattern for a first photolithography step and a second mask pattern for a second photolithography step; wherein the ideal photoresist imaging superimposed pattern of the first mask pattern and the second mask pattern is the same as the target line grid pattern. An optimization module is used to optimize the first mask pattern and the second mask pattern respectively to obtain first mask data and second mask data. Specifically, a genetic algorithm is used to optimize the first mask pattern so that the line widths in the photoresist imaging pattern of the first mask pattern are close to the initial line widths in the first mask pattern, thus obtaining the first mask data. An optical proximity correction algorithm is used to optimize the second mask pattern so that the photoresist imaging pattern of the second mask pattern is close to the second mask pattern, thus obtaining the second mask data. The first calculation module is used to calculate the first light field intensity distribution and the second light field intensity distribution in the photoresist based on the first mask data and the second mask data, respectively, and to adjust the second light field intensity distribution based on the first light field intensity distribution; wherein, the second light field intensity distribution is adjusted by the following formula: in, The peak intensity of the imaging light field of the first mask pattern; The peak intensity of the imaging light field of the second mask pattern; The peak intensity of the imaging light field of the adjusted second mask pattern; The overlay module is used to overlay the first light field intensity distribution and the adjusted second light field intensity distribution, and calculate the actual photoresist imaging overlay pattern. The second calculation module is used to calculate the edge distance error between the actual photoresist imaging overlay pattern and the target line grid pattern; The judgment module is used to determine whether the condition for stopping iteration is met based on the edge distance error and the current cumulative iteration count; if not, the second light field intensity distribution is adjusted and the superposition and subsequent steps are repeated until the condition for stopping iteration is met; if yes, the first light field intensity distribution and the adjusted second light field intensity distribution are the optimized light field parameters, and the correction process is completed.

9. An electronic device, comprising: processor; The memory stores a computer-executable program that, when executed by the processor, causes the processor to perform the correction method for dual-pattern imaging of a line grid pattern as described in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the correction method for dual-image imaging of line grid patterns as described in any one of claims 1 to 6.

11. A computer program product comprising a computer program that, when executed by a processor, implements the correction method for dual-pattern imaging of a line grid pattern according to any one of claims 1 to 6.

Images