Internal controller for error correction code

Abstract

This application relates to an on-die controller for error correction codes. An on-die controller can provide error correction capability for data stored in an array of memory cells located on the same die as the on-die controller. The error correction capability provided by the on-die controller does not require the transfer of error correction code (ECC) data to an external controller that can have provided the error correction capability instead of the on-die controller, which can provide more channel bandwidth for other types of non-user data to further enhance data reliability, security, integrity of a memory system.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically to devices, systems and methods associated with internal controllers for error correction codes (ECC). Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data (e.g., host data, error data, etc.) and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), and Thyristor Random Access Memory (TRAM), among others. Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during operation of a computing or other electronic system. A controller may be used to manage the transfer of data, commands, and / or instructions between the host computer and the memory device. Summary of the Invention

[0004] Embodiments of this disclosure provide an apparatus for on-die error correction code (ECC) operation, comprising: a plurality of memory cells, each of the plurality of memory cells further comprising: a corresponding array of memory cells configured to store: a corresponding portion of one or more user data blocks (UDBs); and auxiliary data corresponding to the corresponding portion of the one or more UDBs, wherein a first portion of the auxiliary data includes error correction information corresponding to the corresponding portion of the one or more UDBs; and a corresponding internal controller configured to, in response to receiving a command to access the corresponding portion of the one or more UDBs: perform an error correction operation on the corresponding portion of the one or more UDBs using the error correction information to correct one or more bit errors on the corresponding portion of the one or more UDBs; and, after performing the error correction operation, exchange the corresponding portion of the one or more UDBs and a second portion of the auxiliary data from the corresponding memory cell via one or more data pins of the corresponding memory cell.

[0005] Another embodiment of this disclosure provides a method for on-chip error correction code (ECC) operation, comprising: performing an error correction operation on the corresponding portions of one or more user data blocks (UDBs) to correct one or more bit errors on the corresponding portions of the one or more UDBs before exchanging the corresponding portions of the one or more UDBs at corresponding memory cells in a plurality of memory cells using first error correction information, wherein each of the plurality of memory cells is configured to store: the corresponding portions of the one or more UDBs; and auxiliary data including the first error correction information and error detection information to indicate one or more bit errors in the one or more UDBs; and exchanging the corresponding portions of the one or more UDBs and a portion of the auxiliary data containing the error detection information after performing the error correction operation.

[0006] Another embodiment of this disclosure provides an apparatus for on-die error correction code (ECC) operation, comprising: a plurality of memory cells configured to store error detection information corresponding to one or more user data blocks (UDBs), each of the plurality of memory cells including: a memory cell array configured to store: a corresponding portion of the one or more UDBs; and auxiliary data including corresponding first error correction information and a corresponding portion of the error detection information; an internal controller configured to generate the corresponding first error correction information based on the corresponding portion of the one or more UDBs; and a memory controller communicatively coupled to the plurality of memory cells, the memory controller being configured such that a corresponding internal controller of a plurality of corresponding internal controllers of a plurality of memory devices responds to receiving a host read command for accessing the first memory device by: performing an error correction operation on the corresponding portion of the one or more UDBs using the corresponding first error correction information; and, after the execution of the error correction operation, transmitting the corresponding portion of the one or more UDBs and the auxiliary data including the error detection information to the memory controller.

[0007] Another embodiment of this disclosure provides a method for on-chip error correction code (ECC) operation, comprising: receiving from a memory controller a read command to access user data blocks (UDBs) from a plurality of memory cells, wherein each of the plurality of memory cells is configured to store: a corresponding portion of one or more user data blocks (UDBs); and auxiliary data comprising corresponding first error correction information and corresponding error detection information corresponding to the corresponding portion of the one or more UDBs; performing an error correction operation using the first error correction information at the corresponding memory cell of the plurality of memory cells before transmitting the corresponding portion of the one or more UDBs; and transmitting the corresponding portion of the one or more UDBs and the auxiliary data comprising the corresponding error detection information to the memory controller. Attached Figure Description

[0008] Figure 1 This is a functional block diagram of a computing system including a memory controller according to several embodiments of the present disclosure.

[0009] Figure 2A This is a functional block diagram of a memory controller with a standalone redundant array of disks (RAID) encoder / decoder according to several embodiments of the present disclosure.

[0010] Figure 2B This is another functional block diagram of a memory controller with a RAID encoder / decoder according to several embodiments of the present disclosure.

[0011] Figure 3A This is a block diagram of a memory die corresponding to a data protection channel according to several embodiments of the present disclosure.

[0012] Figure 3B This is a block diagram illustrating a locking RAID process for data protection of a subset of user data blocks (UDBs) according to several embodiments of the present disclosure.

[0013] Figure 4A This is another block diagram of a memory die corresponding to a data protection channel according to several embodiments of the present disclosure.

[0014] Figure 4B This is a block diagram illustrating a locked RAID process for data protection of a subset of UDBs according to several embodiments of this disclosure.

[0015] Figure 5 This is a flowchart of a method for performing error correction code (ECC) operation at an internal controller, according to several embodiments of the present disclosure.

[0016] Figure 6 This is a flowchart of a method for performing ECC operations at an internal controller, according to several embodiments of the present disclosure. Detailed Implementation

[0017] Systems, apparatus, and methods related to an internal controller for error correction codes (ECC) are described. Various embodiments of this disclosure relate to performing error correction operations (alternatively referred to as "on-die ECC operations") on data stored in a memory cell array on the same die as the on-die controller at an on-die controller, which eliminates the need to transmit (e.g., transfer) error correction information (alternatively referred to as "on-die ECC bits") for on-die ECC operations outside the memory die. Because the on-die ECC bits do not need to be transmitted outside the memory die, channels coupled to the memory die and used for transmitting data outside the memory die can have more bandwidth for other types of auxiliary data (e.g., non-user data) dedicated to ensuring the reliability, security, and integrity of the data in the memory system during predefined groups of data transmissions.

[0018] In some embodiments, the Extended Data Page (EDP) feature is used to transfer (e.g., exchange) auxiliary data to or from an array of memory dies, allowing auxiliary data transfers and data transfers carried via Data Input / Output (DQ) pins to occur substantially simultaneously. As used herein, the term “substantially” means that the feature need not be absolute, but rather sufficiently close to achieve the advantages of the feature. For example, “substantially simultaneous” is not limited to operations that are performed exactly simultaneously, but may include timing sequences that are desired to be simultaneous but may not be precisely simultaneous due to manufacturing limitations. As described above, the bandwidth of the EDP feature reserved for ECC bits on the die (e.g., the amount of bits that the EDP feature can transfer within a certain burst length) can be used for other types of auxiliary data, which can further enhance the data reliability, security, and integrity required by the memory system.

[0019] As used herein, the singular forms “a” and “the” include both singular and plural references unless the content explicitly indicates otherwise. Furthermore, the word “may” is used throughout this application to mean permitted (i.e., possible, able) rather than mandatory (i.e., required). The term “comprising” and its derivatives mean “including (but not limited to)”. The term “coupled” means a direct or indirect connection. It should be understood that data can be transmitted, read, transmitted, received, or exchanged via electronic signals (e.g., current, voltage, etc.).

[0020] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar numbers. For example, 110 could refer to... Figure 1 Component "10" is shown in Figure 2, and a similar component can be referred to as 210. Similar components within the figure may be designated using hyphens and additional numbers or letters. See, for example... Figure 1 Elements 102-1, 102-2, and 102-M are shown in the figures. Such similar elements may be collectively referred to without hyphens or additional numbers or letters. For example, elements 102-1, 102-2, and 102-M may be collectively referred to as element 102. As used herein, the designations “M” and “N”, particularly with respect to reference numerals in the figures, indicate the number of specific features indicated. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the invention and should not be considered as intended to be limiting.

[0021] Figure 1This is a functional block diagram of a computing system 101 (alternatively referred to as a "memory system") including a memory controller 100 according to several embodiments of the present disclosure. The memory controller 100 may include a front-end portion 104, a central controller portion 110, and a back-end portion 119. The computing system 101 may include a host 103 coupled to the memory controller 100 and memory devices 126-1, ..., 126-N.

[0022] The front-end portion 104 includes an interface and interface management circuitry for coupling the memory controller 100 to the host 103 via input / output (I / O) paths 102-1, 102-2, ..., 102-M, and circuitry for managing the I / O paths 102. Any number of I / O paths 102 may exist, such as eight, sixteen, or another number of I / O paths 102. In some embodiments, the I / O path 102 may be configured as a single port.

[0023] In some embodiments, memory controller 100 may be a compute fast link (CXL) compliant memory controller. A host interface (e.g., front-end portion 104) is managed using the CXL protocol and coupled to host 103 via an interface configured for peripheral component interconnect fast (PCIe) protocols. CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to accelerate next-generation data center performance. CXL technology maintains memory coherence between the CPU memory space and memory on the attached device, allowing resource sharing to improve performance, reduce software stack complexity, and lower overall system cost. CXL is designed as an industry-open standard interface for high-speed communication as accelerators are increasingly used to supplement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on PCIe infrastructure, thereby leveraging PCIe physical and electrical interfaces to provide high-level protocols in the region, such as input / output (I / O) protocols, memory protocols (e.g., initially allowing hosts and accelerators to share memory), and coherent interfaces. As an example, the interface of front-end 104 may be a PCIe 5.0 or 6.0 interface coupled to I / O path 102. In some embodiments, the memory controller 100 may receive access requests relating to the memory device 126 via the PCIe 5.0 or 6.0 interface 206 in accordance with the CXL protocol.

[0024] The central controller section 110 may include and / or be referred to as a data management circuitry. The central controller section 110 may control the execution of memory operations in response to a request received from the host 103. Examples of memory operations include read operations that read data from the memory device 126 or write operations that write data to the memory device 126.

[0025] The central controller section 110 can generate error detection information and / or error recovery information based on data received from the host 103. The central controller section 110 can perform error detection operations and / or error recovery operations on data received from the host 103 or from the memory device 126. An example of an error detection operation is a Cyclic Redundancy Check (CRC) operation. CRC can be referred to as algebraic error detection. CRC may contain a check value resulting from algebraic calculations using the data to be protected. CRC can detect unexpected changes in data by comparing a check value stored associated with the data with a check value calculated based on the data. Error correction operations (alternatively referred to as error correction code (ECC) operations) can be performed to correct the amount of bit errors and / or detect the amount of bit errors that may not have been corrected using ECC operations. The error correction information used to perform ECC operations may be parity data (alternatively referred to as "ECC bits" or "ECC data"), which is generated by comparing (e.g., XOR operation) user data (e.g., data received from the host 103) with an encoding matrix. Error recovery operations (alternatively referred to as data recovery operations) can be performed to recover data from one or more memory dies (e.g., one or more memory dies 327-1, ..., 327-4 or 427-1, ..., 427-8) despite their complete failure. Error recovery operations may include chip kill operations.

[0026] Chip-kill operations protect the memory system even if a constituent chip (e.g., memory device 126) is damaged; thereby avoiding a single point of failure (SPOF) situation where one of the chips is the memory system. Typically, chip-kill capability is provided through various ECC schemes that include a "Redundant Array of Independent Disks (RAID)" scheme, which allows data recovery from a damaged chip by reading all constituent chips of the memory system.

[0027] Chip hunting can involve parity data specifically designed for data recovery of damaged chips (e.g., RAID parity). RAID parity data can be generated by comparing (e.g., XOR operations) each subset of user data (e.g., subsets of user data already stored in and / or to be stored in each memory die 327 and / or 427 illustrated in Figures 3 and 4, respectively). User data sharing the same parity data can be referred to as being grouped together.

[0028] Back-end portion 119 may include a media controller and a physical (PHY) layer that couples memory controller 100 to memory device 126. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and may be used to transmit data via a physical data transmission medium. In some embodiments, the physical data transmission medium may include channels 125-1, ..., 125-N. Channels 125 may include various types of data buses, such as four-pin data buses (e.g., data input / output (DQ) buses) and single-pin data mask inversion (DMI) buses, as well as other possible buses.

[0029] Memory device 126 can be various / different types of memory devices. For example, the memory device may include an array (e.g., Figure 2A and 2B The memory cell array 220 described herein includes RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory cells, as well as others. In embodiments where the memory device 126 includes persistent or non-volatile memory, the memory device 126 may be a flash memory device, such as a NAND or NOR flash memory device. However, embodiments are not limited thereto, and the memory device 126 may include other non-volatile memory cell arrays, such as non-volatile random access memory cells (e.g., non-volatile RAM (NVRAM), ReRAM, ferroelectric RAM (FeRAM), MRAM, PCRAM), "emerging" memory cells (e.g., ferroelectric RAM cells containing ferroelectric capacitors that can exhibit hysteresis characteristics), memory devices having resistive, phase-change, or similar memory cells, or combinations thereof.

[0030] As an example, an FeRAM device (e.g., memory device 126 includes an array of FeRAM cells) may include ferroelectric capacitors and may perform bit storage based on the voltage or amount of charge applied to them. In such examples, relatively small and relatively large voltages allow the ferroelectric RAM device to exhibit properties similar to normal dielectric materials (e.g., dielectric materials with relatively high dielectric constants), but at different voltages between these relatively small and large voltages, the ferroelectric RAM device may exhibit polarization reversal that produces nonlinear dielectric behavior.

[0031] In another example, memory device 126 may be a dynamic random access memory (DRAM) device (e.g., memory device 126 comprising an array of DRAM cells) operating according to a protocol such as Low Power Double Data Rate (LPDDRx), which may be referred to herein as an LPDDRx DRAM device, LPDDRx memory, etc. The "x" in LPDDRx refers to any of several generations of protocols (e.g., LPDDR5). In at least one embodiment, at least one of the memory devices 126-1 operates as an LPDDRx DRAM device with low-power features enabled, and at least one of the memory devices 126-N operates as an LPDDRx DRAM device with at least one low-power feature disabled. In some embodiments, although memory device 126 is an LPDDRx memory device, memory device 126 does not include circuitry configured to provide low-power functionality for memory device 126, such as a Dynamic Voltage Frequency Scaling Core (DVFSC), Subthreshold Current Reduction Circuit (SCRC), or other low-power functionality-providing circuitry. Providing an LPDDRx memory device 126 without this circuitry can advantageously reduce the cost, size, and / or complexity of the LPDDRx memory device 126. For example, an LPDDRx memory device 126 with circuitry that reduces low-power functionality can be used in applications other than mobile applications (e.g., if the memory is not intended for use in mobile applications, some or all of the low-power functionality can be sacrificed to reduce the cost of manufacturing the memory).

[0032] Data can be transferred between back-end section 119 and memory device 126, primarily in the form of memory transfer blocks (MTBs) containing several user data blocks (UDBs). As used herein, the term "MTB" refers to a group of UDBs that are grouped together to have the same parity data blocks (PDBs) (e.g., sharing the same PDBs), and thus transferred together from a cache (e.g., cache 212) and / or memory device 126 for each read or write command. For example, a group of UDBs with the same MTB can be transferred back and forth (e.g., written to / read from) memory device 126 via channel 125 within a predefined burst length (e.g., 16-bit or 32-bit BL) operated under memory controller 100.

[0033] A burst is a series of data transfers within multiple cycles (e.g., ticks). As used herein, the term "tick" refers to the clock cycle increment during which an amount of data equal to the width of the memory bus can be transferred. For example, a 32-bit burst length may consist of 32 ticks of data transfer, while a 16-bit burst length may consist of 16 ticks of data transfer. Although embodiments are not limited to this, the bus width corresponding to the size of each tick may be 8 (e.g., alternatively referred to as "x8").

[0034] As used herein, the term "PDB" refers to a data block containing parity data (e.g., RAID parity) configured for chip-hunting (e.g., RAID) operations on UDBs grouped with PDBs. As further described herein, the MTB may be in plaintext or ciphertext form depending on whether the MTB has been encrypted at the memory controller 100 (e.g., security encoder 217-1).

[0035] As used herein, the term "UDB" refers to a block of data containing host data (e.g., data received from host 103 and alternatively referred to as "user data"). While a UDB may correspond to the size of a host read and / or write request, an MTB may be a unit of read and / or write access to a memory device. In addition to MTBs, PDBs may also be transferred between back-end section 119 and memory device 126. Host data or parity data for a single UDB or PDB may correspond to multiple codewords (e.g., 64 codewords).

[0036] In addition to the UDB, other “extra” data bits (e.g., data other than the data corresponding to the UDB and alternatively referred to as “auxiliary data”) may also be transmitted between the back-end section 119 and the memory device 126. The extra data may include data and / or metadata for correcting and / or detecting errors in the UDB and / or authenticating and / or verifying the data integrity of the UDB, but embodiments are not limited thereto. Further details of the extra bits are illustrated and described in conjunction with Figures 2 through 4.

[0037] In some embodiments, some (e.g., one or more) memory devices 126 may be dedicated to the PDB. For example, memory devices configured to store UDBs may be different from memory devices configured to store PDBs (e.g., one or more memory devices).

[0038] In some embodiments, the memory controller 100 may include a management unit 105 for initializing, configuring, and / or monitoring the characteristics of the memory controller 100. The management unit 105 may include: an I / O bus for managing out-of-band data and / or commands; a management unit controller for executing instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller; and a management unit memory for storing data associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 100. As used herein, the term "out-of-band" generally refers to a transmission medium different from the primary transmission medium of the network. For example, out-of-band data and / or commands may be data and / or commands transmitted to the network using a transmission medium different from the transmission medium used to transmit data within the network.

[0039] Figure 2AThis is a functional block diagram of a memory controller 200 for cache line data protection according to several embodiments of the present disclosure. Figure 2A The memory controller 200, central controller section 210, back-end section 219, and memory device 226 described herein are similar to Figure 1 The memory controller 100, central controller section 110, back-end section 119 and memory device 126 are described in the document.

[0040] The central controller section 210 includes a front-end CRC (“FCRC”) encoder 211-1 (e.g., paired with an FCRC decoder 211-2) to generate error detection information (e.g., alternatively referred to as end-to-end CRC (e2e CRC)) based on data (e.g., a UDB in “plaintext” form) received as a write command (e.g., received from host 103) and before writing the data to cache 212. The error detection information generated at the FCRC encoder 211-1 can be a check value, such as CRC data. The read and write commands of the CXL memory system can be the size of a UDB, such as 64 bytes. Therefore, the data received at the FCRC encoder 211-1 can correspond to a UDB.

[0041] Central controller section 210 includes cache 212 to store data associated with the execution of memory operations (e.g., user data), error detection information, error correction information, and / or metadata. An example of cache 212 is a thirty-two (32)-way set-associative cache containing multiple cache lines. While host read and write commands can be UDB-sized (e.g., 64 bytes), the cache line size can be larger than the UDB size (e.g., equal to the size of multiple UDBs). For example, the cache line size can correspond to the size of two UDBs (where each UDB is a 64-byte block), such as 128 bytes.

[0042] These UDBs stored in each cache line (e.g., alternatively referred to as "UDBs corresponding to cache lines") can serve as data transfer units for the data path between cache 212 and memory device 226. For example, even if a host read / write command is the size of a UDB (e.g., 64 bytes), the UDBs corresponding to cache lines can be transferred together as blocks between cache 212 and memory device 226 (e.g., via...). Figure 2A Other encoders / decoders described in the document). Therefore, the UDB corresponding to the cache line can be found in Figure 2A The various encoders / decoders described herein jointly encrypt / decrypt and are located between cache 212 and memory device 226. In some embodiments, these UDBs corresponding to the same cache line may also correspond to MTBs.

[0043] Data (e.g., UDB) stored in cache 212 (e.g., its corresponding cache line) may be further transferred to other components of the central controller section 210 (e.g., security encoder 217-1 and / or authentication encoder 218-1) (e.g., as part of a cache write strategy, such as cache write-back and / or cache write-through) to be finally stored in memory device 226 for use by the host (e.g., ...). Figure 1 When the data received by the host 103 (described in the text) has not yet been written to the memory device 226, the cache 212 is synchronized with the memory device 226.

[0044] Using cache 212 to store data associated with read or write operations improves the speed and / or efficiency of data access because cache 212 can prefetch data and store it in multiple 64-byte blocks (e.g., 128 bytes) when a cache miss occurs. Instead of searching a separate memory device when a cache miss occurs, data can be read from cache 212. Accessing prefetched data uses less time and energy than a memory system that must search for data before accessing it.

[0045] The central controller section 210 further includes a security encoder 217-1 (e.g., paired with a security decoder 217-2) to encrypt data (e.g., MTB or UDB corresponding to a cache line) before transmitting the data to the CRC encoder 213-1 (to write the data to the memory device 226). While embodiments are not limited thereto, the security encoder / decoder pair 217 may use AES encryption / decryption (e.g., algorithm) operations. Unencrypted data (e.g., plaintext) may be converted to ciphertext by the security encoder 217-1 via encryption. The central controller section 210 further includes an authentication encoder 218-1 to generate authentication data based on data received from the cache 212. While embodiments are not limited thereto, the authentication data generated at the authentication encoder 218-1 may be a MAC, such as a KECCAK MAC (KMAC) (e.g., SHA-3-256 MAC).

[0046] In some embodiments, the MAC generated at the authentication encoder 218-1 may be based on Trusted Execution Environment (TEE) data (alternately referred to as "TEE flag"), host physical address (HPA) (e.g., the one associated with a host read / write transaction by...), and other relevant data. Figure 1 The host 103 uses / identifies the memory address described in the document, and calculates the security key identifier (ID) associated with the physical address of the memory device 226 used to execute host write commands.

[0047] The security encoder 217-1 and the authentication encoder 218-1 can operate in parallel. For example, data stored in cache 212 and in plaintext form can be input (e.g., transmitted) to both the security encoder 217-1 and the authentication encoder 218-1. In some embodiments, a security key ID can be further input (along with the data in plaintext form) to the security encoder 217-1. Furthermore, in some embodiments, the security key ID, TEE flag, and HPA associated with a host write command can be further input (along with the data in plaintext form) to the authentication encoder 218-1.

[0048] The central controller section 210 includes a CRC encoder 213-1 (e.g., paired with a CRC decoder 213-2) to jointly generate error detection information (e.g., alternatively referred to as CRC media (CRCm)) based on a UDB corresponding to a cache line (e.g., on an MTB) received from the security encoder 217-1. Data transmitted from the security encoder 217-1 to the CRC encoder 213-1 may be in ciphertext form because the data was previously encrypted at the security encoder 217-1. The error detection information generated at the error detection information generator 213-1 may be a checksum, such as CRC data. The CRC encoder 213-1 and the CRC decoder 213-2 can operate on data having a size equal to or greater than the cache line size.

[0049] The central controller section 210 includes a RAID encoder 214-1 (e.g., paired with a RAID decoder 214-2) to generate and / or update (e.g., of a PDB) RAID parity data based at least in part on data received from the CRC encoder 213-1 (e.g., MTB corresponding to a cache line or one or more UDBs). Data transmitted from the CRC encoder 213-1 to the RAID encoder 214-1 may be in ciphertext form because the data is encrypted at the security encoder 217-1.

[0050] In some embodiments, RAID encoder 214-1 may further generate error correction information (e.g., different from RAID parity data) to correct one or more bit errors and / or detect an error quantity exceeding the number of one or more bit errors. While RAID parity data can be used to recover all bits of the data stored in memory die 227, the error correction information can be used to correct only a portion of the data stored in memory die 227. Further details associated with the error correction information are described below in connection with RAID decoder 214-2.

[0051] The RAID encoder 214-1 can update the PDB to conform to the new UDB received from the host as part of a write command. To update the PDB, the old UDB (which will be replaced by the new UDB) and the old PDB (with the same stripes as the old UDB) can be read (e.g., transmitted to the RAID encoder 214-1) and compared (e.g., by XOR operation) with the new UDB, and the result of the comparison (e.g., by XOR operation) can be further compared (e.g., by XOR operation) with the old PDB (which will be updated) to result in a new (e.g., updated) PDB.

[0052] "Extra" data bits (referred to instead as "auxiliary data") may be transmitted (along with the UDB) to the back-end section 219 for final transmission and writing to the memory device 226. The "extra" bits may include RAID parity data (e.g., in PDB form) generated at RAID 214-1, error detection information (e.g., CRC data) generated at FCRC encoders 211-1 and / or 213-1, and / or authentication data (e.g., MAC data) generated at authentication encoder 218-1, which are associated with the UDB and metadata and / or TEE data.

[0053] like Figure 2A As shown, the memory controller 200 may include a back-end section 219 coupled to the central controller section 210. The back-end section 219 may include media controllers 221-1, ..., 221-X. The back-end section 219 may include PHY memory interfaces 224-1, ..., 224-X. Each physical interface 224 is configured to couple to a corresponding memory device 226.

[0054] Media controllers 221-1, ..., 221-X can be used substantially simultaneously to drive channels 225-1, ..., 225-N. In at least one embodiment, each of the media controllers 221 can receive the same command and address and drive channel 225 substantially simultaneously. By using the same command and address, each of the media controllers 221 can perform the same memory operation on the same memory cell using channel 225.

[0055] As used herein, the term "substantially" means that the characteristics need not be absolute, but are close enough to achieve the advantages of the characteristics. For example, "substantially simultaneous" is not limited to operations that are performed exactly simultaneously, but can include timing that is desired to be simultaneous but may not be precisely simultaneous due to manufacturing limitations. For example, due to the read / write latency that can be exhibited by various interfaces (e.g., LPDDR5 versus PCIe), media controllers utilized "substantially simultaneously" may not start or finish at exactly the same time. For example, memory controllers can be utilized to write data to memory devices at the same time, regardless of whether one of the media controllers starts or terminates before the other.

[0056] PHY memory interface 224 may be an LPDDRx memory interface. In some embodiments, each of the PHY memory interfaces 224 may include data and DMI pins. In embodiments where there is a 1:1:1 correlation between the PHY memory interface, media controller 221, and memory device 226 (or alternatively channel 226), each PHY memory interface 224 may include sixteen DQ pins and two DMI pins corresponding to a single memory device 126. In alternative embodiments, each PHY memory interface 224 may collectively manage several memory devices 226 corresponding to data protection channels (e.g., RAID channels 329 and / or 429 illustrated in Figures 3 and 4, respectively), which may result in each PHY memory interface 224 including seventy-two DQ pins and nine DMI pins (corresponding to nine memory devices 226) or each PHY memory interface 224 including eighty DQ pins and ten DMI pins (corresponding to ten memory devices 226). Media controller 221 can be configured to exchange data with a corresponding memory device 226 (e.g., its memory die 227) via data pins. Media controller 221 can be configured to exchange error detection information and / or metadata via DMI pins instead of data pins. DMI pins can provide various functions, such as data masking, data bus inversion, and parity checking for read operations by setting a mode register. The DMI bus uses bidirectional signaling. In some examples, each data transfer byte has a corresponding signal sent via the DMI pin for data selection. In at least one embodiment, data can be exchanged simultaneously with error correction information and / or error detection information. For example, 128 data bytes (e.g., corresponding to an MTB or UDB of a cache line) can be exchanged (transmitted or received) via data pins, while 128 additional bits are exchanged via DMI pins. Such embodiments reduce the overhead on the data input / output (e.g., also referred to in the art as "DQ") bus that would otherwise be used to transmit error correction information, error detection information, and / or metadata.

[0057] Back-end portion 219 can couple PHY memory interfaces 224-1, ..., 224-X to corresponding memory devices 226-1, ..., 226-N. Each memory device 226 includes at least one memory cell array. In some embodiments, memory devices 226 may be different types of memory. Media controller 221 may be configured to control at least two different types of memory. For example, memory device 226-1 may be an LPDDRx memory operating according to a first protocol and memory device 226-N may be an LPDDRx memory operating according to a second protocol different from the first protocol. In this example, first media controller 221-1 may be configured to control a first subset of memory devices 226-1 according to the first protocol and second media controller 221-X may be configured to control a second subset of memory devices 226-N according to the second protocol.

[0058] Each memory device 226 may include memory cell arrays 220-1, ..., 220-Q, each containing a memory cell array 220-1, ..., 220-Q and an internal controller 228-1, ..., 228-Q (alternatively referred to as "controller on die") that can be dedicated to a respective memory die (e.g., memory dies 327 and / or 427 illustrated in Figures 3 and 4, respectively). Although the embodiments are not limited thereto, the memory cell array 220 may contain FeRAM cells.

[0059] Internal controller 228 may be an on-die controller configured to access corresponding memory cell arrays 220 on the same die (e.g., memory dies 327 and / or 427 illustrated in Figures 3 and 4, respectively). Although Figure 2A The figures are not shown in order to avoid obscuring the contents, but the internal controller 228 may contain various circuit systems to facilitate and / or orchestrate the operations described herein.

[0060] The internal controller 228 can control the execution of memory operations associated with the respective memory dies. Examples of memory operations include read operations that read data from memory dies 327, 427 (e.g., their memory cell arrays) or write operations that write data to memory dies 327, 427 (e.g., their memory cell arrays).

[0061] The internal controller 228 may further provide error correction capabilities. For example, after data (e.g., a portion (subset) of a UDB) is transferred to and received at the memory die 227, the corresponding internal controller 228 may generate error correction information (alternatively referred to as "on-die ECC data") based on the data, store the error correction information in a corresponding array on the same memory die 227, and perform an error correction operation (using the on-die ECC data) (alternatively referred to as "on-die ECC operation") before the data is returned to the memory controller 200.

[0062] On-die ECC data can be used to correct a single error (without detecting the error) (this is called a single error correction (SEC) operation), correct a single error or detect two errors (without correcting the two errors) (this is called a single error correction and double error detection (SECDED) operation), or correct two errors or detect three errors (without correcting the three errors) (this is called a double error correction and triple error detection (DECTED) operation), but the embodiments are not limited thereto. The results of the error correction operation performed at each internal controller 228 can be reported to the memory controller 200 (e.g., a corresponding media controller 221). For example, the results can indicate whether any bit error has been corrected (single or double bit error) or whether there is any amount of bit error (single or double bit error) that cannot be corrected despite the error correction operation being performed.

[0063] Data stored in memory device 226 (corresponding to the MTB or UDB of the cache line) can be transferred to back-end section 219 for final transfer and writing to cache 212 and / or transfer to host (e.g., Figure 1 (Host 103 as described in the document). In some embodiments, data is transmitted in response to a read command that accesses a subset of data (e.g., a UDB) and / or synchronizes cache 212 with memory device 226 to clear “dirty” data from cache 212.

[0064] In addition to the UDB, other “extra” data bits (alternately referred to as “auxiliary data”) may also be transmitted to the back-end section 219. These “extra” bits may include RAID parity data (e.g., in PDB form) generated at RAID encoder 214-1, error detection information generated at FCRC encoders 211-1 and / or 213-1, parity data (e.g., RAID parity data) generated at RAID encoder 214-1, and authentication data generated at authentication encoder 218-1, which are associated with the UDB and metadata and / or TEE data. In some embodiments, the “extra” bits may further include error correction information generated at RAID encoder 214-1. As described herein, the UDB transmitted to the back-end section 219 may be in encrypted form.

[0065] Data transferred from memory device 226 to back-end section 219 (e.g., MTB or UDB corresponding to cache lines) may be further transmitted to CRC decoder 213-2 along with at least error detection information previously generated at CRC encoder 213-1. At CRC decoder 213-2, error detection operations may be performed to detect any errors in the UDB using error detection information (e.g., CRC data).

[0066] The CRC decoder 213-2, together with the RAID decoder 214-2, can further manipulate the data to provide verification and recovery correction. More specifically, the CRC decoder 213-2 can detect errors in the data transmitted from the memory device 226, and the RAID decoder 214-2 can responsively correct and / or recover the data in various ways.

[0067] RAID decoder 214-2 provides error correction capabilities (e.g., by performing ECC operations) and data recovery capabilities (e.g., by performing RAID operations). In one embodiment, RAID decoder 214-2 may cooperate with internal controller 228 to operate CRC decoder 213-2 to implement a “retry mechanism.” For example, if CRC decoder 213-2 indicates one or more bit errors on the MTB, then RAID decoder 214-2 may cause memory device 226 (e.g., a corresponding media controller 221 coupled to memory device 226) to retry the transmission of the corresponding subset (e.g., retransmit) several times (e.g., three times). Using copies of the MTB transmitted within the retransmissions, RAID decoder 214-2 may utilize a “voting mechanism” to correct the amount of bit errors. For example, RAID decoder 214-2 may determine whether a majority of copies match the data pattern and transmit the MTB with the corresponding majority matching data pattern (e.g., transmitted to the CRC decoder of RAID decoder 214-2).

[0068] If an error persists that cannot be corrected by the ECC operation and / or retry mechanism performed by the RAID decoder 214-2 (as indicated by the CRC decoder within the RAID decoder 214-2), then the RAID decoder 214-2 may trigger a RAID process. When the RAID process is triggered, the RAID operation performed on the UDB can recover a subset of the UDB transferred from a (e.g., a failed) memory die based on other subsets of the UDB transferred from other memory dies. Since all subsets (of the UDB) are input (e.g., transferred) to the CRC decoder (e.g., ...), the RAID operation is performed on the UDB. Figure 2AThe CRC decoder 213-2 described in the document checks for one or more errors (alternatively referred to as "locked RAID"). Therefore, the CRC check performed at the CRC decoder cannot indicate which subset has one or more errors. Thus, the triggered RAID process involves several RAID operations, which can be performed separately and independently on each subset to correct the subset that does indeed have errors. For example, considering that UDB is drawn from four memory dies (e.g., ... Figure 3A The memory dies 327-1 to 327-4 described herein can be received separately for each subset of the UDB (e.g., Figure 3B The subsets 354-1, ..., 354-4 described herein perform four RAID operations. Alternatively, considering that UDB is drawn from eight memory dies (e.g., ... Figure 4A The memory dies 427-1 to 427-8 described herein can be received separately for each subset of the UDB (e.g., Figure 4B The subsets 454-1, ..., 454-8 described in the document perform eight RAID operations.

[0069] In some embodiments, RAID decoder 214-2 may further include a CRC decoder that provides the same functionality as CRC decoder 213-2, but performs error detection operations (e.g., CRC check) on the data after the RAID operation. Continuing with the above example, the CRC decoder within RAID decoder 214-2 can be used to perform CRC checks on the results of eight RAID operations to determine which of the RAID operations actually corrected the error (instead of correcting a subset that did not trigger the RAID process). One of the results (e.g., the UDB where the error was correctly corrected) can then be sent to security decoder 217 and / or authentication decoder 218.

[0070] In some embodiments, RAID decoder 214-2 may use error correction information previously generated at RAID encoder 214-1 (alternately referred to as “link ECC data”) to perform a corresponding error correction operation (e.g., a link ECC operation) on each subset (e.g., subsets 354 and / or 454 illustrated in Figures 3 and 4) of one or more UDBs and / or PDBs received from memory device 226. The error correction operation performed on the corresponding subset may be a SEC operation, a SECDED operation, or a DECTED operation, but the embodiments are not limited thereto. The link ECC operation is performed to avoid errors (e.g., random errors) that have occurred within the channel (e.g., channel 225 and alternatively referred to as the “link”). The retry mechanism may be selectively enabled or disabled.

[0071] Data (e.g., MTB or UDB corresponding to a cache line) may be further transmitted to the security decoder 217-2 and the authentication decoder 218-2, along with at least the authentication data previously generated at the authentication encoder 218-1. At the security decoder 217-2, the data can be decrypted (e.g., reversed from ciphertext to plaintext, as initially received from the host). The security decoder 217-2 can use AES decryption to decrypt the data.

[0072] At authentication decoder 218-2, the data decrypted at security decoder 217-2 can be authenticated (and / or have its integrity verified) using authentication data (e.g., MAC data) previously generated at authentication encoder 218-1. In some embodiments, authentication decoder 218-2 may calculate the MAC based on TEE data, HPA, and security key ID associated with the physical address accessed to execute a host read command. The MAC calculated during the read operation may be compared with the MAC transmitted from memory device 226 (corresponding to its physical address location). If the calculated MAC matches the transmitted MAC, then the UDB is written to cache 212 (and further transmitted to the host as needed). If the calculated MAC does not match the transmitted MAC, then the host is notified of the mismatch (and / or poisoning).

[0073] Data authenticated (and / or verified for data integrity) at authentication decoder 218-2 (e.g., MTB or UDB corresponding to a cache line) may be transferred and written to cache 212. In some embodiments, data may be transferred, for example, in response to a request from a host (e.g., Figure 1 The host 103, as described herein, receives a read command and further transmits it from cache 212 to FCRC decoder 211-2. As described herein, host read and write commands for the CXL memory system can be in UDB size, such as 64 bytes. For example, data can be requested by the host at the UDB granularity. In this example, even if the data transmitted from memory device 226 is multiple UDBs (corresponding to cache lines), the data can be transmitted from cache 212 to the host at the UDB granularity. At FCRC decoder 211-2, any errors in the data (e.g., the UDB requested by the host) can be verified (CRC checked) using CRC data previously generated at FCRC encoder 211-1. Data decrypted at FCRC decoder 211-2 can then be further transmitted to the host.

[0074] Figure 2B This is another functional block diagram of a memory controller 200 for cache line data protection according to several embodiments of the present disclosure. Figure 2B The memory controller 200, central controller section 210, back-end section 219, and memory device 226 described herein are similar to Figure 1 The memory controller 100, central controller section 110, back-end section 119 and memory device 126 are described in the document.

[0075] The memory controller 200 may include a central controller section 210 and a back-end section 219. The central controller section 210 may include a front-end CRC (“FCRC”) encoder 211-1-1 paired with FCRC decoder 211-1-2 and an FCRC encoder 211-2-2 paired with FCRC decoder 211-2-1, a cache memory 212 coupled between the paired CRC encoder / decoder 211-1 and CRC encoder / decoder 211-2, a security encoder 217-1 paired with security decoder 217-2, an authentication encoder 218-1 paired with authentication decoder 218-2, a CRC encoder 213-1 paired with CRC decoder 213-2, and a RAID encoder 214-1 paired with RAID decoder 214-2. A pair of security encoders / decoders 217, a pair of authentication encoders / decoders 218, a pair of CRC encoders / decoders 213, and a pair of RAID encoders / decoders 214 may be similar to... Figure 2A The description includes a pair of security encoders / decoders 217, a pair of authentication encoders / decoders 218, a pair of CRC encoders / decoders 213, and a pair of RAID 214. Although... Figure 2B Not specified, but RAID decoder 214-2 may further include a CRC decoder that provides the same functionality as CRC decoder 213-2, but performs error detection operations (e.g., CRC check) on the data after the RAID process.

[0076] The back-end section 219 may include media controllers 221-1, ..., 221-N. The back-end section 219 may further include PHY memory interfaces 224-1, ..., 224-N configured to be coupled to memory devices 226-1, ..., 226-N via channels 225-1, ..., 225-N.

[0077] Figure 2B Similar to Figure 2A It simply includes additional circuitry for using CRC data to verify any errors on the UDB, without requiring the CRC to be transmitted / stored in memory device 226. For example, such as Figure 2BThe description states that the FCRC decoder 211-1-2 coupled between cache 212 and security encoder 217-1 (and / or authentication encoder 218-1) can be configured to use error detection information (e.g., CRC data) generated at FCRC encoder 211-1-1 to verify any errors on the UDB stored in cache 212. The FCRC encoder 211-2-1 coupled between cache 212 and security decoder 217-2 (and / or authentication decoder 218-2) can be configured to generate information about data transmitted to the host (e.g., ...). Figure 1 Error detection information (e.g., CRC data) of the UDB of the host 103 described herein. The error detection information generated at the FCRC encoder 211-2-1 can be used at the FCRC decoder 211-2-2 to verify any errors on the UDB transmitted from the cache 212.

[0078] In some embodiments, CRC encoder / decoder pairs 211-1 and 211-2 may be used only to verify errors in data stored in a cache. Therefore, error detection information (e.g., CRC data) used at pairs 211-1 and 211-2 is not transmitted and written to memory device 226.

[0079] Figure 3A This is a block diagram of memory dies corresponding to several data protection channels (e.g., RAID channels) according to several embodiments of the present disclosure. The diagram illustrates five memory dies 327-1, ..., 327-5 that may be similar to memory die 227.

[0080] Each memory die 327 may include several data pins of different types, such as DQ pins and DMI pins. For each memory die 327, data can be exchanged (e.g., transferred back and forth between memory dies 327) at a rate of Y bits per tick via the DMI pin and at a rate of Z bits per tick via the DQ pin within a burst length of X bits. In one example, each memory die 327 may include 8 DQ pins and 1 DMI pin, such that data is transmitted within a 16-bit burst length at a rate of 8 bits per tick via the 8 DQ pins and at a rate of 1 bit per tick via the 1 DMI pin.

[0081] Although the embodiments are not limited to this, the two memory dies 327 may correspond to Figure 1The channels 125 and / or 225 (e.g., their channel widths) described in section 2 are also considered. For example, memory dies 327-1 and 327-2 may correspond to one channel 125, 225; memory dies 327-3 and 327-4 may correspond to another channel 125, 225; and memory die 327-5 may correspond to a different channel 125, 225 (half of it). Therefore, each channel 125, 225 may be 2*Y bit wide (e.g., 16 bit wide).

[0082] Memory dies 327-1, ..., 327-5 may correspond to memory devices (e.g., Figure 1 The same memory column (and memory devices 126 and / or 226) described in section 2. As used herein, the term "memory column" generally refers to multiple memory chips (e.g., memory dies) that can be accessed simultaneously. Thus, memory dies 327-1, ..., 327-5 can be accessed simultaneously (e.g., "substantially simultaneously" as defined herein).

[0083] The figure illustrates four memory dies 327-1, ..., 327-4 (of RAID channel 329) that can store UDBs 323-1 and 323-2 (corresponding to the same MTB), but the embodiment is not limited to a specific number of memory dies that can be stored in a single UDB. For example, UDB 323-1 can be stored in memory dies 327-1 and 327-2, while UDB 323-2 can be stored in memory dies 327-3 and 327-4, as illustrated in Figure 3. In a particular instance, given that each UDB is 64 bytes, each memory die 327 can be configured to store 32 bytes. UDBs 323 can be swapped via the DQ pin of the corresponding memory die 327.

[0084] Memory dies 327-1, ..., 327-4 may further store and transmit auxiliary data (e.g., 20 bits) via one or more DMI pins. The auxiliary data that can be transmitted from memory dies 327-1, ..., 327-4 via DMI pins within an X-bit burst length (e.g., within a 32-bit burst length) may include (e.g., 28 bits) authentication data (e.g., MAC generated at authentication encoder 218-1 illustrated in FIG. 2), (e.g., 45 bits) error detection data (e.g., including 7 bits of FCRC data generated at CRC encoder 211-1 and 31 bits of CRC data generated at CRC encoder 213-1 for each UDB 323), (e.g., 1 bit) TEE data, and (e.g., 6 bits) metadata (e.g., 3 bits per UDB 323), totaling 80 bits of auxiliary data. In some embodiments, 10 bits of ECC data (e.g., for link ECC operations) and / or 2 bits for indicating the result of the on-chip ECC operation performed on each subset (corresponding to the corresponding memory die 327) (e.g., "no error", "unit error", "two-bit error" or "more than two-bit error") may optionally be transmitted via the DMI pin within an X-bit burst length.

[0085] The figure further illustrates a memory die 327-5 in which a PDB 339 containing RAID parity data (e.g., generated at RAID encoder 214-1) can be stored, but the embodiment is not limited to a specific number of memory dies in which the PDB can be stored.

[0086] Data stored in memory dies 327-1, ..., 327-5 (e.g., PDB and MTB containing UDB) can also be used in memory devices (e.g. Figure 1 and the memory devices 126 and / or 226 described in section 2) and the memory controller (e.g. Figure 1 The data transfer unit between the memory controllers 100 and / or 200 described in section 2. For example, UDB 323, along with auxiliary data 337 and PDB 339, can be transferred together in response to a host read command accessing one of UDB 323.

[0087] Memory dies 327-1, ..., 327-5 may correspond to data protection channels, such as RAID channel 329; therefore, RAID channel 329 may be 5*Y bit wide (corresponding to five memory dies 327) and a "4+1" RAID channel, indicating that four memory dies are configured for one or more UDBs and one memory die is configured for one or more PDBs, resulting in an overhead of 25% (e.g., 1 / 4 = 25%). A memory system (e.g., memory system 101) may contain several RAID channels (e.g., each corresponding to RAID channel 329).

[0088] Figure 3B This is a block diagram 350 illustrating a locked RAID process for data protection of a subset of UDB 323 according to several embodiments of the present disclosure. UDB 323 may be similar to UDB 323 illustrated in FIG. 3.

[0089] like Figure 3B The documentation states that UDB 323 contains four subsets of data (referred to as "subsets" in this document), for example, Figure 3B The subset 354-1 described in the text Figure 3B The subset "A" shown in the text), 354-2 ( Figure 3B The subset "B" shown in the text), 354-3 ( Figure 3B The subset "C" shown in the text), 354-4 ( Figure 3B The subset “D” shown in the text can correspond to the subsets that can be used with PDB (e.g., Figure 3A RAID channels that perform error recovery (e.g., PDB 339 as described in the document) Figure 3A The memory die (e.g., RAID channel 329 as described in the text) Figure 3A The memory dies 327-1, ..., 327-4 are described in the document.

[0090] Figure 3B Illustrate an example case where the subset "B" contains elements that cause problems in the CRC decoder (e.g., ...). Figure 2A One or more errors are caused by a CRC check (e.g., alternatively referred to as an error detection operation) performed at the CRC decoder 213-2 as described in 2B. At the RAID decoder 214-2, one or more RAID operations are performed (e.g., consecutively or in parallel) for four different combinations / cases, as further described below.

[0091] For example, performing a RAID operation based on the assumption that subset "A" has caused the CRC check to fail (352-1). Figure 3B The test is shown as "Test A"; RAID operation 352-2 is performed based on the assumption that subset "B" has caused CRC check failure. Figure 3BThe code is shown as "Test B"; RAID operation 352-3 is performed based on the assumption that subset "C" has caused CRC check failure. Figure 3B The code is shown as "Test C"; and RAID operation 352-4 is performed based on the assumption that subset "D" has caused CRC check failure. Figure 3B (Displayed as "Test D" in the text).

[0092] Errors in UDB 323, which has already undergone RAID operation 352, can be verified separately (e.g., via the corresponding CRC check). For example... Figure 3B The explanation states that UDB 323, which performs RAID operation 352-2, passes the CRC check because RAID operation 352-2, which was executed to recover subset "B", has correctly recovered UDB 323. However, other RAID operations 352-1, 352-3, and 352-4 failed to recover subset "D", and instead caused further errors in the corresponding subsets 354-1, 354-3, and 354-4.

[0093] RAID operation 352 can be performed in various ways along with one or more CRC checks. In one instance, RAID operation 352 is performed sequentially with the corresponding CRC check performed after each RAID operation. For example, RAID operation 352 can be performed in a sequence of 352-1 and 352-2, with two CRC checks performed after each RAID operation 352-1 and 352-2. Since the CRC check performed after RAID operation 352-2 will show "pass" (e.g., no errors in subset 354), the RAID process is complete and RAID operations 352-3 and 352-4 do not need to be performed. In another instance, RAID operation 352 is performed in parallel on subsets 354-1, ..., 354-4 (e.g., copies thereof). In this instance, a copy of UDB 323 (to which RAID operation 352-2 is performed) that has passed the CRC check for RAID operation 352 will be further sent to a security decoder (e.g., ...). Figure 2A and / or the security decoder 217-2 described in 2B).

[0094] In a non-restricted instance, the device (e.g.) Figure 1 , 2A The memory devices 126 and / or 226 described in 2B may include multiple memory cells (e.g., Figure 2A , 2B Memory dies 227, 327, and / or 427 as described in sections 3 and 4. Each memory cell in a plurality of memory cells may contain a corresponding array of memory cells (e.g., ...). Figure 2A and 2BThe array 220 described herein is configured to store corresponding portions of one or more user data blocks (UDBs) (e.g., UDBs 323 and 423 illustrated in Figures 3 and 4) and auxiliary data corresponding to the corresponding portions of the one or more UDBs. The first portion of the auxiliary data may contain error correction information corresponding to the corresponding portions of the one or more UDBs (e.g., in…). Figure 2A and 2B The on-chip ECC data generated at the corresponding internal controller 228 as described in the specification). The corresponding internal controller (e.g., Figure 2A and 2B The internal controller 228 described herein can be configured to perform an error correction operation (e.g., ECC operation) on the corresponding portion of one or more UDBs using error correction information in response to receiving a command to access the corresponding portion of one or more UDBs, in order to correct one or more bit errors on the corresponding portion of one or more UDBs. The corresponding internal controller can be further configured to, after performing the error correction operation, exchange the corresponding portion of one or more UDBs and a second portion of auxiliary data from the corresponding memory cell via one or more data pins (e.g., DQ and DMI pins) of the corresponding memory cell.

[0095] In some embodiments, the corresponding internal controller may be further configured to exchange the results of error correction operations. In some embodiments, the error correction information may correspond to first error correction information. In this example, the corresponding internal controller may be further configured to exchange second error correction information corresponding to corresponding portions of one or more UDBs via one or more data pins of the corresponding memory cell (e.g., in...). Figure 1 , 2A (Generated at memory controller 100 and / or 200 as described in 2B). The corresponding internal controller can be configured to exchange second error correction information via one or more data pins of the corresponding memory cell without exchanging first error correction information.

[0096] In some embodiments, each memory cell may correspond to a memory die. Each of the plurality of internal controllers may correspond to an on-die controller located on the same memory die as the corresponding memory cell array.

[0097] In some embodiments, the corresponding internal controller may be configured to exchange corresponding portions of one or more UDBs via multiple data input / output (DQ) pins of one or more data pins of the corresponding memory cell. The corresponding internal controller may be further configured to exchange auxiliary data via one or more data mask inversion (DMI) pins of one or more data pins of the corresponding memory cell.

[0098] In some embodiments, the second portion of the auxiliary data may further include cyclic redundancy check (CRC) data (e.g., in...). Figure 2A and 2B The corresponding portion of the auxiliary data (the CRC data generated at CRC encoder 213-1 as described in the diagram) is used to indicate one or more bit errors in one or more UDBs. In some embodiments, the second portion of the auxiliary data may further include Cyclic Redundancy Check (CRC) data (e.g., in...). Figure 2A The corresponding portion of the auxiliary data (CRC data generated at CRC encoder 211-1 as described in the diagram) is used to indicate one or more bit errors in the corresponding UDBs. In some embodiments, the second portion of the auxiliary data may further include authentication data (e.g., MAC data generated at authentication encoder 218-1) to verify the data integrity and authenticity of one or more UDBs.

[0099] Figure 4A This is a block diagram of memory dies corresponding to several data protection channels (e.g., RAID channels) according to several embodiments of the present disclosure. The diagram illustrates nine memory dies 427-1, ..., 427-9 that may be similar to memory die 227.

[0100] Each memory die 427 may include several data pins of different types, such as DQ pins and DMI pins. For each memory die 427, data can be exchanged (e.g., transferred back and forth between memory dies 427) at a rate of Y bits per tick via the DMI pin and at a rate of Z bits per tick via the DQ pin within a burst length of X bits. In one example, each memory die 427 may include eight DQ pins and one DMI pin, such that data is transmitted at a rate of 8 bits per tick via the eight DQ pins and at a rate of 1 bit per tick via the one DMI pin within a burst length of 16 bits or 32 bits.

[0101] Although the embodiments are not limited to this, the two memory dies 427 may correspond to Figure 1 The channels 125 and / or 225 (e.g., their channel widths) described in section 2 are as follows. For example, memory dies 427-1 and 427-2 may correspond to one channel 125 and 225; memory dies 427-3 and 427-4 may correspond to another channel 125 and 225; memory dies 427-5 and 427-6 may correspond to different channels 125 and 225; memory dies 427-7 and 427-8 may correspond to different channels 125 and 225; and memory die 427-9 may correspond to a different channel 125 and 225 (half of it). Therefore, each channel 125 and 225 may be 2*Y bit wide (e.g., 16 bit wide).

[0102] Memory dies 427-1, ..., 427-9 may correspond to memory devices (e.g., Figure 1The same memory columns of memory devices 126 and / or 226 described in section 2. Therefore, memory dies 427-1, ..., 427-9 can be accessed simultaneously (e.g., "substantially simultaneously" as defined herein).

[0103] The diagram illustrates eight memory dies 427-1, ..., 427-8 (of RAID channel 429) that can store UDBs 423-1 and 423-2 (which may correspond to MTBs), but the embodiment is not limited to a specific number of memory dies that can be stored in a single UDB. For example, UDB 423-1 can be stored in memory dies 427-1, ..., 427-4, while UDB 423-2 can be stored in memory dies 427-5 to 427-8, as... Figure 4A The following explanation is provided. In a specific instance, given that each UDB is 64 bytes, each memory die 427 can be configured to store 16 bytes (transmittable within a 16-bit burst length), and UDB 423 (423-1 or 423-2) can be 64 bytes. UDB 423 can be swapped via the DQ pin of the corresponding memory die 427.

[0104] Each memory die (e.g., memory die 427) was not in Figure 4B This describes all of it and may further include it. Figure 4B Other parts not described herein. For example, each memory die 427 may be 32 bytes in size, with 16 bytes exhausted for UDB 423-1 or 423-2 and another 16 bytes exhausted for another UDB corresponding to an MTB different from UDB 423-1 or 423-2. In this example, data stored in memory die 427 can be fully transferred (within a 32-bit burst length) to memory controller 200 (in response to a host read command), and transferred UDBs not corresponding to a host read command can be discarded at memory controller 200.

[0105] Memory dies 427-1, ..., 427-8 may further store and transmit auxiliary data (e.g., 10 bits) via one or more DMI pins. For example, each memory die 427 may be configured to store 10 bits of auxiliary data. The auxiliary data that can be transmitted from memory dies 427-1, ..., 427-8 via DMI pins within an X-bit burst length (e.g., within a 16-bit burst length) may include (e.g., 28 bits) authentication data (e.g., MAC generated at authentication encoder 218-1 illustrated in FIG. 2), (e.g., 45 bits) error detection data (e.g., including 7 bits of FCRC data generated at CRC encoder 211-1 and 31 bits of CRC data generated at CRC encoder 213-1 for each UDB 423), (e.g., 1 bit) TEE data, and (e.g., 6 bits) metadata (e.g., 3 bits per UDB 423), totaling 80 bits of auxiliary data. If the link ECC mechanism is enabled, requiring link ECC data to also be transmitted via the DMI pin, then the memory auxiliary data that can be transmitted from memory dies 427-1, ..., 427-8 via the DMI pin within an X-bit burst length (e.g., within a 16-bit burst length) may include (e.g., 28 bits) authentication data (e.g., the MAC generated at authentication encoder 218-1 illustrated in Figure 2), (e.g., 29 bits) error detection data (in... Figure 2B The auxiliary data consists of CRC data generated at CRC encoder 213-1 as described in the specification, TEE data (e.g., 1 bit), and metadata (e.g., 6 bits) (e.g., 3 bits per UDB 423), totaling 64 bits.

[0106] The figure further illustrates a memory die 427-9 in which a PDB 439 containing RAID parity data (e.g., generated at RAID encoder 214-1) can be stored, but the embodiment is not limited to a specific number of memory dies in which the PDB can be stored.

[0107] Data stored in memory dies 427-1, ..., 427-9 (e.g., PDB and MTB containing UDB) can also be used in memory devices (e.g. Figure 1 and the memory devices 126 and / or 226 described in section 2) and the memory controller (e.g. Figure 1 The data transfer unit between the memory controllers 100 and / or 200 described in section 2. For example, UDB 423, auxiliary data 437, and PDB 439 may be transferred together in response to a host read command to access one of UDB 423.

[0108] Memory dies 427-1, ..., 427-9 may correspond to data protection channels, such as RAID channel 429; therefore, RAID channel 429 may be 9*Y bit wide (corresponding to nine memory dies 427) and an "8+1" RAID channel, indicating that eight memory dies are configured for one or more UDBs and one memory die is configured for one or more PDBs, resulting in an overhead of 12.5% ​​(e.g., 1 / 8 = 12.5%). A memory system (e.g., memory system 101) may contain several RAID channels (e.g., each corresponding to RAID channel 429).

[0109] Figure 4B This is a block diagram 450 illustrating a locked RAID process for data protection of a subset of UDB 423 according to several embodiments of the present disclosure. Figure 4B UDB 423 as described in the document can be similar to Figure 4A UDB 423 as described in the document.

[0110] Figure 4B Similar to Figure 3B It's just for those who have Figure 4B The eight subsets 454-1 described in the text Figure 4B The subset "A" shown in the text), 454-2 ( Figure 4B The subset "B" shown in the text), 454-3 ( Figure 4B The subset "C" shown in the text), 454-4 ( Figure 4B The subset “D” shown in the text), 454-5 ( Figure 4B The subset “E” shown in the text), 454-6 ( Figure 4B The subset “F” shown in the text), 454-7 ( Figure 4B The subset “G” shown in the text) and 454-8 ( Figure 4B The subset "H" shown in the diagram performs RAID operation 452 on UDB 423. Subsets 454-1, ..., 454-8 can correspond to PDBs that can be used (e.g., ... Figure 4A RAID channels that perform error recovery (e.g., PDB 439 as described in the document) Figure 4A The memory die (e.g., RAID channel 429 as described in the text) Figure 4A The memory dies described in the document are 427-1, ..., 427-8.

[0111] Figure 4B Illustrate an example case where the subset "D" contains elements that cause problems in the CRC decoder (e.g., ...). Figure 2A One or more errors where the CRC check performed at the CRC decoder 213-2) described in 2B (e.g., alternatively referred to as an error detection operation) fails. Similar to the combination Figure 3BThe described RAID operations 352 and 452 can also be performed in various ways in conjunction with one or more CRC checks. In one instance, RAID operation 452 is performed sequentially with the corresponding CRC checks performed after each RAID operation. For example, RAID operation 452 can be performed in the sequence 452-1 to 452-4, with four CRC checks performed after each RAID operation 452-1, 452-2, 452-3, and 452-4. Since the CRC check performed after RAID operation 452-4 will show "pass" (e.g., no errors in subset 454), the RAID process is complete and there is no need to perform RAID operations 452-5, ..., 452-8. In another instance, RAID operation 452 is performed in parallel on subsets 454-1, ..., 454-8 (e.g., copies thereof). In this instance, a copy of UDB 423 (RAID operation 452-4 performed) that has passed the CRC check for RAID operation 452 will be further sent to a security decoder (e.g., ...). Figure 2A and / or the security decoder 217-2 described in 2B).

[0112] In another non-limiting instance, the device (e.g.) Figure 1 , 2A The memory devices 126 and / or 226 described in 2B may include multiple memory cells (e.g., Figure 2A , 2B The memory dies 227, 327 and / or 427 described in sections 3 and 4 are configured to store error detection information corresponding to one or more user data blocks (UDBs) (e.g., in...). Figure 2A and 2B The CRC data generated at CRC encoder 213-1 as described in the diagram. Each memory cell in a plurality of memory cells may contain an array of memory cells (e.g., Figure 2A and 2B The array 220 described herein is configured to store corresponding portions of one or more UDBs (e.g., UDBs 323 and 423 illustrated in Figures 3 and 4). The memory cell array is configured to store auxiliary data, which includes corresponding first error correction information (e.g., in…). Figure 2A and 2B The ECC data generated on the die at the corresponding internal controller 228 as described in the specification) and error detection information corresponding to the corresponding parts of one or more UDBs (e.g., in Figure 2A and 2B The corresponding portion of the CRC data generated at CRC encoders 211-1 and / or 213-1 as described herein. Each of the plurality of memory cells may further contain an internal controller (e.g., Figure 2A and 2BThe internal controller 228 described herein is configured to generate corresponding first error correction information based on corresponding portions of one or more UDBs. The device may further include a memory controller (e.g., [missing information]) communicatively coupled to multiple memory cells. Figure 1 , 2A And the memory controllers 100 and / or 200 described in 2B). The memory controllers can be configured to cause a first memory device (e.g., ...) of a plurality of memory devices to... Figure 1 , 2A In response to receiving a host read command to access the first memory device, a respective internal controller of the memory device 126 and / or 226 described in 2B performs an error correction operation (e.g., ECC operation) on a corresponding portion of one or more UDBs using corresponding first error correction information. The respective internal controller may be further configured to transmit the corresponding portion of one or more UDBs and auxiliary data containing the corresponding error detection information to the memory controller after the error correction operation is performed.

[0113] In some embodiments, the plurality of memory cells may further include: a plurality of first memory cells (e.g., memory dies 327-1, ..., 327-4 and / or 427-1, ..., 427-8 illustrated in Figures 3 and 4) configured to store one or more UDBs; and one or more second memory cells configured to store independent disk redundant array (RAID) parity data (e.g., PDBs 339 and / or 439 illustrated in Figures 3 and 4) corresponding to respective portions of the one or more UDBs. In this example, the memory controller may be configured to perform an error detection operation (e.g., CRC check) on the one or more UDBs using error detection information. The memory controller may be further configured to perform a RAID operation on the respective portions of the one or more UDBs in response to an error detection operation indicating one or more bit errors in the respective portions of the one or more UDBs.

[0114] In some embodiments, the memory cell array may be further configured to store corresponding second error correction information generated at the memory controller and corresponding to corresponding portions of one or more UDBs. The memory controller may be configured to cause a corresponding internal controller to transmit the second correction information to the memory controller. In some embodiments, the memory controller may be configured to perform an error correction operation (e.g., ECC operation) on corresponding portions of one or more UDBs using the corresponding second error correction information to correct one or more bit errors on the corresponding portions of one or more UDBs.

[0115] In some embodiments, the memory controller may be configured to perform an error detection operation (e.g., CRC check) on a corresponding portion of one or more UDBs using error detection information. The memory controller may be further configured to cause a corresponding internal controller to retransmit the corresponding portion of one or more UDBs to the memory controller several times in response to an error detection operation indicating a bit error in one or more bits of one or more UDBs.

[0116] Continuing this example, the memory controller can be configured to correct the amount of bit errors in one or more UDBs based on a data pattern comparison between copies of one or more UDBs transmitted during several retransmissions, in response to a second error correction message and the retransmission of corresponding portions of one or more UDBs. In this example, the memory controller can be configured to correct the amount of errors based on a majority data pattern match.

[0117] Continuing this example, the memory controller can be configured to perform error detection operations on corresponding portions of one or more UDBs using error detection information. The memory controller can be further configured to perform RAID operations on corresponding portions of one or more UDBs in response to an error detection operation indicating a bit error in one or more bits within those portions.

[0118] Figure 5 This is a flowchart of a method 560 for performing ECC operations at an internal controller according to several embodiments of the present disclosure. Method 560 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 560 is performed by… Figure 2A and 2B The internal controller 228 described in the document or Figure 1 , 2A The memory controllers 100 and / or 200 described in sections 2B and 2B, respectively, are executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0119] At position 561, the first error correction information can be used (e.g., in...). Figure 2A and 2B The on-die ECC data generated at the internal controller 228 as described in the document and in multiple memory cells (e.g. Figure 2A , 2BBefore exchanging corresponding portions of one or more User Data Blocks (UDBs) at corresponding memory cells in the memory dies 227, 327, and / or 427 described in Figures 3 and 4, an error correction operation (e.g., ECC operation) is performed on the corresponding portions of one or more UDBs (e.g., UDBs 323 and 423 described in Figures 3 and 4) to correct one or more bit errors on the corresponding portions of the one or more UDBs. Each of the multiple memory cells may be configured to store the corresponding portions of one or more UDBs. Each memory cell may be further configured to store auxiliary data, including first error correction information and error detection information (e.g., in…). Figure 2A and 2B The CRC data generated at CRC encoders 211-1 and / or 213-1 as described herein is used to indicate one or more bit errors in one or more UDBs.

[0120] At point 563, corresponding portions of one or more UDBs and a portion of auxiliary data containing error detection information may be exchanged after an error correction operation is performed. In some embodiments, second error correction information may be further exchanged (e.g., in...). Figure 1 , 2A The portion of auxiliary data includes the ECC data generated at memory controller 100 and / or 200 as described in 2B.

[0121] In some embodiments, several bits corresponding to the result of an error correction operation performed on corresponding portions of one or more UDBs may be further swapped. In some embodiments, corresponding portions of one or more UDBs and a first portion of auxiliary data may be swapped without swapping the first portion of the auxiliary data.

[0122] In some embodiments, corresponding portions of one or more UDBs can be swapped via one or more Data Input / Output (DQ) pins. The swapping of auxiliary data portions can occur simultaneously with the swapping of corresponding portions of one or more UDBs via one or more Data Mask Inversion (DMI) pins.

[0123] Figure 6 This is a flowchart of a method 670 for performing ECC operations at an internal controller according to several embodiments of the present disclosure. Method 670 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 670 is performed by… Figure 2A and 2B The internal controller 228 described in the document or Figure 1 , 2AThe memory controllers 100 and / or 200 described in sections 2B and 2B, respectively, are executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0124] At 671, access from multiple memory cells (e.g.,) can be received from the memory controller. Figure 2A , 2B The memory cells are configured to store read commands for user data blocks (UDBs) (e.g., UDBs 323 and 423 illustrated in Figures 3 and 4) of the memory dies 227, 327 and / or 427 as described in Figures 3 and 4. Each memory cell is configured to store a corresponding portion of one or more user data blocks (UDBs) (e.g., UDBs 323 and 423 illustrated in Figures 3 and 4). Each memory cell may be further configured to store auxiliary data, which includes corresponding first error correction information (e.g., in...). Figure 2A and 2B The ECC data generated on the die at the corresponding internal controller 228 as described in the specification) and the corresponding error detection information corresponding to the corresponding parts of one or more UDBs (e.g., in Figure 2A and 2B (The CRC data generated at CRC encoders 211-1 and / or 213-1 as described in the document).

[0125] In some embodiments, the auxiliary data may further include second error correction information generated at the memory controller (e.g., in...). Figure 1 , 2A (and the link ECC data generated at memory controller 100 and / or 200 as described in 2B). In this example, the second error correction information can be used to perform an error correction operation (e.g., link ECC operation) at the memory controller to correct one or more bits on the corresponding portions of one or more UDBs.

[0126] At 673, an error correction operation (e.g., on-die ECC operation) can be performed at the corresponding memory cell in one of the multiple memory cells and before the corresponding portion of one or more UDBs is transmitted.

[0127] At point 675, corresponding portions of one or more UDBs and auxiliary data containing corresponding error detection information may be transmitted to the memory controller. In some embodiments, the corresponding error detection information may be transmitted to the memory controller, while error correction information may not be transmitted to the memory controller.

[0128] In some embodiments, corresponding portions of one or more UDBs may be transmitted via one or more data input / output (DQ) pins. Furthermore, auxiliary data containing corresponding error detection information may be transmitted via one or more data mask inversion (DMI) pins simultaneously with the transmission of corresponding portions of the one or more UDBs.

[0129] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon review of the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications in which the foregoing structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their authorized equivalents.

[0130] In the foregoing detailed embodiments, some features are grouped together in a single embodiment for the purpose of simplifying this disclosure. The method of this disclosure should not be interpreted as reflecting an intention that the disclosed embodiments must use more features than are expressly recited in each claim. In fact, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is considered an independent, separate embodiment.

Claims

1. An apparatus for on-die error correction code (ECC) operation, comprising: A plurality of memory cells, each of the plurality of memory cells further comprising: The corresponding memory cell array, configured to store: The corresponding portions of one or more User Data Blocks (UDBs); and Auxiliary data corresponding to the corresponding portions of the one or more UDBs, wherein a first portion of the auxiliary data includes error correction information corresponding to the corresponding portions of the one or more UDBs; and A corresponding internal controller, configured to respond to receiving a command to access the corresponding portion of the one or more UDBs: The error correction information is used to perform error correction operations on the corresponding portions of the one or more UDBs to correct one or more bit errors on the corresponding portions of the one or more UDBs; and After performing the error correction operation, and exchanging the corresponding portions of the one or more UDBs and the second portion of the auxiliary data from the corresponding memory cells via one or more data pins of the corresponding memory cells without exchanging the error correction information, wherein the second portion of the auxiliary data further includes: The corresponding portion of the Cyclic Redundancy Check (CRC) data is used to indicate one or more bit errors in the corresponding UDB of the one or more UDBs.

2. The device according to claim 1, wherein: The error correction information corresponds to the first error correction information; and The corresponding internal controller is further configured to exchange second error correction information corresponding to the corresponding portion of the one or more UDBs via the one or more data pins of the corresponding memory unit.

3. The device of claim 2, wherein the respective internal controller is configured to exchange the second error correction information via the one or more data pins of the respective memory unit without exchanging the first error correction information.

4. The device according to claim 1, wherein: Each memory cell corresponds to a memory die; and Each of the plurality of internal controllers corresponds to an on-chip controller located on the same memory die as the corresponding memory cell array.

5. The device according to claim 1, wherein the corresponding internal controller is configured to: The corresponding portions of the one or more UDBs are exchanged via multiple data input / output (DQ) pins of the one or more data pins of the corresponding memory cells; and The auxiliary data is exchanged via one or more data mask inversion DMI pins of the corresponding memory cell.

6. The device according to claim 1, wherein the second portion of the auxiliary data further includes authentication data to verify the data integrity and authenticity of the one or more UDBs.

7. A method for on-chip error correction code (ECC) operation, comprising: Before using first error correction information and exchanging corresponding portions of one or more User Data Blocks (UDBs) at corresponding memory cells in a plurality of memory cells, an error correction operation is performed on the corresponding portions of one or more UDBs to correct one or more bit errors on the corresponding portions of one or more UDBs, wherein each of the plurality of memory cells is configured to store: The corresponding portions of one or more UDBs; and Auxiliary data, including the first error correction information and error detection information, to indicate one or more bit errors in the one or more UDBs; and After performing the error correction operation, the corresponding portions of one or more UDBs and the portions of the auxiliary data containing the error detection information are exchanged without exchanging the first error correction information.

8. The method of claim 7, further comprising exchanging second error correction information as part of said portion of the auxiliary data.

9. The method of claim 7, further comprising swapping a number of bits corresponding to the result of the error correction operation performed on the respective portions of one or more UDBs.

10. The method of claim 8, further comprising exchanging the corresponding portions of one or more UDBs and the second error correction information.

11. The method of claim 7, further comprising: The corresponding portions of the one or more UDBs are exchanged via one or more data input / output DQ pins; and While exchanging the corresponding portions of the one or more UDBs, the portions of the auxiliary data are exchanged via one or more data mask inversion DMI pins.

12. An apparatus for on-die error correction code (ECC) operation, comprising: A plurality of memory units configured to store error detection information corresponding to one or more user data blocks (UDBs), each of the plurality of memory units comprising: A memory cell array configured to store: The corresponding portions of the one or more UDBs; and Auxiliary data, which includes corresponding first error correction information and corresponding portions of the error detection information; and An internal controller configured to generate the corresponding first error correction information based on the corresponding portions of the one or more UDBs; and A memory controller communicatively coupled to the plurality of memory cells, each of the plurality of memory devices including the plurality of memory cells, and the memory controller being configured such that a respective internal controller of a plurality of respective internal controllers of a first memory device responds to receiving a host read command to access the first memory device: The error correction operation is performed on the corresponding portions of the one or more UDBs using the corresponding first error correction information; and After the error correction operation is performed, the corresponding portions of the one or more UDBs and the auxiliary data containing the error detection information are transmitted to the memory controller without transmitting the first error correction information.

13. The device of claim 12, wherein the plurality of memory cells further comprises: A plurality of first memory units configured to store the one or more UDBs; and One or more second memory units configured to store parity data of independent disk redundant array RAID corresponding to the respective portions of the one or more UDBs.

14. The device of claim 13, wherein the memory controller is configured to: Perform error detection operations on one or more UDBs using the error detection information; and In response to the error detection operation indicating a bit error in a corresponding portion of the one or more UDBs, a RAID operation is performed on the corresponding portion of the one or more UDBs.

15. The device according to claim 12, wherein: The memory cell array is further configured to store corresponding second error correction information generated at the memory controller and corresponding to the corresponding portions of the one or more UDBs; and The memory controller is configured such that the corresponding internal controller transmits the second error correction information to the memory controller.

16. The device of claim 15, wherein the memory controller is configured to perform an error correction operation on the corresponding portions of the one or more UDBs using the corresponding second error correction information to correct one or more bit errors on the corresponding portions of the one or more UDBs.

17. The device of claim 15, wherein the memory controller is configured to: The error detection information is used to perform error detection operations on the corresponding portions of the one or more UDBs; and In response to the error detection operation indicating a bit error in one or more of the one or more UDBs, the corresponding internal controller retransmits the corresponding portion of the one or more UDBs to the memory controller several times.

18. The apparatus of claim 17, wherein the memory controller is configured to correct the amount of bit error in the one or more UDBs based on a data pattern comparison between copies of the one or more UDBs transmitted during the retransmissions in response to the second error correction information and the retransmission of the corresponding portions of the one or more UDBs.

19. The device of claim 18, wherein the memory controller is configured to: The error amount is corrected based on the majority of the data pattern matching described; The error detection information is used to perform error detection operations on the corresponding portions of the one or more UDBs; and In response to the error detection operation indicating a bit error in a corresponding portion of the one or more UDBs, a RAID operation is performed on the corresponding portion of the one or more UDBs.

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