A multi-processor shared memory method and system

Abstract

The application provides a multi-processor shared memory method and system; the multi-processor shared memory method comprises the following steps: obtaining a shared arbitration line idle time, and sequentially outputting a low voltage part and a high voltage part of a current processor address according to the shared arbitration line idle time; then judging whether the high voltage part can pull up the shared arbitration line or not; when the high voltage part can pull up the shared arbitration line, writing preset data into the shared memory through a shared control line. The application uses the shared memory, so that multiple processors can share the same storage device, and the cost of the system can be reduced; using the shared memory can simplify the complexity of data exchange; the processors can write data into the shared memory through the shared control line, and data does not need to be transported multiple times; since the shared memory can be accessed by multiple processors, the processors can directly read or write data into the shared memory, so that the data access efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of shared storage technology, and in particular to a multiprocessor shared storage method and system. Background Technology

[0002] Existing multiprocessor or sensor systems typically have each processor with a separate storage device to record data and exchange data via a common bus.

[0003] Attaching storage devices to each processor in the system increases costs and requires multiple data transfers for data exchange; moreover, general-purpose buses typically require a lot of I / O, such as I2C requiring 2 I / O and SPI requiring 4 I / O. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a multiprocessor shared storage method and system that can reduce costs and improve data access efficiency.

[0005] Specifically, this application provides a multiprocessor shared memory method, including the following steps: S100: Obtain the shared arbitration line idle time, and output the low-level part and high-level part of the current processor address in sequence according to the shared arbitration line idle time.

[0006] S200: Determine whether the high-level portion can pull the shared arbitration line high, so that when the high-level portion can pull the shared arbitration line high, pull the shared arbitration line low and write the preset data into the shared memory through the shared control line.

[0007] In the above technical solution, multiple processors can share the same storage device through shared memory, which can reduce the system cost compared to each processor having its own separate storage device. Using shared memory can simplify the complexity of data exchange, and processors can write data to shared memory through shared control lines without having to move data multiple times. Since shared memory can be accessed by multiple processors, processors can directly read or write data to shared memory, thereby improving data access efficiency.

[0008] The step S100, which involves sequentially outputting the low-level and high-level portions of the current processor address based on the shared arbitration line idle time, specifically includes: S101: Determine whether the idle time of the shared arbitration line is greater than or equal to one arbitration space. If so, output the low level part of the current processor address to make the shared arbitration line non-idle, and output the high level part of the current processor address, and proceed to step S200; otherwise, execute step S102.

[0009] S102: Continue to wait for at least one arbitration space and return to step S100.

[0010] In the above technical solution, by judging the length of the shared arbitration line idle time, it can be determined whether subsequent sharing operations can be performed. This avoids performing sharing operations when the shared arbitration line is busy, thereby reducing data conflicts and errors. Only when the shared arbitration line idle time is greater than or equal to one arbitration space will the high-level portion of the current processor address be output, ensuring output accuracy and avoiding erroneous output and data corruption. The waiting mechanism in step S102 ensures that the process returns to step S100 when the arbitration line is idle, ensuring the reliability and stability of the output. Furthermore, the judgment conditions in step S101 can be set according to specific needs. By adjusting the size of the arbitration space, the idle time of the shared arbitration line can be flexibly controlled. This allows for dynamic adjustment based on system load and real-time requirements to achieve the best output effect.

[0011] Step S200 specifically includes: S201: Determine whether the high-level part can pull the shared arbitration line high. If it can, the right to use the shared memory can be obtained, and proceed to step S202; otherwise, proceed to step S102.

[0012] S202: Pull the shared arbitration line low while keeping it in a low state, then initialize the shared control line, and use the shared control line to write preset data into the shared memory.

[0013] In the above technical solution, step S102 serves as an exception handling mechanism. When the high-level portion fails to pull the shared arbitration line high, there may be hardware or other problems. Proceeding to step S102 allows for additional waiting and processing to attempt to resolve the issue or take appropriate measures to avoid system failure. Proceeding to step S102 also prevents the system from entering an infinite loop or error state. By waiting for at least one arbitration space and re-executing S100, the system has time to recover, avoiding unnecessary data conflicts, race conditions, or other situations that could lead to system crashes.

[0014] Furthermore, step S102 allows for re-waiting for the arbitration space to occur, which means we can adapt the system's workload and performance requirements according to actual conditions and needs; by adjusting the waiting time, we can achieve optimal results under different environments and conditions.

[0015] Furthermore, the shared arbitration line can be raised to request access to the shared memory. This ensures that access to the shared memory is granted before data is written. After gaining access, the shared arbitration line needs to be pulled low and maintained in this state. This prevents other processors or devices from accessing the shared memory simultaneously, thus preventing data conflicts or contention. After gaining access, the shared control line needs to be initialized. This may include setting read / write control signals, address signals, etc. At the same time, it is necessary to ensure that the shared control line is correctly connected to the shared memory and that the signal transmission path is open so that data read and write operations can proceed normally.

[0016] Following step S200, the method further includes: Set the shared control line to a high impedance state and pull the shared arbitration line high so that the shared arbitration line returns to an idle state.

[0017] In the above technical solution, after the initialization and connection of the shared memory are completed, the shared control line is set to a high impedance state to allow other processors or devices to access the shared memory. At the same time, the high-level part of the shared arbitration line is pulled high to notify other processors or devices that the right to use the memory has been released.

[0018] When outputting the high-level portion of multiple processor addresses simultaneously, it also includes: Obtain the address of the processor with the highest priority. If the address of the processor with the highest priority is in a low-level state, the arbitration is determined to have failed, and proceed to step S102; otherwise, proceed to step S200.

[0019] In the above technical solution, by obtaining the address of the processor with the highest priority, the access rights of the shared memory can be flexibly controlled, and it can be ensured that the high-priority processor can obtain access rights first. This helps to meet the access needs of different processors in the system and improve the performance and efficiency of the system. If the processor address with the highest priority fails to successfully pull the shared arbitration line high, it indicates that an abnormal situation has occurred in the arbitration process. By transferring to step S102 for abnormal handling, the system can have the opportunity to wait for the arbitration space again and process it, so as to ensure the correctness of the data and the stability of the system. By checking the status of the processor address with the highest priority, it can be determined whether the arbitration process is successful. If the processor address is in a low level state, that is, the arbitration has failed, and transferring to step S102 can avoid erroneous operation or data conflict and enhance the reliability of the system.

[0020] This also includes partitioning the processor.

[0021] In the above technical solution, partitioning allows for better management of system resources and optimization for different tasks.

[0022] Based on the same concept, this application also provides a multiprocessor shared memory system, the system comprising: Acquisition module: Used to obtain the idle time of the shared arbitration line.

[0023] Output module: Used to sequentially output the low-level part and high-level part of the current processor address or perform waiting work according to the idle time of the shared arbitration line.

[0024] Judgment module: Used to determine whether the high-level part can pull the shared arbitration line high.

[0025] First processing module: used to lower the shared arbitration line according to the judgment result of the judgment module and write the preset data into the shared memory or transfer it to the acquisition module through the shared control line.

[0026] In the above technical solution, by acquiring the idle time of the shared arbitration line through the acquisition module, the system can achieve efficient access to the shared memory. When the shared arbitration line is idle, it can immediately output the low-level part and high-level part of the current processor address in sequence, thereby reducing waiting time and improving the utilization rate of the shared memory and system performance. The judgment module is responsible for determining whether the high-level part can pull the shared arbitration line high. This can avoid arbitration conflicts, ensure the correct access order of the shared memory and data consistency. Timely judgment can reduce the system's waiting time and latency, and improve the real-time performance and responsiveness of the data. The first processing module can flexibly write the preset data into the shared memory or transfer it to the acquisition module based on the judgment result of the judgment module. This flexible processing method allows the system to make decisions and adjust the processing logic according to the actual situation, thereby avoiding unnecessary data conflicts or competition and improving the reliability and stability of the system.

[0027] Furthermore, by using shared memory, multiple processors can share the same storage device, which can reduce system costs compared to each processor having its own separate storage device.

[0028] The output module includes: Judgment unit: used to determine whether the idle time of the shared arbitration line is greater than or equal to one arbitration space.

[0029] Output unit: When the idle time of the shared arbitration line is greater than or equal to one arbitration space, it sequentially outputs the low-level part and high-level part of the current processor address and then transfers the input to the judgment module.

[0030] Waiting unit: Used to continue waiting for at least one arbitration space when the idle time of the shared arbitration line is less than one arbitration space or a preset condition, and then return to the acquisition module.

[0031] In the above technical solution, by judging the length of the shared arbitration line idle time by the judgment unit, it can be determined whether subsequent sharing operations can be performed. This avoids performing sharing operations when the shared arbitration line is busy, thereby reducing data conflicts and errors. The output unit will only output the high-level part of the current processor address when the shared arbitration line idle time is greater than or equal to one arbitration space. This ensures the accuracy of the output and avoids erroneous output and data corruption. The waiting unit is used to continue waiting for at least one arbitration space when the shared arbitration line idle time is less than one arbitration space. This ensures that there is enough time to ensure that the shared arbitration line is idle, avoids arbitration conflicts and competition, and at the same time ensures the stability of the system and the correctness of the data.

[0032] The first processing module includes: First processing unit: When the judgment result of the judgment module is that the high level part can pull the shared arbitration line high, it obtains the right to use the shared memory, pulls the shared arbitration line low, and keeps the shared arbitration line in a low state, and initializes the shared control line.

[0033] The second processing unit is used to transfer to the waiting unit when the judgment result of the judgment module is that the high-level part cannot be pulled high on the shared arbitration line.

[0034] In the above technical solution, the first processing module ensures that the processor can obtain exclusive access to the shared memory before performing subsequent operations. This can avoid conflicts and data errors caused by multiple processors accessing the shared memory at the same time. When the high-level part cannot pull the shared arbitration line high, there may be hardware or other problems. The waiting unit can perform additional waiting and processing to try to solve the problem or take appropriate measures to avoid system failure.

[0035] The system also includes: The second processing module is used to set the shared control line to a high impedance state and pull the shared arbitration line high.

[0036] The third processing module is used to obtain the processor address with the first priority when multiple processor addresses are output at the same time, and to transfer to the waiting unit or the judgment module according to the level state of the processor address with the first priority.

[0037] Partitioning module: Used to partition the processor.

[0038] In the above technical solution, the second processing module sets the shared control line to a high impedance state and pulls the shared arbitration line high. This operation ensures the stability and reliability of the arbitration line and the reasonable access to the shared memory. The third processing module efficiently obtains the processor address and judges based on priority, enabling the system to better manage the access order of the processor and improve the system's performance and efficiency. Through partitioning, the system's resources can be better managed and optimized for different tasks.

[0039] Compared with the prior art, the beneficial effects of this application are as follows: This application first obtains the idle time of the shared arbitration line, and then outputs the low-level part and the high-level part of the current processor address in sequence according to the idle time of the shared arbitration line; then it determines whether the high-level part can pull the shared arbitration line high, so that when the high-level part can pull the shared arbitration line high, the preset data is written to the shared memory through the shared control line.

[0040] This application utilizes shared memory, enabling multiple processors to share the same storage device, thereby reducing system costs. Using shared memory simplifies data exchange complexity, allowing processors to write data to shared memory via shared control lines without requiring multiple data transfers. Since shared memory can be accessed by multiple processors, processors can directly read or write data to it, thus improving data access efficiency.

[0041] This application addresses the technical problem in the prior art where each processor is separately mounted with a storage device and data is exchanged via a general-purpose bus, resulting in high costs and requiring multiple data transfers, which increases the complexity of data exchange. Attached Figure Description

[0042] Figure 1 This is a flowchart of the multiprocessor shared memory method described in this application.

[0043] Figure 2 for Figure 1 The flowchart describes the method of sequentially outputting the low-level and high-level portions of the current processor address.

[0044] Figure 3 for Figure 1 The flowchart describes the method for writing preset data into a shared memory.

[0045] Figure 4 for Figure 1 The system framework diagram of the multiprocessor shared memory method is shown below. Detailed Implementation

[0046] This application provides a multiprocessor shared memory method and system to solve the technical problem in the prior art where each processor is separately connected to a storage device and data is exchanged through a general-purpose bus, resulting in high costs and the need for multiple data transfers, which increases the complexity of data exchange.

[0047] The following describes in further detail a multiprocessor shared memory method and system of this application with reference to specific embodiments and accompanying drawings.

[0048] Example 1: Please see Figure 1 This application provides a multiprocessor shared memory method, including the following steps: S100: Obtain the shared arbitration line idle time, and output the low-level part and high-level part of the current processor address in sequence according to the shared arbitration line idle time.

[0049] In this embodiment, all processors using shared memory are connected together using a single I / O connection, and shared control line arbitration is performed to enable time-sharing use of the shared memory.

[0050] Among them, the shared control line refers to the control bus of existing EEPROM / NAND Flash / Nor Flash such as I2C / SPI / UART, and the shared arbitration line refers to an I / O that connects all processors.

[0051] Please see Figure 2 The step S100, which involves sequentially outputting the low-level and high-level portions of the current processor address based on the idle time of the shared arbitration line, specifically includes: S101: Determine whether the idle time of the shared arbitration line is greater than or equal to one arbitration space. If so, output the low level part of the current processor address to make the shared arbitration line non-idle, and output the high level part of the current processor address, and proceed to step S200; otherwise, execute step S102.

[0052] In this case, if the shared arbitration line continues to exceed one arbitration interval, it means that the shared memory is idle; otherwise, it means that the shared memory is busy.

[0053] It should be noted that all processors need to be assigned addresses. The number of address bits depends on the number of processors, and the bit time (code-named BitSlot) depends on the processing power of the processor system. The faster the processor, the smaller the bit slot. Taking a 4-bit address as an example, when the processors in the system include a central processor, subprocessor 1, subprocessor 2... subprocessor n, the address of the central processor is fixed at 0b0000, the address of subprocessor 1 is 0b0001, the address of subprocessor 2 is 0b0011, and so on.

[0054] S102: Continue to wait for at least one arbitration space and return to step S100.

[0055] In the above technical solution, by judging the length of the shared arbitration line idle time, it can be determined whether subsequent sharing operations can be performed. This avoids performing sharing operations when the shared arbitration line is busy, thereby reducing data conflicts and errors. Only when the shared arbitration line idle time is greater than or equal to one arbitration space will the high-level portion of the current processor address be output, ensuring output accuracy and avoiding erroneous output and data corruption. The waiting mechanism in step S102 ensures that the process returns to step S100 when the arbitration line is idle, ensuring the reliability and stability of the output. Furthermore, the judgment conditions in step S101 can be set according to specific needs. By adjusting the size of the arbitration space, the idle time of the shared arbitration line can be flexibly controlled. This allows for dynamic adjustment based on system load and real-time requirements to achieve the best output effect.

[0056] S200: Determine whether the high-level portion can pull the shared arbitration line high, so that when the high-level portion can pull the shared arbitration line high, pull the shared arbitration line low and write the preset data into the shared memory through the shared control line.

[0057] Please see Figure 3 Step S200 specifically includes: S201: Determine whether the high-level part can pull the shared arbitration line high. If it can, the right to use the shared memory can be obtained, and proceed to step S202; otherwise, proceed to step S102.

[0058] S202: Pull the shared arbitration line low while keeping it in a low state, then initialize the shared control line, and use the shared control line to write preset data into the shared memory.

[0059] In the above technical solution, step S102 serves as an exception handling mechanism. When the high-level portion fails to pull the shared arbitration line high, there may be hardware or other problems. Proceeding to step S102 allows for additional waiting and processing to attempt to resolve the issue or take appropriate measures to avoid system failure. Proceeding to step S102 also prevents the system from entering an infinite loop or error state. By waiting for at least one arbitration space and re-executing S100, the system has time to recover, avoiding unnecessary data conflicts, race conditions, or other situations that could lead to system crashes.

[0060] Furthermore, step S102 allows for re-waiting for the arbitration space to occur, which means we can adapt the system's workload and performance requirements according to actual conditions and needs; by adjusting the waiting time, we can achieve optimal results under different environments and conditions.

[0061] Furthermore, the shared arbitration line can be raised to request access to the shared memory. This ensures that access to the shared memory is granted before data is written. After gaining access, the shared arbitration line needs to be pulled low and maintained in this state. This prevents other processors or devices from accessing the shared memory simultaneously, thus preventing data conflicts or contention. After gaining access, the shared control line needs to be initialized. This may include setting read / write control signals, address signals, etc. At the same time, it is necessary to ensure that the shared control line is correctly connected to the shared memory and that the signal transmission path is open so that data read and write operations can proceed normally.

[0062] Following step S200, the method further includes: Set the shared control line to a high impedance state and pull the shared arbitration line high so that the shared arbitration line returns to an idle state.

[0063] It should be noted that when the shared arbitration line and shared control line are idle, all processors' corresponding I / O must be in high impedance mode; at the same time, if any I / O is pulled low, all other processors cannot pull it high (that is, I / O open-drain mode), so that any processor can freely pull it high or low.

[0064] In the above technical solution, after the initialization and connection of the shared memory are completed, the shared control line is set to a high impedance state to allow other processors or devices to access the shared memory. At the same time, the high-level part of the shared arbitration line is pulled high to notify other processors or devices that the right to use the memory has been released.

[0065] When outputting the high-level portion of multiple processor addresses simultaneously, it also includes: Obtain the address of the processor with the highest priority. If the address of the processor with the highest priority is in a low-level state, the arbitration is determined to have failed, and proceed to step S102; otherwise, proceed to step S200.

[0066] In this embodiment, the two processors may simultaneously determine that the shared arbitration line is high for more than one arbitration interval and simultaneously pull the shared arbitration line low. The subprocessor must determine whether it can pull the shared arbitration line high normally during the high-level interval. If it cannot pull it high, it means that the arbitration has failed and must be avoided, and wait for more than one arbitration interval to pass.

[0067] The processor may include one central processor and a preset number of sub-processors, the number of which is not limited here.

[0068] The processor address has a priority greater than 1 in the high-order bits (0), for example, 0b0011 has a lower priority than 0b0001; the central processor address is 0b0000, which has the highest priority. Because the high-order bits come first, 0b0011 first checks whether it can acquire the right to use the shared memory. At this time, 0b0001 is still in a low-level state, and 0b0011 cannot pull the shared arbitration line high, so the arbitration fails.

[0069] In the above technical solution, by obtaining the address of the processor with the highest priority, the access rights of the shared memory can be flexibly controlled, and it can be ensured that the high-priority processor can obtain access rights first. This helps to meet the access needs of different processors in the system and improve the performance and efficiency of the system. If the processor address with the highest priority fails to successfully pull the shared arbitration line high, it indicates that an abnormal situation has occurred in the arbitration process. By transferring to step S102 for abnormal handling, the system can have the opportunity to wait for the arbitration space again and process it, so as to ensure the correctness of the data and the stability of the system. By checking the status of the processor address with the highest priority, it can be determined whether the arbitration process is successful. If the processor address is in a low level state, that is, the arbitration has failed, and transferring to step S102 can avoid erroneous operation or data conflict and enhance the reliability of the system.

[0070] This also includes partitioning the processor.

[0071] In this embodiment, in order to make efficient use of shared memory, a range is partitioned for each processor.

[0072] The central processor and sub-processors may include shared space and private space; the shared space of the central processor includes the number of processors in the system, the address index of each processor range, and broadcast data space (for broadcasting); the shared space of the sub-processors includes self-describing data and request data (for communicating with the central processor); all private spaces are reserved for the corresponding processors to use themselves.

[0073] For products where processors do not need to communicate with each other, the shared space can be 0; for products where processors need to communicate with each other, the shared space is required for communication.

[0074] In the above technical solution, partitioning allows for better management of system resources and optimization for different tasks.

[0075] Example 2: Please see Figure 4 This application also provides a multiprocessor shared memory system, the system comprising: Acquisition module: Used to obtain the idle time of the shared arbitration line.

[0076] Output module: Used to sequentially output the low-level part and high-level part of the current processor address or perform waiting work according to the idle time of the shared arbitration line.

[0077] The output module includes: Judgment unit: used to determine whether the idle time of the shared arbitration line is greater than or equal to one arbitration space.

[0078] Output unit: When the idle time of the shared arbitration line is greater than or equal to one arbitration space, it sequentially outputs the low-level part and high-level part of the current processor address and then transfers the input to the judgment module.

[0079] Waiting unit: Used to continue waiting for at least one arbitration space when the idle time of the shared arbitration line is less than one arbitration space or a preset condition, and then return to the acquisition module.

[0080] In the above technical solution, by judging the length of the shared arbitration line idle time by the judgment unit, it can be determined whether subsequent sharing operations can be performed. This avoids performing sharing operations when the shared arbitration line is busy, thereby reducing data conflicts and errors. The output unit will only output the high-level part of the current processor address when the shared arbitration line idle time is greater than or equal to one arbitration space. This ensures the accuracy of the output and avoids erroneous output and data corruption. The waiting unit is used to continue waiting for at least one arbitration space when the shared arbitration line idle time is less than one arbitration space. This ensures that there is enough time to ensure that the shared arbitration line is idle, avoids arbitration conflicts and competition, and at the same time ensures the stability of the system and the correctness of the data.

[0081] Judgment module: Used to determine whether the high-level part can pull the shared arbitration line high.

[0082] First processing module: used to lower the shared arbitration line according to the judgment result of the judgment module and write the preset data into the shared memory or transfer it to the acquisition module through the shared control line.

[0083] The first processing module includes: First processing unit: When the judgment result of the judgment module is that the high level part can pull the shared arbitration line high, it obtains the right to use the shared memory, pulls the shared arbitration line low, and keeps the shared arbitration line in a low state, and initializes the shared control line.

[0084] The second processing unit is used to transfer to the waiting unit when the judgment result of the judgment module is that the high-level part cannot be pulled high on the shared arbitration line.

[0085] In the above technical solution, the first processing module ensures that the processor can obtain exclusive access to the shared memory before performing subsequent operations. This can avoid conflicts and data errors caused by multiple processors accessing the shared memory at the same time. When the high-level part cannot pull the shared arbitration line high, there may be hardware or other problems. The waiting unit can perform additional waiting and processing to try to solve the problem or take appropriate measures to avoid system failure.

[0086] Furthermore, by acquiring the idle time of the shared arbitration line through the acquisition module, the system can achieve efficient access to the shared memory. When the shared arbitration line is idle, it can immediately output the low and high levels of the current processor address in sequence, thereby reducing waiting time and improving the utilization of the shared memory and system performance. The judgment module is responsible for determining whether the high level can pull the shared arbitration line high. This can avoid arbitration conflicts, ensure the correct access order of the shared memory and data consistency, and timely judgment can reduce system waiting time and latency, and improve data real-time performance and responsiveness. Based on the judgment result of the judgment module, the first processing module can flexibly write the preset data into the shared memory or transfer it to the acquisition module. This flexible processing method allows the system to make decisions and adjust the processing logic according to the actual situation, thereby avoiding unnecessary data conflicts or competition and improving the reliability and stability of the system.

[0087] Furthermore, by using shared memory, multiple processors can share the same storage device, which can reduce system costs compared to each processor having its own separate storage device.

[0088] The system also includes: The second processing module is used to set the shared control line to a high impedance state and pull the shared arbitration line high.

[0089] The third processing module is used to obtain the processor address with the first priority when multiple processor addresses are output at the same time, and to transfer to the waiting unit or the judgment module according to the level state of the processor address with the first priority.

[0090] Partitioning module: Used to partition the processor.

[0091] In the above technical solution, the second processing module sets the shared control line to a high impedance state and pulls the shared arbitration line high. This operation ensures the stability and reliability of the arbitration line and the reasonable access to the shared memory. The third processing module efficiently obtains the processor address and judges based on priority, enabling the system to better manage the access order of the processor and improve the system's performance and efficiency. Through partitioning, the system's resources can be better managed and optimized for different tasks.

[0092] In summary, this application provides a multiprocessor shared memory method and system; it obtains the idle time of the shared arbitration line and sequentially outputs the low-level and high-level portions of the current processor address according to the idle time of the shared arbitration line; then it determines whether the high-level portion can pull the shared arbitration line high, so that when the high-level portion can pull the shared arbitration line high, preset data is written to the shared memory through the shared control line. This application, through shared memory, allows multiple processors to share the same storage device, reducing system costs; using shared memory simplifies the complexity of data exchange, as processors can write data to the shared memory through the shared control line without needing to move data multiple times; since the shared memory can be accessed by multiple processors, processors can directly read or write data to the shared memory, thereby improving data access efficiency.

[0093] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0094] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] Although the description of this application has been made in conjunction with the specific embodiments described above, it will be apparent to those skilled in the art that many substitutions, modifications, and variations can be made based on the foregoing. Therefore, all such substitutions, modifications, and variations are included within the spirit and scope of the appended claims.

Claims

1. A method for sharing memory across multiple processors, characterized in that, Includes the following steps: S100: Obtain the shared arbitration line idle time, and output the low-level part and high-level part of the current processor address in sequence according to the shared arbitration line idle time; Specifically, step S100, which involves sequentially outputting the low-level and high-level portions of the current processor address based on the shared arbitration line idle time, includes: S101: Determine whether the idle time of the shared arbitration line is greater than or equal to one arbitration space. If so, output the low level part of the current processor address to make the shared arbitration line non-idle, and output the high level part of the current processor address, and proceed to step S200; otherwise, execute step S102. S102: Continue to wait for at least one arbitration space and return to step S100; S200: Determine whether the high-level part can pull the shared arbitration line high, so that when the high-level part can pull the shared arbitration line high, pull the shared arbitration line low and write the preset data into the shared memory through the shared control line; Specifically, step S200 includes: S201: Determine whether the high-level part can pull the shared arbitration line high. If it can, the right to use the shared memory can be obtained, and proceed to step S202; otherwise, proceed to step S102. S202: Pull the shared arbitration line low while keeping it in a low state, then initialize the shared control line, and use the shared control line to write preset data into the shared memory.

2. The multiprocessor shared memory method according to claim 1, characterized in that, Following step S200, the method further includes: Set the shared control line to a high impedance state and pull the shared arbitration line high so that the shared arbitration line returns to an idle state.

3. The multiprocessor shared memory method according to claim 2, characterized in that, When outputting the high-level portion of multiple processor addresses simultaneously, it also includes: Obtain the address of the processor with the highest priority. If the address of the processor with the highest priority is in a low-level state, the arbitration is determined to have failed, and proceed to step S102; otherwise, proceed to step S200.

4. The multiprocessor shared memory method according to claim 3, characterized in that, Also includes: Partition the processor.

5. A system employing the multiprocessor shared memory method as described in any one of claims 1-4, characterized in that, The system includes: Acquisition module: Used to obtain the idle time of the shared arbitration line; Output module: used to sequentially output the low-level part and high-level part of the current processor address or perform waiting work according to the idle time of the shared arbitration line; Judgment module: Used to determine whether the high-level part can pull the shared arbitration line high; First processing module: used to lower the shared arbitration line according to the judgment result of the judgment module and write the preset data into the shared memory or transfer it to the acquisition module through the shared control line.

6. The system according to claim 5, characterized in that, The output module includes: Judgment unit: used to determine whether the idle time of the shared arbitration line is greater than or equal to one arbitration space; Output unit: When the idle time of the shared arbitration line is greater than or equal to one arbitration space, it sequentially outputs the low-level part and high-level part of the current processor address and then transfers the result to the judgment module; Waiting unit: Used to continue waiting for at least one arbitration space when the idle time of the shared arbitration line is less than one arbitration space or a preset condition, and then return to the acquisition module.

7. The system according to claim 6, characterized in that, The first processing module includes: First processing unit: When the judgment result of the judgment module is that the high level part can pull the shared arbitration line high, it obtains the right to use the shared memory, pulls the shared arbitration line low, and keeps the shared arbitration line in a low state, and initializes the shared control line; The second processing unit is used to transfer to the waiting unit when the judgment result of the judgment module is that the high-level part cannot be pulled high on the shared arbitration line.

8. The system according to claim 7, characterized in that, The system also includes: The second processing module is used to set the shared control line to a high impedance state and pull the shared arbitration line high. The third processing module is used to obtain the processor address with the first priority when multiple processor addresses are output at the same time, and to transfer to the waiting unit or the judgment module according to the level state of the processor address with the first priority. Partitioning module: Used to partition the processor.

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