Self-controllable SoC chip system for realizing disk RAID function

Abstract

The application provides a self-controllable SoC chip system for realizing a disk RAID function, when the chip does not work in the RAID function, the RAID enable is 0, a PCIe controller and an AHCI controller are interconnected, a PCIe Master interface is connected to an AHCI Slave interface, and an AHCI Master interface is connected to a PCIe Slave interface; when the chip works in the RAID function, the RAID enable is 1, the PCIe and the AHCI controller access a bus system. The application can flexibly control a storage device, and can be used as a multi-path storage device and can also build a RAID array card to realize disk expansion, disk data encryption and decryption and other functions.

Description

Technical Field

[0001] This invention relates to the field of RAID controller technology, and more specifically, to an independently controllable SoC chip system for implementing disk RAID functionality. Background Technology

[0002] With the advent of the big data era and the development of cloud platform technology, information storage and information security have become paramount. As the primary storage medium in computer systems, expanding disk capacity has always been a research focus. Besides improving disk manufacturing technology, creating a disk array (RAID) is a simple and easily implemented solution. RAID technology is widely used in computer systems requiring large-capacity storage, and many storage chip manufacturers offer corresponding chip products to implement RAID, such as the Marvell 9230 chip. There is a huge domestic demand for storage chips, but most commonly used controller storage chips on the market are designed and manufactured by foreign companies. Information on these chips is limited, and domestic control over them is insufficient. Therefore, reducing or even eliminating domestic dependence on foreign chip companies is crucial for the development of China's chip industry.

[0003] There are many RAID array cards on the market, but the RAID modes they implement are relatively fixed and limited.

[0004] Patent document CN108874719A (application number: CN201710344155.0) discloses an extended storage device based on a PCIe bus, comprising a video processing device and a RAID card; the video processing device and the RAID card are connected via a PCIe bus, and the RAID card is constructed from an embedded system-on-a-chip (SoC). However, this patent cannot completely solve the aforementioned technical problems.

[0005] Terminology in the text:

[0006] RAID: Redundant Array of Independent Disks is a technology that combines multiple disks in different ways to form a hard drive group, providing higher storage performance and data backup than a single disk.

[0007] PCIe: Peripheral Component Interconnect Express is a high-speed serial computer expansion bus standard.

[0008] AHCI: Advanced Host Controller Interface, is a technology standard developed by Intel. It is a hardware mechanism that allows software to communicate with SATA storage devices, enabling SATA storage devices to activate advanced SATA functions. AHCI defines a detailed memory architecture specification for hardware manufacturers, specifying how data should be transferred between system memory and SATA storage devices.

[0009] SATA: Serial Advanced Technology Attachment, is a new hard drive interface specification jointly proposed by companies such as Intel, IBM, Maxtor, and Seagate.

[0010] CPU: Central Processing Unit. As the core of a computer system for computation and control, it is the final execution unit for information processing and program execution.

[0011] DMA: Direct Memory Access.

[0012] UART: Universal Asynchronous Receiver / Transmitter.

[0013] SRAM: Static Random-Access Memory.

[0014] SoC: System on Chip. Summary of the Invention

[0015] In view of the shortcomings of the prior art, the purpose of this invention is to provide an autonomous and controllable SoC chip system for implementing disk RAID function.

[0016] The self-controllable SoC chip system for implementing disk RAID function provided by the present invention includes:

[0017] DMA controller, used for data transfer between modules;

[0018] The CPU is used to control how the entire system works.

[0019] SRAM is used to store data during system operation;

[0020] The control system module is used to coordinate the control process of the entire system.

[0021] The SPI Flash controller is used to load user configuration information externally.

[0022] UART controller, used for debugging;

[0023] The DMA controller, CPU, SRAM, and control system modules are interconnected via the AXI bus, while the SPI Flash controller and UART controller are connected to the AXI bus via the APB bus.

[0024] When the chip is not operating in RAID mode, RAID enable is 0, the PCIe controller is interconnected with the AHCI controller, the PCIe Master interface is connected to the AHCI Slave interface, and the AHCI Master interface is connected to the PCIe Slave interface; when the chip is operating in RAID mode, RAID enable is 1, and the PCIe and AHCI controllers are connected to the bus system.

[0025] Preferably, the control system module is used to integrate the control information of the entire chip system in RAID mode, and realizes the following functions: receiving information from the PCIe controller and notifying the CPU to extract information; generating MSI interrupts or INTx interrupts to the PCIe controller and configuring the RAID mode; storing key disk information;

[0026] The control system module includes two AXImaster interfaces, supporting access from the PCIe controller and master devices on the AXI bus.

[0027] Preferably, the chip's software code is embedded in an external SPI Flash device. After power-on reset, the chip loads the SPI Flash data into SRAM0, and the CPU extracts the code from SRAM0 to configure the chip.

[0028] When it is determined that RAID functionality is not needed, the circuitry except for the PCIe controller and AHCI controller enters a low-power mode, and the computer host completes the interaction with the disk through the general SATA disk driver.

[0029] When it is determined that RAID functionality is required, the CPU first obtains the status of the AHCI controller to understand the current disk connection status on the chip, including the number of disks, disk connection speed, and disk storage space size. Then, the CPU obtains the RAID mode that needs to be supported based on the information loaded in the SPI Flash or the computer host.

[0030] When the PCIe interface reads and writes to the control system module, the module generates an interrupt to notify the CPU to determine the information sent by the current PCIe interface, and according to the current RAID mode, synchronizes the values ​​of the corresponding registers to the AHCI controller and feeds back the values ​​of the corresponding registers to the PCIe controller.

[0031] Preferably, the CPU establishes fixed storage locations for the Command Table, Received FIS structure, and Command List structure in SRAM1, and allocates a region in SRAM1 for transferring information from various disks; and configures the addresses of the corresponding data information stored in SRAM1 into the AHCI registers PxCLB(U) and PxFB(U);

[0032] When the host needs to retrieve data from the disk, the CPU first reconfigures the information to be transmitted from the PCIe port into the Command Table, Received FIS structure, and Command List structure established in SRAM1 according to the current RAID mode. Then, the CPU configures the AHCI controller to start working. The AHCI controller extracts the information from the Command Table, Received FIS structure, and Command List structure established in SRAM1, writes the data of the specified disk and the corresponding Received FIS data into SRAM1 according to the RAID mode structure, and then configures the DMA controller to move the data in SRAM1 to the PCIe controller bus and transfer it to the host memory through the PCIe interface.

[0033] Preferably, when data needs to be written to the disk, the CPU first reconfigures the information to be transmitted from the PCIe port into the Command Table, Received FIS structure, and Command List structure established in SRAM1 according to the current RAID mode. Then, the CPU configures the DMA controller to read the host memory data from the interface of the PCIe controller into SRAM1. After that, the CPU configures the AHCI controller to start working. The AHCI controller extracts the information from the Command Table, Received FIS structure, and Command List structure established in SRAM1 and writes the data in SRAM1 to each disk. Finally, the CPU writes the Received FIS information in SRAM1 to the host through the PCIe interface.

[0034] During this process, the CPU receives an interrupt generated by the AHCI terminal. After processing and judging, the interrupt signal is sent to the PCIe controller terminal through the control system module. The computer host obtains the information in the Received FIS structure based on the interrupt to determine the completion status of the currently issued command.

[0035] Preferably, when the RAID function is disabled, the AHCI controller module's MSI interrupt and INTa interrupt signals are transmitted to the PCIe controller module's interrupt pin; when the RAID function is enabled, the system module's MSI interrupt and INTa interrupt signals are transmitted to the PCIe controller module's interrupt pin. At this time, the system module's MSI interrupt and INTa interrupt signals are controlled by the CPU; the interrupt pins of the AHCI controller module (both types of interrupts), the system module, the DMA controller module, and the UART controller module are connected to the CPU module.

[0036] Preferably, when RAID is enabled, the CPU handles interrupts from the AHCI controller, the control system module, the DMA controller, and the UART controller; when the PCIe controller reads or writes the AHCI controller registers, it is mapped to the control system module, at which point the control system generates an interrupt request for the CPU to handle; the CPU uses this to obtain the configuration information sent by the host to the AHCI controller, and configures the AHCI controller registers according to the configuration information and the RAID mode.

[0037] Preferably, after each AHCI control operation is completed, an assertion signal of MSI or INTa is sent to the CPU. After the CPU enters the interrupt function, it reads the P#IS and P#IE registers of the AHCI controller to obtain the interrupt type and performs different operations according to the interrupt type. If the contents of the RFIS field of the Received FIS structure in the host memory need to be updated when processing DMA commands and Non-Data commands, a DHRS type interrupt is generated. At this time, it is necessary to read the RFIS field information of the Received FIS structure sent by each port device of the AHCI controller in SRAM1 and update it in the host memory after the command is completed.

[0038] Preferably, if the PSFIS field of the Received FIS structure in the host memory needs to be updated when processing a PIO command, resulting in a PSS type interrupt, then the PSFIS field information of the Received FIS structure sent by each port device of the AHCI controller in SRAM1 needs to be read and updated in the host memory after the command is completed.

[0039] Preferably, if the command field in the host memory requires the AHCI controller to send an MSI or INTa interrupt to the host during the operation process, the software, after receiving the interrupt signal from the AHCI controller, generates a signal through the MSI and INTa pins of the system control module to tell the PCIe controller to send an interrupt to the host; in the command operation process, when the DMA controller completes the data transfer work, it generates an interrupt to inform the CPU to complete the operation.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] (1) The present invention provides an independent and controllable SoC chip system for implementing disk RAID function. The system is equipped with PCIe interface and SATA interface and can be used in general computers or some devices that require large capacity storage. Under this system, storage devices can be flexibly controlled. It can be used as a multi-channel storage device or a RAID array card to realize disk expansion, disk data encryption and decryption and other functions.

[0042] (2) The RAID SoC system designed in this invention implements RAID modes flexibly and the entire chip operation process is completely autonomous and controllable. Designers can implement the required RAID modes according to their actual needs. The system designed in this invention can put some modules into low-power mode when not in RAID mode. This invention contains an AHCI controller module, which is compatible with the drivers of most operating systems, reducing the workload of chip driver development. This invention belongs to computer peripheral devices and can occupy less computer resources when implementing RAID controller. Attached Figure Description

[0043] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0044] Figure 1 Arbitration structure diagram for RAID function;

[0045] Figure 2 Design a block diagram for bus devices;

[0046] Figure 3 This is a method to interrupt internal connections. Detailed Implementation

[0047] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0048] Example

[0049] This invention provides an independently controllable SoC chip system for implementing disk RAID functionality, comprising two parts: a RAID function arbitration and a SoC system for building a RAID controller. Figure 1This is the chip's RAID function arbitration scheme. When the chip is not operating in RAID mode (RAID Enable is 0), the PCIe controller and AHCI controller are interconnected, with the PCIe Master interface connected to the AHCI Slave interface, and the AHCI Master interface connected to the PCIe Slave interface. When the chip is operating in RAID mode (RAID Enable is 1), it enables... Figure 2 The diagram shows a bus device design block diagram implementing RAID functionality. In this case, the PCIe and AHCI controllers are connected to the bus system. The DMA controller is used for data transfer between modules, the CPU controls the overall system operation, SRAM stores data during system operation, the control system module coordinates the overall system control process, the SPI Flash controller can be used to load user configuration information externally, and the UART controller is used for debugging. Furthermore, when the chip's RAID function is not used, [the following can be added:] Figure 2 The system enters a low-power mode to reduce chip power consumption.

[0050] The control system module integrates control information for the entire chip system in RAID mode, primarily performing the following three functions: 1. Receiving information from the PCIe controller and notifying the CPU to retrieve the information; 2. Generating MSI or INTx interrupts to the PCIe controller and configuring the RAID mode; 3. Storing critical disk information. The control system includes two AXI master interfaces, supporting access from the PCIe controller and master devices on the AXI bus.

[0051] The chip's software code is embedded in an external SPI Flash device. After power-on reset, the chip loads the SPI Flash data into SRAM0, and the CPU extracts the code from SRAM0 for chip configuration. When RAID functionality is not required, all circuitry except the PCIe controller and AHCI controller enters a low-power mode, allowing the computer host to interact with the disks via a standard SATA disk drive. When RAID functionality is required, the CPU first obtains the AHCI controller's status to understand the current disk connections on the chip (including the number of disks, connection speed, and storage size). The CPU can then determine the required RAID mode based on the information loaded in the SPI Flash or from the computer host. When the PCIe interface reads or writes to the control system module (configuring AHCI controller register information), the module generates an interrupt to notify the CPU to assess the information sent by the PCIe interface and, based on the current RAID mode, synchronously configure the corresponding register values ​​to the AHCI controller and feed back the corresponding register values ​​to the PCIe controller. The CPU establishes fixed storage locations in SRAM1 similar to the Command Table, Received FIS, and Command List structures, and allocates a region in SRAM1 to store information from various disks. It also configures the addresses of the corresponding data information stored in SRAM1 into the AHCI registers PxCLB(U) and PxFB(U). The host's configuration of the PxCLB(U) and PxFB(U) registers for each port is also stored. When the host needs to retrieve data from the disk, the CPU first reconfigures the information to be transferred (Command Table, Received FIS, and Command List) from the PCIe port into the Command Table, Received FIS, and Command List structures established in SRAM1 according to the current RAID mode. Afterward, the CPU configures the AHCI controller to begin operation. The AHCI controller extracts information from the Command Table, Received FIS structure, and Command List structure established in SRAM1, writes the data from the specified disk and the corresponding Received FIS data into SRAM1 according to the RAID mode structure, and then the CPU configures the DMA controller to move the data in SRAM1 to the PCIe controller bus and transfer it to the host memory through the PCIe interface.When data needs to be written to the disk, the CPU first reconfigures the information to be transferred (Command Table, Received FIS, and Command List) from the PCIe port into the Command Table, Received FIS, and Command List structures created in SRAM1 according to the current RAID mode. The CPU then configures the DMA controller to read data from the host memory into SRAM1 from the PCIe controller interface. Afterward, the CPU configures the AHCI controller to begin operation. The AHCI controller extracts information from the Command Table, Received FIS, and Command List structures created in SRAM1 and writes the data from SRAM1 to the respective disks. Finally, the CPU writes the Received FIS information from SRAM1 to the host computer via the PCIe interface. During this process, the CPU receives interrupts (MSI or INTa) generated by the AHCI side. After processing and judging, the interrupt signal is sent to the PCIe controller through the control system module. The host computer uses the interrupt to obtain information from the Received FIS structure to determine the completion status of the currently issued command.

[0052] The system includes the following interrupt pins: AHCI controller MSI interrupt and INTa interrupt output, PCIe controller MSI interrupt and INTa interrupt input, DMA controller interrupt output, UART controller interrupt output, control system module interrupt output, and CPU interrupt input. The connection method for interrupt signals between modules is as follows: Figure 3 As shown.

[0053] When RAID is disabled, the AHCI controller module's MSI and INTa interrupt signals are transmitted to the PCIe controller module's interrupt pins. When RAID is enabled, the system module's MSI and INTa interrupt signals are transmitted to the PCIe controller module's interrupt pins, at which point the system module's MSI and INTa interrupt signals are controlled by the CPU. The AHCI controller module's two types of interrupts, as well as the interrupt pins of the system module, DMA controller module, and UART controller module, are connected to the CPU module.

[0054] When RAID is enabled, the CPU handles interrupts from the AHCI controller, the control system module, the DMA controller, and the UART controller. When the PCIe controller reads or writes to the AHCI controller registers, it is mapped to the control system module, at which point the control system generates an interrupt request for the CPU to process. The CPU uses this to obtain the configuration information sent by the host to the AHCI controller and configures the AHCI controller registers according to the configuration information and the RAID mode. If, during the processing of the above commands, the AHCI controller asserts the MSI or INTa signal to the CPU after each completion, the CPU enters the interrupt function and reads the P#IS and P#IE registers of the AHCI controller to obtain the interrupt type. Different operations are performed based on the interrupt type. For example, when processing DMA and Non-Data commands, updating the RFIS field of the Received FIS structure in the host memory will generate a DHRS type interrupt. In this case, the RFIS field information of the Received FIS structure sent by each port device of the AHCI controller in SRAM1 needs to be read and updated in the host memory after the command is completed. Similarly, when processing PIO commands, updating the PSFIS field of the Received FIS structure in the host memory will generate a PSS type interrupt. In this case, the PSFIS field information of the Received FIS structure sent by each port device of the AHCI controller in SRAM1 needs to be read and updated in the host memory after the command is completed. If the software receives an interrupt signal from the host memory command field requiring the AHCI controller to send an MSI or INTa interrupt to the host during an operation, it will control the system module's MSI and INTa pins to generate signals instructing the PCIe controller to send an interrupt to the host. During the command operation flow, once the DMA controller completes the data transfer, it will generate an interrupt to notify the CPU that the operation is complete.

[0055] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0057] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A self-controllable SoC chip system for implementing disk RAID functionality, characterized in that, include: DMA controller, used for data transfer between modules; The CPU is used to control how the entire system works. SRAM is used to store data during system operation; The control system module is used to coordinate the control process of the entire system. The SPI Flash controller is used to load user configuration information externally. UART controller, used for debugging; The DMA controller, CPU, SRAM, and control system modules are interconnected via the AXI bus, while the SPI Flash controller and UART controller are connected to the AXI bus via the APB bus. When the chip is not operating in RAID mode, RAID enable is 0, the PCIe controller is interconnected with the AHCI controller, the PCIe Master interface is connected to the AHCI Slave interface, and the AHCI Master interface is connected to the PCIe Slave interface; when the chip is operating in RAID mode, RAID enable is 1, and the PCIe and AHCI controllers are connected to the bus system. The control system module is used to integrate the control information of the entire chip system in RAID mode, and performs the following functions: receiving information from the PCIe controller and notifying the CPU to extract the information; generating MSI interrupts or INTa interrupts to the PCIe controller and configuring the RAID mode; and storing critical disk information. The control system module includes two AXImaster interfaces, which support access from the PCIe controller and master devices on the AXI bus. The chip's software code is embedded in an external SPI Flash device. After power-on reset, the chip loads the SPI Flash data into SRAM0, and the CPU extracts the code from SRAM0 to configure the chip. When it is determined that RAID functionality is not needed, the circuitry except for the PCIe controller and AHCI controller enters a low-power mode, and the computer host completes the interaction with the disk through the general SATA disk driver. When it is determined that RAID functionality is required, the CPU first obtains the status of the AHCI controller to understand the current disk connection status on the chip, including the number of disks, disk connection speed, and disk storage space size. Then, the CPU obtains the RAID mode that needs to be supported based on the information loaded in the SPI Flash or the computer host. When the PCIe interface reads and writes to the control system module, the module generates an interrupt to notify the CPU to determine the information sent by the current PCIe interface, and according to the current RAID mode, synchronize the value of the corresponding register to the AHCI controller and feed back the value of the corresponding register to the PCIe controller. When RAID is disabled, the MSI and INTa interrupt signals from the AHCI controller module are transmitted to the interrupt pin of the PCIe controller module. When RAID is enabled, the MSI and INTa interrupt signals from the control system module pins are transmitted to the interrupt pin of the PCIe controller module. At this time, the MSI and INTa interrupt signals from the control system module pins are controlled by the CPU. The interrupt pins of the AHCI controller module, control system module, DMA controller module, and UART controller module are connected to the CPU module. When RAID is enabled, the CPU handles interrupts from the AHCI controller, the control system module, the DMA controller, and the UART controller. When the PCIe controller reads or writes to the AHCI controller registers, it is mapped to the control system module. At this time, the control system generates an interrupt request for the CPU to handle. The CPU uses this to obtain the configuration information sent by the host to the AHCI controller and configures the AHCI controller registers according to the configuration information and RAID mode.

2. The independently controllable SoC chip system for implementing disk RAID function according to claim 1, characterized in that, The CPU establishes fixed storage locations for the Command Table, Received FIS structure, and Command List structure in SRAM1, and allocates a region in SRAM1 to transfer information from various disks; and configures the addresses of the corresponding data information stored in SRAM1 into the AHCI registers PxCLB(U) and PxFB(U); When the host needs to retrieve data from the disk, the CPU first reconfigures the information to be transferred from the PCIe port into the Command Table, Received FIS structure, and Command List structure established in SRAM1 according to the current RAID mode. Then, the CPU configures the AHCI controller to start working. The AHCI controller extracts the information from the Command Table, Received FIS structure, and Command List structure established in SRAM1, writes the data of the specified disk and the corresponding Received FIS structure data into SRAM1 according to the RAID mode structure, and then configures the DMA controller to move the data in SRAM1 to the PCIe controller bus and transfer it to the host memory through the PCIe interface.

3. The independently controllable SoC chip system for implementing disk RAID function according to claim 2, characterized in that, When data needs to be written to the disk, the CPU first reconfigures the information to be transferred from the PCIe port into the Command Table, Received FIS structure, and Command List structure established in SRAM1 according to the current RAID mode. Then, the CPU configures the DMA controller to read the host memory data from the PCIe Slave interface into SRAM1. After that, the CPU configures the AHCI controller to start working. The AHCI controller extracts the information from the Command Table, Received FIS structure, and Command List structure established in SRAM1 and writes the data in SRAM1 to the respective disks. Finally, the CPU writes the Received FIS information in SRAM1 to the host through the PCIe interface. During this process, the CPU receives an interrupt generated by the AHCI terminal. After processing and judging, the interrupt signal is sent to the PCIe controller terminal through the control system module. The computer host obtains the information in the Received FIS structure based on the interrupt to determine the completion status of the currently issued command.

4. The independently controllable SoC chip system for implementing disk RAID function according to claim 1, characterized in that, After each AHCI controller completes its operation, it sends an MSI or INTa interrupt signal to the CPU. After entering the interrupt function, the CPU reads the P#IS and P#IE registers of the AHCI controller to obtain the interrupt type and performs different operations according to the interrupt type. If the RFIS field of the Received FIS structure in the host memory needs to be updated when processing DMA commands and Non-Data commands, a DHRS type interrupt is generated. At this time, it is necessary to read the RFIS field information of the Received FIS structure sent by each port device of the AHCI controller in SRAM1 and update it to the host memory after the command is completed.

5. The independently controllable SoC chip system for implementing disk RAID function according to claim 4, characterized in that, If the PSFIS field of the Received FIS structure in the host memory needs to be updated when processing a PIO command, and a PSS type interrupt is generated, then the PSFIS field information of the Received FIS structure sent by each port device of the AHCI controller in SRAM1 needs to be read and updated to the host memory after the command is completed.

6. The independently controllable SoC chip system for implementing disk RAID function according to claim 4, characterized in that, If the software receives the interrupt signal from the AHCI controller after obtaining the interrupt signal from the host memory command field, it will generate a signal through the MSI and INTa pins of the system control module to tell the PCIe controller to send an interrupt to the host. In the command operation process, when the DMA controller completes the data transfer, it will generate an interrupt to inform the CPU to complete the operation.

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