A hardware package-based system chip design control method and device

Abstract

The embodiment of the present specification provides a kind of hardware package-based system chip design control method and device, associate combination of hardware engine and software engine, compatible with the advantages of both hardware engine and software engine, more higher expansibility and flexibility, it is convenient to more efficiently realize design iteration optimization.The method is applied to the soft and hard association engine device in system chip design system, comprising: receiving the task data packet forwarded by the work management engine in the system chip design system;Initial transmission verification is carried out for the task data packet;In response to initial transmission verification, it is determined that the work mode in which the soft and hard association engine is located;In interrupt work mode, function interrupt event is generated for the task data packet, and the software engine connected with the soft and hard association engine is notified;In event work mode, hardware event is generated according to the task data packet, and the hardware event is written into the work management engine after arbitration.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and more specifically to a system-on-a-chip design control method and apparatus based on hardware packaging. Background Technology

[0002] A system-on-a-chip (SoC) is an integrated circuit chip that integrates various modules of a circuit onto a single substrate. SoCs offer digital, analog, mixed-signal, and general-purpose radio frequency signal processing capabilities, reducing power consumption and minimizing chip size. With rapid advancements in manufacturing processes, more and more modules and components are integrated onto the same chip, ushering in the SoC era for integrated circuits.

[0003] A System-on-a-Chip (SoC) typically consists of software and hardware. SoC design can be divided into software and hardware design, which are then combined to form a complete system. Hardware engineers use hardware description languages ​​such as VHDL or Verilog to design and build hardware engines. Based on hardware circuit modules, these engines enable information exchange between circuits, such as algorithm and functional modules. Hardware engines offer faster speeds and stable parallel processing, but they require lengthy iterative calculations, and subsequent chip design modifications necessitate recalculations, incurring significant time and implementation costs. Software engineers use programming languages ​​such as C or C++ to design and build software engines. Software engines offer higher flexibility and lower cost. However, they lack independent hardware and interfaces, consume CPU resources, are susceptible to operating system instability, and generally have lower performance. Summary of the Invention

[0004] In view of this, the embodiments of this specification provide a system control device, method, electronic device and storage medium for system chip design, which combines hardware engine and software engine, and makes full use of the advantages of both hardware engine and software engine, with higher scalability and flexibility, and facilitates more efficient design iteration and optimization.

[0005] In a first aspect, embodiments of this specification provide a hardware-software coherence engine device for a system-on-a-chip (SoC) design system, comprising: It includes a data packet reading module, a parity check module, an interrupt generation module, an aggregation module, and an arbitration module; The data packet reading module is used to obtain data packets from the buffered FIFO queue through the register interface; The parity check module is used to perform parity check on the data content of the data packets obtained by the data packet reading module; The interrupt generation module is used to generate functional interrupts and / or error interrupts, wherein error interrupts have a higher priority than functional interrupts. The aggregation module is used to perform data aggregation on multiple data packets; The arbitration module is used to arbitrate hardware events of the hardware engine in the system chip design system using a polling method.

[0006] In a second aspect, embodiments of this specification also provide a system-on-a-chip (SoC) design control method based on hardware packaging, the method being applied to a hardware-software co-location engine device in a SoC design system as described in the first aspect; the method includes: Receive task data packets forwarded by the work management engine in the system chip design system, wherein the task data packets include task data corresponding to the system chip design business; An initial transmission verification is performed on the task data packet to determine whether the task data packet is a legitimate data packet; In response to the successful initial transmission verification, the operating mode of the hardware-software correlation engine device is determined; In response to the hardware-software integration engine device being in interrupt mode, a function interruption event is generated for the task data packet, and the software engine connected to the hardware-software integration engine device is notified. In response to the hardware-software association engine device being in event-driven mode, a hardware event is generated based on the task data packet, and the hardware event is arbitrated before being written into the task management engine.

[0007] This specification also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the hardware-packaged system-on-a-chip design control method as described in the second aspect.

[0008] This specification also provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the hardware-package-based system-on-a-chip design control method as described in the second aspect.

[0009] As can be seen from the above, the control device, method, electronic device, and storage medium for a system-on-a-chip design system provided in the embodiments of this specification have the following beneficial technical effects: The hardware-software co-location engine device, designed with a hardware package structure, is positioned between the hardware engine and the software engine. It connects to the system chip's (SIC) work management module via an on-chip interconnect network to receive and process SIC task data packets, thereby enabling task forwarding from the hardware engine. When the hardware engine encounters problems, the software engine can handle the issue. This approach, combining the hardware and software engines, leverages the advantages of both, balancing time, cost, power consumption, and hardware area. It allows for rapid anomaly handling, higher scalability and flexibility, and facilitates more efficient design iteration and optimization. Attached Figure Description

[0010] The features and advantages of the invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the invention in any way. In the drawings: Figure 1 This specification shows a schematic diagram of the structure of a hardware-software co-processing engine device in a system-on-a-chip design system provided in an embodiment of this specification; Figure 2 This diagram illustrates a hardware-packaged system-on-a-chip design control method provided in an embodiment of this specification. Figure 3 This diagram illustrates the communication connection method of the software-hardware association engine in a hardware-packaged system-on-a-chip design control method provided in an embodiment of this specification. Figure 4 This diagram illustrates an initial transmission verification method in a hardware-packaged system-on-a-chip design control method provided in an embodiment of this specification. Figure 5 This document illustrates a schematic diagram of the operational process in an event-driven mode of a hardware-package-based system-on-a-chip design control method provided in an embodiment of this specification. Figure 6 This diagram illustrates the workflow of the hardware-software co-processing engine in a hardware-package-based system-on-a-chip design control method provided in an embodiment of this specification. Figure 7 This document illustrates a schematic diagram of a hardware-packaged system-on-a-chip (SoC) design for controlling electronic devices, as provided in an embodiment of this specification. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] A system-on-a-chip (SoC) is an integrated circuit chip that integrates various modules of a circuit onto a single substrate. SoCs offer digital, analog, mixed-signal, and general-purpose radio frequency signal processing capabilities, reducing power consumption and minimizing chip size. With rapid advancements in manufacturing processes, more and more modules and components are integrated onto the same chip, ushering in the SoC era for integrated circuits.

[0013] A System-on-a-Chip (SoC) typically consists of software and hardware. SoC design can be divided into software and hardware design, which are then combined to form a complete system. Hardware engineers use hardware description languages ​​such as VHDL or Verilog to design and build hardware engines. Based on hardware circuit modules, these engines enable information exchange between circuits, such as algorithm and functional modules. Hardware engines offer faster speeds and stable parallel processing, but they require lengthy iterative calculations, and subsequent chip design modifications necessitate recalculations, incurring significant time and implementation costs. Software engineers use programming languages ​​such as C or C++ to design and build software engines. Software engines offer higher flexibility and lower cost. However, they lack independent hardware and interfaces, consume CPU resources, are susceptible to operating system instability, and generally have lower performance.

[0014] Therefore, in SoC design, there is a contradiction between the goals of low cost and high performance, as well as between the design iteration cycle and the design functional complexity.

[0015] To address the aforementioned issues, the purpose of this specification is to propose a hardware-packaged system-on-a-chip (SoC) design and control method. The hardware package structure is designed to connect between the hardware engine and the software engine, and accesses the SoC's work management module via an on-chip interconnect network. This module receives and processes the SoC's task data packets, enabling task forwarding from the hardware engine. When the hardware engine encounters problems, the software engine can handle the processing. This approach combines the hardware and software engines, leveraging their respective advantages while considering time, cost, power consumption, and hardware area. It allows for rapid anomaly handling, higher scalability and flexibility, and facilitates more efficient design iteration and optimization.

[0016] To achieve the above objectives, this specification provides a hardware-software coherence engine device for a system-on-a-chip design system.

[0017] like Figure 1As shown in one or more optional embodiments of this specification, a software engine bank (SWEB) device for a system-on-a-chip design system includes a data packet reading module, a parity check module, an interrupt generation module, an aggregation module, and an arbitration module.

[0018] The data packet reading module is used to retrieve data packets from the buffered FIFO queue via a register interface. The CPU in the software engine instructs the SWEB to read task data packets forwarded from the job management engine by writing to the register. The SWEB reads the data packets from the corresponding buffered FIFO and places them in the data packet reading register based on the register write trigger signal.

[0019] The parity check module is used to perform parity check on the data packet content obtained by the data packet reading module.

[0020] The interrupt generation module is used to generate functional interrupts and / or error interrupts, with error interrupts having higher priority than functional interrupts. There are eight types of error interrupts, in which case SWEB generates an interrupt notification software and updates the interrupt status register. ① The hardware event buffer FIFO is full, but hardware events are still being written. ② The data packet FIFO is full, but hardware events are still being written. ③ Data packet parity error. ④ The data packet FIFO is empty, but data packet read operations are still being performed. ⑤ The number of data packets in the data packet FIFO exceeds the configuration depth. ⑥ A channel is not configured, but data packets are still being written. ⑦ The engine ID checksum in the data packet does not match the channel's engine ID. ⑧ The AXI bus returns an error response.

[0021] The aggregation module is used to perform data aggregation on multiple data packets. The aggregation module starts timing and counting from the receipt of the first data packet. When the time reaches the configured time or the number of data packets reaches the pre-configured number, it triggers data packet aggregation and then notifies the software engine.

[0022] The arbitration module is used to arbitrate hardware events using a polling method. For a given software engine, there may be a next data packet being written during the arbitration waiting process; therefore, a buffer FIFO is also required for the corresponding hardware event. That is, the hardware event buffer FIFO is used to cache the next data packet during the arbitration waiting process, and an error interrupt is triggered when the hardware event buffer FIFO is full. Each hardware event includes engine ID and FIFO load information.

[0023] The hardware-software interconnection engine device is located between the hardware engine and the software engine. It is connected to the system chip's work management module through an on-chip interconnection network to receive and process the system chip's task data packets, thereby enabling hardware engine task forwarding. When the hardware engine encounters a problem, the software engine can handle it on its behalf.

[0024] For the same purpose, embodiments of this specification also provide a system-on-a-chip design control method based on hardware packaging, the method being applied to the hardware-software interconnection engine device.

[0025] like Figure 2 As shown, one or more optional embodiments of this specification provide a system-on-a-chip design control method based on hardware packaging, comprising: S1: Receive the task data packet forwarded by the work management engine in the system chip design system. The task data packet includes task data corresponding to the system chip design business.

[0026] like Figure 3 As shown, the software-hardware co-processing engine SWEB can connect with both the software engine (CPU) and the hardware engine (e.g., the I / O controller) to form a software-hardware module. A typical application scenario for this software-hardware module is using the CPU for I / O coprocessing. SWEB is responsible for connecting the software-hardware module to the on-chip network. The task management engine can send data packets to the software-hardware module and, upon receiving the data packets, notify the CPU to process them via interrupt response or a hardware event queue.

[0027] In the hardware and software modules, the task data packet can be viewed as a task order for an engine to complete a task, encompassing all the necessary information to complete that task. Depending on the type of hardware engine, the data packet size can be 16B, 32B, 48B, ..., up to a maximum of 128B. The CPU completes the defined engine task by operating the hardware module it is bound to, and returns a "completed" message and an "enqueued" message for the next data packet to the work management engine.

[0028] When a hardware engine in the circuit malfunctions, the software and hardware modules process the data packets and complete the abnormal recovery and recording of the hardware engine.

[0029] The hardware-software interconnected engine SWEB can also be connected to the CPU to form a universal module, mainly implementing pure software algorithm-based software engines. SWEB is responsible for accessing the on-chip network. The task management engine can send task data packets to SWEB, and after receiving the task data packets, SWEB notifies the CPU to process them via interrupts or hardware event queues. After completing the specified engine task, the CPU returns a "complete" message and an "enqueue" message for the next data packet to the task management engine.

[0030] S2: Perform an initial transmission verification on the task data packet to determine whether the task data packet is a valid data packet.

[0031] After receiving a data packet from the job management engine, the software-hardware association engine can first perform an initial transmission verification on the data packet to ensure the legality of the received data packet.

[0032] like Figure 4 As shown, in one or more optional embodiments of this specification, a system-on-a-chip design control method based on hardware packaging is provided, in which an initial transmission verification is performed on the task data packet to determine whether the task data packet is a valid data packet, including: S201: Perform a channel enable verification on the task data packet to determine whether the corresponding transmission channel of the task data packet is enabled.

[0033] Upon receiving the task data packet, the system first determines whether the channel through which the task data packet was transmitted is enabled. If the channel is not enabled, it indicates that the task data packet was transmitted through an illegal channel, and the current data packet may pose a risk. In this case, the current task data packet is discarded, and an error interruption is triggered.

[0034] S202: In response to determining that the transmission channel is enabled, a channel matching check is performed on the task data packet to determine whether the engine ID in the task data packet matches the engine ID corresponding to the transmission channel.

[0035] After confirming that the transmission channel is enabled, a further matching and verification is required for the channel to determine whether the task data packet matches the engine ID corresponding to the transmission channel. If the engine IDs do not match, it indicates an error in the data transmission channel. In this case, the current task data packet is discarded, and an error interruption is triggered.

[0036] S203: In response to the matching of the task data packet with the engine ID of the transmission channel, perform data parity check on the task data packet.

[0037] If the task data packet channel matching verification passes, it means that the task data packet was transmitted through a correct transmission channel and a legitimate transmission path. Next, a parity check needs to be performed on the task data packet itself to determine whether the data content of the task data packet has changed during transmission. If the parity check fails, it indicates that the task data packet may have been subjected to an illegal attack during transmission, causing changes to the data content within the data packet.

[0038] In this case, the current task data packet is discarded, and an error interruption is triggered.

[0039] S204: In response to the data parity check passing, the task data packet is determined to be a valid data packet, and the task data packet is written into the cache FIFO queue.

[0040] If the task data packet passes the parity check, it indicates that the task data packet was legally transmitted through the correct data channel and was not illegally modified during transmission; therefore, it is a valid data packet. After determining that the task data packet is valid, it is written into a buffer FIFO queue for subsequent processing of the task data within the data packet.

[0041] S3: In response to the initial transmission verification passing, determine the operating mode of the software-hardware association engine device.

[0042] After the initial transmission verification of the task data packet passes, processing can be performed on the task data packet. The software-hardware association engine may be in different operating modes. It is necessary to first determine the current operating mode of the software-hardware association engine so as to take appropriate processing measures for the task data packet according to the operating mode.

[0043] S4: In response to the hardware-software association engine device being in interrupt working mode, generate a function interruption event for the task data packet and notify the software engine connected to the hardware-software association engine device.

[0044] In a hardware-packaged system-on-a-chip design control method provided in one or more optional embodiments of this specification, generating a function interruption event for the task data packet and notifying the software engine connected to the hardware-software association engine includes: The buffered FIFO queue is monitored in real time to determine whether the interruption conditions are met.

[0045] The interruption occurs when the number of data packets in the buffered FIFO queue reaches a first preset data packet threshold. This preset data packet threshold is determined by the software engine.

[0046] The interruption condition can also cause the data packet storage time in the cache FIFO to reach a first preset time threshold.

[0047] If the interruption conditions are met, multiple task data packets in the cached FIFO queue are aggregated, and a functional interruption is generated.

[0048] When the number of data packets in the cached FIFO queue reaches a preset threshold, or the cache time of the cached FIFO queue reaches a preset time threshold, the aggregation module in the SWEB software-hardware association engine performs data aggregation on multiple data packets of the person in the cached FIFO queue and generates a function interruption.

[0049] In some alternative implementations, if the current operating mode is interrupt mode, a functional interrupt is generated to directly notify the software. Each software engine has an independent status register that displays the number of valid data packets in the buffer FIFO in real time. When the buffer FIFOs of the 32 software engines are not empty, the packet aggregation register aggregates a certain number of data packets, or a functional interrupt is generated at a configured interval. When handling an interrupt, the software reads the independent status register of each software engine and determines the number of data packets to read based on the value. Furthermore, the packet buffer FIFO depths of the 32 software engines are not consistent; the smaller the channel ID, the deeper the packet buffer FIFO.

[0050] S5: In response to the hardware-software association engine device being in event working mode, generate a hardware event based on the task data packet, arbitrate the hardware event, and write it into the work management engine.

[0051] like Figure 5 As shown, in a hardware-packaged system-on-a-chip design control method provided in one or more optional embodiments of this specification, generating hardware events based on the task data packet, arbitrating the hardware events, and writing them into the work management engine includes: S301: Monitor the cached FIFO queue in real time to determine whether the conditions for an event to occur are met.

[0052] The event generation conditions include the number of data packets in the cached FIFO queue reaching a second preset data packet threshold, or the cached FIFO storing data packets for a period of time reaching a second preset time threshold.

[0053] S302: When the event generation conditions are met, perform data aggregation on multiple task data packets in the cached FIFO queue and generate a hardware event.

[0054] S303: Perform parity check on the hardware event, and write the hardware event into the event FIFO queue after the parity check passes.

[0055] S304: Arbitrate multiple hardware events in the event FIFO queue in a round-robin manner, and send the hardware events that pass the arbitration to the work management engine.

[0056] In some alternative implementations, if the current operating mode is event-driven, hardware events are generated to indirectly notify the software. Timing and counting begin from the receipt of the first data packet, and packet aggregation is triggered when the configured time is reached or the configured number of data packets is reached.

[0057] After data packet aggregation, hardware time is generated. After parity checking of hardware events, they are cached in the hardware event FIFO. The arbitration module uses polling to arbitrate hardware events and then writes them to the work management engine through the on-chip interconnect network.

[0058] The described system-on-a-chip (SoC) design and control method based on hardware packaging involves a hardware-software co-location engine device connected between the hardware engine and the software engine. This device connects to the SoC's management module via an on-chip interconnect network to receive and process the SoC's task data packets, enabling task forwarding from the hardware engine. This allows the software engine to handle issues that arise in the hardware engine. This approach, combining the hardware and software engines, leverages their respective advantages, balancing time, cost, power consumption, and hardware area considerations. It allows for rapid anomaly handling, greater scalability and flexibility, and facilitates more efficient design iteration and optimization.

[0059] like Figure 6 As shown, in a hardware-packaged system-on-a-chip design control method provided in one or more optional embodiments of this specification, SWEB and the task management engine communicate through registers to complete the forwarding of software tasks by the hardware engine.

[0060] After receiving a data packet from the work management engine, the SWEB does not perform packet block parsing. Instead, it performs channel enable checks, engine ID matching checks, and parity checks before writing the data packet to the FIFO. Subsequently, it processes the data packet according to the operating mode, generating a functional interrupt or hardware event, which is then written to the work management engine via the AXI bus. The specific process is as follows: (1) Initially, the task data packets of the job management engine are received using the read data packet module in SWEB.

[0061] (2) Use the data packet reading module to determine whether the channel is enabled.

[0062] If not enabled, the current packet is discarded and an error interrupt is triggered.

[0063] If enabled, engine ID verification will be performed.

[0064] (3) Continue to use the data packet reading module to determine whether the engine ID in the data packet matches the engine ID of the channel.

[0065] If there is no match, the current packet is discarded and an error interruption is triggered.

[0066] If a match is found, a parity check is performed.

[0067] (4) Use the parity check module in SWEB to perform parity check on the received task data packet and determine whether the parity check matches.

[0068] If there is no match, the current packet is discarded and an error interruption is triggered.

[0069] If a match is found, the packet is written to the FIFO.

[0070] (5) Use the data packet reading module to determine the working mode based on the data content in the task data packet.

[0071] In interrupt mode, the interrupt generation module in SWEB is used to monitor the buffer FIFO queue in real time to determine whether the interrupt generation conditions are met. If the interrupt generation conditions are met, the interrupt generation module is controlled to generate a functional interrupt and notify the corresponding software engine.

[0072] Each software engine has an independent status register that displays the number of valid data packets in its buffer FIFO in real time. When the buffer FIFOs of the 32 software engines are not empty, the packet aggregation register aggregates a certain number of data packets or generates a function interrupt at the configured interval. When handling the interrupt, the software reads the independent status register of each software engine and determines the number of data packets to read based on the value. Furthermore, the packet buffer FIFO depths of the 32 software engines are not consistent; the smaller the channel ID, the deeper the packet buffer FIFO.

[0073] In event-driven mode, the data packet reading module monitors the buffered FIFO queue in real time to determine if the event generation conditions are met. If the conditions are met, the aggregation module in SWEB aggregates multiple task data packets in the buffered FIFO queue and generates a hardware event.

[0074] The timing and counting begin from the first data packet received. When the time reaches the configured time or the number of data packets reaches the configured number, data packet aggregation is triggered. The aggregation module in SWEB is used to aggregate data packets from multiple tasks in the FIFO.

[0075] After data packet aggregation, parity check is enabled. After parity check of hardware events, they are cached in the hardware event FIFO. The arbitration module in the control SWEB uses polling to arbitrate hardware events and then writes them to the work management engine through the on-chip interconnect network.

[0076] It should be noted that the methods of one or more embodiments of this specification can be executed by a single device, such as a computer or server. The methods of this embodiment can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the methods of one or more embodiments of this specification, and the multiple devices will interact with each other to complete the method described.

[0077] It should be noted that the above description describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims may be performed in a different order than that shown in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0078] Figure 7 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0079] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0080] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0081] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0082] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0083] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0084] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0085] The electronic devices described above are used to implement the corresponding methods in the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0086] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to execute the hardware-packaged system chip design control method as described in any of the above embodiments.

[0087] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0088] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the hardware-packaged system chip design control method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0089] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0090] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0091] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0092] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0093] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0094] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0095] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0096] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this specification as described above, which are not provided in detail for the sake of brevity.

[0097] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0098] One or more embodiments of this specification are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of this disclosure.

Claims

1. A system-on-a-chip design and control method based on hardware packaging, characterized in that, The method includes: Receive task data packets forwarded by the work management engine in the system chip design system, wherein the task data packets include task data corresponding to the system chip design business; An initial transmission verification is performed on the task data packet to determine whether the task data packet is a legitimate data packet; In response to the successful initial transmission verification, the operating mode of the hardware-software association engine device is determined; In response to the hardware-software integration engine device being in interrupt mode, a function interruption event is generated for the task data packet, and the software engine connected to the hardware-software integration engine device is notified. In response to the hardware-software association engine device being in event-driven mode, a hardware event is generated based on the task data packet, and the hardware event is arbitrated and then written into the task management engine. The system uses a data packet reading module to receive task data packets forwarded by the work management engine in the system chip design system. The task data packets include task data corresponding to the system chip design business. The data packet reading module is used to perform channel enable verification on the task data packet to determine whether the corresponding transmission channel of the task data packet is enabled. In response to determining that the transmission channel is enabled, the read data packet module performs a channel matching verification on the task data packet to determine whether the engine ID in the task data packet matches the engine ID corresponding to the transmission channel. In response to the matching of the task data packet with the engine ID of the transmission channel, data parity check is performed using the task data packet; In response to the data parity check passing, the task data packet is determined to be a valid data packet, and the task data packet is written into the cache FIFO queue; The operating mode of the hardware-software association engine device is determined using the data packet reading module. In response to the hardware-software correlation engine device being in interrupt working mode, the interrupt generation module is used to monitor the cache FIFO queue in real time to determine whether the interrupt generation conditions are met. When the interruption conditions are met, the aggregation module is used to aggregate multiple task data packets in the cache FIFO queue, and after the data aggregation, the interruption generation module is controlled to generate a functional interrupt. The interruption conditions include the number of data packets in the buffered FIFO queue reaching a first preset data packet threshold or the time the buffered FIFO queue stores data packets reaching a first preset time threshold. After a function interruption occurs, a function interruption message is sent to the software engine connected to the hardware-software interconnection engine device; In response to the hardware-software association engine device being in event-driven mode, the data packet reading module is used to monitor the cache FIFO queue in real time to determine whether the event generation conditions are met. When the conditions for event generation are met, the aggregation module is used to aggregate multiple task data packets in the cached FIFO queue and generate a hardware event. The parity check module is used to perform parity check on the hardware event, and after the parity check passes, the hardware event is written into the event FIFO queue. The arbitration module uses a round-robin approach to arbitrate multiple hardware events in the event FIFO queue, and sends the hardware events that pass arbitration to the work management engine.

2. The method according to claim 1, characterized in that, In response to the interruption event of the task data packet generation function, and to notify the software engine connected to the hardware-software association engine device, the following steps are taken: The buffer FIFO queue is monitored in real time to determine whether the interruption conditions are met. If the interruption conditions are met, multiple task data packets in the buffer FIFO queue are aggregated, and a functional interruption is generated. The interruption conditions include the number of data packets in the buffered FIFO queue reaching a first preset data packet threshold or the time the buffered FIFO queue stores data packets reaching a first preset time threshold. The first preset data packet threshold is obtained and determined from the software engine.

3. The method according to claim 1, characterized in that, The conditions for the occurrence of the event include: The number of data packets in the cached FIFO queue reaches the second preset data packet threshold; Or the time for which the cached FIFO queue stores data packets reaches a second preset time threshold.

4. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1 to 3.

5. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method described in any one of claims 1 to 3.

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