Register combination method and device, electronic equipment and computer readable storage medium

Abstract

The application relates to a register combination method and device, electronic equipment and a computer readable storage medium, and belongs to the field of integrated circuit design. The register combination method comprises the following steps: acquiring first timing information of each boundary register in an integrated circuit design, first port position information of each boundary register, and a first logical correlation coefficient between the boundary registers; and grouping all the boundary registers based on the first timing information, the first port position information and the first logical correlation coefficient to obtain a register grouping result. The application combines the boundary registers by comprehensively considering multiple factors, can bring a higher combination rate and more accurate register combination, and can bring a better timing result in subsequent optimization of design implementation.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design, and specifically relates to a register combination method, apparatus, electronic device and computer-readable storage medium. Background Technology

[0002] In the process of integrated circuit design and implementation, in order to achieve better timing and power consumption, it is often necessary to combine multiple single-bit registers, usually combining 2, 4, or 8 registers, and then replacing the register combination with a multi-bit register. The general register combination is basically implemented by Electronic Design Automation (EDA) tools.

[0003] As integrated circuit design becomes larger and more complex, the precision requirements for register assembly become higher, especially for boundary registers driven by input ports or output ports. These registers are called boundary registers. Since typical assembly methods relying on EDA tools often only consider the timing of registers when assembling them, the assembly results obtained by automated tools often fail to meet expectations, leading to unexpected conflicts in timing convergence between modules. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a register combination method, apparatus, electronic device, and computer-readable storage medium to improve the problem of unsatisfactory combination effect of existing register combination methods.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, embodiments of this application provide a register grouping method, comprising: acquiring first timing information of each boundary register in an integrated circuit design, first port location information of each boundary register, and a first logical dependency coefficient between the boundary registers; and grouping all boundary registers based on the first timing information, the first port location information, and the first logical dependency coefficient to obtain register grouping results.

[0007] In this embodiment, combining multiple factors (such as timing information, port location information, and logical dependencies) to combine boundary registers can result in more accurate register combination effects and better timing results in subsequent optimizations of the design and implementation.

[0008] In one possible implementation of the first aspect embodiment, based on the first timing information, the first port location information, and the first logical correlation coefficient, all boundary registers are grouped to obtain register grouping results, including: performing first-level grouping of all boundary registers based on the first timing information to obtain first-level grouping results; performing second-level grouping of the first-level grouping results based on the first port location information to obtain second-level grouping results; and performing third-level grouping of the second-level grouping results based on the first logical correlation coefficient to obtain register grouping results.

[0009] By grouping all boundary registers using the above method, we can obtain the ideal register combination scheme more quickly and accurately, and provide a higher combination rate.

[0010] In one possible implementation of the first aspect embodiment, the first timing information includes receiver timing information and transmitter timing information. Based on the first timing information, all boundary registers are grouped at a first level to obtain a first-level grouping result. This includes: grouping all boundary input registers at a first level based on the receiver timing information, and grouping all boundary output registers at a first level based on the transmitter timing information; wherein, during grouping, boundary registers within a specified range of the receiver timing information or the transmitter timing information are grouped together.

[0011] In this embodiment of the application, when performing first-level grouping of boundary registers, boundary output registers and boundary input registers are grouped separately. During grouping, boundary registers whose timing information of the receiving end or the timing information of the transmitting end is within a specified range are grouped together. This can ensure that the timing of the registers in the group is good.

[0012] In one possible implementation of the first aspect embodiment, the first-level grouping result is grouped into a second-level grouping result based on the first port location information, including: determining the Manhattan distance between two corresponding boundary registers based on the first port location information of each pair of boundary registers in the first-level grouping result; and performing the second-level grouping result based on the Manhattan distance to obtain the second-level grouping result.

[0013] In this embodiment, the boundary registers are grouped in two stages based on the port location distance (Manhattan distance), which can effectively prevent boundary registers with large port location distances from being grouped together, thereby reducing the adverse effects on subsequent timing optimization.

[0014] In one possible implementation of the first aspect embodiment, the second-level grouping results are grouped into third-level groups based on the first logical correlation coefficient to obtain register grouping results, including: grouping the multiple registers with the best first logical correlation coefficient in the second-level grouping results into a group to obtain register grouping results.

[0015] In this embodiment of the application, the multiple registers with the best first logical correlation coefficient in the secondary grouping results are grouped together, which can help with subsequent timing optimization.

[0016] In one possible implementation of the first aspect embodiment, obtaining the first logical correlation coefficient between the boundary registers includes: for any two boundary registers among all boundary registers, determining the first logical correlation coefficient between the two boundary registers based on the area of ​​the circular region where the two boundary registers are located and the correlation between the circular regions where the two boundary registers are located, wherein the circular region where each boundary register is located is obtained by drawing a circle with a specified position as the center and a specified radius.

[0017] In this embodiment, the logical correlation coefficient between boundary registers is solved by the spatial positional relationship of the boundary registers, thereby quickly and accurately obtaining the logical correlation coefficient between the boundary registers.

[0018] In one possible implementation of the first aspect embodiment, if the correlation indicates that the circular regions where the two boundary registers are located do not intersect, then the first logical correlation coefficient is a default value; if the correlation indicates that the circular regions where the two boundary registers are located intersect, then the first logical correlation coefficient is determined based on the intersection area of ​​the circular regions where the two boundary registers are located and the area of ​​the circular regions where the two boundary registers are located; if the correlation indicates that the circular regions where the two boundary registers are located have an inclusion relationship, then the first logical correlation coefficient is determined based on the area of ​​the circular regions where the two boundary registers are located.

[0019] In this embodiment, different logical correlation coefficients are solved based on the correlation between two circular regions. Through fine subdivision, the logical correlation coefficients between registers can be determined more accurately.

[0020] In one possible implementation of the first aspect embodiment, after obtaining the register grouping result, the method further includes: acquiring second timing information of each specified register in the integrated circuit design, second port location information of each specified register, and a second logical dependency coefficient between the registers; wherein, one specified register is a multi-bit register or a remaining boundary register; wherein, the remaining boundary register is the boundary register remaining among all boundary registers in the integrated circuit design after being replaced by a multi-bit register, and the multi-bit register is obtained by replacing multiple registers divided into the same group in the register grouping result; based on the second timing information, the second port location information, and the second logical dependency coefficient, all specified registers are grouped to obtain the register grouping result.

[0021] In this embodiment of the application, after obtaining the register grouping result, the multi-bit registers and the remaining boundary registers can also be grouped. That is, the multi-bit registers and the remaining boundary registers are treated as designated registers and the designated registers are grouped. By repeating the above grouping method, register groups with undesirable timing or logical dependencies can be re-split and grouped, thereby achieving more accurate grouping, and finally obtaining better timing and register combinations, and obtaining better timing results.

[0022] Secondly, embodiments of this application also provide a register combination device, including: an acquisition module and a grouping module; the acquisition module is used to acquire first timing information of each boundary register in the integrated circuit design, first port location information of each boundary register, and a first logical dependency coefficient between the boundary registers; the grouping module is used to group all boundary registers based on the first timing information, the first port location information, and the first logical dependency coefficient to obtain register grouping results.

[0023] Thirdly, embodiments of this application also provide an electronic device, including: a memory and a processor, the processor being connected to the memory; the memory being used to store a program; the processor being used to invoke the program stored in the memory to perform a method provided as described in the first aspect embodiments and / or in combination with any possible implementation of the first aspect embodiments.

[0024] Fourthly, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the method provided by any possible implementation of the first aspect embodiments and / or in combination with the first aspect embodiments.

[0025] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features and advantages of this application will become clearer through the drawings.

[0027] Figure 1 A flowchart illustrating a register combination method provided in an embodiment of this application is shown.

[0028] Figure 2 This illustration shows a schematic diagram of the relationship between two circular regions containing boundary registers, as provided in an embodiment of this application.

[0029] Figure 3 This illustration shows a schematic diagram of the principle of boundary register grouping provided in an embodiment of this application.

[0030] Figure 4 The illustration shows an example diagram of an edge register combination provided in an embodiment of this application.

[0031] Figure 5 This illustration shows a schematic diagram of another boundary register grouping principle provided in an embodiment of this application.

[0032] Figure 6 A schematic diagram of a register combination device provided in an embodiment of this application is shown.

[0033] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0035] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0037] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "electrical connection" can refer to a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0038] Given that current boundary register combination methods (considering only the timing of boundary registers) often fail to achieve the desired results, this application provides a register combination method, apparatus, electronic device, and computer-readable storage medium. These methods and apparatuses can accurately and effectively combine registers based on their timing information, port location information, and logical dependencies, achieving higher-precision grouping of boundary registers. Compared with existing technologies, this application offers the following advantages:

[0039] (1) By analyzing the port positions of the boundary registers, this application can effectively prevent the combination of boundary registers with far-away port positions, improve the shortcomings of the general boundary register combination method that ignores the port positions, and thus be more conducive to subsequent timing optimization.

[0040] (2) This application analyzes the logical dependencies between boundary registers and combines the boundary registers based on the logical dependencies, which can effectively improve the accuracy of boundary register combination.

[0041] (3) This application combines multiple factors to combine boundary registers, which can bring higher combination rate and more accurate register combination, and can bring better timing results in the subsequent optimization of design and implementation.

[0042] To better understand, let's combine the following... Figure 1 The register combination method provided in the embodiments of this application will be described.

[0043] S1: Obtain the first timing information of each boundary register in the integrated circuit design, the first port location information of each boundary register, and the first logical dependency coefficient between the boundary registers.

[0044] The aforementioned integrated circuit design can be customized as needed; for example, it can be a cache control logic design. Different integrated circuits will have different numbers of boundary registers, as well as different first timing information, first port location information, and first logic dependency coefficients between boundary registers.

[0045] A boundary register is a register in an integrated circuit that interacts with the outside world, including boundary input registers and boundary output registers. The input of the boundary input register comes from the outside world, and the output of the boundary output register is sent to the outside world. The register located between the boundary input register and the boundary output register is called an intermediate register.

[0046] When grouping boundary registers, it is typically done by grouping all boundary input registers and all boundary output registers separately. When grouping boundary input registers, it is necessary to obtain the first timing information, the first port location information, and the first logical dependency coefficient between each boundary input register in the integrated circuit design. Similarly, when grouping boundary output registers, it is necessary to obtain the first timing information, the first port location information, and the first logical dependency coefficient between each boundary output register in the integrated circuit design.

[0047] The first timing information of the boundary register represents the relationship between the clock and the data, including the delay required for the data to travel from the input register to the output register, and the relationship between the data end time and the sampling edge, i.e., the timing relationship of the register setup time and hold time.

[0048] In one implementation, the first timing information includes receiver timing information and transmitter timing information; for the boundary input register, its first timing information may be receiver timing information, and for the boundary output register, its first timing information may be transmitter timing information.

[0049] The first port location information of a boundary register refers to the coordinates of its data input port or data output port. For example, for a boundary input register, its first port location information is the coordinates of its data input port; for a boundary output register, its first port location information is the coordinates of its data output port. Each component in an integrated circuit (including boundary registers) has its own coordinates.

[0050] The first logical correlation coefficient between boundary registers characterizes the direction of data flow between multiple boundary registers. It can be solved by the spatial relationship between the boundary registers. The stronger the logical correlation, the higher the overlap of the data flow direction of the boundary registers.

[0051] The first logical correlation coefficient between boundary registers can be determined based on the area of ​​the circular region where the boundary registers are located and the correlation between the circular regions where different boundary registers are located. For example, in one implementation, the first logical correlation coefficient between boundary registers can be obtained in the following way:

[0052] For any two boundary registers among all boundary registers, the first logical correlation coefficient between the two boundary registers is determined based on the area of ​​the circular region where the two boundary registers are located and the correlation between the circular regions where the two boundary registers are located. The circular region where each boundary register is located is obtained by drawing a circle with a specified position as the center and a specified radius.

[0053] For example, for any two boundary input registers, the first logical correlation coefficient between them is determined based on the area of ​​the circular region containing the two boundary input registers and the correlation between these circular regions. The circular region containing each boundary input register is obtained by drawing a circle with the average position coordinates of all fan-out cells of that register as its center and the standard deviation of the positions of all fan-out cells as its radius.

[0054] For boundary output registers, for any two boundary output registers, the first logical correlation coefficient between the two boundary output registers is determined based on the area of ​​the circular region where the two boundary output registers are located and the correlation between the circular regions where the two boundary output registers are located. The circular region where each boundary output register is located is obtained by drawing a circle with the average position coordinates of all fan-in cells of its own boundary output register as the center and the standard deviation of the positions of all fan-in cells of its own boundary output register as the radius.

[0055] The relationship between the circular regions containing the two boundary registers can be categorized as intersecting, non-intersecting, or containing. A schematic diagram is shown below. Figure 2 As shown, Figure 2 In the diagram, (a) indicates non-intersecting elements. Figure 2 (b) in the diagram represents intersection. Figure 2 (c) in the text represents an inclusion relationship.

[0056] If the correlation indicates that the circular regions containing two boundary registers (which can be boundary input registers or boundary output registers) do not intersect, then the first logical correlation coefficient is the default value, for example, zero.

[0057] If the correlation indicates that the circular regions containing the two boundary registers intersect, then the first logical correlation coefficient is determined based on the intersection area of ​​the circular regions containing the two boundary registers and the area of ​​the circular regions containing the two boundary registers. For example, it can be determined using the formula C = γ*S. overlap / (S R1 +S R2 Determine the first logical relevance coefficient, where C represents the first logical relevance coefficient, and S... overlap S is the area of ​​intersection. R1 S represents the area of ​​the circular region containing boundary register R1. R2 γ is the area of ​​the circular region where the boundary register R2 is located, and γ is the multiplication coefficient, which is an empirical value used to normalize the first logic correlation coefficient.

[0058] If the correlation indicates that the circular regions containing the two boundary registers are inclusive, then the first logical correlation coefficient is determined based on the area of ​​the circular regions containing the two boundary registers. For example, it can be determined using the formula C = γ * min(S R1 ,S R2 ) / max(S R1 ,S R2 Determine the first logical relevance coefficient.

[0059] In one possible implementation, when γ = 1, the multiplication coefficients mentioned above can be ignored. In this case, when the correlation relationship indicates that the circular regions where the two boundary registers are located intersect or have an inclusion relationship, the first logical correlation coefficient between the two boundary registers can be determined by directly using the formula mentioned above that omits γ.

[0060] The average position coordinates of all fan-in or fan-out units can be obtained using the following formula:

[0061] E(x,y)=∑D i (x,y) / n, where E(x,y) is the average position coordinate, and D... i(x,y) represents the position coordinates of the i-th fan-in or fan-out unit, and n represents the number of fan-in or fan-out units.

[0062] The positional standard deviation of all fan-in or fan-out elements can be obtained using the following formula:

[0063] Where σ is the standard deviation of the location.

[0064] In one alternative implementation, besides using the standard deviation of position as the radius, the product of the standard deviation of position and an empirical coefficient can also be used as the radius, as expressed by the following formula:

[0065] Where R is the radius and λ is an empirical coefficient. The empirical coefficient λ is mainly used to adjust the radius of the circle. When fan-in or fan-out cells are concentrated, the position standard deviation is very small, which causes two circles with high actual logical correlation to be unable to intersect. Introducing the empirical coefficient can reduce the occurrence of this situation.

[0066] S2: Based on the first timing information, the first port location information, and the first logic correlation coefficient, all boundary registers are grouped to obtain the register grouping results.

[0067] After obtaining the first timing information, the first port location information, and the first logical correlation coefficient, all boundary registers can be grouped based on the first timing information, the first port location information, and the first logical correlation coefficient to obtain the register grouping results.

[0068] In one optional implementation, when grouping all boundary registers, the grouping can be performed separately for all boundary input registers and all boundary output registers. In this case, the implementation process of S2 can be: grouping all boundary input registers based on the first timing information of each boundary input register, the first port location information of each boundary input register, and the first logical dependency coefficient between boundary input registers to obtain register grouping results; and grouping all boundary output registers based on the first timing information of each boundary output register, the first port location information of each boundary output register, and the first logical dependency coefficient between boundary output registers to obtain register grouping results.

[0069] In one optional implementation, when grouping all boundary registers, timing information, port location information, and logic dependency coefficients can be considered simultaneously, or they can be considered step by step. For example, in one possible implementation, the process of S2 can be: performing a first-level grouping (also called pre-grouping) on ​​all boundary registers (which can be boundary input registers or boundary output registers) based on the first timing information to obtain the first-level grouping result; performing a second-level grouping on the first-level grouping result based on the first port location information to obtain the second-level grouping result; and performing a third-level grouping on the second-level grouping result based on the first logic dependency coefficient to obtain the register grouping result. The schematic diagram is shown below. Figure 3 As shown.

[0070] Grouping boundary registers by port location effectively prevents boundary registers with widely dispersed port locations from being grouped together, thus reducing the impact on subsequent optimizations. For example, using... Figure 4 Taking the four boundary registers shown as an example, typical boundary register grouping methods often group these four registers into one group. However, the port locations of boundary register 1 and boundary register 4 are actually quite far apart. When these four boundary registers are grouped together, subsequent optimizations will always result in a situation where the combined register is far from a certain port, leading to timing issues. Through the two-level grouping based on port distance in this application, boundary register 1 and boundary register 4 will not be grouped together due to their large port distance, effectively avoiding the aforementioned problem.

[0071] The boundary register combination method based on logical dependence can effectively separate the boundary registers of different logic groups. For example, Figure 4 Taking the four boundary register combinations shown as an example, after performing logical dependency analysis, registers 1, 2 and 3 and 4 can be grouped into different groups, which can help with subsequent timing optimization.

[0072] In one implementation, the process of S2 can also be to perform a first-level grouping of all boundary registers (which may be boundary input registers or boundary output registers) based on the first timing information, and the process of obtaining the first-level grouping result can be: performing a second-level grouping of the first-level grouping result based on the first logical correlation coefficient to obtain the second-level grouping result; and performing a third-level grouping of the second-level grouping result based on the first port location information to obtain the register grouping result.

[0073] In one implementation, the first timing information includes receiver timing information and transmitter timing information. The process of performing a first-level grouping of all boundary registers based on the first timing information to obtain a first-level grouping result can be: performing a first-level grouping of all boundary input registers based on receiver timing information, and performing a first-level grouping of all boundary output registers based on transmitter timing information to obtain a first-level grouping result; wherein, during grouping, boundary registers within a specified range of receiver timing information or transmitter timing information are grouped together.

[0074] When performing first-level grouping, timing state differences (such as timing violations exceeding a set value T) can be eliminated. thr The boundary registers of this part will not be grouped. The grouping is as follows:

[0075] Group 1:T launch <T i or T capture <T j ;

[0076] Group 2:T i+1 <T launch <T i+2 or T j+1 <T capture <T j+2 ; ......

[0078] Group n:T i+2n-1 <T launch <T i+2n or T j+2n-1 <T capture <T j+2n

[0079] Where Group 1, Group 2, and Group n are the names of the first-level groups, and it can be understood that the grouping results can include multiple groups; T launch For the timing information of the sending end, T capture For the timing information of the receiving end, T i T i+1 T i+2 T i+2n-1 T i+2n T j T j+1 T j+2 T j+2n-1 T j+2n For the timing constraints during grouping, T thr To abandon the timing restrictions of grouping.

[0080] During the grouping process, the timing information of the receiving end (corresponding to the boundary input register) and the timing information of the transmitting end (corresponding to the boundary output register) are grouped separately.

[0081] In one implementation, the process of performing secondary grouping on the primary grouping result based on the first port location information to obtain the secondary grouping result can be as follows: determine the Manhattan distance between the corresponding two boundary registers based on the first port location information of each pair of boundary registers in the primary grouping result; perform secondary grouping on the primary grouping result based on the Manhattan distance to obtain the secondary grouping result.

[0082] If a first-level grouping result contains four boundary registers, then these four boundary registers are grouped together. The Manhattan distance needs to be calculated between every two boundary registers, for a total of six Manhattan distances. The Manhattan distance can be calculated using the following formula:

[0083] L = |P1(x)-P2(x)|+|P1(y)-P2(y)|, where L is the Manhattan distance, P1 is the port corresponding to register R1, P2 is the port corresponding to register R2, x is the x-coordinate value, and y is the y-coordinate value.

[0084] When performing secondary grouping on the first-level grouping results based on Manhattan distance, the boundary registers whose Manhattan distance is less than a set distance value in the first-level grouping results can be grouped together. The principle of secondary grouping is as follows:

[0085]

[0086] Where sub_group 1 and sub_group 2 are the second-level groupings, L i For Manhattan distance, L set Set the distance value.

[0087] When performing secondary grouping, only those that meet the criteria are grouped together; those that do not meet the criteria may not be grouped.

[0088] Understandably, by performing secondary grouping based on the primary grouping results, multiple secondary grouping results can be obtained. For example, if the primary grouping results contain 10 boundary registers, and assuming that boundary registers 1 to 4 are physically close, boundary registers 5 to 8 are physically close, and boundary registers 9 to 10 are physically close, then they can be divided into three groups. This can be understood as the registers being in clusters, where the Manhattan distance between each cluster is, for example, less than a set value of 100, and the distance between clusters is greater than the set value of 100. Thus, by simply setting a single value of 100, they can be divided into multiple groups.

[0089] The process of performing tertiary grouping on the secondary grouping results based on the first logical correlation coefficient to obtain the register grouping results can be as follows: Group the registers with the best (e.g., largest) first logical correlation coefficients in the secondary grouping results into one group to obtain the register grouping results. For example, the boundary registers in the secondary grouping results can be sorted according to their logical correlation coefficients; based on the sorting results, the registers with the largest logical correlation coefficients can be grouped into one group to obtain the register grouping results.

[0090] Assuming the secondary grouping result includes four boundary registers (let's say boundary register R1, boundary register R2, boundary register R3, and boundary register R4), then there are six first logical dependence coefficients involved. If two boundary registers are grouped together, then during the grouping process, these six first logical dependence coefficients can be compared, and the one with the largest logical dependence coefficient can be grouped together. For example, if the logical dependence coefficient between boundary register R2 and boundary register R3 is the largest, then boundary register R2 and boundary register R3 can be grouped together. As for boundary register R1 and boundary register R4, they can be grouped together or not.

[0091] When performing three-level grouping, only those that meet the criteria are grouped together, while those that do not meet the criteria are not grouped.

[0092] In one optional implementation, the optimal logical correlation coefficient is not limited to the largest logical correlation coefficient. For example, if the circles containing boundary registers R2 and R3 are inclusive, the corresponding logical correlation coefficient is the largest. If the circles containing boundary registers R1 and R4 do not intersect, the corresponding logical correlation coefficient is the smallest. If the circles containing boundary registers R1 and R2 intersect, and the circles containing boundary registers R3 and R4 intersect, then boundary registers R1 and R2 can be grouped together, and boundary registers R3 and R4 can be grouped together. This ensures that the logical correlation between the two boundary registers in each group is moderate and avoids extreme cases, such as grouping two boundary registers with zero logical correlation together.

[0093] Among them, in adopting Figure 3 When performing boundary register grouping in the hierarchical manner shown, the port location distance (Manhattan distance) can be calculated after the first level of grouping is completed, and the logical dependency coefficient between boundary registers can be calculated after the second level of grouping is completed.

[0094] To better understand the above combination process, the following will combine... Figure 5 The schematic diagram shown is used for explanation. It is understandable that... Figure 5The schematic diagram shown is only one of many embodiments in this application. For the acquired boundary registers, boundary registers whose timing does not meet the set values ​​are not grouped; only boundary registers whose timing meets the requirements are pre-grouped (first-level grouping), resulting in multiple pre-grouping results. For each pre-grouping result, the port position distance between every two boundary registers in the pre-grouping result is calculated, and this distance is used for second-level grouping, resulting in multiple second-level grouping results. For each second-level grouping result, the logic dependency coefficient between every two boundary registers in the second-level grouping result is calculated, and this coefficient is used for boundary register combination, resulting in multiple boundary register combination results.

[0095] In one optional implementation, after obtaining the register grouping result, the register combination method may further include: acquiring second timing information of each specified register in the integrated circuit design, second port location information of each specified register, and a second logical dependency coefficient between registers; and grouping all specified registers based on the second timing information, second port location information, and second logical dependency coefficient to obtain a register grouping result. Wherein, a specified register is a multi-bit register or a remaining boundary register; wherein, the remaining boundary register is the boundary register remaining among all boundary registers in the integrated circuit design after being replaced by a multi-bit register, and the multi-bit register is obtained by replacing multiple registers divided into the same group in the register grouping result.

[0096] In this implementation, after obtaining the register grouping results, multiple registers grouped into the same group can be replaced with corresponding multi-bit registers based on these results. For example, if two registers are grouped into the same group, they can be replaced with a 2-bit register; if four registers are grouped into the same group, they can be replaced with a 4-bit register. After completing the boundary register grouping and replacement, the new port positions and timing information of the multi-bit registers can be obtained. Then, the multi-bit registers and the remaining boundary registers can be grouped. That is, the multi-bit registers and the remaining boundary registers are treated as designated registers, and these designated registers are grouped.

[0097] The principle for grouping specified registers is the same as the grouping principle described above. It also requires obtaining timing information, port location information, and logic dependency coefficients for grouping. By repeating the above grouping method, register groups with unsatisfactory timing or logic dependency can be re-split and grouped. In actual design and implementation, this process can be repeated iteratively multiple times, splitting and reorganizing the register groups in multiple rounds to achieve more accurate grouping, ultimately obtaining better timing and register combinations, and achieving better timing results.

[0098] Since multi-bit registers are obtained by replacing multiple registers grouped together, and have multiple data input or output ports, grouping multi-bit registers involves acquiring multiple timing information for the same register and grouping them accordingly. This process may also involve register reassembly and splitting. Similarly, when calculating port location distances (Manhattan distances), for the same multi-bit register, the Manhattan distances between each pair of its ports need to be calculated, and register grouping is performed accordingly. This process may also involve register reassembly and splitting. Likewise, when calculating logical dependencies, multiple circular regions are drawn for the same multi-bit register to calculate pairwise logical dependencies and group the registers accordingly. This process may also involve register reassembly and splitting. In short, when grouping multi-bit registers, they are treated as multiple single registers, which is similar to the processing logic described above for single boundary registers.

[0099] In practical design and implementation, the boundary register combination method based on timing, port location, and logical dependence proposed in this application achieves a higher combination rate. Furthermore, comparative verification demonstrates that this application effectively avoids combining boundary registers with widely dispersed port locations. In subsequent timing optimization, the boundary register combination method of this application yields better timing results than general register combination methods, proving that this application achieves higher accuracy in boundary register combination methods based on logical dependence.

[0100] This application embodiment also provides a register combination device 110, such as Figure 6 As shown, the register combination device 100 includes an acquisition module 110 and a grouping module 120.

[0101] The acquisition module 110 is used to acquire the first timing information of each boundary register in the integrated circuit design, the first port location information of each boundary register, and the first logical correlation coefficient between the boundary registers.

[0102] The grouping module 120 is used to group all boundary registers based on the first timing information, the first port location information and the first logic correlation coefficient to obtain register grouping results.

[0103] The grouping module 120 is used to perform first-level grouping of all boundary registers based on the first timing information to obtain first-level grouping results; to perform second-level grouping of the first-level grouping results based on the first port location information to obtain second-level grouping results; and to perform third-level grouping of the second-level grouping results based on the first logical correlation coefficient to obtain register grouping results.

[0104] The grouping module 120 is used to perform first-level grouping of all boundary input registers based on the receiving end timing information and to perform first-level grouping of all boundary output registers based on the transmitting end timing information to obtain first-level grouping results; wherein, during grouping, the boundary registers within a specified range of the receiving end timing information or the transmitting end timing information are grouped into one group.

[0105] The grouping module 120 is used to determine the Manhattan distance between two boundary registers based on the first port position information of each pair of boundary registers in the first-level grouping result; and to perform second-level grouping on the first-level grouping result based on the Manhattan distance to obtain the second-level grouping result.

[0106] Grouping module 120 is used to group the multiple registers with the best first logical correlation coefficient in the secondary grouping results into a group to obtain register grouping results.

[0107] The acquisition module 110 is used to determine the first logical correlation coefficient between any two boundary registers among all boundary registers, based on the area of ​​the circular region where the two boundary registers are located and the correlation between the circular regions where the two boundary registers are located. The circular region where each boundary register is located is obtained by drawing a circle with a specified position as the center and a specified radius.

[0108] The acquisition module 110 is further configured to acquire second timing information of each specified register in the integrated circuit design, second port location information of each specified register, and second logical dependency coefficient between the registers; wherein, one specified register is a multi-bit register or a remaining boundary register; wherein, the remaining boundary register is the boundary register remaining in all boundary registers in the integrated circuit design except for those replaced by multi-bit registers, and the multi-bit register is obtained by replacing multiple registers in the same group according to the register grouping result.

[0109] The grouping module 120 is used to group all specified registers based on the second timing information, the second port location information, and the second logic correlation coefficient to obtain register grouping results.

[0110] The register combination device 100 provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0111] like Figure 7 As shown, Figure 7This diagram illustrates a structural block diagram of an electronic device 200 provided in an embodiment of this application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

[0112] The transceiver 210, memory 220, and processor 240 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, such as... Figure 6 The software functional module shown is the register combination device 100. The register combination device 100 includes at least one software functional module that can be stored in the memory 220 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 200. The processor 240 is used to execute executable modules stored in the memory 220, such as the software functional module or computer program included in the register combination device 100. For example, the processor 240 is used to acquire first timing information of each boundary register in the integrated circuit design, first port location information of each boundary register, and a first logical dependency coefficient between the boundary registers; based on the first timing information, the first port location information, and the first logical dependency coefficient, all boundary registers are grouped to obtain register grouping results.

[0113] The memory 220 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0114] Processor 240 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, processor 240 can also be any conventional processor.

[0115] Among them, the aforementioned electronic devices 200 include, but are not limited to, mobile phones, tablets, computers, servers, etc.

[0116] This application embodiment also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which, when run by a computer such as the electronic device 200 described above, executes the register combination method described above.

[0117] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0119] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0120] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0121] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A register combination method, characterized in that, include: The first timing information of each boundary register in the integrated circuit design, the first port location information of each boundary register, and the first logical correlation coefficient between the boundary registers are obtained. The first logical correlation coefficient characterizes the direction of data flow between multiple boundary registers. Based on the first timing information, the first port location information, and the first logical correlation coefficient, all boundary registers are grouped to obtain register grouping results. Obtaining the first logical correlation coefficient between the boundary registers includes: For any two boundary registers among all boundary registers, a first logical correlation coefficient between the two boundary registers is determined based on the area of ​​the circular region where the two boundary registers are located and the correlation between the circular regions where the two boundary registers are located. The circular region where each boundary register is located is obtained by drawing a circle with a specified position as the center and a specified radius. Based on the first timing information, the first port location information, and the first logic correlation coefficient, all boundary registers are grouped to obtain register grouping results, including: Based on the first timing information, all boundary registers are grouped into first-level groups to obtain the first-level grouping results; The first-level grouping result is then divided into second-level groups based on the first port location information to obtain the second-level grouping result. Based on the first logical correlation coefficient, the secondary grouping results are grouped into tertiary groups to obtain register grouping results.

2. The register combination method according to claim 1, characterized in that, The first timing information includes receiver timing information and transmitter timing information. Based on the first timing information, all boundary registers are grouped at the first level to obtain the first-level grouping result, which includes: Based on the timing information of the receiving end, all boundary input registers are grouped into a first-level group, and based on the timing information of the transmitting end, all boundary output registers are grouped into a first-level group, to obtain the first-level grouping result; During grouping, the boundary registers of the receiving end timing information or the sending end timing information within a specified range are grouped together.

3. The register combination method according to claim 1 or 2, characterized in that, The first-level grouping result is further grouped into second-level groups based on the first port location information to obtain the second-level grouping result, including: Based on the first port position information of every two boundary registers in the first-level grouping results, determine the Manhattan distance between the corresponding two boundary registers; The first-level grouping results are then grouped into second-level groups based on the Manhattan distance to obtain the second-level grouping results.

4. The register combination method according to claim 1 or 2, characterized in that, Based on the first logical correlation coefficient, the secondary grouping results are further grouped into tertiary groupings to obtain register grouping results, including: The registers with the best first logical correlation coefficient in the secondary grouping results are grouped together to obtain the register grouping results, wherein the registers with the best logical correlation coefficient include those with the largest logical correlation coefficient.

5. The register combination method according to claim 1, characterized in that, If the correlation indicates that the circular regions where the two boundary registers are located do not intersect, then the first logical correlation coefficient is the default value; If the correlation indicates that the circular regions where the two boundary registers are located intersect, then the first logical correlation coefficient is determined based on the intersection area of ​​the circular regions where the two boundary registers are located and the area of ​​the circular regions where the two boundary registers are located. If the correlation indicates that the circular regions where the two boundary registers are located are inclusive, then the first logical correlation coefficient is determined based on the area of ​​the circular regions where the two boundary registers are located.

6. The register combination method according to claim 1, characterized in that, After obtaining the register grouping results, the method further includes: The second timing information of each specified register in the integrated circuit design, the second port location information of each specified register, and the second logical dependency coefficient between the registers are obtained; wherein, one specified register is a multi-bit register or a remaining boundary register; wherein, the remaining boundary register is the boundary register remaining among all boundary registers in the integrated circuit design except for those replaced by multi-bit registers, and the multi-bit register is obtained by replacing multiple registers divided into the same group in the register grouping result; Based on the second timing information, the second port location information, and the second logic dependency coefficient, all specified registers are grouped to obtain the register grouping results.

7. A register combination device, characterized in that, include: The acquisition module is used to acquire the first timing information of each boundary register in the integrated circuit design, the first port location information of each boundary register, and the first logical correlation coefficient between the boundary registers; wherein, the first logical correlation coefficient characterizes the direction of data flow between multiple boundary registers; The grouping module is used to group all boundary registers based on the first timing information, the first port location information, and the first logical correlation coefficient to obtain register grouping results; Obtaining the first logical correlation coefficient between the boundary registers includes: For any two boundary registers among all boundary registers, a first logical correlation coefficient between the two boundary registers is determined based on the area of ​​the circular region where the two boundary registers are located and the correlation between the circular regions where the two boundary registers are located. The circular region where each boundary register is located is obtained by drawing a circle with a specified position as the center and a specified radius. Based on the first timing information, the first port location information, and the first logic correlation coefficient, all boundary registers are grouped to obtain register grouping results, including: Based on the first timing information, all boundary registers are grouped into first-level groups to obtain the first-level grouping results; The first-level grouping result is then divided into second-level groups based on the first port location information to obtain the second-level grouping result. Based on the first logical correlation coefficient, the secondary grouping results are grouped into tertiary groups to obtain register grouping results.

8. An electronic device, characterized in that, include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is configured to invoke a program stored in the memory to execute the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, performs the method as described in any one of claims 1-6.

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