神经网络推理芯片、方法及终端设备
By introducing a control scheduler (SSP), a vector processor (VSP), a multiplication matrix processor (MMP), and a partial sum processor (PSUM) into the neural network inference chip, the reuse of convolutional and non-convolutional computations in non-depth directions is achieved, solving the problem of insufficient computing resource utilization and improving computing efficiency and energy efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP LTD
- Filing Date
- 2022-06-22
- Publication Date
- 2026-07-17
AI Technical Summary
Existing dedicated neural network inference chips suffer from insufficient utilization of computing resources under high computational and memory resource requirements, making it difficult to effectively improve their efficiency.
By introducing a control scheduler (SSP), a vector processor (VSP), a multiplication matrix processor (MMP), and a partial sum processor (PSUM) into the neural network inference chip, the reuse of convolutional and non-convolutional computations in non-depth directions is achieved, sharing hardware computing resources.
It improves the utilization rate of computing resources, reduces the duplication of hardware resources for different computing types, and enhances the computing efficiency and energy efficiency of the chip.
Smart Images
Figure CN117332809B_ABST