A neuron circuit, application method, neuron chip and electronic device

Abstract

This application provides a neuron circuit, application method, neuron chip, and electronic device. The neuron circuit can simulate various characteristics of a neuron, including integration characteristics, leakage characteristics, threshold firing characteristics, delayed reset characteristics, and adaptive characteristics. This neuron circuit converts the weighting coefficients of a digital signal into an analog signal of the neuron in the time dimension. The configuration of the neuron's parameters can be accomplished by modifying the weighting coefficients, greatly reducing computational overhead. It also avoids the use of complex devices such as traditional digital-to-analog converters and large-area capacitors, significantly saving space.

Description

Technical Field

[0001] This application relates to the field of spiking neural network computing technology, and in particular to a neuron circuit, application method, neuron chip, and electronic device. Background Technology

[0002] Spiking Neural Networks (SNNs) are neural networks that mimic the connection and encoding mechanisms of the brain, characterized by low power consumption, low latency, and spatiotemporal characteristics. A spiking neural network comprises numerous neurons that are not activated in every iteration, but rather when their membrane potential reaches a specific value. When a neuron is activated, it generates a signal that is transmitted to other neurons, raising or lowering their membrane potentials. Unlike traditional artificial neural networks, spiking neural networks use pulses to encode information, making them more similar to biological nervous systems. Therefore, neurons in a spiking neural network need to possess one or more characteristics of biological neurons, such as integration, leakage, fire, and adaptation. The specific characteristics included depend on the actual application scenario and algorithm.

[0003] One method of implementing a neuron involves using multiple capacitors, each with a capacitance value proportional to the unit capacitance, to form a neuron circuit. This neuron circuit converts digital signal weights into analog voltage signals using multiple capacitors, and then accumulates these analog voltage signals onto the membrane potential using an adder circuit, thereby simulating the integration characteristics of a neuron. However, this neuron circuit requires a large number of capacitors to convert digital signals into analog voltage signals, and the capacitors occupy an excessively large area. Summary of the Invention

[0004] This application provides a neuron circuit, application method, neuron chip, and electronic device, which solves the problems of a large number of capacitors and excessively large capacitor area.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a neuron circuit is provided, comprising a pulse width conversion circuit, a first capacitor, and a threshold comparator; the output of the pulse width conversion circuit is coupled to the first capacitor and the first input of the threshold comparator; the second input of the threshold comparator is used to input a threshold voltage; the voltage of the first capacitor is used to indicate the membrane potential of the neuron circuit; the pulse width conversion circuit is used to: input an enable signal and a weighting coefficient including multiple bits, and when the enable signal is valid, output multiple first levels corresponding to the multiple bits of the weighting coefficient to the first capacitor, the high or low level of each first level is determined by the value of a corresponding bit in the weighting coefficient, and the duration of each first level is determined by the number of bits of the corresponding bit in the weighting coefficient; when the first level is high, the first capacitor is charged, and when the first level is low, the first capacitor is discharged; the threshold comparator is used to: compare the voltage of the first capacitor with the threshold voltage, and if the voltage of the first capacitor is greater than or equal to the threshold voltage, output a high level.

[0007] In this embodiment, the weighting coefficients, in digital signal form, are converted into analog signals in the time dimension using a pulse width conversion circuit. The pulse width conversion circuit receives an enable signal and a first level output from a first memory, and determines whether to output a high or low level to a first capacitor based on the enable signal and the first level. The high and low levels output by the pulse width conversion circuit charge and discharge the first capacitor, thereby reducing the area overhead of the neuron circuit while simulating the integration characteristics of a neuron. A threshold comparator compares the voltage of the first capacitor with a threshold voltage. When the voltage of the first capacitor is greater than or equal to the threshold voltage, the threshold comparator outputs a high level, thus simulating the threshold firing characteristics of the neuron.

[0008] In one possible implementation, the pulse width conversion circuit includes a first controller and a first switch array; the first switch array includes a plurality of first switches; the first terminal of each first switch is used to input a bit of a weighting coefficient, and the second terminal of each first switch is coupled to a first capacitor and a first input terminal of a threshold comparator; the first controller is used to: input an enable signal and a counting signal of a fixed frequency; when the enable signal is valid, determine the first conduction time of the corresponding first switch according to the number of bits in the plurality of bits of the weighting coefficient, and conduct the corresponding first switch according to the first conduction time, wherein the first conduction time is an integer multiple of the counting signal.

[0009] This application embodiment receives different bits of the weighting coefficient through a first switch and converts a digital signal into an analog signal in the time dimension by controlling the conduction of different first switches. Compared with the method of using a large-area capacitor to simulate different voltages, this application embodiment reduces area overhead while achieving more precise control and simulation of integrated characteristics.

[0010] In one possible implementation, the duration of the level corresponding to the high bit in the weighting coefficient is greater than the duration of the level corresponding to the low bit in the weighting coefficient. By assigning different first conduction times to the first switches corresponding to the weighting coefficients of the bits, different weight values ​​can be assigned to the weighting coefficients.

[0011] In one possible implementation, the neuron circuit further includes a frequency conversion circuit and an equivalent resistance circuit; a first terminal of the equivalent resistance circuit is coupled to the output terminal of the frequency conversion circuit, and a second terminal of the equivalent resistance circuit is coupled to a first capacitor and a first input terminal of a threshold comparator; the frequency conversion circuit is used to: input a leakage velocity constant including multiple bits, and, when the enable signal is invalid, output multiple fixed-period pulse control signals corresponding to the multiple bits of the leakage velocity constant to the equivalent resistance circuit, wherein the number of pulses of each pulse control signal is determined by the value of a corresponding bit in the leakage velocity constant; when the pulse control signal is high, control the equivalent resistance circuit to input the charge stored in the first capacitor, and when the pulse control signal is low, control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

[0012] In this embodiment, a frequency conversion circuit generates a pulse control signal based on the leakage velocity constant. When the pulse control signal is high, it controls the equivalent resistance circuit to input the charge stored in the first capacitor. The charge in the first capacitor is transferred to the equivalent resistance circuit to simulate the leakage characteristics of the neuron. When the pulse control signal is low, it controls the equivalent resistance circuit to release the stored charge, ensuring that the equivalent resistance circuit will not be unable to input the charge stored in the first capacitor due to the stored charge reaching its capacity limit.

[0013] In one possible implementation, the frequency conversion circuit includes a second controller, a second switch array, and an AND gate; the second switch array includes multiple second switches; the first terminal of each second switch is used to input a bit of the leakage velocity constant, and the second terminal of each second switch is coupled to the first input terminal of the AND gate; the second input terminal of the AND gate is used to input a clock signal; the output terminal of the AND gate is coupled to the first terminal of the equivalent resistance circuit as the output terminal of the frequency conversion circuit; the second controller is used to: input a counting signal of a fixed frequency; when the enable signal is invalid, determine the second conduction time of the corresponding second switch according to the number of bits in the multiple bits of the leakage velocity constant, and conduct the corresponding second switch according to the second conduction time, wherein the second conduction time is an integer multiple of the counting signal.

[0014] This embodiment of the application receives different bits of the leakage velocity constant through a second switch, and by controlling the conduction of different second switches, it converts the digital signal into an analog signal in the time dimension. An AND operation is then performed on the analog signal and the clock signal to obtain a pulse control signal including a single pulse. This pulse control signal is used to control the leakage current of the first capacitor. Compared to using a large-area capacitor to simulate different voltages, this embodiment of the application reduces area overhead while achieving more precise control and simulation of leakage characteristics.

[0015] In one possible implementation, the number of pulse control signals corresponding to the high bits of the leakage velocity constant is greater than the number of pulse control signals corresponding to the low bits of the leakage velocity constant.

[0016] In this embodiment, the second conduction time of the second switch corresponding to the high bit is set to be greater than the second conduction time of the second switch corresponding to the low bit, thereby assigning a larger value to the leakage velocity constant of the high bit. This results in a larger number of pulses in the pulse control signal corresponding to the leakage velocity constant.

[0017] In some possible implementations, the second controller is also used to: compare the magnitude of the counting signal with the set value; within a counting cycle: control all second switches to turn off before the counting signal equals the set value; and when the counting information equals the set value and thereafter, turn on the corresponding second switch according to the second on-time when the enable information is invalid.

[0018] This application embodiment stores a set value in a second memory and compares the counting signal with the set value. Within a counting cycle, the corresponding second switch is activated only when the enable signal is invalid, based on a second conduction time, starting from when the counting signal equals the set value. Different application scenarios can be achieved by adjusting the set value. For example, if the set value is set to never equal the counting signal, the neural circuit will be unable to simulate leakage characteristics. When the set value equals the counting signal at certain time intervals, the neural circuit exhibits leakage characteristics. Adjusting the set value can also control the leakage rate, thereby meeting the needs of different applications.

[0019] In one possible implementation, the equivalent resistance circuit includes a second capacitor, a third switch, and a fourth switch; the first terminal of the third switch is coupled to the first input terminal of the threshold comparator, the first capacitor, and the coupling point of the pulse width conversion circuit; the second terminal of the third switch is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is grounded; the first terminal of the fourth switch is coupled to the coupling point between the second terminal of the third switch and the first terminal of the second capacitor; the second terminal of the fourth switch is grounded; the second controller is specifically used to: output a level corresponding to the leakage velocity constant to the third switch and the fourth switch; when the level corresponding to the leakage velocity constant is high, control the third switch to turn on and control the fourth switch to turn off, so as to control the charge stored in the first capacitor input to the equivalent resistance circuit; when the level corresponding to the leakage velocity constant is low, control the third switch to turn off and control the fourth switch to turn on, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

[0020] In this embodiment, a third switch is used to control the second capacitor to receive the charge stored in the first capacitor, thereby discharging the first capacitor and simulating the leakage characteristics of a neuron. A fourth switch is used to discharge the second capacitor, ensuring that the second capacitor can retain the charge stored in the first capacitor.

[0021] In one possible implementation, the equivalent resistance circuit further includes a fifth switch and a sixth switch; the first terminal of the fifth switch is coupled to the second terminal of the second capacitor; the second terminal of the fifth switch is grounded; the first terminal of the sixth switch is coupled to the coupling point between the second terminal of the second capacitor and the first terminal of the fifth switch; the second terminal of the sixth switch is grounded; the second controller is specifically used to: output the level corresponding to the leakage velocity constant to the third switch, the fourth switch, the fifth switch and the sixth switch; when the level corresponding to the leakage velocity constant is high, control the third switch and the fifth switch to turn on and control the fourth switch and the sixth switch to turn off, so as to control the equivalent resistance circuit to input the charge stored in the first capacitor; when the level corresponding to the leakage velocity constant is low, control the third switch and the fifth switch to turn off and control the fourth switch and the sixth switch to turn on, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

[0022] This embodiment achieves circuit symmetry by setting a fifth and a sixth switch. While theoretically the switches are equivalent to wires, in practical applications, they also possess resistance. By setting the fifth and sixth switches, the charge stored in the second capacitor is partially consumed during their alternating switching, aiding in the discharge of the second capacitor and further preventing insufficient discharge that could affect the leakage current from the first capacitor. Furthermore, the product of the resistance of the equivalent resistance circuit and the film potential corresponding to the voltage of the first capacitor determines the leakage velocity constant. Therefore, different leakage velocity constants can adjust the resistance of the equivalent resistance circuit. Under different leakage velocity constants, the switching frequencies of the switches in the equivalent resistance circuit differ. The lower the switching frequency related to leakage current in the neuron circuit, the larger the resistance of the equivalent resistance circuit. Adjusting the resistance of the equivalent resistance circuit using the leakage velocity constant avoids large-area, high-capacitance film potential capacitors, reducing the area overhead of the neuron circuit.

[0023] In one possible implementation, the neuron circuit further includes a delayed reset module; the delayed reset module includes a delay unit, a seventh switch, and a reset voltage unit; the first end of the seventh switch is coupled to the first input terminal of the threshold comparator, the first capacitor, and the coupling point of the pulse width conversion circuit; the second end of the seventh switch is coupled to the reset voltage unit for inputting the reset voltage output by the reset voltage unit; the reset voltage is used to: reduce the voltage of the first capacitor when the seventh switch is turned on; the delay unit is used to receive the high level output by the threshold comparator and send a control signal to the seventh switch after a first time interval; the control signal is used to control the seventh switch to turn on.

[0024] In this embodiment, a high-level signal is input to the threshold comparator via a delay unit, and then output to the seventh switch after a first time interval. The high-level signal of the threshold comparator is used to control the seventh switch to turn on. After the seventh switch turns on, a reset voltage is output to the second capacitor, thereby reducing the voltage of the first capacitor in the second capacitor to simulate the delayed reset characteristic of a neuron. Simultaneously, when the reset voltage is set to a voltage lower than the initial membrane potential of the neuron, during each delayed reset, the voltage of the first capacitor is reduced to a potential lower than the initial membrane potential of the neuron, thereby prolonging the threshold firing of the neuron circuit to simulate the adaptive characteristics of the neuron.

[0025] Secondly, embodiments of this application also provide an application method for a neuron circuit. Based on the neuron circuit, the neuron circuit includes a pulse width conversion circuit and a first capacitor. The voltage of the first capacitor is used to indicate the membrane potential of the neuron circuit. The pulse width conversion circuit includes a first switch array. The first switch array includes multiple first switches. The first terminal of each first switch is used to input one bit of a weighting coefficient, and the second terminal of each first switch is coupled to the first capacitor and the first input terminal of a threshold comparator. The method includes: inputting an enable signal; when the enable signal is valid, determining the first conduction time of the corresponding first switch according to the number of bits of the weighting coefficient, and conducting the corresponding first switch according to the first conduction time; outputting multiple first levels corresponding to the multiple bits of the weighting coefficient to the first capacitor through the conducted first switches; the high or low level of each first level is determined by the value of the corresponding bit in the weighting coefficient, and the duration of each first level is determined by the number of bits of the corresponding bit in the weighting coefficient; charging the first capacitor when the first level is high, and discharging the first capacitor when the first level is low.

[0026] In one possible implementation, the first conduction time is determined by a counting signal, and the first conduction time is an integer multiple of the counting signal.

[0027] In one possible implementation, the duration of the level corresponding to the high bit in the weighting coefficient is greater than the duration of the level corresponding to the low bit in the weighting coefficient.

[0028] In one possible implementation, the neuron circuit further includes a frequency conversion circuit and an equivalent resistance circuit; the frequency conversion circuit includes a second switch array and an AND gate; the second switch array includes a plurality of second switches; the first terminal of each second switch is used to input a bit of a leakage velocity constant including multiple bits, and the second terminal of each second switch is coupled to the first input terminal of the AND gate; the second input terminal of the AND gate is used to input a clock signal; the output terminal of the AND gate is coupled to the first terminal of the equivalent resistance circuit as the output terminal of the frequency conversion circuit; the second terminal of the equivalent resistance circuit is coupled to a first capacitor; the method further includes: when the enable signal is invalid, according to the leakage velocity constant... The number of bits in the number determines the second conduction time of the corresponding second switch, and the corresponding second switch is turned on according to the second conduction time. The turned-on second switch outputs multiple second levels corresponding to multiple bits of the leakage velocity constant to the first input terminal of the AND gate. The high or low level of each second level is determined by the value of a bit in the time. The AND gate outputs multiple fixed-period pulse control signals corresponding to multiple bits of the leakage velocity constant to the equivalent resistance circuit. The pulse control signals control the equivalent resistance circuit to input the charge stored in the first capacitor or control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

[0029] In one possible implementation, the second conduction time is determined by a counting signal, and the second conduction time is an integer multiple of the counting signal.

[0030] In one possible implementation, the number of pulse control signals corresponding to the high bits of the leakage velocity constant is greater than the number of pulse control signals corresponding to the low bits of the leakage velocity constant.

[0031] In one possible implementation, the method further includes: comparing the magnitude of the counting signal with a set value; controlling all second switches to turn off before the counting signal equals the set value within a counting cycle; and turning on the corresponding second switch according to the second on-time when the counting information equals the set value and thereafter, provided that the enable information is invalid.

[0032] In one possible implementation, the equivalent resistance circuit includes a second capacitor, a third switch, and a fourth switch. The first terminal of the third switch is coupled to the first input terminal of the threshold comparator, the first capacitor, and the coupling point of the pulse width conversion circuit. The second terminal of the third switch is coupled to the first terminal of the second capacitor. The second terminal of the second capacitor is grounded. The first terminal of the fourth switch is coupled to the coupling point between the second terminal of the third switch and the first terminal of the second capacitor. The second terminal of the fourth switch is grounded. A pulse control signal controls the equivalent resistance circuit to input the charge stored in the first capacitor or to release the charge stored in the equivalent resistance circuit. Specifically, this includes: outputting a pulse control signal to the third and fourth switches; when the pulse control signal is high, controlling the third switch to turn on and the fourth switch to turn off, thereby controlling the equivalent resistance circuit to input the charge stored in the first capacitor; when the pulse control signal is low, controlling the third switch to turn off and the fourth switch to turn on, thereby controlling the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

[0033] In one possible implementation, the equivalent resistance circuit further includes a fifth switch and a sixth switch; the first end of the fifth switch is coupled to the second end of the second capacitor; the second end of the fifth switch is grounded; the first end of the sixth switch is coupled to the coupling point between the second end of the second capacitor and the first end of the fifth switch; the second end of the sixth switch is grounded; the equivalent resistance circuit is controlled by a pulse control signal to input the charge stored in the first capacitor or to release the charge stored in the equivalent resistance circuit, specifically including: outputting pulse control signals to the third switch, fourth switch, fifth switch, and sixth switch; when the pulse control signal is high, controlling the third switch and fifth switch to conduct and controlling the fourth switch and sixth switch to turn off, so as to control the equivalent resistance circuit to input the charge stored in the first capacitor; when the pulse control signal is low, controlling the third switch and fifth switch to turn off and controlling the fourth switch and sixth switch to conduct, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

[0034] Thirdly, embodiments of this application also provide a neuron chip, which includes a first memory, a second memory, a third memory, a counter, a clock unit, and a plurality of neuron circuits as described in the first aspect; the neuron circuits are coupled to the first memory, the second memory, the third memory, the counter, and the clock unit respectively; the first memory is used to output a weighting coefficient including multiple bits to the neuron circuit; the second memory is used to output a leakage velocity constant including multiple bits to the neuron circuit; the third memory is used to output a selection signal to the neuron circuit, the selection signal being used to instruct the neuron circuit to select a reset voltage of different amplitudes; the counter is used to output a counting signal to the neuron circuit; the clock unit is used to output a clock signal to the neuron circuit; the neuron circuit is used to input an enable signal and output a high level or a low level according to the weighting coefficients and the first signal; the first signal includes at least one of the following signals: leakage velocity constant, reset voltage, counting signal, and clock signal.

[0035] Fourthly, embodiments of this application also provide an electronic device, which includes at least one neuron circuit as described in the first aspect; the neuron circuit is used to input an enable signal and output a high level or a low level according to the enable signal.

[0036] Fifthly, embodiments of this application also provide a chip system. The chip system includes at least one processor and at least one interface circuit. The at least one processor and at least one interface circuit are interconnected via lines. The processor is used to support the chip system in implementing the various functions or steps in the above method embodiments, and the at least one interface circuit can be used to receive signals from other devices (e.g., memory) or to send signals to other devices (e.g., a communication interface). The chip system may include a chip and may also include other discrete devices.

[0037] In a sixth aspect, embodiments of this application also provide a computer-readable storage medium including instructions that, when executed on the aforementioned electronic device or chip system, cause the electronic device to perform the method described in the second aspect.

[0038] In a seventh aspect, embodiments of this application also provide a computer program product including instructions that, when executed on the aforementioned chip system or electronic device, cause the chip system or electronic device to perform various functions or steps in the above-described method embodiments, such as performing the method described in the second aspect above.

[0039] The technical effects of the second, third, fourth, fifth, sixth, and seventh aspects are described in the first aspect. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a neuron circuit provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram of a switched-capacitor neuron circuit provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram of the structure of a neuron chip provided in an embodiment of this application;

[0045] Figure 6 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0046] Figure 7 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0047] Figure 8 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0048] Figure 9 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0049] Figure 10 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0050] Figure 11 This is a schematic diagram of another neuron circuit provided in an embodiment of this application;

[0051] Figure 12 This is a schematic diagram illustrating an application method of a neuron circuit provided in an embodiment of this application;

[0052] Figure 13 This is a schematic diagram illustrating another application method of a neuron circuit provided in an embodiment of this application;

[0053] Figure 14 A schematic diagram of the input and output signals of a pulse width conversion circuit provided in an embodiment of this application;

[0054] Figure 15 A schematic diagram of the input and output signals of a frequency conversion circuit provided in an embodiment of this application;

[0055] Figure 16This is a schematic diagram of membrane potential changes in a neuron circuit provided in an embodiment of this application;

[0056] Figure 17 A schematic diagram of membrane potential changes in another neuronal circuit provided in an embodiment of this application;

[0057] Figure 18 A schematic diagram of membrane potential changes in another neuronal circuit provided in an embodiment of this application;

[0058] Figure 19 A schematic diagram of membrane potential changes in another neuronal circuit provided in an embodiment of this application;

[0059] Figure 20 A schematic diagram of membrane potential changes in another neuronal circuit provided in an embodiment of this application;

[0060] Figure 21 A schematic diagram illustrating the workflow of a neuron circuit provided in an embodiment of this application;

[0061] Figure 22 This is a schematic diagram of a chip system provided in an embodiment of this application. Detailed Implementation

[0062] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0063] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0064] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0065] First, let me explain the basic concepts of this application:

[0066] Spiking Neural Networks (SNNs) are a type of neural network that mimics the connection and encoding mechanisms of the brain. They are characterized by low power consumption, low latency, and spatiotemporal characteristics. Originating from biologically inspired next-generation artificial neural network models, they belong to a subset of deep learning and have strong biological foundations. Unlike typical multilayer perceptron networks, which are activated in every iteration, neurons in spiking neural networks are activated only when their membrane potential reaches a specific value. When a neuron is activated, it generates a pulse signal that is transmitted to other neurons, raising or lowering the membrane potential of those neurons. Unlike traditional artificial neural networks, spiking neural networks use pulses to encode information, making them more similar to biological nervous systems, and their simulated neurons are closer to actual biological neurons. Furthermore, they consider the influence of temporal information. Therefore, in time-related applications, neurons used to build spiking neural networks need to possess one or more characteristics of biological neurons, such as integration, leakage, fire, and adaptive properties. The specific characteristics included depend on the actual use case and application algorithm. In spiking neural networks, the current activation level of a neuron is typically considered its current state, which can be modeled as a differential equation. An input pulse sequence can increase the value of this differential equation for a period of time, outputting a pulse sequence, which then gradually decays. In practical applications, many encoding methods can be used, combining the pulse frequency and pulse interval time, to interpret these output pulse sequences as a real number.

[0067] This application provides a neuron circuit, such as... Figure 1 As shown, the neuron circuit 1 includes a data memory 11, a data selection circuit 12, a weight memory 13, a switched capacitor circuit 14, an adder circuit 15, and a latch circuit 16.

[0068] The neuron circuit 1 stores the enable signal through the data memory 11 and the weight coefficients corresponding to the enable signal through the weight memory 13. The enable signal is selected by the data selection circuit 12 and output to the switched-capacitor circuit 14. The switched-capacitor circuit 14 performs a convolution operation on the input enable signal and weight coefficients to obtain the corresponding analog voltage value. The latch circuit 16 is used to lock and store the analog voltage value obtained by the adder circuit 15. The adder circuit 15 is used to perform an addition calculation on the analog voltage value latched in the latch circuit 16 and the analog voltage value obtained by the current convolution operation.

[0069] like Figure 2As shown, the switched capacitor circuit 14 includes an XOR logic circuit (not shown in the figure), a switched capacitor array 141, a bias circuit 142, and an operational amplifier 143. In this neuron circuit 1, the enable signal is equivalent to the input pulse sequence. The neuron circuit 1 generates a voltage signal by weighting the input pulse sequence with different weighting coefficients. The generated voltage signal is then amplified and used as the membrane potential of the neuron circuit 1. The XOR logic circuit is used to perform a multiplication and weighting operation on the input enable signal and the weighting coefficients. Before the wide vector summation operation, both plates of each capacitor in the switched capacitor array 141 are grounded to achieve zeroing of the capacitor. After the zeroing operation, one plate of the capacitor is connected to the reference power supply or reference ground via a switch, and the other plate of the capacitor is connected to the positive input terminal of the operational amplifier 143 to provide a voltage divider to the operational amplifier 143. Based on the enable signal and stored weighting coefficients, capacitors of different sizes are charged, converting the binary information stored in the digital domain into capacitor charge. Multiple capacitors collectively generate a voltage signal input to operational amplifier 143. The amplified voltage signal is then used as the updated membrane potential. However, this neuron circuit 1 requires multiple proportionally varying capacitors in the switched capacitor circuit 14 to meet different precision requirements. The capacitance values ​​are 2 times the unit capacitance value. 0 times, 2 1 times,...,2 n-1 The value is 1 times the precision of the digital signal to analog signal conversion, where n is the precision. Therefore, the capacitor area required for implementing this neuron circuit 1 is very large. Furthermore, the design of this neuron circuit 1 is relatively simple, only able to simulate the integration and threshold firing characteristics of neurons, thus limiting its application scenarios.

[0070] This application also proposes a neuron circuit, such as... Figure 3 As shown, this neuron circuit is a simulated subthreshold neuron circuit, which uses capacitor C. mem The voltage is used to represent the membrane potential of the neuron circuit, and the capacitance C is used to represent the membrane potential. mem The charging and discharging of the capacitor C are used to simulate the integration and leakage characteristics of neurons, respectively. During the simulation of integration and leakage characteristics, the capacitor C is controlled by a transistor. mem The speed of charging and discharging, thereby controlling the speed of integration and leakage.

[0071] The embodiments of this application propose, as follows: Figure 3While the illustrated neural network circuit can simulate both integration and leakage characteristics, the magnitude of its charging and discharging currents requires precise control of the corresponding transistor gate voltages. The selection of the gate voltage is highly dependent on the transistor device. Therefore, the implementation of this neural network circuit is incompatible with different process nodes or different wafer fabs. Furthermore, this neural network circuit uses a purely analog signal design, resulting in poor flexibility and applicability; once the neural network circuit is designed, the circuit parameters are difficult to modify. In addition, each neural network circuit requires a large number of components, and the overall area is also excessively large.

[0072] Therefore, embodiments of this application provide an electronic device, such as... Figure 4 As shown, the electronic device 2 includes a neuron chip 21; as Figure 5 As shown, the neuron chip 21 includes a first memory 211, a second memory 212, a third memory 213, a counter 214, a clock unit 215, and multiple neuron circuits 3. A neuron circuit 3 is used to: input at least one enable signal and output a high or low level; the high or low level output by a neuron circuit 3 can be used as an enable signal to output to at least one other neuron circuit 3; the first memory 211 is used to output a weighting coefficient comprising multiple bits to the neuron circuit 3; the second memory 212 is used to output a leakage current rate constant comprising multiple bits to the neuron circuit 3; the third memory 213 is used to output a selection signal to the neuron circuit 3, which instructs the neuron circuit 3 to select a reset voltage of different amplitudes; the counter 214 is used to output a counting signal to the neuron circuit; and the clock unit 215 is used to output a clock signal to the neuron circuit 3.

[0073] like Figure 6 As shown, the neuron circuit 3 includes a pulse width conversion circuit 31, a first capacitor 32, a frequency conversion circuit 33, an equivalent resistance circuit 34, a threshold comparator 35, and a delayed reset module 36. The input terminal of the pulse width conversion circuit 31 is coupled to the first memory 211 and the counter 214; the output terminal of the pulse width conversion circuit 31 is coupled to the first capacitor 32 and the first input terminal of the threshold comparator 35; the second input terminal of the threshold comparator 35 is used to input the threshold voltage. The input terminal of the frequency conversion circuit 33 is coupled to the second memory 212; the output terminal of the frequency conversion circuit 33 is coupled to the first terminal of the equivalent resistance circuit 34; the second terminal of the equivalent resistance circuit 34 is coupled to the coupling point of the pulse width conversion circuit 31, the first capacitor 32, and the threshold comparator 35. The output terminal of the delayed reset module 36 is coupled to the first input terminal of the threshold comparator 35, the first input terminal of the delayed reset module 36 is coupled to the output terminal of the threshold comparator 35, and the second input terminal of the delayed reset module 36 is coupled to the third memory 213. This neuron circuit 3 simulates integration characteristics, leakage characteristics, threshold firing characteristics, and adaptive characteristics.

[0074] In some possible implementations, the simulation of the integration characteristics of neuron circuit 3 is as follows: Figure 6 As shown, the pulse width conversion circuit 31 is used to receive an enable signal and a weighting coefficient including multiple bits. When the enable signal is valid, it outputs multiple first levels corresponding to the multiple bits of the weighting coefficient to the first capacitor 32. The high or low level of each first level is determined by the value of a corresponding bit in the weighting coefficient, and the duration of each first level is determined by the number of bits of the corresponding bit in the weighting coefficient. When the first level is high, the first capacitor 32 is charged; when the first level is low, the first capacitor 32 is discharged.

[0075] In this embodiment, the weight coefficients of the neuron are stored in the first memory 211 as digital signals, and the digital weight coefficients are converted into analog signals in the time dimension by a pulse width conversion circuit 31. The pulse width conversion circuit 31 receives an enable signal and a first level output from the first memory 211, and determines whether to output the first level to the first capacitor 32 through the enable signal. The first level output by the pulse width conversion circuit 31 enables the charging and discharging of the first capacitor 32, thereby realizing the integration characteristics of the analog neuron.

[0076] The above are as follows Figure 6 The neuron circuit 3 shown can perform the following: Figure 12 The application method shown includes steps S101-S102:

[0077] Step S101: The pulse width conversion circuit 31 receives the enable signal and the first level.

[0078] In some possible implementations, such as Figure 7 As shown, the pulse width conversion circuit 31 includes a first controller 311 and a first switch array 312; the first switch array 312 includes a plurality of first switches 3121. The first terminal of each first switch 3121 is coupled to the first memory 211 and is used to input one bit of the weight coefficient stored in the first memory 211; the second terminal of each first switch 3121 is coupled to the coupling point of the first capacitor 32 and the first input terminal of the threshold comparator 35.

[0079] For example, consider a four-bit weighting coefficient stored in the first memory 211. In this case, there are four first switches 3121, each coupled to the first memory 211 and corresponding to one bit of the weighting coefficient. If the currently stored weighting coefficient is 1011, the first level inputs to the least significant first switch 3121, the second first switch 3121, and the fourth first switch 3121 are high, while the first level input to the fourth first switch 3121 is low.

[0080] Step S102: The pulse width conversion circuit 31 outputs a first level to the first capacitor 32 according to the enable signal, and charges or discharges the first capacitor 32 according to the output first level.

[0081] In some possible implementations, the first controller 311 is configured to: sequentially select a first switch 3121 according to the bit correspondence between the first switch 3121 and the weighting coefficient; input an enable signal, and determine whether to turn on the selected first switch 3121 based on the enable signal. When the enable signal is high, the selected first switch 3121 is turned on; when the enable signal is low, the selected first switch 3121 is turned off. When the first switch 3121 is turned on, if the corresponding weighting coefficient is 1, the first level is high, and the high-level first level is output to the first capacitor 32 to charge the first capacitor 32; if the corresponding weighting coefficient is 0, the first level is low, and the low-level first level is output to the first capacitor 32 to discharge the first capacitor 32.

[0082] For example, taking a four-digit weighting coefficient of 1011 as an example, such as Figure 14 As shown, the first row represents the enable signal input to the first controller 311; the second row represents the first level corresponding to the weighting coefficient 1011 input to the first switch array 312; and the third row represents the first level output by the first controller 311 controlling the first switch 3121 in the first switch array 312 to turn on. When the enable signal is valid (i.e., when the enable signal is 1), the corresponding first switch 3121 is turned on, thereby controlling the first switch 3121 to output the received first level. When the enable signal is invalid (i.e., when the enable signal is 0), the first switch 3121 is turned off, and no first level is output.

[0083] In some possible implementations, the first controller 311 is used to determine different first conduction times of the first switch 3121 based on the high or low bit of the weight coefficient corresponding to the first switch 3121.

[0084] For example, the first controller 311 receives the counting signal output by the counter 214, determines the first conduction time of each first switch 3121 based on the counting signal, and selects the corresponding first switch 3121 based on the counting signal. Specifically, if the first conduction time of the first switch 3121 corresponding to the least significant bit of the weighting coefficient is set to x, then the first conduction time of the first switch 3121 corresponding to the nth bit before the least significant bit is x multiplied by 2. n-1 Taking a weighting coefficient of 1011 as an example, when controlling the first switch 3121 to be turned on, the first turn-on time of the first switch 3121 corresponding to each bit is determined according to the counting signal, such as... Figure 14 As shown, taking the first conduction time of the least significant bit as one count duration as an example, the time period from time 0 to time t1 is the first conduction time of the first switch 3121 of the least significant bit. Then, the first conduction time of the second bit is two count durations (i.e., from time t1 to time t2), the first conduction time of the third bit is four count durations (i.e., from time t2 to time t3), and the first conduction time of the fourth bit is eight count durations (i.e., from time t3 to time t4).

[0085] In some possible implementations, the simulation of the threshold firing characteristics of neurons is as follows: Figure 6 As shown, the first input terminal of the threshold comparator 35 is used to input the voltage of the first capacitor 32, and the voltage of the first capacitor 32 is compared with the threshold voltage input to the second input terminal of the threshold comparator 35. When the voltage of the first capacitor 32 is greater than or equal to the threshold voltage, the threshold comparator 35 outputs a high voltage.

[0086] In this embodiment, a threshold comparator 35 compares the voltage of the first capacitor 32 with a threshold voltage. When the voltage of the first capacitor 32 is greater than or equal to the threshold voltage, a high-level signal lasting for a first time interval is output through the output terminal of the threshold comparator 35. This simulates the threshold firing characteristics of a neuron.

[0087] In some possible implementations, the simulation of the leakage characteristics of the neuron is as follows: the frequency conversion circuit 33 inputs a leakage velocity constant, comprising multiple bits, stored in the second memory 212. When the enable signal is invalid (i.e., when the enable signal is 0), multiple fixed-period pulse control signals corresponding to the multiple bits of the leakage velocity constant are output to the equivalent resistance circuit 34. The number of pulses in each pulse control signal is determined by the value of a corresponding bit in the leakage velocity constant. When the pulse control signal is high, it controls the equivalent resistance circuit 34 to input the charge stored in the first capacitor 32; when the pulse control signal is low, it controls the equivalent resistance circuit 34 to release the charge stored in the equivalent resistance circuit 34.

[0088] In this embodiment, the frequency conversion circuit 33 generates a pulse control signal based on the leakage velocity constant. When the pulse control signal is high, the equivalent resistance circuit 34 receives the charge stored in the first capacitor 32, and the charge in the first capacitor 32 is transferred to the equivalent resistance circuit 34 to simulate the leakage characteristics of the neuron. When the pulse control signal is low, the equivalent resistance circuit 34 releases the stored charge to ensure that the equivalent resistance circuit 34 will not be unable to continue receiving the charge stored in the first capacitor 32 due to the stored charge reaching its capacity limit.

[0089] The above are as follows Figure 6 The neuron circuit 3 shown can perform the following: Figure 13 The application method shown includes steps S201-S202:

[0090] Step S201: Frequency conversion circuit 33 receives leakage current velocity constant and clock signal.

[0091] In some possible implementations, such as Figure 8 As shown, the frequency conversion circuit 33 includes a second controller 331 and a second switch array 332; the second switch array 332 includes a plurality of second switches 3321. The first terminal of each second switch 3321 is coupled to the second memory 212 and is used to input a bit of the leakage current velocity constant stored in the second memory 212. Each bit corresponds to a second level, and the high or low level of the second level is determined by the value of the corresponding bit.

[0092] For example, a four-bit leakage velocity constant is stored in the second memory 212. Four second switches 3321 are selected, coupled to the second memory 212, and each corresponds to a bit of the weighting coefficient. If the currently stored leakage velocity constant is 1011, the second level inputs of the least significant second switch 3321, the second second switch 3321, and the fourth second switch 3321 are high, while the second level input of the third second switch 3321 is low.

[0093] Step S202: The frequency conversion circuit 33 generates a pulse control signal based on the leakage current velocity constant and the clock signal. The pulse control signal controls the equivalent resistance circuit 34 to input the charge stored in the first capacitor 32 or to release the charge stored in the equivalent resistance circuit 34.

[0094] In some possible implementations, such as Figure 8As shown, the frequency conversion circuit 33 also includes an AND gate 333. The first input terminal of the AND gate 333 is coupled to the second switch 3321 for inputting a second level; the second input terminal of the AND gate 333 is coupled to the clock unit 215 for inputting a clock signal. By performing an AND operation between the second level and the clock signal through the AND gate 333, a pulse control signal including multiple pulses is obtained.

[0095] For example, such as Figure 15 As shown, taking a leakage velocity constant of 1011 as an example, when the enable signal is disabled (i.e., when the enable signal is 0), the first row in the figure represents the second level corresponding to the leakage velocity constant of 1011, the second row represents the input fixed-frequency clock signal, and the third row represents the generated pulse control signal. By performing an AND operation with the clock signal, the second level, which is a continuous high or low level, is converted into a series of pulse signals. With a fixed time interval as the period, a series of fixed-period pulse control signals can be obtained. The high-level pulse signal controls the equivalent resistance circuit 34 to input the charge stored in the first capacitor 32 to simulate the leakage characteristics of a neuron. The low-level pulse control signal controls the equivalent resistance circuit 34 to release the charge, ensuring that the equivalent resistance circuit 34 retains the ability to input the charge stored in the first capacitor 32.

[0096] In some possible implementations, the second controller 331 is used to determine different second conduction times of the second switch 3321 based on the high or low bit of the leakage current velocity constant corresponding to the second switch 3321.

[0097] For example, if the second conduction time of the second switch 3321 corresponding to the least significant bit of the leakage current velocity constant is set to x, then the second conduction time of the second switch 3321 corresponding to the nth bit before the least significant bit is x multiplied by 2. n-1 .like Figure 15 As shown, for different bit levels of the second level, the number of individual pulses in the corresponding generated pulse control signal is also different. The number of individual pulses generated when the second level of the higher bit level is high is greater than the number of individual pulses generated when the second level of the lower bit level is high.

[0098] In some possible implementations, the second controller 331 receives the counting signal output by the counter 214, determines the second conduction time of each second switch 3321 based on the counting signal, and selects the corresponding second switch 3321 based on the counting signal.

[0099] In some possible implementations, a set value is stored in the second memory 212. The second controller 331 is also configured to: compare the magnitude of the counting signal with the set value; control all second switches to turn off before the counting signal equals the set value within a counting cycle; and turn on the corresponding second switch according to the second on-time when the count information equals the set value and thereafter, provided that the enable information is invalid.

[0100] For example, taking a counter that cycles through 16 numbers as an example, when the set value is 0, the second controller 331 always controls the second switch 3321 to remain off. Therefore, the equivalent resistance circuit 34 fails, and the neuron circuit 3 loses its leakage characteristic. At this time, the equivalent resistance circuit 34 remains in a state of releasing the charge stored in it. The neuron circuit 3 at this time is an integrated-and-fire (IF) neuron circuit, suitable for scenarios requiring both integrated and threshold firing characteristics. Figure 16 The diagram shows the enable signal input to neuron circuit 3, the membrane potential change, and the output voltage through threshold comparator 35 when the set value is 0. The first row shows the input enable signal, the second row shows the corresponding membrane potential change, and the third row shows the output voltage of threshold comparator 35.

[0101] When the set value is 13, the frequency conversion circuit 33 generates a pulse control signal based on the second level and the clock signal when the enable signal is disabled, and outputs the pulse control signal to the equivalent resistance circuit 34. For example... Figure 17 The diagram shows the input, output, and membrane potential changes of neuron circuit 3 when the setpoint is 13. The first row shows the input enable signal, the second row shows the corresponding membrane potential changes, and the third row shows the voltage output of the threshold comparator 35. Through comparison... Figure 16 and Figure 17 It can be seen that when the set value is 13, the equivalent resistance circuit 34 will input the charge stored in the first capacitor 32 once at regular intervals, causing the membrane potential to decrease. After the membrane potential reaches the threshold, the threshold comparator 35 will perform a threshold firing, causing the membrane potential to decrease to the initial membrane potential. At this time, the neuron circuit 3 has leakage characteristics, exhibiting a Leaky Integrate-and-Fire (LIF) neuron circuit, suitable for scenarios requiring neurons with integration characteristics, threshold firing characteristics, and leakage characteristics. Its threshold firing frequency is lower than that of the Integrate-and-Fire (IF) neuron circuit with a set value of 0.

[0102] For the same leakage velocity constant, when the set value is changed from 1 to 15, the decrease in membrane potential of neuron circuit 3 is as follows: Figure 18As shown. By Figure 18 It can be seen that when the enable signal fails, the larger the set value, the faster the membrane potential drops. Therefore, given a fixed stored leakage velocity constant, adjusting the set value can change the value of that leakage velocity constant (i.e., for the same leakage velocity constant, the smaller the corresponding set value, the smaller the actual value represented by the leakage velocity constant).

[0103] This embodiment stores the leakage velocity constant as a digital signal in the second memory 212, and uses the second switch 3321 to convert the digital leakage velocity constant into an analog signal in the time dimension. Compared with using a complex digital-to-analog converter to achieve digital-to-analog conversion, this embodiment has less component overhead, and the parameters of the neuron circuit 3 can be modified by changing the leakage velocity constant stored in the second memory 212, making it more convenient to use and more applicable.

[0104] In some possible implementations, such as Figure 9 As shown, the equivalent resistance circuit 34 includes a second capacitor 341, a third switch 342, and a fourth switch 343. The first end of the third switch 342 serves as the first end of the equivalent resistance circuit 34 and is coupled to the coupling point of the first input terminal of the threshold comparator 35, the first capacitor 32, and the pulse width conversion circuit 31. The second end of the third switch 342 is coupled to the first end of the second capacitor 341. The second end of the second capacitor 341 is grounded. The first end of the fourth switch 343 is coupled to the coupling point between the second end of the third switch 342 and the first end of the second capacitor 341. The second terminal of the fourth switch 343 is grounded; the second controller 331 is specifically used to: output a second level corresponding to the leakage current velocity constant to the third switch 342 and the fourth switch 343; when the second level is high, control the third switch 342 to turn on and control the fourth switch 343 to turn off, so as to control the equivalent resistance circuit 34 to input the charge stored in the first capacitor 32; when the second level is low, control the third switch 342 to turn off and control the fourth switch 343 to turn on, so as to control the equivalent resistance circuit 34 to release the charge stored in the equivalent resistance circuit 34.

[0105] In this embodiment, a high-level pulse control signal is used to control the third switch 342 to turn on and the fourth switch 343 to turn off. When the third switch 342 is on, the second capacitor 341 and the first capacitor 32 are connected, and the charge of the first capacitor 32 is input through the second capacitor 341 to simulate the leakage characteristics of a neuron.

[0106] For example, the capacitance of the first capacitor 32 is larger than the capacitance of the second capacitor 341. Optionally, the capacitance of the first capacitor 32 is one to two orders of magnitude larger than the capacitance of the second capacitor 341.

[0107] For example, such as Figure 9 As shown, the equivalent resistance circuit 34 also includes a fifth switch 344 and a sixth switch 345. The first terminal of the fifth switch 344 is coupled to the second terminal of the second capacitor 341; the second terminal of the fifth switch 344 is grounded; the first terminal of the sixth switch 345 is coupled to the coupling point between the second terminal of the second capacitor 341 and the first terminal of the fifth switch 344; the second terminal of the sixth switch 345 is grounded; the second controller 331 is specifically used to: output a second level to the third switch 342, the fourth switch 343, the fifth switch 344, and the sixth switch 345; when the second level is high, it controls the third switch 342 and the fifth switch 344 to be turned on and controls the fourth switch 343 and the sixth switch 345 to be turned off, so as to control the equivalent resistance circuit 34 to input the charge stored in the first capacitor 32; when the second level is low, it controls the third switch 342 and the fifth switch 344 to be turned off and controls the fourth switch 343 and the sixth switch 345 to be turned on, so as to control the equivalent resistance circuit 34 to output the charge stored in the equivalent resistance circuit 34.

[0108] This embodiment achieves circuit symmetry by setting a fifth switch 344 and a sixth switch 345. While theoretically the switches are equivalent to wires, in practical applications, they also possess a certain resistance. By setting the fifth and sixth switches 344 and 345, the charge stored in the second capacitor 341 is consumed to a certain extent during their alternating switching, which helps the second capacitor 341 release its charge and further prevents insufficient charge release from affecting the leakage current from the second capacitor 341 to the first capacitor 32. Furthermore, the product of the resistance of the equivalent resistance circuit 34 and the film potential corresponding to the voltage of the first capacitor 32 can be used to indicate the leakage current velocity constant. Therefore, setting different leakage current velocity constants allows for adjustment of the resistance value of the equivalent resistance circuit 34. Under different leakage current velocity constants, the switching frequency in the equivalent resistance circuit 34 is different. The lower the switching frequency related to leakage current in the neuron circuit 3, the higher the resistance value of the equivalent resistance circuit 34. By using the leakage velocity constant to adjust the resistance value of the equivalent resistance circuit 34, the use of large-area and large-capacitance membrane potential capacitors is avoided, thus reducing the area overhead of the neuron circuit 3.

[0109] In some possible implementations, the simulation of the delayed reset characteristics of neurons is as follows: Figure 6As shown, the first input terminal of the delayed reset module 36 is coupled to the output terminal of the threshold comparator 35, and is used to input the high level output by the threshold comparator 35; the high level output by the threshold comparator 35 is used to control the output terminal of the delayed reset module 36 to be turned on after the first time interval; the second input terminal of the delayed reset module 36 is coupled to the third memory 213, and is used to input the selection signal stored in the third memory 213, and select a reset voltage of different amplitudes according to the value of the selection signal; the output terminal of the delayed reset module 36 is coupled to the first input terminal of the threshold comparator 35, and is used to output a reset voltage to the first capacitor 32.

[0110] In this embodiment, a delayed reset module 36 receives a reset voltage. When the delayed reset module 36 receives a high level output from the threshold comparator 35, after a first time interval of delay, the delayed reset module 36 outputs a reset voltage to the first capacitor 32, thereby reducing and resetting the voltage of the first capacitor 32.

[0111] In some possible implementations, such as Figure 10 As shown, the delayed reset module 36 includes a delay unit 361, a seventh switch 362, and a reset voltage unit 363. The first end of the seventh switch 362 is coupled to the first input terminal of the threshold comparator 35, the first capacitor 32, and the coupling point of the pulse width conversion circuit 31. The second end of the seventh switch 362 is coupled to the reset voltage unit 363 and is used to input the selection signal stored in the third memory 213 and select a reset voltage of different amplitudes according to the value of the selection signal. The delay unit 361 receives the high level output by the threshold comparator 35 and sends a control signal to the seventh switch 362 after a first time interval. The control signal is used to control the seventh switch 362 to turn on.

[0112] In this embodiment, the high-level signal output from the threshold comparator 35 is input through the delay unit 361 and output to the seventh switch 362 after a first time interval delay. The high-level signal from the threshold comparator 35 is used to control the seventh switch 362 to turn on. After the seventh switch 362 turns on, the reset voltage output from the reset voltage unit 363 is output to the second capacitor 32, thereby reducing the voltage of the first capacitor 32 of the second capacitor 32 to realize the delayed reset characteristic of the simulated neuron. The reset voltage unit 363 is coupled to the third memory 216 and is used for the selection signal stored in the third memory 213, and selects a reset voltage of different amplitudes according to the value of the selection signal.

[0113] In some possible implementations, the simulation of the adaptive characteristics of the neuron is as follows: The third memory 213 stores selection signals corresponding to the first reset voltage and / or the second reset voltage. The reset voltage unit 363 outputs the first reset voltage or the second reset voltage to the seventh switch 362 according to the input selection signal. The first reset voltage serves as the initial membrane potential of the neuron circuit 3, and the second reset voltage serves as a potential lower than the first reset voltage. When the third memory 213 only stores the selection signal corresponding to the first reset voltage, the first reset voltage is output to the first capacitor 32 through the delayed reset module 36 to reduce the membrane potential of the neuron circuit 3 to the initial membrane potential. When the third memory 213 stores the selection signal corresponding to the second reset voltage, the second reset voltage is output to the first capacitor 32 through the delayed reset module 36 to reduce the voltage of the first capacitor 32 to a potential lower than the initial membrane potential of the neuron circuit 3. In this case, the neuron circuit 3 requires a longer time to reach the threshold membrane potential, thereby achieving the characteristic of suppressing the neuron circuit 3 from firing a large number of threshold signals in a short period of time, i.e., the adaptive characteristics of the neuron.

[0114] For example, when the reset voltage is set to the second reset voltage, the input enable signal is... Figure 16 and Figure 17 When the same enable signal is shown, such as Figure 19 As shown in the figure, the first row is the input enable signal, and the second row is a schematic diagram of the change in membrane potential. Figure 3 A schematic diagram of the voltage applied to the threshold of neuron circuit 3. (Comparison) Figure 16 , Figure 17 and Figure 19 It can be seen that when the same enable signal is input, Figure 19 When the neuron circuit 3 in the middle uses a second reset voltage that is lower than the first reset voltage which is the initial membrane potential for delayed reset, the delay time becomes longer, which avoids the threshold comparator 35 from issuing high levels that are too close together. It exhibits a variable characteristic, that is, an adaptive characteristic.

[0115] The above embodiments all use an enable signal input as an example, such as Figure 11 As shown, when two enable signals are input to the neuron circuit 3, two pulse width conversion circuits 31 are correspondingly set up, and the two pulse width conversion circuits 31 jointly output the first level to the first capacitor 32. Figure 20 As shown, the first row is the first input enable signal, the second row is the second input enable signal, the third row is a schematic diagram of the membrane potential change of neuron circuit 3, and the fourth row is a schematic diagram of the threshold firing voltage of neuron circuit 3. According to... Figure 20 It can be seen that the neuron circuit 3 proposed in this application embodiment can still work normally under multiple input conditions.

[0116] The above are as follows Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The flowchart of the described neuron circuit 3 in simulating integration characteristics, leakage characteristics, threshold firing characteristics, delayed reset characteristics, and adaptive characteristics is as follows: Figure 21 As shown.

[0117] In summary, the neuron circuit 3 proposed in this application embodiment can simulate various characteristics of neurons, such as integration characteristics, leakage characteristics, threshold firing characteristics, delayed reset characteristics, and adaptive characteristics. Furthermore, the neuron circuit 3 has a simpler structure, is easier to modify parameters, and is applicable to various scenarios and applications of neuron networks under various algorithms. In this application embodiment, the weight coefficients are stored in the digital domain as digital signals through the first memory 211. The value of each bit of the weight coefficient is used to input a corresponding high or low level to the first switch array 312. An enable signal is used to determine whether to control the first switch array 312 to output a high level to charge the first capacitor 32 or output a low level to discharge the first capacitor 32. This application embodiment achieves the conversion of the weight coefficients of the digital signal into analog signals of the neuron in the time dimension. The configuration of the neuron parameters can be completed by modifying the weight coefficients in the first memory 211. This significantly reduces computational overhead, avoids the use of complex devices such as traditional digital-to-analog converters, and avoids the use of large-area capacitors and other components, greatly saving space. The resistance value of the equivalent resistance circuit 34 is increased by adjusting the leakage velocity constant, thereby reducing the area overhead. The threshold firing characteristics of the neuron are implemented using the threshold comparator 35. The first and second reset voltages are stored in the third memory 213 to achieve delayed reset and adaptive characteristics.

[0118] like Figure 22 As shown in the illustration, this application also provides a chip system 600. The chip system 600 includes at least one processor 610 and at least one interface circuit 620. The at least one processor 610 and the at least one interface circuit 620 are interconnected via lines. The processor 610 is used to support the chip system 600 in implementing various functions or steps in the above method embodiments, such as... Figure 12 and Figure 13 The method shown allows at least one interface circuit 620 to be used to receive signals from other devices (e.g., memory) or to send signals to other devices (e.g., a communication interface). The chip system 600 may include a chip and may also include other discrete components.

[0119] This application also provides a computer-readable storage medium including instructions that, when executed on the aforementioned electronic device, cause the electronic device to perform the following actions: Figure 12 and Figure 13 The method shown.

[0120] This application also provides a computer program product including instructions. When the instructions are executed on the aforementioned chip system or electronic device, the chip system or electronic device causes the chip system or electronic device to perform various functions or steps in the above method embodiments, such as performing... Figure 12 and Figure 13 The method shown.

[0121] The technical effects of the chip system, computer-readable storage medium, and computer program product are described in the preceding method embodiments.

[0122] The processor involved in the embodiments of this application can be a chip. For example, it can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0123] The memory involved in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0124] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0125] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0127] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0128] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located on one device or distributed across multiple devices. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0129] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0130] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A neuron circuit, characterized in that, It includes a pulse width conversion circuit, a first capacitor, and a threshold comparator; the output of the pulse width conversion circuit is coupled to the first capacitor and the first input of the threshold comparator; the second input of the threshold comparator is used to input a threshold voltage; the voltage of the first capacitor is used to indicate the membrane potential of the neuron circuit. The pulse width conversion circuit is used to: input an enable signal and a weighting coefficient including multiple bits, and when the enable signal is valid, output multiple first levels corresponding to the multiple bits of the weighting coefficient to the first capacitor, wherein the high or low level of each first level is determined by the value of a corresponding bit in the weighting coefficient, and the duration of each first level is determined by the number of bits of the corresponding bit in the weighting coefficient. When the first level is high, the first capacitor is charged; when the first level is low, the first capacitor is discharged. The threshold comparator is used to compare the voltage of the first capacitor with the threshold voltage, and output a high level if the voltage of the first capacitor is greater than or equal to the threshold voltage.

2. The circuit according to claim 1, characterized in that, The pulse width conversion circuit includes a first controller and a first switch array; the first switch array includes a plurality of first switches; a first terminal of each first switch is used to input one bit of the weighting coefficient, and a second terminal of each first switch is coupled to the first capacitor and the first input terminal of the threshold comparator; the first controller is used for: Input the enable signal and the fixed-frequency counting signal; When the enable signal is valid, the first conduction time of the corresponding first switch is determined according to the number of bits in the multiple bits of the weighting coefficient, and the corresponding first switch is turned on according to the first conduction time, wherein the first conduction time is an integer multiple of the counting signal.

3. The circuit according to claim 1 or 2, characterized in that, The duration of the level corresponding to the high bit in the weighting coefficient is greater than the duration of the level corresponding to the low bit in the weighting coefficient.

4. The circuit according to claim 1, characterized in that, The neuron circuit further includes a frequency conversion circuit and an equivalent resistance circuit; a first terminal of the equivalent resistance circuit is coupled to the output terminal of the frequency conversion circuit, and a second terminal of the equivalent resistance circuit is coupled to the first capacitor and the first input terminal of the threshold comparator; the frequency conversion circuit is used for: The input includes a leakage velocity constant with multiple bits. When the enable signal is invalid, multiple fixed-period pulse control signals corresponding to the multiple bits of the leakage velocity constant are output to the equivalent resistance circuit. The number of pulses in each pulse control signal is determined by the value of a corresponding bit in the leakage velocity constant. When the pulse control signal is high, the equivalent resistance circuit is controlled to input the charge stored in the first capacitor. When the pulse control signal is low, the equivalent resistance circuit is controlled to release the charge stored in the equivalent resistance circuit.

5. The circuit according to claim 4, characterized in that, The frequency conversion circuit includes a second controller, a second switch array, and an AND gate; the second switch array includes multiple second switches; the first terminal of each second switch is used to input one bit of the leakage current velocity constant, and the second terminal of each second switch is coupled to the first input terminal of the AND gate; the second input terminal of the AND gate is used to input a clock signal; the output terminal of the AND gate is coupled to the first terminal of the equivalent resistance circuit as the output terminal of the frequency conversion circuit; the second controller is used for: Input a counting signal of fixed frequency; When the enable signal is invalid, the second conduction time of the corresponding second switch is determined according to the number of bits in the multiple bits of the leakage current speed constant, and the corresponding second switch is turned on according to the second conduction time, wherein the second conduction time is an integer multiple of the counting signal.

6. The circuit according to claim 5, characterized in that, The number of pulse control signals corresponding to the high bits of the leakage current velocity constant is greater than the number of pulse control signals corresponding to the low bits of the leakage current velocity constant.

7. The circuit according to claim 5 or 6, characterized in that, The second controller is also used for: Compare the magnitude of the counting signal with the set value; Within one counting cycle, before the counting signal equals the set value, control all the second switches to turn off; When the counting signal equals the set value and thereafter, and when the enable signal is invalid, the corresponding second switch is turned on according to the second on-time.

8. The circuit according to claim 5, characterized in that, The equivalent resistance circuit includes a second capacitor, a third switch, and a fourth switch; the first terminal of the third switch serves as the first terminal of the equivalent resistance circuit and is coupled to the first input terminal of the threshold comparator, the first capacitor, and the coupling point of the pulse width conversion circuit; the second terminal of the third switch is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is grounded; the first terminal of the fourth switch is coupled to the coupling point between the second terminal of the third switch and the first terminal of the second capacitor; the second terminal of the fourth switch is grounded. The second controller is specifically used for: The leakage current velocity constant is output to the third switch and the fourth switch; when the leakage current velocity constant is high, the third switch is turned on and the fourth switch is turned off, so as to control the charge stored in the first capacitor to be input into the equivalent resistance circuit. When the level corresponding to the leakage current velocity constant is low, the third switch is controlled to turn off and the fourth switch is controlled to turn on, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

9. The circuit according to claim 8, characterized in that, The equivalent resistance circuit further includes a fifth switch and a sixth switch; the first end of the fifth switch is coupled to the second end of the second capacitor; the second end of the fifth switch is grounded; the first end of the sixth switch is coupled to the coupling point between the second end of the second capacitor and the first end of the fifth switch; the second end of the sixth switch is grounded. The second controller is specifically used for: The leakage velocity constant level is output to the third switch, the fourth switch, the fifth switch and the sixth switch; when the leakage velocity constant level is high, the third switch and the fifth switch are turned on and the fourth switch and the sixth switch are turned off, so as to control the charge stored in the first capacitor to be input into the equivalent resistance circuit. When the level corresponding to the leakage current velocity constant is low, the third and fifth switches are controlled to turn off and the fourth and sixth switches are controlled to turn on, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

10. The circuit according to claim 1 or 2, characterized in that, The neuron circuit also includes a delayed reset module; the delayed reset module includes a delay unit, a seventh switch, and a reset voltage unit. The first end of the seventh switch is coupled to the first input terminal of the threshold comparator, the first capacitor, and the coupling point of the pulse width conversion circuit; the second end of the seventh switch is coupled to the reset voltage unit and is used to input the reset voltage output by the reset voltage unit; the reset voltage is used to: reduce the voltage of the first capacitor when the seventh switch is turned on; The delay unit is used to receive the high level output by the threshold comparator and send a control signal to the seventh switch after a first time interval; the control signal is used to control the seventh switch to be turned on.

11. A method for applying a neuron circuit, characterized in that, Based on the neuron circuit according to any one of claims 1-10, the neuron circuit includes a pulse width conversion circuit and a first capacitor; the voltage of the first capacitor is used to indicate the membrane potential of the neuron circuit; the pulse width conversion circuit includes a first switch array; the first switch array includes a plurality of first switches; a first terminal of each first switch is used to input one bit of the weighting coefficient, and a second terminal of each first switch is coupled to the first capacitor and a first input terminal of the threshold comparator; the method includes: Input enable signal; When the enable signal is valid, the first conduction time of the corresponding first switch is determined according to the number of bits of each bit in the weighting coefficient, which includes multiple bits. The first switch is turned on according to the first conduction time. The turned-on first switch outputs multiple first levels to the first capacitor, which are respectively corresponding to the multiple bits of the weighting coefficient. The high or low level of each first level is determined by the value of a bit in the weighting coefficient. The duration of each first level is determined by the number of bits of the bit in the weighting coefficient. When the first level is high, the first capacitor is charged. When the first level is low, the first capacitor is discharged.

12. The method according to claim 11, characterized in that, The first conduction time is determined by a counting signal, and the first conduction time is an integer multiple of the counting signal.

13. The method according to claim 11 or 12, characterized in that, The duration of the level corresponding to the high bit in the weighting coefficient is greater than the duration of the level corresponding to the low bit in the weighting coefficient.

14. The method according to claim 12, characterized in that, The neuron circuit further includes a frequency conversion circuit and an equivalent resistance circuit; the frequency conversion circuit includes a second switch array and an AND gate; the second switch array includes multiple second switches; the first terminal of each second switch is used to input one bit of a leakage velocity constant including multiple bits, and the second terminal of each second switch is coupled to the first input terminal of the AND gate; the second input terminal of the AND gate is used to input a clock signal; the output terminal of the AND gate is coupled to the first terminal of the equivalent resistance circuit as the output terminal of the frequency conversion circuit. The second terminal of the equivalent resistance circuit is coupled to the first capacitor; the method further includes: When the enable signal is invalid, the second conduction time of the corresponding second switch is determined according to the number of bits of each bit of the leakage current velocity constant, and the corresponding second switch is turned on according to the second conduction time. The turned-on second switch outputs multiple second levels corresponding to multiple bits of the leakage current velocity constant to the first input terminal of the AND gate. The high or low level of each second level is determined by the value of a bit corresponding to the time. The AND gate outputs multiple fixed-cycle pulse control signals to the equivalent resistance circuit, corresponding to multiple bits of the leakage velocity constant; the pulse control signals control the equivalent resistance circuit to input the charge stored in the first capacitor or control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

15. The method according to claim 14, characterized in that, The second conduction time is determined by a counting signal, and the second conduction time is an integer multiple of the counting signal.

16. The method according to claim 14, characterized in that, The number of pulse control signals corresponding to the high bits of the leakage current velocity constant is greater than the number of pulse control signals corresponding to the low bits of the leakage current velocity constant.

17. The method according to claim 14, characterized in that, The method further includes: Compare the magnitude of the counting signal with the set value; Within one counting cycle, before the counting signal equals the set value, control all the second switches to turn off; When the counting signal equals the set value and thereafter, and when the enable signal is invalid, the corresponding second switch is turned on according to the second on-time.

18. The method according to claim 14, characterized in that, The equivalent resistance circuit includes a second capacitor, a third switch, and a fourth switch; the first terminal of the third switch serves as the first terminal of the equivalent resistance circuit and is coupled to the first input terminal of the threshold comparator, the first capacitor, and the coupling point of the pulse width conversion circuit; the second terminal of the third switch is coupled to the first terminal of the second capacitor; the second terminal of the second capacitor is grounded; the first terminal of the fourth switch is coupled to the coupling point between the second terminal of the third switch and the first terminal of the second capacitor; the second terminal of the fourth switch is grounded. The step of controlling the equivalent resistance circuit to input the charge stored in the first capacitor or controlling the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit via the pulse control signal specifically includes: The pulse control signal is output to the third switch and the fourth switch; when the pulse control signal is high, the third switch is turned on and the fourth switch is turned off, so as to control the equivalent resistance circuit to input the charge stored in the first capacitor; when the pulse control signal is low, the third switch is turned off and the fourth switch is turned on, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

19. The method according to claim 18, characterized in that, The equivalent resistance circuit further includes a fifth switch and a sixth switch; the first end of the fifth switch is coupled to the second end of the second capacitor; the second end of the fifth switch is grounded; the first end of the sixth switch is coupled to the coupling point between the second end of the second capacitor and the first end of the fifth switch; the second end of the sixth switch is grounded. The step of controlling the equivalent resistance circuit to input the charge stored in the first capacitor or controlling the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit via the pulse control signal specifically includes: The pulse control signal is output to the third, fourth, fifth, and sixth switches; when the pulse control signal is high, the third and fifth switches are turned on and the fourth and sixth switches are turned off, so as to control the equivalent resistance circuit to input the charge stored in the first capacitor; when the pulse control signal is low, the third and fifth switches are turned off and the fourth and sixth switches are turned on, so as to control the equivalent resistance circuit to release the charge stored in the equivalent resistance circuit.

20. A neuron chip, characterized in that, The device includes a first memory, a second memory, a third memory, a counter, a clock unit, and multiple neuron circuits as described in any one of claims 1-10; the neuron circuits are coupled to the first memory, the second memory, the third memory, the counter, and the clock unit, respectively; the first memory is used to output a weighting coefficient comprising multiple bits to the neuron circuit; the second memory is used to output a leakage velocity constant comprising multiple bits to the neuron circuit; the third memory is used to output a selection signal to the neuron circuit, the selection signal being used to instruct the neuron circuit to select a reset voltage of different amplitudes; the counter is used to output a counting signal to the neuron circuit; the clock unit is used to output a clock signal to the neuron circuit; the neuron circuit is used to input an enable signal and output a high level or a low level according to the weighting coefficients and the first signal; the first signal includes at least one of the following signals: the leakage velocity constant, the reset voltage, the counting signal, and the clock signal.

21. An electronic device, characterized in that, It includes at least one neuron chip as described in claim 20; the neuron chip is used to input an enable signal and output a high level or a low level according to the enable signal.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on the electronic device of claim 21, cause the electronic device to perform the method of any one of claims 11-19.

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