An in-memory computing circuit, method, and semiconductor memory

Abstract

The embodiment of the present disclosure provides an in-memory computing circuit, method and semiconductor memory. The in-memory computing circuit comprises an initial computing circuit and a target computing circuit. The initial computing circuit is configured to perform first operation processing on first data and second data, output a first operation result; and perform second operation processing on the first data and the second data, output a second operation result. The target computing circuit is configured to perform first operation processing on the second operation result and the first operation result, output a first target result; and perform second operation processing on the first data and the second operation result, output a second target result.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit technology, and in particular to an in-memory computing circuit, method, and semiconductor memory. Background Technology

[0002] Currently, in the architecture of mainstream computers, the computing / processing unit and memory are two completely separate units. The computing / processing unit reads data from memory according to instructions, performs calculations / processing, and then stores the data back into memory. However, because the performance improvement rate of the computing / processing unit is faster than that of the memory unit, the read / write speed of the memory unit has become a major bottleneck limiting the overall performance of the computer.

[0003] In other words, when performing calculations on large amounts of data, frequent data transfers are required between the processor and memory, resulting in lengthy computation times and increased power consumption. While the concept of in-memory computing has been proposed in recent years to address this issue, a unified solution for its implementation remains elusive. Summary of the Invention

[0004] This disclosure provides an in-memory computing circuit, method, and semiconductor memory.

[0005] The technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide an in-memory computing circuit, including:

[0007] An initial calculation circuit is used to perform a first operation on the first data and the second data and output a first operation result; and to perform a second operation on the first data and the second data and output a second operation result.

[0008] The target calculation circuit is used to perform a first calculation on the second calculation result and the first calculation result, and output a first target result; and to perform a second calculation on the first data and the second calculation result, and output a second target result.

[0009] In some embodiments, the initial calculation circuit includes a first arithmetic circuit and a second arithmetic circuit; wherein,

[0010] The first arithmetic circuit is used to perform a first arithmetic processing on the first data and the second data, and output the first arithmetic result;

[0011] The second arithmetic circuit is used to perform a second arithmetic processing on the first data and the second data, and output the second arithmetic result.

[0012] In some embodiments, the first arithmetic circuit includes a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells, and a plurality of second memory cells; wherein...

[0013] The word line control circuit is used to change the level state of the target first word line after determining the target first word line, and to control the level state of the remaining first word lines other than the target first word line according to the first data, so as to obtain the level state of the plurality of first word lines.

[0014] The first bit line is used to determine the level state of the first bit line based on the first data;

[0015] The plurality of first storage cells are configured to determine the level state of the plurality of first storage cells based on the level state of the plurality of first word lines and the level state of the first bit lines;

[0016] The word line control circuit is further configured to control the level state of the plurality of second word lines according to the second data, so as to obtain the level state of the plurality of second word lines;

[0017] The second bit line is used to determine the level state of the second bit line based on the second data;

[0018] The plurality of second storage cells are configured to determine the level state of the plurality of second storage cells based on the level state of the plurality of second word lines and the level state of the second bit lines;

[0019] The sensitive amplifier is used to output the first calculation result based on the level states of the plurality of first storage cells and the level states of the plurality of second storage cells.

[0020] In some embodiments, the word line control circuit is configured to control the target first word line to be in an activated state after receiving a first activation instruction.

[0021] In some embodiments, the word line control circuit is further configured to, upon receiving a second activation instruction, control at least two first word lines other than the target first word line to be in an active state if the first data is a first value; and control the remaining first word lines other than the target first word line to be in an inactive state if the first data is a second value.

[0022] In some embodiments, the word line control circuit is further configured to, upon receiving a third activation instruction, control at least two second word lines to be in an active state if the second data is a first value, and control all of the plurality of second word lines to be in an inactive state if the second data is a second value.

[0023] In some embodiments, the sensitive amplifier is configured to, upon receiving a preset comparison instruction, read a first voltage provided by the plurality of first storage cells and a second voltage provided by the plurality of second storage cells, perform a comparison operation on the first data and the second data based on the first voltage and the second voltage, and output the first calculation result; wherein...

[0024] If the first voltage is higher than the second voltage, the first calculation result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the first calculation result output by the sensitive amplifier is the second result value.

[0025] In some embodiments, the second operational circuit includes a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells, and a plurality of second memory cells; wherein...

[0026] The word line control circuit is used to control the level state of the plurality of first word lines according to the first data, so as to obtain the level state of the plurality of first word lines;

[0027] The first bit line is used to determine the level state of the first bit line based on the first data;

[0028] The plurality of first storage cells are configured to determine the level state of the plurality of first storage cells based on the level state of the plurality of first word lines and the level state of the first bit lines;

[0029] The word line control circuit is further configured to change the level state of the target second word line after determining the target second word line, and to control the level state of the remaining second word lines other than the target second word line according to the second data, so as to obtain the level state of the plurality of second word lines.

[0030] The second bit line is used to determine the level state of the second bit line based on the second data;

[0031] The plurality of second storage cells are configured to determine the level state of the plurality of second storage cells based on the level state of the plurality of second word lines and the level state of the second bit lines;

[0032] The sensitive amplifier is used to output the second calculation result based on the level states of the plurality of first storage cells and the level states of the plurality of second storage cells.

[0033] In some embodiments, the word line control circuit is configured to control the target second word line to be in an activated state after receiving a first activation instruction.

[0034] In some embodiments, the word line control circuit is further configured to, upon receiving a second activation instruction, control at least two first word lines to be in an active state if the first data is a first value, and control all of the plurality of first word lines to be in an inactive state if the first data is a second value.

[0035] In some embodiments, the word line control circuit is further configured to, upon receiving a third activation instruction, control at least two second word lines other than the target second word line to be in an active state if the second data is a first value; and control the remaining second word lines other than the target second word line to be in an inactive state if the second data is a second value.

[0036] In some embodiments, the sensitive amplifier is configured to, upon receiving a preset comparison instruction, read a first voltage provided by the plurality of first storage cells and a second voltage provided by the plurality of second storage cells, perform a comparison operation on the first data and the second data based on the first voltage and the second voltage, and output the second operation result; wherein...

[0037] If the first voltage is higher than the second voltage, the second calculation result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the second calculation result output by the sensitive amplifier is the second result value.

[0038] In some embodiments, the target computing circuit includes a third arithmetic circuit and a fourth arithmetic circuit; wherein,

[0039] The third arithmetic circuit is used to perform a first arithmetic process on the second arithmetic result and the first arithmetic result, and output the first target result;

[0040] The fourth arithmetic circuit is used to perform a second arithmetic processing on the first data and the second arithmetic result, and output the second target result.

[0041] In some embodiments, the operation method of the third arithmetic circuit is the same as that of the first arithmetic circuit, and the operation method of the fourth arithmetic circuit is the same as that of the second arithmetic circuit.

[0042] In some embodiments, the in-memory computing circuit satisfies at least one of the following operations: half addition, full addition, and multiplication.

[0043] In some embodiments, the first target result is used to indicate the result of the XOR operation between the first data and the second data, and the second target result is used to indicate the result of the AND operation between the first data and the second data.

[0044] Secondly, embodiments of this disclosure provide an in-memory computing method applied to an in-memory computing circuit, the in-memory computing circuit including an initial computing circuit and a target computing circuit; the method includes:

[0045] The initial calculation circuit performs a first operation on the first data and the second data, and outputs a first operation result; and performs a second operation on the first data and the second data, and outputs a second operation result.

[0046] The target computing circuit performs a first operation on the second operation result and the first operation result to output a first target result; and performs a second operation on the first data and the second operation result to output a second target result.

[0047] In some embodiments, the initial computing circuit includes a first computing circuit and a second computing circuit, and the target computing circuit includes a third computing circuit and a fourth computing circuit;

[0048] The first operation, performed on the first data and the second data by the initial calculation circuit and outputting the first operation result, and the second operation, performed on the first data and the second data and outputting the second operation result, include:

[0049] The first arithmetic circuit performs a first arithmetic processing on the first data and the second data, and outputs the first arithmetic result.

[0050] The second arithmetic circuit performs a second arithmetic processing on the first data and the second data, and outputs the second arithmetic result.

[0051] The first operation, performed on the second calculation result and the first calculation result by the target calculation circuit, outputs a first target result; and the second operation, performed on the first data and the second calculation result, outputs a second target result, includes:

[0052] The third arithmetic circuit performs a first arithmetic process on the second arithmetic result and the first arithmetic result, and outputs the first target result.

[0053] The fourth arithmetic circuit performs a second arithmetic process on the first data and the second arithmetic result, and outputs the second target result.

[0054] In some embodiments, the operation method of the third arithmetic circuit is the same as that of the first arithmetic circuit, and the operation method of the fourth arithmetic circuit is the same as that of the second arithmetic circuit.

[0055] In some embodiments, the first target result is used to indicate the result of the XOR operation between the first data and the second data, and the second target result is used to indicate the result of the AND operation between the first data and the second data.

[0056] Thirdly, embodiments of this disclosure provide a semiconductor memory, including in-memory computing circuitry as described in any of the first aspects.

[0057] This disclosure provides an in-memory computing circuit, method, and semiconductor memory. The in-memory computing circuit includes an initial computing circuit and a target computing circuit. The initial computing circuit is used to perform a first operation on first data and second data and output a first operation result; and to perform a second operation on the first data and second data and output a second operation result. The target computing circuit is used to perform a first operation on the second operation result and the first operation result and output a first target result; and to perform a second operation on the first data and the second operation result and output a second target result. Attached Figure Description

[0058] Figure 1 A schematic diagram of the components of a computer architecture. Figure 1 ;

[0059] Figure 2 A schematic diagram of the components of a computer architecture. Figure 2 ;

[0060] Figure 3 A schematic diagram of the composition structure of an in-memory computing circuit provided in an embodiment of this disclosure;

[0061] Figure 4 This is a schematic diagram of a half-adder provided in an embodiment of the present disclosure;

[0062] Figure 5 A schematic diagram of the composition structure of an initial calculation circuit provided in an embodiment of this disclosure;

[0063] Figure 6 A schematic diagram of the composition structure of an arithmetic circuit provided in an embodiment of this disclosure;

[0064] Figure 7 A schematic diagram of the circuit structure of a first operational circuit provided in an embodiment of this disclosure. Figure 1 ;

[0065] Figure 8 A schematic diagram of the circuit structure of a first operational circuit provided in an embodiment of this disclosure. Figure 2 ;

[0066] Figure 9 A schematic diagram of the circuit structure of a second operational circuit provided in an embodiment of this disclosure. Figure 1;

[0067] Figure 10 A schematic diagram of the circuit structure of a second operational circuit provided in an embodiment of this disclosure. Figure 2 ;

[0068] Figure 11 A schematic diagram of the composition structure of a target computing circuit provided in an embodiment of this disclosure;

[0069] Figure 12 A simplified structural diagram of an in-memory computing circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0070] Figure 13 A simplified structural diagram of an in-memory computing circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0071] Figure 14 A schematic diagram of the circuit structure of an arithmetic circuit provided in an embodiment of this disclosure;

[0072] Figure 15 This is a schematic diagram of the architecture of a computing device provided in an embodiment of the present disclosure;

[0073] Figure 16 A schematic flowchart of an in-memory computing method provided in an embodiment of this disclosure;

[0074] Figure 17 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0075] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0076] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure.

[0077] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0078] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. The "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0079] The von Neumann architecture is a classic computer architecture and remains the mainstream architecture for current computers and processor chips. (See also...) Figure 1 It illustrates the composition of a computer architecture. Figure 1 .like Figure 1 As shown, the von Neumann architecture includes memory units (including RAM, flash memory, etc.) and computation / processing units (including neural network accelerators, caches, microprocessors, input / output modules, etc.). In the classic von Neumann architecture, the computation / processing unit and the memory unit are two completely separate units. The computation / processing unit reads data from the memory unit according to instructions, performs computation / processing within the computation / processing unit, and then stores the data back to the memory unit.

[0080] However, because the performance improvement rate of computing / processing units is faster than that of memory units, the read / write speed of memory units has become a major bottleneck limiting overall computer performance. Currently, the energy consumed by current Dynamic Random Access Memory (DRAM) to read and write 32 bits of data at a time is two to three orders of magnitude greater than the energy consumed by computing 32 bits of data, thus becoming a bottleneck in the overall energy efficiency of computing devices. To address this problem, the concept of in-memory computing (or in-memory arithmetic) was proposed.

[0081] The main improvement of in-memory computing is that it embeds computation into memory units, turning memory units into powerful tools for both storage and computation. It performs calculations while storing / retrieving data, reducing the overhead of data access during computation. All computations are transformed into weighted summations, with the weights stored in memory units, thus enabling these units to perform computations.

[0082] To achieve in-memory computing, additional storage space and a new computer architecture are required. See [link / reference] Figure 2 It illustrates the composition of a computer architecture. Figure 2 .like Figure 2 As shown, the architecture includes an in-memory computing module, a microprocessor, and a cache, with the cache connected to other components via sensors. According to... Figure 1 and Figure 2 It can be seen that in-memory computing also requires a large amount of additional space and involves significant changes to the computer architecture, which leads to high implementation costs and limits the development of in-memory computing.

[0083] Based on this, embodiments of this disclosure provide an in-memory computing circuit, including an initial computing circuit and a target computing circuit. The initial computing circuit performs a first operation on first data and second data, outputting a first operation result; and performs a second operation on the first data and second data, outputting a second operation result. The target computing circuit performs a first operation on the second operation result and the first operation result, outputting a first target result; and performs a second operation on the first data and the second operation result, outputting a second target result. The first target result indicates the XOR operation result of the first data and the second data, and the second target result indicates the AND operation result of the first data and the second data. Thus, by performing two first operations and two second operations on the first data and the second data using the in-memory computing circuit, the XOR operation result and the AND operation result of the first data and the second data can be obtained, achieving an operational effect equivalent to a half-adder, thereby improving the data processing speed through the in-memory computing circuit.

[0084] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0085] In one embodiment of this disclosure, see Figure 3 This illustrates a schematic diagram of the composition structure of an in-memory computing circuit 30 provided in an embodiment of this disclosure. For example... Figure 3 The in-memory computing circuit 30 may include:

[0086] The initial calculation circuit 31 is used to perform a first operation on the first data and the second data and output the first operation result; and to perform a second operation on the first data and the second data and output the second operation result.

[0087] The target calculation circuit 32 is used to perform a first operation on the second operation result and the first operation result, and output a first target result; and to perform a second operation on the first data and the second operation result, and output a second target result.

[0088] It should be noted that this in-memory computing circuit 30 can be applied to semiconductor memories, utilizing the operation and characteristics of memory array circuits (such as DRAM) for data computation within a computer architecture. For example... Figure 3As shown, the in-memory computing circuit 30 provided in this embodiment mainly includes two parts: an initial computing circuit 31 and a target computing circuit 32. The first data and the second data represent the original data to be calculated. By processing the first data and the second data through the initial computing circuit 31, two intermediate calculation results can be obtained, namely the first calculation result and the second calculation result. By processing the first data, the first calculation result, and the second calculation result through the target computing circuit 32, the final calculation result can be obtained, namely the first target result and the second target result.

[0089] It should also be noted that the in-memory computing circuit 30 can be used to implement the function of a half adder. In this embodiment of the present disclosure, taking a half adder as an example, in the half addition operation finally performed by the half adder, the first data represents the addend and the second data represents the augend.

[0090] See Figure 4 This illustration shows a schematic diagram of a half-adder provided in an embodiment of this disclosure. A half-adder is a device used to perform addition operations on two one-bit binary numbers. Figure 4 As shown, the half-adder has two inputs and two outputs, consisting of an XOR gate and an AND gate. The two inputs are used to input the addend A and the sum B, respectively, and the two outputs are used to output the sum S and the carry C, respectively. The truth table of the half-adder is shown in Table 1:

[0091] Table 1

[0092] 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

[0093] In other words, for a half adder, the input addends A and B are two one-bit binary numbers; the addends A and B are XORed by an XOR gate to obtain the sum S; the addends A and B are ANDed by an AND gate to obtain the carry C.

[0094] Figure 3 The in-memory calculation circuit 30 shown can implement the function of a half adder. Here, the first data represents the addend A, and the second data represents the addend B. After the first and second data are input into the initial calculation circuit 31, the initial calculation circuit 31 performs a first operation on the first and second data, thereby outputting a first operation result; the initial calculation circuit 31 also performs a second operation on the first and second data, thereby outputting a second operation result. Here, the first operation and the second operation are two different operation methods.

[0095] The first data, along with the first and second operation results, is input into the target calculation circuit 32. The target calculation circuit 32 performs a first operation on the second and first operation results to output a first target result; the target calculation circuit 32 also performs a second operation on the first data and the second operation results to output a second target result.

[0096] The first target result is used to indicate the result of the XOR operation of the first data and the second data, which is the sum S obtained by the half addition operation. The second target result is used to indicate the result of the AND operation of the first data and the second data, which is the carry C obtained by the half addition operation.

[0097] In other words, through the in-memory computing circuit 30, after two first operations and two second operations, the first target result (sum S) and the second target result (carry C) of the first data (addend A) and the second data (addend B) can be obtained. Thus, the equivalent operation result of a half adder can be obtained solely through the in-memory computing circuit 30. In this way, by using this in-memory computing method to obtain the XOR operation result and the AND operation result of the first and second data, the computing efficiency is improved.

[0098] For the initial calculation circuit 31, see Figure 5 This illustrates a schematic diagram of the composition structure of an initial calculation circuit 31 provided in an embodiment of this disclosure. For example... Figure 5 As shown, in some embodiments, the initial calculation circuit 31 may include a first arithmetic circuit 311 and a second arithmetic circuit 312; wherein,

[0099] The first arithmetic circuit 311 is used to perform a first arithmetic processing on the first data and the second data, and output the first arithmetic result;

[0100] The second arithmetic circuit 312 is used to perform a second arithmetic processing on the first data and the second data, and output the second arithmetic result.

[0101] It should be noted that, as Figure 5 As shown, the initial calculation circuit 31 may include a first arithmetic circuit 311 and a second arithmetic circuit 312. The first arithmetic circuit 311 is a circuit unit in the initial calculation circuit 31 used to perform the first arithmetic process, and the second arithmetic circuit 312 is a circuit unit in the initial calculation circuit 31 used to perform the second arithmetic process.

[0102] First data is input to the first arithmetic circuit 311 and the second arithmetic circuit 312, respectively, and second data is also input to the first arithmetic circuit 311 and the second arithmetic circuit 312, respectively. The first arithmetic circuit 311 performs a first arithmetic process on the first data and the second data to obtain a first arithmetic result; the second arithmetic circuit 312 performs a second arithmetic process on the first data and the second data to obtain a second arithmetic result.

[0103] It should also be noted that, for the first operational circuit 311, the truth table obtained by performing the first operational process is shown in Table 2:

[0104] Table 2

[0105]

[0106] For the second operational circuit 312, the truth table obtained by performing the second operational process is shown in Table 3:

[0107] Table 3

[0108]

[0109] For the first operational circuit 311, see Figure 6 It shows a schematic diagram of the composition structure of an operational circuit provided in an embodiment of this disclosure, wherein, Figure 6 This can be used to represent the structural composition of the first operational circuit 311. For example... Figure 6 As shown, in some embodiments, the first operational circuit 311 may include a plurality of first word lines 3111, a plurality of second word lines 3112, a first bit line 3113, a second bit line 3114, a sensitive amplifier 3115, a word line control circuit 3116, a plurality of first memory cells 3117, and a plurality of second memory cells 3118; wherein,

[0110] The word line control circuit 3116 is used to change the level state of the target first word line after determining the target first word line, and to control the level state of the remaining first word lines 3111 other than the target first word line according to the first data, so as to obtain the level state of multiple first word lines 3111.

[0111] The first line 3113 is used to determine the level state of the first line 3113 based on the first data;

[0112] A plurality of first storage cells 3117 are configured to determine the level state of the plurality of first storage cells 3117 based on the level state of the plurality of first word lines 3111 and the level state of the first bit line 3113.

[0113] The word line control circuit 3116 is also used to control the level state of a plurality of second word lines 3112 according to the second data, so as to obtain the level state of a plurality of second word lines 3112;

[0114] The second bit line 3114 is used to determine the level state of the second bit line 3114 according to the second data;

[0115] A plurality of second storage cells 3118 are configured to determine the level state of the plurality of second storage cells 3118 based on the level state of the plurality of second word lines 3112 and the level state of the second bit line 3114.

[0116] The sensitive amplifier 3115 is used to output a first calculation result based on the level states of the plurality of first storage cells 3117 and the level states of the plurality of second storage cells 3118.

[0117] It should be noted that there are multiple first word lines 3111 and second word lines 3112. For example, there are N first word lines 3111 and N second word lines 3112, where N is a positive integer greater than or equal to 3. At the same time, there are also multiple first storage units 3117 and second storage units 3118. For example, there are M first storage units 3117 and M second storage units 3118, where M is a positive integer greater than or equal to 3.

[0118] Furthermore, the voltage levels of word lines differ when they are in an active (or enabled) state and an inactive state, thus controlling the opening of the connected memory cells. Based on this, by controlling the voltage levels of word lines, different memory cells can be opened according to the voltage levels of different word lines, thereby enabling the operation of the first and second data.

[0119] like Figure 6 As shown, in order to facilitate the distinction between the first word line 3111 and the second word line 3112, and between the first storage unit 3117 and the second storage unit 3118 in the first arithmetic circuit 311, a first region 401 and a second region 402 are divided in the first arithmetic circuit 311. It is understood that the division of the first region 401 and the second region 402 is only for the convenience of describing the embodiments of this disclosure, and is not necessary, and does not constitute a limitation on the embodiments of this disclosure.

[0120] like Figure 6 As shown, the word line control circuit 3116 is connected to a plurality of first word lines 3111 and a plurality of second word lines 3112. Through the word line control circuit 3116, the plurality of first word lines 3111 and the plurality of second word lines 3112 can be controlled to be in an active state or in an inactive state.

[0121] It should also be noted that, such as Figure 6 As shown, the first operational circuit 311 also includes a first bit line 3113 and a second bit line 3114, both of which are connected to the sensitive amplifier 3115.

[0122] That is, in the first region 401, there is a first bit line 3113, a plurality of first word lines 3111 and a plurality of first memory cells 3117; in the second region 402, there is a second bit line 3114, a plurality of second word lines 3112 and a plurality of second memory cells 3118.

[0123] When performing the first operation on the first data and the second data, the first region 401 is used to activate a certain number of first word lines 3111 according to the first data; the second region 402 is used to activate a certain number of second word lines 3112 according to the second data.

[0124] It should also be noted that when performing the first operation on the first and second data, it is first ensured that both the first region 401 and the second region 402 are in a cleared state, that is, the multiple first word lines 3111 and the multiple second word lines 3112 are in an inactive state. At this point, if both the first region 401 and the second region 402 are already in a cleared state, a target first word line is directly determined from the multiple first word lines 3111, and the level state of the target first word line is changed. If the first region 401 and the second region 402 are not both in a cleared state, a clearing process must be performed first.

[0125] Therefore, in some embodiments of the first arithmetic circuit 311, the word line control circuit 3116 is also used to clear a plurality of first word lines 3111 and a plurality of second word lines 3112.

[0126] After clearing multiple first word lines 3111 and multiple second word lines 3112, all of them are in an inactive state. In this embodiment of the present disclosure, the clearing state of the storage area can be that the word lines in the storage area are inactive. The inactive state of the word lines is the word line off state, which is achieved by providing a low-level signal to the word lines, i.e., writing data "0".

[0127] In some embodiments, a low-level state can also be relative to a high-level state that can activate a word line; it is a relative high and low, and is not limited to a fixed level value.

[0128] It should also be noted that the target first word line can be any one of the multiple first word lines 3111. The word line control circuit 3116 can change the level state of the target first word line to activate it. For example, changing the level state of the target first word line from a low level state to a high level state activates the target first word line. In this embodiment, the inactive state (low level state) of the word line can be denoted as the first level state, and the active state (high level state) of the word line can be denoted as the second level state. That is, the second level state can be a higher level state than the first level state. Changing the level state of the target first word line to a high level state is equivalent to writing the data "1" to the target first word line.

[0129] For example, see Figure 7 It shows a schematic diagram of the circuit structure of a first operational circuit 311 provided in an embodiment of this disclosure. Figure 1 .like Figure 7 As shown, in the first region 401, the first word line 3111 can be connected to multiple memory cells 3117, that is, the first word line 3111 can be connected to multiple first memory cells 3117 (only one first memory cell 3117 connected to the first word line 3111 is shown in the figure). In the second region 402, the second word line 3112 can be connected to multiple memory cells 3118, that is, one second word line 3112 can be connected to multiple second memory cells 3118 (only one second memory cell 3118 connected to the second word line 3112 is shown in the figure).

[0130] The first memory cell 3117 and the second memory cell 3118 can each be composed of a capacitor and a transistor. The gate of the transistor is connected to the word line, the source / drain is connected to the bit line, and the source / drain is connected to the capacitor.

[0131] by Figure 7 For example, the target first character line can be the last first character line 3111 in the first region 401, or any other first character line 3111 in the first region 401.

[0132] After the target first word line is activated by changing its level, in the first arithmetic circuit 311, the first region 401 includes one activated first word line and multiple deactivated first word lines 3111, while the multiple deactivated second word lines 3112 in the second region 402 are all deactivated. That is, before the first and second data are written, the number of activated word lines in the first region 401 is greater than that in the second region 402.

[0133] When writing the first data into the first region 401, the level states of the remaining first word lines 3111 (excluding the target first word line) are controlled based on the first data, thereby obtaining the level states of multiple first word lines 3111. In other words, based on the specific value of the first data, the level states of the first word lines 3111 (excluding the target first word line) in the first region 401 are controlled to realize the writing of the first data into the first region 401.

[0134] When writing the second data into the second region 402, the level states of multiple second word lines 3112 are controlled based on the second data, thereby obtaining the level states of multiple second word lines 3112. In other words, based on the specific value of the second data, the level states of multiple second word lines 3112 in the second region 402 are controlled to realize the writing of the second data into the second region 402.

[0135] After writing the first data to the first region 401 and the second data to the second region 402, the number of activated first word lines 3111, excluding the target first word line, corresponds to the specific value of the first data; that is, the level states of the multiple first word lines 3111 correspond to the specific values ​​of the first data. Similarly, the number of activated second word lines 3112 corresponds to the specific values ​​of the second data; that is, the level states of the multiple second word lines 3112 correspond to the specific values ​​of the second data. At this point, the level states of the multiple first word lines 3111 and the multiple second word lines 3112 can be obtained respectively.

[0136] The level states of the first bit line 3113 and the second bit line 3114 are related to the first data and the second data; when the first data is the first value "1", the first bit line 3113 is in a high level state, and when the first data is the second value "0", the first bit line 3113 is in a low level state; when the second data is the first value "1", the second bit line 3114 is in a high level state, and when the second data is the second value "0", the second bit line 3114 is in a low level state.

[0137] For any memory cell, when both the word line and bit line connected to it are at a high level, the high level of the word line will turn on the transistor in the memory cell, so that the high level of the bit line is written into the capacitor of the memory cell, that is, the data "1" is written into the capacitor.

[0138] In this way, each memory cell 3117 can write data to its capacitor according to the level state of the first bit line 3113 and the first word line 3111 connected to it, so as to determine its own level state; each memory cell 3118 can write data to its capacitor according to the level state of the second bit line 3114 and the second word line 3112 connected to it, so as to determine its own level state; thus, the level states of multiple memory cells 3117 and multiple memory cells 3118 can be obtained.

[0139] The sensitive amplifier 3115 outputs the first calculation result based on the level states of the plurality of first storage cells 3117 and the plurality of second storage cells 3118.

[0140] In this way, the embodiments of this disclosure can complete the data operation and output the first operation result by means of word lines, without having to move the data from the storage module to the processor and then use the processor for comparison and operation, thereby improving the speed and efficiency of data processing and saving energy.

[0141] Furthermore, in some embodiments, the word line control circuit 3116 is used to control the target first word line to be in an activated state after receiving a first activation instruction.

[0142] It should be noted that in the first operational circuit 311, the first activation instruction represents the instruction to activate the target first word line. When the word line control circuit 3116 receives the first activation instruction, it indicates that the level state of the target first word line needs to be changed to activate the target first word line. At this time, the word line control circuit 3116 can adjust the target first word line from a low level state (first level state) to a high level state (second level state), thereby controlling the target first word line to be in an activated state.

[0143] It should also be noted that in the first arithmetic circuit 311, when a clearing process is required, a preset clearing instruction can be received through the word line control circuit 3116. The preset clearing instruction indicates an instruction to clear a specified memory area. After receiving the preset clearing instruction, the word line control circuit 3116 controls multiple first word lines 3111 and multiple second word lines 3112 to be inactive.

[0144] In the first arithmetic circuit 311, regarding the writing method of the first data, in some embodiments, the word line control circuit 3116 is further configured to, upon receiving the second activation instruction, control at least two first word lines 3111 other than the target first word line to be in an active state if the first data is a first value; and control the remaining first word lines 3111 other than the target first word line to be in an inactive state if the first data is a second value.

[0145] It should be noted that in the first arithmetic circuit 311, the second activation instruction represents an instruction to write the first data. When the word line control circuit 3116 receives the second activation instruction, it indicates that the first data needs to be written. Since the first data is a one-bit binary number, it can be divided into two cases: the first data is a first value "1", or the first data is a second value "0".

[0146] If the first data is the first value, then at least two first word lines 3111 other than the target first word line are determined from the plurality of first word lines 3111, and these at least two first word lines 3111 are controlled to be in an active state, that is, the level state of the at least two first word lines 3111 is changed from a low level state to a high level state, so that there are at least three active first word lines 3111 in the first region 401.

[0147] If the first data is the second value, since all the first word lines 3111 except the target first word line are already inactive, there is no need to process the multiple first word lines 3111. This ensures that all the remaining first word lines 3111 except the target first word line are inactive. In other words, all the other first word lines 3111 except the target first word line remain inactive, so that there is at least one active first word line 3111 in the first region 401.

[0148] For example, see Figure 8 It shows a schematic diagram of the circuit structure of a first operational circuit 311 provided in an embodiment of this disclosure. Figure 2 .like Figure 8 (or Figure 7 As shown in the diagram, in the first region 401, the vertical solid lines represent the first character line 3111 in the active state, and the vertical dashed lines represent the first character line 3111 in the inactive state; Figure 8 In the first region 401, the first and second first character lines 3111 and the last first character line 3111 (i.e. the target first character line) are active, while the remaining first character lines 3111 are inactive.

[0149] In this way, by controlling the level state of the first word line 3111, a certain number of the first word lines 3111 can be made active, so that the first data can be written into the first area 401 in the first arithmetic circuit 311, thereby eliminating the need to transfer data between the processor and the storage module and improving the data processing speed.

[0150] In the first arithmetic circuit 311, regarding the writing method of the second data, in some embodiments, when the second data is written to the second region 402, the word line control circuit 3116 is further configured to, after receiving the third activation instruction, control at least two second word lines 3112 in the second region 402 to be in an active state if the second data is a first value; and control multiple second word lines 3112 to be in an inactive state if the second data is a second value.

[0151] It should be noted that in the first arithmetic circuit 311, the third activation instruction represents an instruction to write the second data. When the word line control circuit 3116 receives the third activation instruction, it indicates that the second data needs to be written. Similar to the first data, since the second data is also a one-bit binary number, it can be divided into two cases: the second data is the first value "1", and the second data is the second value "0".

[0152] If the second data is the first value, then at least two second word lines 3112 are determined from the plurality of second word lines 3112, and these at least two second word lines 3112 are controlled to be in an active state.

[0153] It should also be noted that, in this embodiment, for the first word line 3111 and the second word line 3112, when changing the level state, if the low level state of the first word line 3111 and the low level state of the second word line 3112 are at the same level, and the high level state of the first word line 3111 and the high level state of the second word line 3112 are at the same level (within the allowable error range of the same level), then when both the first data and the second data are the first values, the number of at least two activated first word lines 3111 and at least two activated second word lines 3112 is the same. That is, if two first word lines 3111 are activated when the first data is the first value, then two second word lines 3112 are also activated when the second data is the second value; if three first word lines 3111 are activated when the first data is the first value, then three second word lines 3112 are also activated when the second data is the second value, and so on.

[0154] If the second data is the second value, since multiple second word lines 3112 are already inactive, there is no need to process the multiple second word lines 3112 anymore. At this time, all second word lines 3112 are inactive.

[0155] In other words, apart from the target first word line, when the data is the first value "1", at least two word lines need to be activated in the corresponding area, and when the data is the second value "0", no word lines in the corresponding area need to be activated.

[0156] For example, such as Figure 8 (or Figure 7 As shown in the diagram, in the second region 402, the vertical solid lines represent the second character line 3112 in the active state, and the vertical dashed lines represent the second character line 3112 in the inactive state; Figure 8 In the second region 402, the last and second-to-last second character lines 3112 are active, while the rest of the second character lines 3112 are inactive.

[0157] In other words, Figure 8 The diagram shows the state of the first arithmetic circuit 311 when both the first data and the second data are the first values.

[0158] When writing the first and second data, word lines can be selectively activated based on the high or low levels of the first bit line 3113 and the second bit line 3114. For example, for the first region 401, if the first data is a first value "1", the first bit line 3113 is at a high level, indicating that at least two first word lines 3111 in the first region 401, excluding the target first word line, need to be activated. If the first data is a second value "0", the first bit line 3113 is at a low level, and in this case, it is not necessary to activate the first word lines 3111 in the first region 401, excluding the target first word line. For the second region 402, if the second data is a first value "1", the second bit line 3114 is at a high level, indicating that at least two second word lines 3112 in the second region 402 need to be activated. If the second data is a second value "0", the second bit line 3114 is at a low level, and in this case, it is not necessary to activate the second word lines 3112 in the second region 402.

[0159] In this way, by controlling the level state of the word lines, a certain number of second word lines 3112 can be activated, enabling the second data to be written into the second region 402 in the first arithmetic circuit 311, thereby eliminating the need for data transmission between the processor and the storage module and improving data processing speed.

[0160] Furthermore, in some embodiments, the sensitive amplifier 3115 is used to perform a comparison operation on the first data and the second data after receiving a preset comparison instruction and output the first operation result.

[0161] In the first arithmetic circuit 311, a preset comparison instruction indicates an instruction to compare and perform a calculation on first data and second data, and output a first calculation result. After receiving the preset comparison instruction, the sensitive amplifier 3115 can read the first voltage provided by multiple first storage units 3117 and the second voltage provided by multiple second storage units 3118, and compare and perform a calculation on the first data and second data according to the first voltage and the second voltage, thereby obtaining and outputting the first calculation result; wherein, if the first voltage is higher than the second voltage, the first calculation result output by the sensitive amplifier 3115 is the first result value; or, if the first voltage is lower than the second voltage, the sensitive amplifier 3115 outputs the first calculation result as the second result value.

[0162] Specifically, when writing the first and second data, when the first bit line 3113 and the second bit line 3114 are at a high potential (high level state), the first word line 3111 and the second word line 3112 will be selectively activated. After activation, the first word line 3111 and the second word line 3112 are in the on state. At this time, the first bit line 3113 and the second bit line 3114 can write data to the capacitors of the memory cells connected to them respectively. That is, when the first bit line 3113 and the second bit line 3114 are both at a high potential, the first capacitor of the first memory cell 3117, which is connected to the first bit line 3113 and the first word line 3111 in the on state, will be written with the data "1". The second capacitor of the second memory cell 3118, which is connected to the second bit line 3114 and the second word line 3112 in the on state, will also be written with the data "1". When the first word line 3111 and the second word line 3112 are both at a high potential, the first word line 3111 and the second word line 3112 in the on state, will be written with the data "1". When multiple second word lines 3112 are activated, it indicates that multiple corresponding first and second capacitors have been written with data. The first and second capacitors are located in the first region 401 and the second region 402, respectively. After receiving a preset comparison command, the sensitive amplifier 3115 reads the data in the first and second capacitors respectively and compares the first voltage read from the first capacitor with the second voltage read from the second capacitor. If the first voltage is higher than the second voltage, it means that the overall level of the first region 401 is higher than the overall level of the second region 402. That is, the number of first capacitors with data written is greater than the number of second capacitors, that is, the number of first word lines 3111 in the active state is greater than the number of second word lines 3112 in the active state. Then, the first result value is output as the first operation result. The first result value can be the same as the first value, which is "1".

[0163] If the first voltage is lower than the second voltage, it means that the overall level of the first region 401 is lower than the overall level of the second region 402. That is, the number of first capacitors to which data is written is less than the number of second capacitors, and the number of first word lines 3111 in the active state is less than the number of second word lines 3112 in the active state. Then, the second result value is output as the first operation result. The second result value can be the same as the second value, which is "0".

[0164] In some embodiments, for the first operational circuit 311, if both the first data and the second data are the second value "0", then in the first region 401, there is a target first word line in an active state; in the second region 402, all the second word lines 3112 are in an inactive state; that is, the number of first word lines 3111 in the first region 401 in an active state is greater than the number of second word lines 3112 in the second region 402 in an active state, so the number of first capacitors to be written with data is greater than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the first result value "1".

[0165] If the first data is the second value "0" and the second data is the first value "1", then in the first region 401, only the target first word line is active; in the second region 402, at least two second word lines 3112 are active, that is, the number of active first word lines 3111 in the first region 401 is less than the number of active second word lines 3112 in the second region 402, so the number of first capacitors to be written with data is less than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the second result value "0".

[0166] If the first data is a first value "1" and the second data is a second value "0", then in the first region 401, at least three first word lines 3111 (including the target first word line) are active; in the second region 402, all second word lines 3112 are inactive, that is, the number of active first word lines 3111 in the first region 401 is greater than the number of active second word lines 3112 in the second region 402, so the number of first capacitors to be written with data is greater than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the first result value "1".

[0167] If both the first data and the second data are the first value "1", then in the first region 401, there are at least three first word lines 3111 (including the target first word line) in an active state; in the second region 402, there are at least two second word lines 3112 in an active state; and except for the target first word line, the number of first word lines 3111 and second word lines 3112 in an active state are the same in the first region 401 and the second region 402. Therefore, the first region 401 has one more target first word line in an active state than the second region 402, so the number of first capacitors to be written with data is more than the number of second capacitors to be written with data. Then the sensitive amplifier 3115 outputs the first result value "1".

[0168] Based on the first arithmetic circuit 311 provided in this embodiment, a truth table as shown in Table 3 can be obtained under four different combinations of the first and second data values. The first arithmetic circuit 311 in the storage area completes the data processing without transferring the data from the storage module to the processor, effectively improving the processing speed and saving energy.

[0169] For the second operational circuit 312, see Figure 6 , Figure 6It can also be used to represent the composition structure of the second operational circuit 312. That is, the first operational circuit 311 and the second operational circuit 312 can have the same composition structure. In this case, it is only necessary to set the output of the sensitive amplifier 3115 to the second operational result. For example... Figure 6 As shown, in some embodiments, the second operational circuit 312 may include a plurality of first word lines 3111, a plurality of second word lines 3112, a first bit line 3113, a second bit line 3114, a sensitive amplifier 3115, a word line control circuit 3116, a plurality of first memory cells 3117, and a plurality of second memory cells 3118; wherein,

[0170] The word line control circuit 3116 is used to control the level state of a plurality of first word lines 3111 according to the first data, so as to obtain the level state of the plurality of first word lines 3111;

[0171] The first line 3113 is used to determine the level state of the first line 3113 based on the first data;

[0172] Multiple first storage cells 3117 are used to determine the level state of multiple first storage cells 3117 based on the level state of multiple first word lines 3111 and the level state of the first bit line 3113.

[0173] The word line control circuit 3116 is also used to change the level state of the target second word line after the target second word line is determined, and to control the level state of the remaining second word lines 3112 other than the target second word line according to the second data, so as to obtain the level state of multiple second word lines 3112.

[0174] The second bit line 3114 is used to determine the level state of the second bit line 3114 according to the second data;

[0175] A plurality of second storage cells 3118 are configured to determine the level state of the plurality of second storage cells 3118 based on the level state of the plurality of second word lines 3112 and the level state of the second bit line 3114.

[0176] The sensitive amplifier 3115 is used to output a second calculation result based on the level states of the plurality of first storage cells 3117 and the level states of the plurality of second storage cells 3118.

[0177] It should be noted that, as Figure 6 As shown, the second operational circuit 312 and the first operational circuit 311 can have the same structure, but their operating methods differ. In the second operational circuit 312, the connection methods between the components are the same as in the first operational circuit 311, and will not be described again here.

[0178] It should also be noted that, similar to the first arithmetic unit 311, when performing the second arithmetic processing on the first and second data, it is first ensured that both the first region 401 and the second region 402 are in a cleared state. At this point, if both the first region 401 and the second region 402 are already in a cleared state, a target second word line is directly determined from the plurality of second word lines 3112, and the level state of the target second word line is changed. If neither the first region 401 nor the second region 402 are in a cleared state, a clearing process must be performed first.

[0179] Therefore, in some embodiments of the second operation circuit 312, the word line control circuit 3116 is also used to clear a plurality of first word lines 3111 and a plurality of second word lines 3112.

[0180] After clearing multiple first character lines 3111 and multiple second character lines 3112, all of them are inactive.

[0181] It should also be noted that the target second word line can be any one of the multiple second word lines 3112. The word line control circuit 3116 can change the level state of the target second word line, thereby activating the target second word line.

[0182] For example, see Figure 9 It shows a schematic diagram of the circuit structure of a second operational circuit 312 provided in an embodiment of this disclosure. Figure 1 .like Figure 9 As shown, the circuit structure of the second operational circuit 312 and the first operational circuit 311 can be the same, only their operating methods differ. See also... Figure 6 , Figure 6 It can also be used to represent the composition structure of the second operational circuit 312.

[0183] by Figure 9 For example, the target second character line can be the first second character line 3112 in the second region 402, or any other second character line 3112 in the second region 402.

[0184] After activating the target second word line by changing its level, in the second operational circuit 312, multiple first word lines 3111 in the first region 401 are inactive, while the second region 402 includes one activated target second word line and multiple inactive second word lines 3112. That is, before the first and second data are written, the number of activated word lines in the first region 401 is less than the number of activated word lines in the second region 402, and the overall level of the first region 401 is lower than that of the second region 402.

[0185] When writing the first data into the first region 401, the level states of multiple first word lines 3111 are controlled based on the first data, thereby obtaining the level states of multiple first word lines 3111. In other words, based on the specific value of the first data, the level states of multiple first word lines 3111 in the first region 401 are controlled to realize the writing of the first data into the first region 401.

[0186] When writing the second data into the second region 402, the level states of the remaining second word lines 3112 (excluding the target second word line) are controlled based on the second data, thereby obtaining the level states of the multiple second word lines 3112. In other words, based on the specific value of the second data, the level states of the second word lines 3112 (excluding the target second word line) in the second region 402 are controlled to achieve the writing of the second data into the second region 402.

[0187] After writing the first data to the first region 401 and the second data to the second region 402, the number of activated first word lines 3111 corresponds to the specific value of the first data, that is, the level states of the multiple first word lines 3111 correspond to the specific values ​​of the first data; except for the target second word line, the number of activated second word lines 3112 corresponds to the specific values ​​of the second data, that is, the level states of the multiple second word lines 3112 correspond to the specific values ​​of the second data. At this time, the level states of the multiple first word lines 3111 and the multiple second word lines 3112 can be obtained respectively.

[0188] Similarly to the first arithmetic circuit 311, in the second arithmetic circuit 312, based on the first data and the second data, the level states of the first bit line 3113, the second bit line 3114, the multiple first word lines 3111 and the multiple second word lines 3112 can be used to obtain the level states of the multiple memory cells 3117 and the multiple memory cells 3118.

[0189] The sensitive amplifier 3115 outputs a second calculation result based on the level states of multiple first storage cells 3117 and multiple second storage cells 3118.

[0190] The embodiments disclosed herein can complete the data processing by means of the device structure of the storage area and output the second calculation result, without having to transfer the data from the storage module to the processor and then use the processor for comparison and calculation, thereby improving the speed and efficiency of data processing and saving energy consumption.

[0191] Furthermore, in some embodiments, the word line control circuit 3116 is used to control the target second word line to be in an active state after receiving a first activation instruction.

[0192] It should be noted that in the second operation circuit 312, the first activation instruction represents the instruction to activate the target second word line. When the word line control circuit 3116 receives the first activation instruction, it controls the target second word line to be in an activated state.

[0193] It should also be noted that in the second operational circuit 312, when a clearing process is required, the implementation process can refer to the clearing process in the first operational circuit 311 mentioned above, which will not be repeated here.

[0194] In the second operation circuit 312, regarding the writing method of the first data, in some embodiments, the word line control circuit 3116 is further configured to, upon receiving the second activation instruction, control at least two first word lines 3111 to be in an active state if the first data is a first value; and control multiple first word lines 3111 to be in an inactive state if the first data is a second value.

[0195] It should be noted that in the second operational circuit 312, the second activation instruction represents an instruction to write the first data. When the word line control circuit 3116 receives the second activation instruction, it indicates that the first data needs to be written. At this time, there are still two cases: the value of the first data is the first value "1", or the value of the first data is the second value "0".

[0196] If the first data is the first value, then at least two first word lines 3111 are determined from the plurality of first word lines 3111, and these at least two first word lines 3111 are controlled to be in an active state, so that there are at least two first word lines 3111 in an active state in the first region 401.

[0197] If the first data is the second value, since multiple first word lines 3111 are already in an inactive state, there is no need to process multiple first word lines 3111 to control all first word lines 3111 to be in an inactive state.

[0198] For example, see Figure 10 It shows a schematic diagram of the circuit structure of a second operational circuit 312 provided in an embodiment of this disclosure. Figure 2 .like Figure 10 (or Figure 9 As shown in the diagram, in the first region 401, the vertical solid lines represent the first character line 3111 in the active state, and the vertical dashed lines represent the first character line 3111 in the inactive state; Figure 11 In the first region 401, the first and second first word lines 3111 are active, while the rest of the first word lines 3111 are inactive.

[0199] In the second operation circuit 312, regarding the writing method of the second data, in some embodiments, when the second data is written to the second region 402, the word line control circuit 3116 is further configured to, after receiving the third activation instruction, if the second data is the first value, control at least two second word lines 3112 in the second region 402 other than the target second word line to be in an active state; if the second data is the second value, control the remaining second word lines 3112 other than the target second word line to be in an inactive state.

[0200] It should be noted that in the second operational circuit 312, the third activation instruction represents an instruction to write the second data. When the word line control circuit 3116 receives the third activation instruction, it indicates that the second data needs to be written. At this time, there are still two cases: the value of the second data is the first value "1", and the value of the second data is the second value "0".

[0201] If the second data is the first value, then at least two second word lines 3112 other than the target second word line are determined from the plurality of second word lines 3112, and these at least two second word lines 3112 are controlled to be in an active state.

[0202] If the second data is the second value, since all second word lines 3112 except the target second word line are already inactive (i.e., in a low-level state), there is no need to process the multiple second word lines 3112. At this time, the remaining second word lines 3112 except the target second word line are controlled to be inactive.

[0203] In other words, apart from the target second word line, when the data is the first value "1", at least two word lines need to be activated in the corresponding area, and when the data is the second value "0", no word lines in the corresponding area need to be activated.

[0204] For example, such as Figure 10 (or Figure 9 As shown in the diagram, in the second region 402, the vertical solid lines represent the second character line 3112 in the active state, and the vertical dashed lines represent the second character line 3112 in the inactive state; Figure 11In the second region 402, the last and second-to-last second character lines 3112 and the first second character line 3112 (i.e. the target second character line) are active, while the rest of the second character lines 3112 are inactive.

[0205] In other words, Figure 10 The diagram shows the state of the second operational circuit 312 when both the first and second data are the first values.

[0206] When writing the first and second data, word lines can be selectively activated based on the high or low levels of the first bit line 3113 and the second bit line 3114. For example, for the first region 401, if the first data is the first value "1", the first bit line 3113 is at a high level, indicating that at least two first word lines 3111 in the first region 401 need to be activated. If the first data is the second value "0", the first bit line 3113 is at a low level, and in this case, the first word lines 3111 in the first region 401 do not need to be activated. For the second region 402, if the second data is the first value "1", the second bit line 3114 is at a high level, indicating that at least two second word lines 3112 in the second region 402, excluding the target second word line, need to be activated. If the second data is the second value "0", the second bit line 3114 is at a low level, and in this case, the second word lines 3112 in the second region 402, excluding the target second word line, do not need to be activated.

[0207] Furthermore, regarding the second calculation result, in some embodiments, the sensitive amplifier 3115 is used to compare and perform calculations on the first data and the second data after receiving a preset comparison instruction and output the second calculation result.

[0208] In the second operational circuit 312, a preset comparison instruction indicates an instruction to compare and perform a calculation on the first data and the second data, and output the second calculation result. Upon receiving the preset comparison instruction, the sensitive amplifier 3115 can read the first voltage provided by multiple first storage units 3117 and the second voltage provided by multiple second storage units 3118, and compare and perform a calculation on the first data and the second data based on the first voltage and the second voltage, thereby obtaining the second calculation result for output; wherein,

[0209] If the first voltage is higher than the second voltage, the second calculation result output by the sensitive amplifier 3115 is the first result value; or, if the first voltage is lower than the second voltage, the second calculation result output by the sensitive amplifier 3115 is the second result value.

[0210] Here, the specific method of data writing is the same as that of the first operational circuit 311 mentioned above, and will not be repeated here.

[0211] If the first voltage is higher than the second voltage, the first result value is output as the second calculation result. The first result value can be the same as the first value, which is "1".

[0212] If the first voltage is lower than the second voltage, the second result value is output as the second calculation result. The second result value can be the same as the second value, which is "0".

[0213] Thus, for the second operational circuit 312, if both the first data and the second data are the second value "0", then in the first region 401, all the first word lines 3111 are inactive; in the second region 402, there is a target second word line that is active; that is, the number of first word lines 3111 in the first region 401 that are active is less than the number of second word lines 3112 in the second region 402 that are active, so the number of first capacitors to be written with data is less than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the second result value "0".

[0214] If the first data is the second value "0" and the second data is the first value "1", then in the first region 401, all the first word lines 3111 are inactive; in the second region 402, at least three second word lines 3112 (including the target second word line) are active; that is, the number of active first word lines 3111 in the first region 401 is less than the number of active second word lines 3112 in the second region 402, so the number of first capacitors to be written with data is less than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the second result value "0".

[0215] If the first data is a first value "1" and the second data is a second value "0", then in the first region 401, there are at least two first word lines 3111 in an active state; in the second region 402, only the target second word line is active; that is, the number of first word lines 3111 in the first region 401 in an active state is greater than the number of second word lines 3112 in the second region 402 in an active state, so the number of first capacitors to be written with data is greater than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the first result value "1".

[0216] If both the first data and the second data are the first value "1", then in the first region 401, there are at least two first word lines 3111 in the active state; in the second region 402, there are at least three second word lines 3112 (including the target second word line) in the active state; and except for the target second word line, the number of first word lines 3111 and second word lines 3112 in the active state in the first region 401 and the second region 402 are the same. Then, the second region 402 has one more target second word line in the active state than the first region 401, so the number of first capacitors to be written with data is less than the number of second capacitors to be written with data, and the sensitive amplifier 3115 outputs the second result value "0".

[0217] Based on the second arithmetic circuit 312 provided in this embodiment, a truth table as shown in Table 3 can be obtained under four different combinations of the first and second data values. The second arithmetic circuit 312 eliminates the need to transfer data from the storage module to the processor for computation, effectively improving processing speed and saving energy.

[0218] For the target computing circuit 32, see Figure 11 This illustrates a schematic diagram of the composition structure of a target computing circuit 32 provided in an embodiment of this disclosure. For example... Figure 11 As shown, in some embodiments, the target computing circuit 32 may include a third arithmetic circuit 321 and a fourth arithmetic circuit 322; wherein,

[0219] The third arithmetic circuit 321 is used to perform a first arithmetic processing on the second arithmetic result and the first arithmetic result, and output the first target result;

[0220] The fourth arithmetic circuit 322 is used to perform a second arithmetic processing on the first data and the second arithmetic result, and output the second target result.

[0221] It should be noted that, as Figure 11 As shown, the target computing circuit 32 may include a third arithmetic circuit 321 and a fourth arithmetic circuit 322. The third arithmetic circuit 321 is a circuit unit in the target computing circuit 32 used to perform the first arithmetic process, and the third arithmetic circuit 322 is a circuit unit in the target computing circuit 32 used to perform the second arithmetic process.

[0222] The third arithmetic circuit 321 receives the first arithmetic result output by the first arithmetic circuit 311 and the second arithmetic result output by the second arithmetic circuit 312 as inputs, performs a first arithmetic process on the first and second arithmetic results, and outputs the first target result.

[0223] The fourth arithmetic circuit 322 takes the first data and the second arithmetic result output by the second arithmetic circuit 312 as inputs, performs the second arithmetic processing on the first data and the second arithmetic result, and outputs the second target result.

[0224] It should also be noted that the truth table obtained by the third operational circuit 321 after performing the first operational process is shown in Table 4:

[0225] Table 4

[0226]

[0227] It should be noted that the operation methods of the third operation circuit 321 and the first operation circuit 311 are both the first operation processing, that is, the operation methods of the two are the same. Therefore, the truth tables of the third operation circuit and the first operation processing are the same. The only difference is that the input of the third operation circuit 321 depends on the output of the first operation circuit 311 and the second operation circuit 312.

[0228] In other words, the input to the third arithmetic circuit 321 is the result of processing the first and second data by the first arithmetic circuit 311 and the second arithmetic circuit 312. For the first and second data, there are four different combinations as shown in the first and second columns of Table 4. The first and second operation results obtained under different combinations are shown in the fourth and third columns of Table 4. After the third arithmetic circuit 321 performs the first operation on the first and second operation results, the output first target result is shown in the fifth column of Table 5. The first target result is the XOR operation result of the first and second data, i.e., the sum S.

[0229] For the fourth operational circuit 322, the truth table obtained by performing the second operation is shown in Table 5:

[0230] Table 5

[0231]

[0232] It should be noted that the operation methods of the fourth operation circuit 322 and the second operation circuit 312 are both second operation processing, that is, the operation methods of the two are the same, only the input of the fourth operation circuit 322 depends on the output of the second operation circuit 312.

[0233] The input to the fourth arithmetic circuit 322 is the first data, and the second operation result obtained after the second arithmetic circuit 312 performs a second operation on the first and second data. For the first and second data, there are four different combinations as shown in the first and second columns of Table 5. The second operation result obtained under different combinations is shown in the fourth column of Table 5. After the fourth arithmetic circuit 322 performs the second operation on the first data and the second operation result, the output second target result is shown in the fifth column of Table 5. The second target result is the result of the AND operation of the first and second data, i.e., the carry C. Thus, based on the first arithmetic circuit 311, the second arithmetic circuit 312, the third arithmetic circuit 321, and the fourth arithmetic circuit 322, an in-memory computing circuit 30 is formed. For the in-memory computing circuit 30, its truth table is Table 1. That is, based on the in-memory computing circuit 30, the function of a half-adder can be implemented in memory without data transfer.

[0234] It should be noted that, in the disclosed embodiments, the structures of the first operational circuit 311, the second operational circuit 312, the third operational circuit 321, and the fourth operational circuit 322 can be the same, and can all be referred to as follows: Figure 6 The diagram shows the structural composition. For the third operational circuit 321, the input to the first region 401 is the second operational result, the input to the second region 402 is the first operational result, and the output of the sensitive amplifier 3115 is the first target result. For the fourth operational circuit 322, the input to the first region 401 is the first data, the input to the second region 402 is the second operational result, and the output of the sensitive amplifier 3115 is the second target result.

[0235] Therefore, for the third operational circuit 321:

[0236] In some embodiments, the third operational circuit may include a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells, and a plurality of second memory cells; wherein,

[0237] The word line control circuit is used to change the level state of the target first word line after determining the target first word line, and to control the level state of the remaining first word lines other than the target first word line according to the second calculation result, so as to obtain the level state of multiple first word lines.

[0238] The first line is used to determine the voltage level of the first line based on the result of the second operation.

[0239] Multiple first storage cells are configured to determine the level state of the multiple first storage cells based on the level state of the multiple first word lines and the level state of the first bit line.

[0240] The word line control circuit is also used to control the level state of multiple second word lines according to the first calculation result, so as to obtain the level state of multiple second word lines;

[0241] The second bit line is used to determine the level state of the second bit line based on the result of the first operation;

[0242] Multiple second storage cells are used to determine the level state of the multiple second storage cells based on the level state of multiple second word lines and the level state of multiple bit lines;

[0243] A sensitive amplifier is used to output a first target result based on the level states of a plurality of first memory cells and a plurality of second memory cells.

[0244] In some embodiments, the word line control circuit is further configured to clear a plurality of first word lines and a plurality of second word lines.

[0245] In some embodiments, the word line control circuit is configured to control the target first word line to be in an activated state after receiving a first activation instruction.

[0246] In some embodiments, the word line control circuit is further configured to, upon receiving a second activation instruction, control at least two first word lines other than the target first word line to be in an active state if the second operation result is a first result value; and control the remaining first word lines other than the target first word line to be in an inactive state if the first operation result is a second result value.

[0247] In some embodiments, the word line control circuit is further configured to, upon receiving a third activation instruction, control at least two second word lines to be in an active state if the first operation result is a first result value, and control multiple second word lines to be in an inactive state if the first operation result is a second result value.

[0248] In some embodiments, the sensitive amplifier is configured to, upon receiving a preset comparison instruction, read a first voltage provided by a plurality of first memory cells and a second voltage provided by a plurality of second memory cells, and compare a second calculation result with a first calculation result based on the first voltage and the second voltage, and output a first target result; wherein,

[0249] If the first voltage is higher than the second voltage, the first target result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the first target result output by the sensitive amplifier is the second result value.

[0250] It should be noted that the third operational circuit operates in the same way as the first operational circuit. For a detailed description of the operation method of the third operational circuit, please refer to the description of the first operational circuit. It will not be repeated here.

[0251] For the fourth operational circuit 322:

[0252] In some embodiments, the fourth operational circuit may include a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells, and a plurality of second memory cells; wherein,

[0253] A word line control circuit is used to control the level state of multiple first word lines according to the first data, so as to obtain the level state of multiple first word lines;

[0254] The first line is used to determine the voltage level of the first line based on the first data.

[0255] Multiple first storage cells are configured to determine the level state of the multiple first storage cells based on the level state of the multiple first word lines and the level state of the first bit line.

[0256] The word line control circuit is also used to change the level state of the target second word line after the target second word line is determined, and to control the level state of the remaining second word lines other than the target second word line according to the second calculation result, so as to obtain the level state of multiple second word lines.

[0257] The second bit line is used to determine the level state of the second bit line based on the result of the second operation.

[0258] Multiple second storage cells are used to determine the level state of the multiple second storage cells based on the level state of multiple second word lines and the level state of multiple bit lines;

[0259] A sensitive amplifier is used to output a second target result based on the level states of a plurality of first memory cells and a plurality of second memory cells.

[0260] In some embodiments, the word line control circuit is further configured to clear a plurality of first word lines and a plurality of second word lines.

[0261] In some embodiments, the word line control circuit is used to control the target second word line to be in an active state after receiving a first activation instruction.

[0262] In some embodiments, the word line control circuit is further configured to, upon receiving a second activation instruction, control at least two first word lines to be in an active state if the first data is a first value, and control multiple first word lines to be in an inactive state if the first data is a second value.

[0263] In some embodiments, the word line control circuit is further configured to, upon receiving a third activation instruction, control at least two second word lines other than the target second word line to be in an active state if the second operation result is the first result value; and control the remaining second word lines other than the target second word line to be in an inactive state if the second data is the second result value.

[0264] In some embodiments, the sensitive amplifier is configured to, upon receiving a preset comparison instruction, read a first voltage provided by a plurality of first memory cells and a second voltage provided by a plurality of second memory cells, perform a comparison operation on first data and second data based on the first voltage and the second voltage, and output a second target result; wherein,

[0265] If the first voltage is higher than the second voltage, the second target result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the second target result output by the sensitive amplifier is the second result value.

[0266] It should be noted that the fourth operational circuit operates in the same way as the second operational circuit. For a detailed description of the operation method of the fourth operational circuit, please refer to the description of the second operational circuit. It will not be repeated here.

[0267] It should also be noted that, in the embodiments of this disclosure, the level states of the word lines are adjusted using relatively low and high level states. In practical applications, the changes in the level states of each word line are not necessarily exactly the same, nor do they completely follow the exemplary high and low states provided in the embodiments of this application. The adjustment of the level states is only necessary to achieve the function of each arithmetic circuit, and the embodiments of this disclosure do not impose specific limitations on this.

[0268] Further, see Figure 12 It shows a simplified structural diagram of an in-memory computing circuit 30 provided in an embodiment of the present disclosure. Figure 1 In this context, SA represents the Sense Amplifier in the operational circuit. In the initial calculation circuit 31 and the target calculation circuit 32, the solid box indicates the operational circuit in the in-memory calculation circuit 30, and the dashed box indicates other circuits in the in-memory calculation circuit used to perform other functions of the circuit.

[0269] like Figure 13 As shown, for the first arithmetic circuit 311 and the second arithmetic circuit 312 included in the initial calculation circuit 31, the first arithmetic circuit 311 processes the first data and the second data according to the first arithmetic processing method to obtain the first arithmetic result.

[0270] The second arithmetic circuit 312 processes the first data and the second data according to the second arithmetic processing method to obtain the second arithmetic result.

[0271] For the third arithmetic circuit 321 and the fourth arithmetic circuit 322 included in the target calculation circuit 32, the third arithmetic circuit 321 processes the second arithmetic result and the first arithmetic result according to the arithmetic method of the first arithmetic processing to obtain the first target result, which is the XOR operation result of the first data and the second data.

[0272] The fourth arithmetic circuit 322 processes the first data and the second arithmetic result according to the arithmetic method of the second arithmetic processing to obtain the second target result. The second target data is the result of the AND operation of the first data and the second data.

[0273] Further, see Figure 13 It shows a simplified structural diagram of an in-memory computing circuit 30 provided in an embodiment of the present disclosure. Figure 2 .like Figure 13 As shown, the in-memory computing circuit 30 may include multiple first arithmetic circuits 311, multiple second arithmetic circuits 312, multiple third arithmetic circuits 321, and multiple fourth arithmetic circuits 322.

[0274] like Figure 13 As shown, taking 8G fourth-generation double data rate synchronous dynamic random access memory (DDR4) as an example, at least 1024 sensitive amplifiers are activated when one word line is active, so 1024 bits can be added simultaneously. Data 1 and Data 2 are both 1024-bit binary numbers. Data 1 provides the first data (addend), and Data 2 provides the second data (addend). In the first row of the in-memory calculation circuit 30, the first data is the 1024th bit of Data 1, which is 1, and the second data is the 1024th bit of Data 2, which is 1. In the second row of the in-memory calculation circuit 30, the first data is the 1023rd bit of Data 1, which is 0, and the second data is the 1023rd bit of Data 2, which is 1. ... In the 1023rd row of the in-memory calculation circuit 30, the first data is the 2nd bit of Data 1, which is 1, and the second data is the 2nd bit of Data 2, which is 1. In the 1024th row of the in-memory calculation circuit 30, the first data is the 1024th bit of Data 1, which is 0, and the second data is the 1024th bit of Data 2, which is 0.

[0275] In this way, through the calculation of each of the 1024 rows of the internal computing circuit 30, the XOR operation result and AND operation result of each corresponding number of data 1 and data 2 can be obtained.

[0276] In this embodiment, the in-memory computing circuit is implemented using memory devices such as DRAM and SRAM. Both DRAM and SRAM include word lines, bit lines, and memory cells. By controlling the activation of word lines and comparing data using a sensitive amplifier, data operations can be performed. In other words, the in-memory computing circuit 30 has the same structure as a conventional memory module and can be applied to conventional memory modules without changing the existing computer architecture, making it highly feasible and cost-effective.

[0277] Furthermore, in some embodiments, see Figure 14 It shows a schematic diagram of the circuit structure of an arithmetic circuit provided in an embodiment of this disclosure. Figure 14 It can represent any one of the following operational circuits: the first operational circuit 311, the second operational circuit 312, the third operational circuit 321, and the fourth operational circuit 322. Here, we take the first operational circuit 311 as an example.

[0278] like Figure 14 As shown, the first operational circuit 311 may further include a plurality of first adjacent memory cells 3211, a plurality of second adjacent memory cells 3212, a first adjacent bit line 3213, a second adjacent bit line 3214, and an adjacent sensitive amplifier 3215. The plurality of first adjacent memory cells 3211 are connected to the adjacent sensitive amplifier 3215 through the first adjacent bit line 3213, and the plurality of second adjacent memory cells 3212 are connected to the adjacent sensitive amplifier 3215 through the second adjacent bit line 3214.

[0279] In other words, the first word line 3111 can connect not only to one first memory cell 3117, but also to one or more first adjacent memory cells 3211; the second word line 3112 can connect not only to one second memory cell 3118, but also to one or more second adjacent memory cells 3212. That is, for a first word line 3111, it is connected to one first memory cell 3117 and at least one first adjacent memory cell 3211; for a second word line 3112, it is connected to one second memory cell 3118 and at least one second adjacent memory cell 3212.

[0280] In this situation, opening all first word lines 3111 and second word lines 3112 could potentially corrupt data in other memory cells connected to the same word line. To address this issue, embodiments of this disclosure may provide an isolation transistor between two adjacent memory cells connected to the same word line to isolate the memory cells, thereby preventing corruption of other data.

[0281] For example, an a-th first isolation transistor 3151 is disposed between the a-th first adjacent memory cell 3211 and the a-th first memory cell 3117 located on the same first word line 3111; a b-th second isolation transistor 3152 is disposed between the b-th second adjacent memory cell 3212 and the b-th second memory cell 3118 located on the same second word line 3112. Here, a and b are both positive integers.

[0282] In addition, the drain of the a-th first isolation transistor 3151 is connected to the gate of the transistor in the a-th first memory cell 3117 through the first word line 3111, and the source of the a-th first isolation transistor 3151 is connected to the gate of the transistor in the a-th first adjacent memory cell 3211 through the first word line 3111.

[0283] The drain of the b-th second isolation transistor 3152 is connected to the gate of the transistor in the b-th second memory cell 3118 through the second word line 3112, and the source of the b-th second isolation transistor 3152 is connected to the gate of the transistor in the b-th second adjacent memory cell 3212 through the second word line 3112.

[0284] By adding an isolation transistor between two adjacent memory cells, the data in adjacent memory cells can be prevented from being corrupted after all word lines are opened. At the same time, when only a portion of the memory area is needed to store data, the isolation transistor can electrically isolate the data storage area from the memory area where operations are performed, thus achieving both storage and operation in the memory area and improving the utilization rate of the memory area device.

[0285] In some embodiments, the in-memory computing circuit 30 satisfies at least one of the following operations: half addition, full addition, and multiplication.

[0286] It should be noted that, in addition to being able to perform half addition operations, the in-memory computing circuit 30 provided in this embodiment can also perform operations such as full addition and multiplication operations based on the same operational principle.

[0287] Further, see Figure 15 This illustrates a schematic diagram of the architecture of a computing device provided in an embodiment of this disclosure. Figure 15 As shown, the architecture includes main memory, L3 cache, L2 cache, L1d cache, L1i cache, and CPU core. Both main memory and L3 cache are connected to the data bus. The connections of other modules are illustrated in the diagram. Table 6 shows the clock cycles required to access several key locations.

[0288] Table 6

[0289] register Less than or equal to 1 Level 1 data cache Approximately 3 Second-level cache Approximately 14 main memory Approximately 240

[0290] As shown in Table 6, each memory access requires approximately 240 clock cycles. This means that if data comparison operations are required, the processor needs to access memory multiple times to obtain the data before performing the comparison. However, in this embodiment, memory is used for data processing, thus saving processor time accessing memory. Specifically, each memory-based data comparison operation saves approximately 240 (N-2) clock cycles, where N is the number of accesses.

[0291] In short, in the in-memory computing circuit provided in the embodiments of this disclosure, for each arithmetic circuit, when performing a calculation, the specified area in the memory (e.g., DRAM) is first cleared (data 0 is written), and 1 is pre-written on the specified bit line (target first bit line / target second bit line).

[0292] The processor then stores the data requiring addition into the cleared regions. The data storage rule is as follows: for the first and second arithmetic circuits, the first data (addend) is stored in the first region, and the second data (addend) is stored in the second region. When the sensitive amplifier in the circuit is activated, the first operation result can be obtained based on the first arithmetic operation, and the second operation result can be obtained based on the second arithmetic operation.

[0293] Then, the second and first operation results are input into the third operation circuit, and the first data and second operation results are input into the fourth operation circuit. The data storage rules are as follows: for the third operation circuit, the second operation result is stored in the first area, and the first operation result is stored in the second area; for the fourth operation circuit, the first data is stored in the first area, and the second operation result is stored in the second area. The first operation is executed again to obtain the first target result, and the second operation is executed again to obtain the second target result. This achieves the XOR and AND operations, realizing the function of a half adder.

[0294] In other words, in this embodiment of the present disclosure, data that requires a large number of addition operations in the computer can be first divided into addends and augends and stored in memory. Then, a large number of addition operations can be achieved in memory by simultaneously activating multiple word lines and the operating characteristics of the sensitive amplifier, which can greatly reduce the operation time and power consumption.

[0295] This disclosure provides an in-memory computing circuit, including an initial computing circuit and a target computing circuit. The initial computing circuit performs a first operation on first data and second data, outputting a first operation result; and performs a second operation on the first data and second data, outputting a second operation result. The target computing circuit performs a first operation on the second operation result and the first operation result, outputting a first target result; and performs a second operation on the first data and the second operation result, outputting a second target result. Thus, by performing two first operation operations and two second operation operations on the first data and second data through the in-memory computing circuit, the XOR operation result and the AND operation result of the first data and second data can be obtained, achieving an operation effect equivalent to a half-adder, thereby improving the data processing speed. Furthermore, this disclosure embodiment can complete data processing using a storage unit, eliminating the need to transfer data from the storage module to the processor for processing, improving data processing speed and efficiency, and saving energy. Moreover, the in-memory computing circuit includes a storage unit and a sensitive amplifier, with the same structure as a common storage module, and can be applied to conventional storage modules without changing the existing memory device structure, making it highly feasible and low-cost to implement.

[0296] In another embodiment of this application, see Figure 16 This illustrates a flowchart of an in-memory computing method provided in an embodiment of this disclosure. Figure 16 As shown, the method may include:

[0297] S101: Perform a first operation on the first data and the second data through the initial calculation circuit and output the first operation result; and perform a second operation on the first data and the second data and output the second operation result.

[0298] S102: Perform a first operation on the second operation result and the first operation result through the target calculation circuit, and output the first target result; and perform a second operation on the first data and the second operation result, and output the second target result.

[0299] It should be noted that this in-memory calculation method is applied to the in-memory calculation circuit 30 described in the foregoing embodiment. The first target result indicates the result of the XOR operation between the first data and the second data, and the second target result indicates the result of the AND operation between the first data and the second data.

[0300] In some embodiments, the initial computing circuit may include a first computing circuit and a second computing circuit, and the target computing circuit may include a third computing circuit and a fourth computing circuit.

[0301] The process involves performing a first operation on the first data and the second data using an initial calculation circuit, outputting a first operation result; and performing a second operation on the first data and the second data, outputting a second operation result. This process may include:

[0302] The first arithmetic circuit performs a first arithmetic process on the first data and the second data, and outputs the first arithmetic result.

[0303] The second arithmetic circuit performs a second arithmetic operation on the first and second data, and outputs the second arithmetic result.

[0304] The first calculation process, which involves performing a first operation on the second and first calculation results using a target calculation circuit to output a first target result, and the second calculation process, which involves performing a second operation on the first data and the second calculation result to output a second target result, may include:

[0305] The third arithmetic circuit performs a first arithmetic process on the second arithmetic result and the first arithmetic result, and outputs a first target result; the fourth arithmetic circuit performs a second arithmetic process on the first data and the second arithmetic result, and outputs a second target result.

[0306] It should be noted that, in this embodiment of the disclosure, the operation method of the third operation circuit is the same as that of the first operation circuit, and the operation method of the fourth operation circuit is the same as that of the second operation circuit.

[0307] Furthermore, for the first operation result, in some embodiments, the first operation circuit may include a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells and a plurality of second memory cells;

[0308] The first arithmetic circuit performs a first arithmetic operation on the first data and the second data, and outputs the first arithmetic result, which may include:

[0309] After determining the target first word line, the level state of the target first word line is changed by the word line control circuit, and the level state of the remaining first word lines other than the target first word line is controlled according to the first data to obtain the level state of multiple first word lines;

[0310] The word line control circuit controls the level state of multiple second word lines according to the second data to obtain the level state of multiple second word lines.

[0311] Based on the first data, determine the level state of the first line;

[0312] The level states of multiple first memory cells are determined based on the level states of multiple first word lines and the level state of the first bit line.

[0313] Based on the second data, determine the level state of the second bit line;

[0314] The level states of multiple second memory cells are determined based on the level states of multiple second word lines and second bit lines.

[0315] The first calculation result is output by a sensitive amplifier based on the level states of multiple first memory cells and multiple second memory cells.

[0316] In some embodiments, changing the level state of a target first word line via a word line control circuit may include:

[0317] The word line control circuit receives the first activation command and controls the target first word line to be in an activated state.

[0318] In some embodiments, before changing the level state of the target first word line via the word line control circuit, the method may further include:

[0319] Multiple first word lines are cleared using the word line control circuit; and

[0320] Multiple second word lines are cleared using a word line control circuit.

[0321] In some embodiments, controlling the level state of the remaining first word lines other than the target first word line based on the first data may include:

[0322] The word line control circuit receives a second activation command. If the first data is the first value, it controls at least two first word lines other than the target first word line to be in an active state. If the first data is the second value, it controls the remaining first word lines other than the target first word line to be in an inactive state.

[0323] In some embodiments, controlling the level states of a plurality of second word lines based on second data may include:

[0324] The word line control circuit receives a third activation command. If the second data is the first value, it controls at least two second word lines to be in an active state; if the second data is the second value, it controls multiple second word lines to be in an inactive state.

[0325] In some embodiments, outputting a first calculation result by a sensitive amplifier based on the level states of a plurality of first memory cells and a plurality of second memory cells may include:

[0326] After receiving a preset comparison command, the system reads the first voltage provided by multiple first storage cells and the second voltage provided by multiple second storage cells through a sensitive amplifier, and performs comparison operations on the first data and the second data based on the first voltage and the second voltage, and outputs the first calculation result.

[0327] Specifically, if the first voltage is higher than the second voltage, the first calculation result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the first calculation result output by the sensitive amplifier is the second result value.

[0328] Furthermore, for the second operation result, in some embodiments, the second operation circuit may include a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells and a plurality of second memory cells;

[0329] The second processing circuit performs a second operation on the first and second data, and outputs the second operation result, which may include:

[0330] The word line control circuit controls the level state of multiple first word lines according to the first data to obtain the level state of multiple first word lines;

[0331] After determining the target second word line, the level state of the target second word line is changed by the word line control circuit, and the level state of the remaining second word lines other than the target second word line is controlled according to the second data to obtain the level state of multiple second word lines.

[0332] Based on the first data, determine the level state of the first line;

[0333] The level states of multiple first memory cells are determined based on the level states of multiple first word lines and the level state of the first bit line.

[0334] Based on the second data, determine the level state of the second bit line;

[0335] The level states of multiple second memory cells are determined based on the level states of multiple second word lines and second bit lines.

[0336] The second calculation result is output by a sensitive amplifier based on the level states of multiple first memory cells and multiple second memory cells.

[0337] In some embodiments, changing the level state of the target second word line via a word line control circuit may include:

[0338] The word line control circuit receives the first activation command and controls the target second word line to be in an activated state.

[0339] In some embodiments, before changing the level state of the target second word line via the word line control circuit, the method may further include:

[0340] Multiple first word lines are cleared using the word line control circuit; and

[0341] Multiple second word lines are cleared using a word line control circuit.

[0342] In some embodiments, controlling the level states of a plurality of first word lines based on first data may include:

[0343] The word line control circuit receives a second activation command. If the first data is the first value, it controls at least two first word lines to be in an active state; if the first data is the second value, it controls multiple first word lines to be in an inactive state.

[0344] In some embodiments, controlling the level state of the remaining second word lines other than the target second word line based on the second data may include:

[0345] The word line control circuit receives a third activation command. If the second data is the first value, it controls at least two second word lines other than the target second word line to be in an active state. If the second data is the second value, it controls the remaining second word lines other than the target second word line to be in an inactive state.

[0346] In some embodiments, outputting a second calculation result by a sensitive amplifier based on the level states of a plurality of first memory cells and a plurality of second memory cells may include:

[0347] After receiving a preset comparison command, the system reads the first voltage provided by multiple first storage cells and the second voltage provided by multiple second storage cells through a sensitive amplifier, and performs comparison operations on the first data and the second data based on the first voltage and the second voltage, and outputs the second operation result.

[0348] Specifically, if the first voltage is higher than the second voltage, the second calculation result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the second calculation result output by the sensitive amplifier is the second result value.

[0349] Furthermore, for the first target result, in some embodiments, the third operational circuit may include a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells, and a plurality of second memory cells;

[0350] The third arithmetic circuit performs a first arithmetic process on the second and first arithmetic results to output the first target result, which may include:

[0351] After determining the target first word line, the level state of the target first word line is changed through the word line control circuit, and the level state of the remaining first word lines other than the target first word line is controlled according to the second calculation result to obtain the level state of multiple first word lines;

[0352] The word line control circuit controls the level state of multiple second word lines according to the first calculation result, thereby obtaining the level state of multiple second word lines.

[0353] Based on the result of the second operation, determine the level state of the first line;

[0354] The level states of multiple first memory cells are determined based on the level states of multiple first word lines and the level state of the first bit line.

[0355] Based on the result of the first operation, determine the level state of the second bit line;

[0356] The level states of multiple second memory cells are determined based on the level states of multiple second word lines and second bit lines.

[0357] The first target result is output by a sensitive amplifier based on the level states of multiple first memory cells and multiple second memory cells.

[0358] In some embodiments, changing the level state of a target first word line via a word line control circuit may include:

[0359] The word line control circuit receives the first activation command and controls the target first word line to be in an activated state.

[0360] In some embodiments, before changing the level state of the target first word line via the word line control circuit, the method may further include:

[0361] Multiple first word lines are cleared using the word line control circuit; and

[0362] Multiple second word lines are cleared using a word line control circuit.

[0363] In some embodiments, controlling the level state of the remaining first word lines other than the target first word line based on the second calculation result may include:

[0364] The word line control circuit receives a second activation command. If the second operation result is the first result value, then at least two first word lines other than the target first word line are controlled to be in an active state. If the first operation result is the second result value, then all remaining first word lines other than the target first word line are controlled to be in an inactive state.

[0365] In some embodiments, controlling the level states of a plurality of second word lines based on the first calculation result may include:

[0366] The word line control circuit receives a third activation command. If the first calculation result is the first result value, then at least two second word lines are controlled to be in an active state; if the first calculation result is the second result value, then multiple second word lines are controlled to be in an inactive state.

[0367] In some embodiments, outputting a first target result by a sensitive amplifier based on the level states of a plurality of first medication doses and a plurality of second storage units may include:

[0368] After receiving a preset comparison instruction, the system reads the first voltage provided by multiple first memory cells and the second voltage provided by multiple second memory cells through a sensitive amplifier, and compares the second calculation result with the first calculation result based on the first voltage and the second voltage, and outputs the first target result.

[0369] Wherein, if the first voltage is higher than the second voltage, the first target result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the first target result output by the sensitive amplifier is the second result value.

[0370] Furthermore, for the second target result, in some embodiments, the fourth operational circuit may include a plurality of first word lines, a plurality of second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, a plurality of first memory cells, and a plurality of second memory cells;

[0371] The second processing step, which involves a fourth processing circuit performing a second processing on the first data and the second processing result to output a second target result, may include:

[0372] The level states of multiple first word lines are controlled according to the first data to obtain the level states of multiple first word lines;

[0373] After determining the target second word line, the level state of the target second word line is changed through the word line control circuit, and the level state of the remaining second word lines other than the target second word line is controlled according to the second calculation result to obtain the level state of multiple second word lines.

[0374] Based on the first data, determine the level state of the first line;

[0375] The level states of multiple first memory cells are determined based on the level states of multiple first word lines and the level state of the first bit line.

[0376] Based on the result of the second operation, determine the level state of the second bit line;

[0377] The level states of multiple second memory cells are determined based on the level states of multiple second word lines and second bit lines.

[0378] The second target result is output by a sensitive amplifier based on the level states of multiple first memory cells and multiple second memory cells.

[0379] In some embodiments, changing the level state of the target second word line via a word line control circuit may include:

[0380] The word line control circuit receives the first activation command and controls the target second word line to be in an activated state.

[0381] In some embodiments, before changing the level state of the target second word line via the word line control circuit, the method may further include:

[0382] Multiple first word lines are cleared using the word line control circuit; and

[0383] Multiple second word lines are cleared using a word line control circuit.

[0384] In some embodiments, controlling the level states of a plurality of first word lines based on first data may include:

[0385] The word line control circuit receives a second activation command. If the first data is the first value, it controls at least two first word lines to be in an active state; if the first data is the second value, it controls multiple first word lines to be in an inactive state.

[0386] In some embodiments, controlling the level state of the remaining second word lines other than the target second word line based on the second calculation result may include:

[0387] The word line control circuit receives a third activation command. If the second operation result is the first result value, then at least two second word lines other than the target second word line are controlled to be in an active state. If the second data is the second value, then the remaining second word lines other than the target second word line are controlled to be in an inactive state.

[0388] In some embodiments, outputting a second target result by means of a sensitive amplifier based on the level states of a plurality of first memory cells and a plurality of second memory cells may include:

[0389] After receiving a preset comparison command, the system reads the first voltage provided by multiple first memory cells and the second voltage provided by multiple second memory cells through a sensitive amplifier, and performs comparison operations on the first data and the second data based on the first voltage and the second voltage, and outputs the second target result.

[0390] Wherein, if the first voltage is higher than the second voltage, the second target result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the second target result output by the sensitive amplifier is the second result value.

[0391] It should be noted that for details not disclosed in this method embodiment, please refer to the description of the foregoing embodiment for understanding.

[0392] This disclosure provides an in-memory computation method. An initial computation circuit performs a first operation on first and second data, outputting a first operation result; then performs a second operation on the first and second data, outputting a second operation result; a target computation circuit performs a first operation on the second and first operation results, outputting a first target result; and finally performs a second operation on the first and second data, outputting a second target result. By performing two first operations and two second operations on the first and second data, the XOR and AND operation results of the first and second data can be obtained, achieving an operation effect equivalent to a half-adder, thus improving data processing speed.

[0393] In another embodiment of this disclosure, see [reference needed]. Figure 17 This illustrates a schematic diagram of the structural composition of a semiconductor memory 17 provided in an embodiment of this disclosure. For example... Figure 17 As shown, the semiconductor memory 18 includes at least the in-memory computing circuit 30 described in any of the foregoing embodiments.

[0394] In some embodiments, the semiconductor memory is a dynamic random access memory (DRAM) chip.

[0395] As for the semiconductor memory 18, since it includes the in-memory computing circuit 30 described in any of the foregoing embodiments, it can perform two first operations and two second operations on the first data and the second data through the in-memory computing circuit, and obtain the XOR operation result and the AND operation result of the first data and the second data, thus obtaining the operation effect equivalent to a half adder, thereby improving the data processing speed through the in-memory computing circuit.

[0396] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0397] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0398] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0399] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An in-memory computing circuit, characterized in that, include: An initial calculation circuit is used to perform a first operation on the first data and the second data, and output the first operation result; And perform a second operation on the first data and the second data, and output the second operation result; The target calculation circuit is used to perform a first calculation on the second calculation result and the first calculation result, and output a first target result; and to perform a second calculation on the first data and the second calculation result, and output a second target result; The initial calculation circuit includes a first arithmetic circuit and a second arithmetic circuit; wherein... The first arithmetic circuit is used to perform a first arithmetic processing on the first data and the second data, and output the first arithmetic result; The second arithmetic circuit is used to perform a second arithmetic processing on the first data and the second data, and output the second arithmetic result; The first operational circuit includes multiple first word lines, multiple second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, multiple first memory cells, and multiple second memory cells; wherein, The word line control circuit is used to change the level state of the target first word line after determining the target first word line, and to control the level state of the remaining first word lines other than the target first word line according to the first data, so as to obtain the level state of the plurality of first word lines. The first bit line is used to determine the level state of the first bit line based on the first data; The plurality of first storage cells are configured to determine the level state of the plurality of first storage cells based on the level state of the plurality of first word lines and the level state of the first bit lines; The word line control circuit is further configured to control the level state of the plurality of second word lines according to the second data, so as to obtain the level state of the plurality of second word lines; The second bit line is used to determine the level state of the second bit line based on the second data; The plurality of second storage cells are configured to determine the level state of the plurality of second storage cells based on the level state of the plurality of second word lines and the level state of the second bit lines; The sensitive amplifier is used to output the first calculation result based on the level states of the plurality of first storage cells and the level states of the plurality of second storage cells.

2. The in-memory computing circuit according to claim 1, characterized in that, The word line control circuit is used to control the target first word line to be in an active state after receiving a first activation command.

3. The in-memory computing circuit according to claim 2, characterized in that, The word line control circuit is further configured to, upon receiving a second activation instruction, control at least two first word lines other than the target first word line to be in an active state if the first data is a first value; and control the remaining first word lines other than the target first word line to be in an inactive state if the first data is a second value.

4. The in-memory computing circuit according to claim 2, characterized in that, The word line control circuit is further configured to, upon receiving a third activation instruction, control at least two second word lines to be in an active state if the second data is a first value, and control all of the plurality of second word lines to be in an inactive state if the second data is a second value.

5. The in-memory computing circuit according to claim 1, characterized in that, The sensitive amplifier is configured to, upon receiving a preset comparison command, read a first voltage provided by the plurality of first storage units and a second voltage provided by the plurality of second storage units, perform a comparison operation on the first data and the second data based on the first voltage and the second voltage, and output the first operation result; wherein, If the first voltage is higher than the second voltage, the first calculation result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the first calculation result output by the sensitive amplifier is the second result value.

6. The in-memory computing circuit according to claim 1, characterized in that, The second operational circuit includes multiple first word lines, multiple second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, multiple first memory cells, and multiple second memory cells; wherein, The word line control circuit is used to control the level state of the plurality of first word lines according to the first data, so as to obtain the level state of the plurality of first word lines; The first bit line is used to determine the level state of the first bit line based on the first data; The plurality of first storage cells are configured to determine the level state of the plurality of first storage cells based on the level state of the plurality of first word lines and the level state of the first bit lines; The word line control circuit is further configured to change the level state of the target second word line after determining the target second word line, and to control the level state of the remaining second word lines other than the target second word line according to the second data, so as to obtain the level state of the plurality of second word lines. The second bit line is used to determine the level state of the second bit line based on the second data; The plurality of second storage cells are configured to determine the level state of the plurality of second storage cells based on the level state of the plurality of second word lines and the level state of the second bit lines; The sensitive amplifier is used to output the second calculation result based on the level states of the plurality of first storage cells and the level states of the plurality of second storage cells.

7. The in-memory computing circuit according to claim 6, characterized in that, The word line control circuit is used to control the target second word line to be in an active state after receiving the first activation command.

8. The in-memory computing circuit according to claim 7, characterized in that, The word line control circuit is further configured to, upon receiving a second activation instruction, control at least two first word lines to be in an active state if the first data is a first value, and control all of the plurality of first word lines to be in an inactive state if the first data is a second value.

9. The in-memory computing circuit according to claim 7, characterized in that, The word line control circuit is further configured to, upon receiving a third activation instruction, control at least two second word lines other than the target second word line to be in an active state if the second data is a first value; and control the remaining second word lines other than the target second word line to be in an inactive state if the second data is a second value.

10. The in-memory computing circuit according to claim 6, characterized in that, The sensitive amplifier is configured to, upon receiving a preset comparison command, read the first voltage provided by the plurality of first storage units and the second voltage provided by the plurality of second storage units, perform a comparison operation on the first data and the second data based on the first voltage and the second voltage, and output the second operation result; wherein, If the first voltage is higher than the second voltage, the second calculation result output by the sensitive amplifier is the first result value; or, if the first voltage is lower than the second voltage, the second calculation result output by the sensitive amplifier is the second result value.

11. The in-memory computing circuit according to claim 1, characterized in that, The target computing circuit includes a third arithmetic circuit and a fourth arithmetic circuit; wherein... The third arithmetic circuit is used to perform a first arithmetic processing on the second arithmetic result and the first arithmetic result, and output the first target result; The fourth arithmetic circuit is used to perform a second arithmetic processing on the first data and the second arithmetic result, and output the second target result.

12. The in-memory computing circuit according to claim 11, characterized in that, The operation method of the third operation circuit is the same as that of the first operation circuit, and the operation method of the fourth operation circuit is the same as that of the second operation circuit.

13. The in-memory computing circuit according to any one of claims 1 to 12, characterized in that, The in-memory computing circuit must satisfy at least one of the following operations: half addition, full addition, and multiplication.

14. The in-memory computing circuit according to any one of claims 1 to 12, characterized in that, The first target result is used to indicate the result of the XOR operation between the first data and the second data, and the second target result is used to indicate the result of the AND operation between the first data and the second data.

15. An in-memory computation method, characterized in that, The method is applied to an in-memory computing circuit, which includes an initial computing circuit and a target computing circuit; the method includes: The initial calculation circuit performs a first operation on the first data and the second data, and outputs a first operation result; and performs a second operation on the first data and the second data, and outputs a second operation result. The target computing circuit performs a first operation on the second operation result and the first operation result to output a first target result; and performs a second operation on the first data and the second operation result to output a second target result. The initial calculation circuit includes a first arithmetic circuit and a second arithmetic circuit. The first arithmetic circuit includes multiple first word lines, multiple second word lines, a first bit line, a second bit line, a sensitive amplifier, a word line control circuit, multiple first memory cells, and multiple second memory cells. The word line control circuit is used to change the level state of the target first word line after determining the target first word line, and to control the level state of the remaining first word lines other than the target first word line according to the first data, so as to obtain the level state of the plurality of first word lines. The first bit line is used to determine the level state of the first bit line based on the first data; The plurality of first storage cells are configured to determine the level state of the plurality of first storage cells based on the level state of the plurality of first word lines and the level state of the first bit lines; The word line control circuit is further configured to control the level state of the plurality of second word lines according to the second data, so as to obtain the level state of the plurality of second word lines; The second bit line is used to determine the level state of the second bit line based on the second data; The plurality of second storage cells are configured to determine the level state of the plurality of second storage cells based on the level state of the plurality of second word lines and the level state of the second bit lines; The sensitive amplifier is used to output the first calculation result based on the level state of the plurality of first storage units and the level state of the plurality of second storage units. The target calculation circuit includes a third calculation circuit and a fourth calculation circuit. The first calculation circuit performs a first operation on the first data and the second data, and outputs a first operation result. And perform a second operation on the first data and the second data, and output the second operation result, including: The first arithmetic circuit performs a first arithmetic processing on the first data and the second data, and outputs the first arithmetic result. The second arithmetic circuit performs a second arithmetic processing on the first data and the second data, and outputs the second arithmetic result. The first operation, performed on the second calculation result and the first calculation result by the target calculation circuit, outputs a first target result; and the second operation, performed on the first data and the second calculation result, outputs a second target result, includes: The third arithmetic circuit performs a first arithmetic process on the second arithmetic result and the first arithmetic result, and outputs the first target result. The fourth arithmetic circuit performs a second arithmetic process on the first data and the second arithmetic result, and outputs the second target result.

16. The method according to claim 15, characterized in that, The operation method of the third operation circuit is the same as that of the first operation circuit, and the operation method of the fourth operation circuit is the same as that of the second operation circuit.

17. The method according to any one of claims 15 to 16, characterized in that, The first target result is used to indicate the result of the XOR operation between the first data and the second data, and the second target result is used to indicate the result of the AND operation between the first data and the second data.

18. A semiconductor memory, characterized in that, The semiconductor memory includes the in-memory computing circuitry as described in any one of claims 1 to 14.

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