Firmware repair for three-dimensional NAND memory

Abstract

The present disclosure relates to firmware repair for three-dimensional NAND memory. The present disclosure provides a content addressable memory (CAM) for repairing firmware for a multi-plane read operation in a flash memory device. The CAM includes a set of CAM registers configured to store a mapping table. The mapping table includes a plurality of old addresses each corresponding to a new address. The CAM further includes N comparators coupled to the set of CAM registers and configured to compare the old addresses to N input signals for performing a multi-plane read operation on N memory planes, where N is an integer greater than 1. The CAM further includes N multiplexers respectively coupled to the N comparators and to the set of CAM registers and configured to generate N output signals for the multi-plane read operation. At least one of the N output signals includes a new address from the mapping table and a comparison output by the comparators.

Description

[0001] This application is a divisional application. The original application was filed with the China Patent Office on July 8, 2021 (international filing date was June 4, 2021), application number 202180001816.4, entitled "Firmware Repair for Three-Dimensional NAND Memory". Technical Field

[0002] This disclosure generally relates to the field of semiconductor technology, and more particularly to the design and method of error correction in 3D NAND memory. Background Technology

[0003] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase memory density, scaling planar memory cells faces challenges attributed to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations in planar memory cells.

[0004] In 3D NAND flash memory, many layers of memory cells can be stacked vertically, allowing for a significant increase in storage density per unit area. Vertically stacked memory cells form memory strings, where channels of the memory cells are connected within each memory string. Each memory cell can be addressed via word lines and bit lines. Data (i.e., logical state) of memory cells across an entire memory page sharing the same word line can be read or programmed simultaneously. However, due to process variations, not every memory cell can be programmed to or held in a target state. Redundant memory cells or memory strings can be used to replace defective memory cells or memory strings. During a read operation, the firmware of 3D NAND can be repaired by replacing the address of a defective memory cell or memory string with the address of a redundant memory cell or memory string. Traditionally, content-addressable memory (CAM) can be used to store a mapping table where the old address of a defective memory cell or memory string corresponds to a new address of a redundant memory cell or memory string.

[0005] To improve efficiency, 3D NAND memories can perform multi-faceted read operations, in which memory pages on different memory faces can be read in parallel. While CAMs can be used to repair firmware during individual read operations, multiple CAMs are required to support multi-faceted read operations, increasing manufacturing costs. Therefore, a design and methodology is needed to repair firmware for 3D NAND memories to provide a low-cost yet efficient solution for multi-faceted read operations. Summary of the Invention

[0006] This disclosure describes embodiments of methods and circuits for firmware repair in three-dimensional (3D) memory devices.

[0007] One aspect of this disclosure provides a content-addressable memory (CAM) for repairing multi-faceted read operations in a flash memory device. The CAM includes a set of CAM registers configured as a memory mapping table. The mapping table includes multiple old addresses, each corresponding to a new address. The CAM also includes N comparators coupled to the set of CAM registers and configured to compare the old addresses with N input signals for performing multi-faceted read operations on N memory faces, where N is an integer greater than 1. The CAM also includes N multiplexers, each coupled to one of the N comparators and to the set of CAM registers, and configured to generate N output signals for the multi-faceted read operations. At least one of the N output signals includes a comparison based on the new address in the mapping table and the output of the comparators.

[0008] In some embodiments, each of the N comparators is further configured to: generate an output enable signal; and send the output enable signal to one of the N multiplexers.

[0009] In some embodiments, each of the N multiplexers is further configured to: receive an output enable signal sent by a comparator; and receive a new address stored in a mapping table.

[0010] In some embodiments, when the input address in the input signal matches one of a plurality of old addresses, the output enable signal indicates the matching status.

[0011] In some embodiments, when the input address in the input signal does not match any of the multiple old addresses, the output enable signal indicates NULL.

[0012] In some embodiments, the input address in the input signal identifies a memory cell, memory string, memory page, memory block, or memory plane in the flash memory device.

[0013] In some embodiments, multiple old addresses stored in a mapping table identify defective memory cells, defective memory strings, defective memory pages, or defective memory blocks in a flash memory device.

[0014] In some embodiments, the new address stored in the mapping table identifies redundant memory cells, redundant memory strings, redundant memory pages, redundant memory blocks, or redundant memory planes in the flash memory device.

[0015] In some embodiments, the input signal includes a first face index and a second face index different from the first face index, wherein the multi-face read operation simultaneously points to a first memory page in a first memory face with the first face index and a second memory page in a second memory face with the second face index.

[0016] In some embodiments, the flash memory includes a three-dimensional NAND flash memory.

[0017] In some embodiments, the three-dimensional NAND flash memory includes a plurality of memory strings that extend vertically through a stack of films with alternating conductive and dielectric layers, wherein each of the plurality of memory strings includes: a channel layer disposed on the sidewall of a core filling film; and a memory film disposed on the sidewall of the channel layer.

[0018] This disclosure also provides a flash memory device having M memory planes, where M is an integer greater than 1. The flash memory device further includes control circuitry coupled to the M memory planes via word line drivers and / or bit line drivers. The control circuitry includes M asynchronous multiple-plane (AMPI) read units with independent page addresses, each read unit configured to provide AMPI read control signals for a corresponding memory plane among the M memory planes to control AMPI read operations on the corresponding memory plane. The control circuitry also includes content-addressable memory (CAM) including a set of CAM registers shared by the M AMPI read units for firmware repair of AMPI read operations.

[0019] In some embodiments, the M AMPI readout units are microcontroller units (MCUs).

[0020] In some embodiments, each of the M memory planes includes a plurality of memory strings extending vertically through a film stack of alternating conductive and dielectric layers. Each memory string includes: a channel layer disposed on the sidewall of a core filling film; and a memory film disposed on the sidewall of the channel layer.

[0021] In some embodiments, the CAM further includes M comparators. Each comparator is coupled to a set of CAM registers and is configured to compare multiple old addresses stored in the set of CAM registers with AMPI read control signals for the corresponding memory planes.

[0022] In some embodiments, multiple old addresses identify defective memory cells, defective memory strings, defective memory pages, or defective memory blocks in a flash memory device.

[0023] In some embodiments, the CAM further includes M multiplexers, each multiplexer coupled to a corresponding comparator and a set of CAM registers. Each multiplexer is configured to generate an output signal for performing an AMPI read operation on the corresponding memory plane.

[0024] In some embodiments, the output signal includes a new address provided by a set of CAM registers, the new address identifying a redundant memory cell, redundant memory string, redundant memory page, or redundant memory block in the flash memory device.

[0025] In some embodiments, each comparator is further configured to: generate an output enable signal indicating a matching state when the input address in the AMPI read control signal matches one of a plurality of old addresses; and send the output enable signal to a corresponding multiplexer to generate an output signal for performing an AMPI read operation on the corresponding memory surface.

[0026] This disclosure also provides a memory storage system having a flash memory device. The flash memory device includes M memory planes, where M is an integer greater than 1. The flash memory device also includes control circuitry coupled to the M memory planes via word line drivers and / or bit line drivers. The control circuitry includes M asynchronous multiple access (AMPI) read units with independent page addresses, each read unit configured to provide AMPI read control signals for a corresponding memory plane among the M memory planes to control AMPI read operations on the corresponding memory plane. The control circuitry also includes content-addressable memory (CAM) having a set of CAM registers shared by the M AMPI read units for firmware repair of AMPI read operations.

[0027] This disclosure also provides a method for repairing firmware for multi-faceted read operations in a flash memory device. The method includes the steps of: receiving N input signals at a content-addressable memory (CAM) to perform multi-faceted read operations on N memory faces, where N is an integer greater than 1; comparing the N input signals with a first old address stored in a set of CAM registers by N comparators in the CAM; generating N output enable signals by the N comparators in the CAM to indicate whether a corresponding input signal includes an input address matching the first old address; and generating N output signals based on the N output enable signals by N multiplexers in the CAM, wherein at least one of the N output signals points to a new address stored in a set of CAM registers, where the new address corresponds to the first old address.

[0028] In some embodiments, the method further includes determining, by a corresponding comparator, whether the input address of the corresponding input signal matches the first old address.

[0029] In some embodiments, the method further includes generating a corresponding output enable signal indicating a matching state when the input address matches a first old address.

[0030] In some embodiments, generating N output signals includes generating a corresponding output signal with a new address when the corresponding output enable signal indicates a matching state.

[0031] In some embodiments, the method further includes: when the input address does not match the first old address, comparing the input address of the corresponding input signal with a second old address stored in a set of CAM registers by a corresponding comparator, wherein the second old address is different from the first old address.

[0032] In some embodiments, the method further includes generating a corresponding output enable signal to indicate NULL when the input address does not match any old address stored in a set of CAM registers.

[0033] In some embodiments, generating N output signals includes generating a corresponding output signal with an unchanged input address when the corresponding output enable signal indicates NULL.

[0034] In some embodiments, the method further includes receiving an input enable signal to activate the CAM.

[0035] In some embodiments, the method further includes storing a first old address in a set of CAM registers to identify a defective memory cell, defective memory page, or defective memory block in the flash memory device.

[0036] In some embodiments, the method further includes storing a new address in a set of CAM registers to identify redundant memory cells, redundant memory pages, or redundant memory blocks in the flash memory device.

[0037] In some embodiments, the method further includes repairing firmware for multi-faceted read operations in a three-dimensional NAND flash memory. The three-dimensional NAND flash memory includes a plurality of memory strings extending vertically through a stack of alternating conductive and dielectric layers. Each of the memory strings includes: a channel layer disposed on the sidewalls of a core filler film; and a memory film disposed on the sidewalls of the channel layer.

[0038] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims and drawings. Attached Figure Description

[0039] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0040] Figure 1 and Figures 2A-2B A storage system having one or more memory chips is shown according to some embodiments of the present disclosure.

[0041] Figure 3 A schematic diagram of a memory die according to some embodiments of the present disclosure is shown.

[0042] Figure 4 A schematic diagram of a three-dimensional (3D) memory die according to some embodiments of the present disclosure is shown.

[0043] Figure 5 A perspective view of a portion of a 3D memory structure according to some embodiments of the present disclosure is shown.

[0044] Figure 6 Timing diagrams of multifaceted read operations according to some embodiments of the present disclosure are shown.

[0045] Figure 7 Schemes for read operations having asynchronous multifaceted interfaces (AMPI) with independent page addresses are illustrated according to some embodiments of the present disclosure.

[0046] Figure 8A A schematic diagram of a control circuit for a 3D NAND memory according to some embodiments of the present disclosure is shown.

[0047] Figure 8B A schematic diagram of an AMPI readout unit according to some embodiments of the present disclosure is shown.

[0048] Figure 9 and Figure 10 Content-addressable memory for multi-faceted read operations is illustrated according to some embodiments of the present disclosure.

[0049] Figure 11 A method for firmware repair in a 3D NAND memory according to some embodiments of the present disclosure is shown.

[0050] The features and advantages of the invention will become more apparent from the specific embodiments set forth below when taken in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral(s) of the corresponding reference numeral.

[0051] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0052] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used for a variety of other applications.

[0053] Note that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in this specification indicate that the described embodiments include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge scope of those skilled in the art.

[0054] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0055] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes “on something” with an intermediate feature or layer therebetween. Furthermore, “above” or “on top of” not only means “above” or “on top of” something, but can also include “above” or “on top of” something without an intermediate feature or layer therebetween (i.e., directly on something).

[0056] Furthermore, spatial relative terms, such as “below,” “under,” “lower,” “above,” and “upper,” are used herein for ease of description to describe the relationship between one element or feature and another element(s) or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in device use or process steps other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0057] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore semiconductor devices are formed on the top side of the substrate, unless otherwise stated. The bottom surface is opposite to the top surface, and therefore the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0058] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively distant from the substrate. A layer may extend over the entire upper or lower layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnects, and / or vertical interconnect pathways (VIAs) are formed) and one or more dielectric layers.

[0059] In this disclosure, for ease of description, the term "level" is used to refer to elements having substantially the same height along the vertical direction. For example, a word line and an underlying gate dielectric layer may be referred to as a "level", a word line and an underlying insulating layer together may be referred to as a "level", word lines having substantially the same height may be referred to as a "word line level" or similar, and so on.

[0060] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may arise due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can indicate a value of a given quantity that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0061] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the terms "vertical" or "perpendicularly" mean nominally perpendicular to the lateral surface of the substrate.

[0062] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate.

[0063] Figure 1 A block diagram of an exemplary system S1 having a storage system 10 according to some embodiments of the present disclosure is shown. System S1 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other electronic device having storage. Storage system 10 (also referred to as a NAND storage system) may include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory chip 25 (hereinafter simply referred to as a "memory chip") may be a NAND chip (i.e., "flash memory", "NAND flash", or "NAND"). Storage system 10 may communicate with host computer 15 via memory controller 20, wherein memory controller 20 may be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory chip 25 may be managed by the memory controller 20 via the memory channel 30.

[0064] In some embodiments, host computer 15 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host computer 15 sends data to be stored in NAND storage system or storage system 10, or retrieves data by reading storage system 10.

[0065] The memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory chip 25. To perform these tasks, the controller runs firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller units) within the controller 20. For example, the controller 20 runs firmware 21 to map logical addresses (i.e., addresses used by the host associated with host data) to physical addresses (i.e., the actual location of data storage) in the memory chip 25. The controller 20 also runs firmware 21 to manage defective memory blocks in the memory chip 25, where firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. The controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) for storing various metadata used by the firmware 21.

[0066] The memory channel 30 can provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 can select one of the memory chips 25 based on a chip enable signal.

[0067] In some embodiments, Figure 1 Each memory chip 25 may include one or more memory dies 100, wherein each memory die may be a 3D NAND memory.

[0068] The memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 10 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 20 and a single memory chip 25 can be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a connector for connecting the memory card 26 to a host computer (e.g., ...). Figure 1 The host computer 15) is coupled to the memory card connector 24. In such a way... Figure 2B In another example shown, the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a connection between the SSD 27 and a host (e.g., Figure 1 The host computer 15) is coupled to the SSD connector 28.

[0069] Figure 3 A top view of an exemplary memory die 100 according to some embodiments of the present disclosure is shown. The memory die 100 may include one or more memory surfaces 101, and each of the memory surfaces 101 may include a plurality of memory blocks 103. The same and concurrent operations may occur at each memory surface 101. The size may be megabytes (MB). The memory block 103 is the minimum size for performing an erase operation. Figure 3 As shown, the exemplary memory die 100 includes four memory surfaces 101, and each memory surface 101 includes six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell can be addressed via interconnects (e.g., bit lines and word lines). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. Figure 3 In this disclosure, the directions of the bit lines and word lines are marked as "BL" and "WL". The memory block 103 is also referred to as a "memory array" or "array". A memory array is the core region of a memory device that performs storage functions.

[0070] The memory die 100 also includes a peripheral region 105, which is the region surrounding the memory surface 101. The peripheral region 105 contains a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row decoders, column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0071] It should be noted that Figure 3 The arrangement of memory facets 101 in the memory die 100 and the arrangement of memory blocks 103 in each memory facet 101 shown are for illustrative purposes only and do not limit the scope of this disclosure.

[0072] Figure 4A schematic diagram of a memory die 100 according to some embodiments of the present disclosure is shown. The memory die 100 includes one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 includes a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. Memory cells 340 sharing the same word line form memory pages 432. Each memory string 212 also includes at least one field-effect transistor (e.g., MOSFET) at each end, the at least one field-effect transistor being controlled by a lower select gate (LSG) 332 and a top select gate (TSG) 334, respectively. The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the lower select transistor 332-T may be connected to an array common source (ACS) 430. The ACS 430 may be shared by the memory strings 212 throughout the memory block and is also referred to as the common source line.

[0073] The memory die 100 also includes peripheral circuitry, comprising a variety of digital, analog, and / or mixed-signal circuits to support the functionality of the memory block 103, such as a page buffer / sensor amplifier 50, a row decoder / word line driver 40, a column decoder / bit line driver 52, control circuitry 70, a voltage generator 65, and an input / output buffer 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0074] Memory block 103 can be coupled to row decoder / word line driver 40 via word line (WL) 333, lower select gate (LSG) 332, and top select gate (TSG) 334. Memory block 103 can be coupled to page buffer / sensor amplifier 50 via bit line (BL) 341. Row decoder / word line driver 40 can select one of the memory blocks 103 on memory die 100 in response to an X-path control signal provided by control circuitry 70. Row decoder / word line driver 40 can deliver voltage from voltage generator 65 to word line according to X-path control signal. During read and program operations, row decoder / word line driver 40 can deliver read voltage V according to X-path control signal received from control circuitry 70. read and programming voltage V pgm It is passed to the selected word line and will be transmitted through voltage V. pass Pass to unselected word lines.

[0075] The column decoder / bit line driver 52 can disable the voltage V based on the Y-path control signal received from the control circuit 70. inhibitThe selected positioning line is then passed to the unselected positioning line and connected to ground. In other words, the column decoder / bit line driver 52 can be configured to select or deselect one or more memory strings 212 according to the Y-path control signal from the control circuitry 70. The page buffer / sensor amplifier 50 can be configured to read data from the memory block 103 and program (write) data to the memory block 103 according to the Y-path control signal from the control circuitry 70. For example, the page buffer / sensor amplifier 50 can store a page of data to be programmed into a memory page 432. In another example, the page buffer / sensor amplifier 50 can perform a verification operation to ensure that data has been correctly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sensor amplifier 50 can sense the current flowing through the bit line 341 reflecting the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification.

[0076] The input / output buffer 55 can pass I / O data from or to the page buffer / sensor amplifier 50, and pass address ADDR or command CMD to the control circuitry 70. In some embodiments, the input / output buffer 55 can be used in the memory controller 20 ( Figure 1 The interface between the memory chip 25 and the memory die 100 on the memory chip 25.

[0077] Control circuitry 70 can control page buffer / sensor amplifier 50 and row decoder / word line driver 40 in response to command CMD passed from input / output buffer 55. During programming operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to program selected memory cells. During read operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to read selected memory cells. X-path control signals and Y-path control signals include row address X-ADDR and column address Y-ADDR, which can be used to locate selected memory cells in memory block 103. Row address X-ADDR may include page index PD, block index BD, and face index PL to identify memory page 432, memory block 103, and memory face 101, respectively. Figure 3 (In the context of memory). The column address Y-ADDR can identify a byte or word in the data of memory page 432.

[0078] Voltage generator 65, under the control of control circuit 70, generates the voltage to be supplied to the word lines and bit lines. The voltage generated by voltage generator 65 includes the read voltage V. read Programming voltage V pgm Through voltage V passProhibited voltage V inhibit wait.

[0079] It should be noted that Figure 1 , Figures 2A-2B as well as Figures 3-4 The arrangement of electronic components in the storage system 10 and memory die 100 is shown as an example. The storage system 10 and memory die 100 may have other arrangements and may include additional components. For example, the memory die 100 may also have a sense amplifier, a row decoder, and a column decoder, etc. Figure 4 Components on the memory die 100 shown (e.g., control circuitry 70, I / O buffer 55) can also be moved outside the memory die 100 as independent electrical components in the storage system 10. Figure 4 Components on the memory die 100 shown (e.g., control circuitry 70, I / O buffer 55) can also be moved to other components in the memory system 10. For example, a portion of the control circuitry 70 can be combined with the memory controller 20, or vice versa.

[0080] Figure 5 A perspective view of a 3D memory structure 500 according to some embodiments of the present disclosure is shown. In this example, the memory die 100 may be a 3D NAND memory. The 3D memory structure 500 may be, for example... Figure 3 This refers to a portion of the memory die 100 in region 108. The 3D memory structure 500 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include a plurality of memory strings 212, each memory string 212 including a plurality of stacked memory cells 340. The stepped region 210 may include a stepped structure.

[0081] The 3D memory structure 500 includes a substrate 330, an insulating film 331 on the substrate 330, a lower select gate (LSG) 332 on the insulating film 331, and multiple layers (also referred to as "word lines (WLs)") of a control gate 333 stacked on top of the LSG 332 to form alternating conductive and dielectric layers. For clarity, in Figure 5 The dielectric layer adjacent to the layer of the control gate is not shown.

[0082] Each layer's control gate is separated by slot structures 216-1 and 216-2 through the film stack 335. The 3D memory structure 500 also includes a layer of top select gate (TSG) 334 above the stack of control gate 333. The stack of TSG 334, control gate 333, and LSG 332 is also referred to as the "gate electrode". The 3D memory structure 500 also includes a doped source electrode region 344 in a portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 of the 3D memory structure 500 includes a channel via 336 extending through an insulating film 331 and a film stack 335 of alternating conductive and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core fill film 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed at the intersection of control gates 333 (e.g., 333-1, 333-2, 333-3) and memory strings 212. A portion of the channel layer 338 responsive to the respective control gate is also referred to as the channel 338 of the memory cell. The 3D memory structure 500 also includes multiple bit lines (BLs) 341 connected to the memory strings 212 over the TSG 334. The 3D memory structure 500 also includes multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connections to each level of the gate electrode.

[0083] exist Figure 5 For illustrative purposes, the three levels of control gates 333-1, 333-2, and 333-3 are shown together with one level of TSG 334 and one level of LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3 corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may exceed three to increase storage capacity. The 3D memory structure 500 may also include other structures, such as TSG notches, common source contacts (i.e., arrayed common sources), and dummy memory strings. For simplicity, in Figure 5 These structures are not shown in the text.

[0084] Return to reference Figure 4 In some embodiments, memory block 103 may be formed based on floating gate technology. In some embodiments, memory block 103 may be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. It stores data or logical states (“states”, for example, the threshold voltage V of memory cell 340).th It depends on the number of charge carriers trapped in the memory film 337 of the memory cell 340.

[0085] In a NAND flash memory, read and write operations (also known as programming operations) can be performed on memory page 432, and erase operations can be performed on memory block 103.

[0086] In the NAND memory, memory cell 340 can be in an erase state ER or a programmable state P1. Initially, by applying a negative voltage difference between the control gate 333 and the channel 338, the memory cell 340 in the memory block 103 can be reset to the erase state ER, which is logic "1", so that the trapped charge carriers in the storage layer of the memory cell 340 can be removed. For example, by setting the control gate 333 of the memory cell 340 to ground and applying a high positive voltage (erasure voltage V) erase Applying a voltage difference to the ACS 430 can induce a negative voltage difference. In the erase state ER (“state ER”), the threshold voltage V of memory cell 340 can be... th Reset to the lowest value.

[0087] During programming (i.e., writing), a programming voltage V is applied, for example, to the control gate 333. pgm (For example, a positive voltage pulse between 10V and 20V) and grounding the corresponding bit line 341 can establish a positive voltage difference between the control gate 333 and the channel 338. As a result, charge carriers (e.g., electrons) can be injected into the storage layer of the memory cell 340, thereby increasing the threshold voltage V of the memory cell 340. th Therefore, memory cell 340 can be programmed to programming state P1 (“state P1”).

[0088] By measuring or sensing the threshold voltage V of the memory cell th This allows the determination of the state of a memory cell (e.g., state ER or state P1). During a read operation, the read voltage V can be... read It is applied to the control gate 333 of the memory cell, and the current flowing through the memory cell can be measured at bit line 341. The voltage V can be applied... pass Apply to an unselected word line to activate an unselected memory cell.

[0089] NAND flash memory can be configured to operate in Single-Level Cell (SLC) mode. To increase storage capacity, NAND flash memory can also be configured to operate in Multi-Level Cell (MLC), Three-Level Cell (TLC), Quadruple-Level Cell (QLC) mode, or a combination of these modes. In SLC mode, a memory cell stores 1 bit and has two logical states (“states”), namely, state ER and P1. In MLC mode, a memory cell stores 2 bits and has four states, namely, states ER, P1, P2, and P3. In TLC mode, a memory cell stores 3 bits and has eight states, namely, state ER and states P1–P7. In QLC mode, a memory cell stores 4 bits and has 16 states.

[0090] Although a memory block is the smallest erasable unit in 3D NAND memory, a memory page is the smallest addressable unit used for read and program operations. During a read operation, data from a memory page in a selected memory block can be read based on the page index PD and block index BD included in the address ADDR received by control circuitry 70. To increase read throughput, multi-faceted read operations can be implemented by simultaneously reading memory pages in multiple memory faces. Traditionally, multi-faceted read operations cannot be performed on memory pages with different page addresses (e.g., different word lines at different levels, different page indices PD, etc.). However, in 3D NAND memory, multi-faceted read operations can be performed on memory pages with different page addresses. Multi-faceted read operations can be synchronous or asynchronous. While read operations on different memory faces can begin simultaneously during a synchronous multi-faceted read operation, asynchronous multi-faceted read operations begin at different times.

[0091] Figure 6 A timing diagram of a multi-faceted read operation 600 according to some embodiments of the present disclosure is shown. In this example, the multi-faceted read operation 600 can be executed synchronously in a 3D NAND memory, wherein a multi-faceted read operation MPR0 (for a memory face having face index PL0) and a multi-faceted read operation MPR1 (for a memory face having face index PL1 different from face index PL0) start simultaneously. The multi-faceted read operation MPR0 manages the command CMD0, address ADDR0, and data DOUT0, wherein address ADDR0 includes face index PL0, block index BD0, and page index PD0. The multi-faceted read operation MPR1 manages the command CMD1, address ADDR1, and data DOUT1, wherein address ADDR1 includes face index PL1, block index BD1, and page index PD1.

[0092] The multi-page read operation 600 may include a read step and a transfer step, wherein the read steps of multi-page read operations MPR0 and MPR1 can be executed in parallel. During the transfer step, data from memory pages PD0 and PD1 can be sent to the page buffer / sensor amplifier 50 and further sent to the I / O buffer 55.

[0093] In some embodiments, the read and pass steps can also be performed in parallel to reduce the latency of multi-sided read operations. In this example, an additional cache can be used during parallel operations to temporarily store data DOUT0 / DOUT1, commands CMD0 / CMD1, or addresses ADDR0 / ADDR1. In some embodiments, multi-sided read operations can be implemented to pass data requested by the system, rather than entire memory pages, thereby further reducing the latency of multi-sided read operations.

[0094] Figure 7 A scheme 700 for asynchronous multifaceted (AMPI) read operations with independent page addresses, according to some embodiments of the present disclosure, is illustrated. In this example, the command CMD (such as...) received at control circuitry 70... Figure 4 The diagram shows control signals cache_rbn_en, true_rbn_en, cache_rbn_0, cache_rbn_1, cache_rbn_2, and cache_rbn_3 to facilitate AMPI read operations. After the enable signals cache_rbn_en and true_rbn_en are triggered to initiate the AMPI read operation, the enable signals cache_rbn_0, cache_rbn_1, cache_rbn_2, and cache_rbn_3 for the memory planes with plane indices PL0, PL1, PL2, and PL3 can be sequentially set to enable levels at times t0, t2, t1, and t3. In some embodiments, the enable level can be a falling edge used to trigger the read operation. As a result, each memory plane can initiate a read operation independently.

[0095] Structurally, the top select gates 334 of different memory planes can be electrically separated, for example, through a TSG cutout or a separate step structure, to allow independent operation of the memory planes. Random access to memory pages can be achieved by implementing AMPI read operations. Thus, random read operations can be performed in 3D NAND memory.

[0096] Due to process variations, not every memory cell can be programmed to or maintained in the target state. Defective memory cells, defective memory strings, defective memory pages, or defective memory blocks can be replaced by redundant memory cells, redundant memory strings, redundant memory pages, or redundant memory blocks. In some embodiments, random access memory (RAM) (e.g., dynamic random access memory (DRAM) or static random access memory (SRAM)) can be used to store a mapping table that stores the old addresses ADDR_ of defective memory cells, defective memory strings, defective memory pages, or defective memory blocks. old ADDR_ is a new address mapped to a redundant memory cell, redundant memory string, redundant memory page, or redundant memory block. new However, the hardware and firmware design for RAM is complex and typically occupies a large area. In one example, content-addressable memory (CAM) can be used to store a mapping table. CAM includes a set of registers (also known as "a set of CAM registers"). For example, if a word line or bit line in memory block 103 is found to be faulty, its address can be programmed into the CAM. Thereafter, whenever a "faulty" word line or bit line is addressed, the CAM can provide the address in place of the word line or bit line.

[0097] Figure 8A An exemplary control circuit 70 according to some embodiments of the present disclosure is shown. In this example, the control circuit 70 includes a plurality of AMPI read units 846 (e.g., 846_0, 846_1, 846_2, etc.). Each AMPI read unit 846 includes a CAM 850 (e.g., 850_0, 850_1, 850_2, etc.) and a microcontroller unit (MCU) 848 (848_0, 848_1, 848_2, etc.). Each AMPI read unit 846 is responsible for controlling AMPI read operations (e.g., MPR0, MPR1, MPR2) on a corresponding memory surface (e.g., with surface indices PL0, PL1, PL2). That is, if there are N memory surfaces (N≥2), the control circuit 70 can implement N AMPI read units 846. Therefore, the control circuit 70 can have N MCUs and N CAMs.

[0098] In some embodiments, each MCU 848 may include one or more processing cores (e.g., arithmetic logic units), control logic, addressing logic, and instruction logic capable of executing firmware and / or software code. Each MCU 848 may also include one or more memories (e.g., DRAM, SRAM, flash memory, registers, etc.). It should be understood that the MCU 848 may include any suitable type of processor.

[0099] In some embodiments, while the AMPI read unit 846 (e.g., 846_0) is performing an AMPI read operation (e.g., MPR0) for the memory plane (e.g., PL0), the MCU 848 (e.g., 848_0) may execute firmware and / or software code and communicate with the CAM 850 (e.g., 850_0) to repair the firmware and / or software code if necessary.

[0100] Figure 8B Another embodiment of an AMPI read unit 846, designed to perform multifaceted read operations in a 3D NAND memory, is shown according to some embodiments of the present disclosure. In this example, multiple AMPI read units 846 share the same CAM 850. For example, the MCU 848-0 of AMPI read unit 846-0 may be coupled to the CAM 850 to perform a multifaceted read operation (e.g., an AMPI read operation) MPR0 for memory plane PL0. Similarly, the MCU 848-1 of AMPI read unit 846-1 (not shown) is also coupled to the CAM 850 to perform a multifaceted read operation (e.g., an AMPI read operation) MPR1 for memory plane PL1. And the MCU 848-2 of AMPI read unit 846-2 (not shown) is also coupled to the CAM 850 to perform a multifaceted read operation (e.g., an AMPI read operation) MPR2 for memory plane PL2.

[0101] In 3D NAND flash memory, storage density has increased significantly. However, due to structural and design complexities, various process variations can lead to defective memory cells, strings, pages, or blocks. The CAM850 can be used to store the addresses of defective memory cells / strings / pages / blocks, and also to store the addresses of corresponding redundant memory cells / strings / pages / blocks as replacements. However, with the increase in error bits, the CAM850 can have a large size and occupy a large area. Therefore, sharing the same CAM with the AMPI read unit 846 can significantly save area and reduce costs.

[0102] like Figure 8BAs shown, CAM 850 includes a set of CAM registers 852 that store a mapping table with a first set of old addresses and a second set of new addresses. Each old address corresponds to a new address. CAM 850 can retrieve a new address ADDR_new based on the old address ADDR_old according to the mapping table stored in CAM 850. When CAM 850 is activated by one of the MCUs 848, the mapping table is searched based on an input signal (AMPI read control signal). If the input signal matches an old address in old address ADDR_old, the corresponding address (e.g., the new address ADDR_new) can be returned. If the input signal does not match any old address in old address ADDR_old, CAM 850 returns logical NULL.

[0103] For example, during multi-face read operations MPR0, MPR1, and MPR2, the corresponding MCU can compare the input address in the input signal with the old address pointed to by the first set of programming counters old_pc_0, old_pc_1, and old_pc_2. In some embodiments, the input address in the input signal includes the address of a previously known memory cell / string / page / block / face to be read. When the CAM 850 receives the input signal from the associated MCU, it searches the mapping table and compares the input address with the old address pointed to by the programming counters old_pc_0, old_pc_1, and old_pc_2. In some embodiments, the first set of programming counters old_pc_0, old_pc_1, and old_pc_2 can temporarily store the old address.

[0104] If a matching old address ADDR_old is found in the mapping table, it indicates that the memory cell / string / page / block located at the previously known address is defective and should be replaced by a redundant memory cell / string / page / block located at the new address ADDR_new. In some embodiments, the second set of programming counters new_pc_0, new_pc_1, and new_pc_2 can be used to point to the new address ADDR_new. In some embodiments, the second set of programming counters new_pc_0, new_pc_1, and new_pc_2 can temporarily store the new address ADDR_new.

[0105] By updating the programming counter, the firmware associated with multi-sided read operations MPR0, MPR1, and MPR2 can be updated accordingly. Then, the MCU 848 in each AMPI read unit 846 can execute the updated firmware for the corresponding multi-sided read operation. This repairs the firmware of the 3D NAND memory used for multi-sided read operations to avoid defective memory cells / strings / pages / blocks. When the AMPI read unit 846 performs a multi-sided read operation, the repaired firmware can point to redundant memory cells / strings / pages / blocks located at the new address ADDR_new.

[0106] In this example, each MCU 848 may include firmware and software. In some embodiments, each MCU 848 may also extract and execute firmware and software installed in another memory element associated with the respective MCU 848.

[0107] As described above, Figure 8B The AMPI read unit 846 in the memory shares a CAM 850. For example, to perform AMPI read operations for a number of M memory planes (M≥2), a number of M AMPI read units can be implemented, where each AMPI read unit includes an MCU. However, the number of M AMPI read units can share a single CAM. As a result, the area of ​​the control circuitry 70 can be scaled down to a smaller size. Furthermore, because fixed firmware can be used to repair faulty bits (defective memory cells / strings / pages / blocks) during multiple read operations, the performance of the 3D NAND memory can be made more efficient.

[0108] In some embodiments, the control circuit 70 may further include a main MCU ( Figures 8A-8B (Not shown in the image). The main MCU can control the operation of the AMPI read unit 846 and facilitate read or programming operations in addition to AMPI read operations.

[0109] Figure 9 A schematic diagram of a 3D NAND memory 900 according to some embodiments of the present disclosure is shown. (Compared with previous descriptions...) Figure 1 , Figure 3 and Figure 4 Similar to the memory die 100 discussed, the 3D NAND memory 900 also includes one or more memory blocks 103, page buffers / sensor amplifiers 50, row decoders / word line drivers 40, column decoders / bit line drivers 52, voltage generators 65, and control circuitry 70.

[0110] In this example, with about Figure 8BSimilar to the described AMPI read unit 846, the control circuitry 70 includes multiple MCUs 848 sharing the CAM 850. The firmware executed by the MCUs 848 may include a first set of programming counters, old_pc_0, old_pc_1, and old_pc_2, which can be used to contain addresses of previously known memory cells / strings / pages / blocks for which multifaceted read operations are to be performed. When a mapping table stored in the CAM 850 is searched by a specific MCU 848 (e.g., MCU0), and if it is determined that an address stored in the first programming counter (e.g., old_pc_0) matches an old address stored in the CAM 850, the CAM 850 can return a corresponding new address, which can be pointed to by a second set of programming counters (new_pc_0, new_pc_1, and new_pc_2) or can be stored in the second set of programming counters. When the corresponding MCU 848 (e.g., MCU0) executes the associated firmware for a multifaceted read operation (e.g., AMPI read operation MPR0), the addresses in the firmware can be updated and corrected accordingly. As a result, based on the CAM 850 mapping table, defective memory cells / strings / pages / blocks at old addresses can be replaced by redundant memory cells / strings / pages / blocks at new addresses.

[0111] In some embodiments, the second set of programming counters, new_pc0, new_pc1, and new_pc2, can then be used in subsequent firmware and hardware for multifaceted read operations to, for example, generate X-path control signals and Y-path control signals for the row decoder / WL driver 40, column decoder / BL driver 52, and page buffer / sensor amplifier 50, respectively. Thus, the CAM850 can be used to facilitate multifaceted read operations with repaired (or new) addresses. It should be noted that the old and new addresses stored in the first and second sets of programming counters may include a page index PD, a block index BD, and a face index PL, wherein the face index PL may differ for read operations on different memory faces.

[0112] Figure 10 Another embodiment of a CAM 850 for multifaceted read operations (e.g., AMPI read operations) of 3D NAND memory is shown. In this example, the CAM 850 includes multiple CAM registers 852, multiple comparators 854 (e.g., 854-1, 854-2, 854-3), and multiple multiplexers (MUX) 856 (e.g., 856-1, 856-2, 856-3). Here, the multiple CAM registers 852 can be used to store and... Figure 8BThe mapping table shown is similar to the one described above. In this example, the input signals (e.g., AMPI read control signals) MPR0_in, MPR1_in, and MPR2_in received by CAM 850 can be generated by MCU 848 to perform multi-faceted read operations MPR0, MPR1, and MPR2 for memory faces with face indices PL0, PL1, and PL2. Additionally, the input enable signal PC_remap_en can be generated by the main MCU 858 within control circuitry 70, where PC_remap_en can be used to activate CAM 850. In some embodiments, the multi-faceted read operation can be the AMPI read operation described previously, and MCU 848 can be configured with respect to... Figures 8A-8B and Figure 9 The MCU 848 of the AMPI read unit in the described control circuit 70 is similar. As described above, each AMPI read unit includes an MCU 848 associated with a CAM 850, wherein the CAM 850 is shared by the MCU 848 of the other AMPI read units.

[0113] like Figure 10 As shown, each of the input signals MPR0_in, MPR1_in, and MPR2_in can be compared with a first programming counter old_pc at one of the comparators 854. Here, the first programming counter old_pc can be used to store an old address (e.g., old_pc_0) in a mapping table of multiple CAM registers 852. If the input signals MPR0_in, MPR1_in, or MPR2_in have a content that matches the old address (e.g., old_pc_0), output enable signals MPR0_out_en, MPR1_out_en, or MPR2_out_en can be generated to indicate a matching state (e.g., "TRUE" or "1"), and the output enable signals are sent to MUX 856-1, 856-2, and 856-3, respectively.

[0114] If the input signals MPR0_in, MPR1_in, or MPR2_in do not match an old address (e.g., old_pc_0), the first programming counter old_pc can point to the next old address in the mapping table, such as old_pc_1, and the next old address is compared again with the input signals MPR0_in, MPR1_in, or MPR2_in at the corresponding comparators 854-1, 854-2, and 854-3. This comparison process can be repeated until all old addresses in the mapping table have been compared with the input signals MPR0_in, MPR1_in, or MPR2_in. If the input signals MPR0_in, MPR1_in, or MPR2_in do not match any old address in the mapping table, the output enable signals MPR0_out_en, MPR1_out_en, or MPR2_out_en can be set to "NULL" or "0".

[0115] The output enable signals MPR0_out_en, MPR1_out_en, or MPR2_out_en can be multiplexed with a second programming counter new_pc that contains the new address ADDR_new in the mapping table. In one example, the second programming counter new_pc corresponds to the first programming counter old_pc. For example, when the first programming counter points to old_pc_0, the second programming counter points to new_pc_0. When the first programming counter points to old_pc_1, the second programming counter points to new_pc_1, and so on. When the first programming counter points to old_pc_n, the second programming counter points to new_pc_n. If the output enable signals MPR0_out_en, MPR1_out_en, or MPR2_out_en indicate a match state (e.g., "TRUE" or "1"), the MUX 856-1, 856-2, or 856-3 can generate output signals MPR0_out, MPR1_out, or MPR2_out that contain the new address pointed to by the second programming counter new_pc. In this way, the input signals MPR0_in, MPR1_in, and MPR2_in with the old addresses can be updated to output signals MPR0_out, MPR1_out, and MPR2_out with the new addresses. This fixes the firmware used for multi-faceted read operations.

[0116] If the output enable signals MPR0_out_en, MPR1_out_en, and MPR2_out_en indicate that no match for all old addresses was found in the mapping table, then the output signals MPR0_out, MPR1_out, and MPR2_out can be set to remain unchanged from the input signals MPR0_in, MPR1_in, and MPR2_in; that is, the input address remains unchanged because it does not correspond to the defective memory cell / string / page / block.

[0117] exist Figure 10 In the example, the CAM 850 also includes data buses MBUS WR and MBUS RD for updating a mapping table stored in multiple CAM registers 852, such as writing new data to the mapping table and reading / verifying new data, which can be controlled by the main MCU 858.

[0118] It should be noted that Figure 10 The number of multifaceted read operations shown is not limited to this. In some embodiments, a similar scheme can be used for N multifaceted read operations on N memory faces (N≥2). In this example, CAM 850 may include N comparators and N MUXs. However, a set of CAM registers 852 can be used for N multifaceted read operations. By sharing multiple CAM registers 852 when fixing firmware for multifaceted read operations, area can be saved, manufacturing costs can be greatly reduced, and operations can be made more efficient by using the same fixed firmware.

[0119] It should also be noted that, as shown in Figure 8- Figure 10 The design and layout of the CAM 850 are shown as an example only. The CAM 850 used to repair firmware for multifaceted read operations in 3D NAND memory may also include other layouts and additional components. In some embodiments, the CAM 850 may be included in the memory controller 20 ( Figure 1 In some implementations, the CAM 850 can be moved outside the memory die 100, and the CAM 850 can be designed as a separate electrical component in the memory system 10.

[0120] Figure 11 A method 1100 for repairing firmware in a 3D NAND flash memory according to some embodiments of the present disclosure is illustrated. It should be understood that the steps shown in method 1100 are not exhaustive, and other steps may be performed before, after, or between any of the steps shown. In some embodiments, some steps of method 1100 may be omitted, or other steps not described herein for simplicity may be included. In some embodiments, the steps of method 1100 may be performed in a different order and / or in variations.

[0121] The following text will use Figure 10 The CAM 850 in the example is used to describe method 1100. Similar methods can be used for other CAM designs.

[0122] At step S1110, input signals (e.g., MPR0_in, MPR1_in, and MPR2_in) are received at CAM 850. The input signals MPR0_in, MPR1_in, and MPR2_in are associated with multifaceted read operations MPR0, MPR1, and MPR2 for performing read operations at memory pages (with page indices PD0, PD1, and PD2) located on different memory faces (with face indices PL0, PL1, and PL2). Additionally, the input enable signal PC_remap_en can be used to activate CAM 850.

[0123] In some embodiments, the input signals MPR0_in, MPR1_in, and MPR2_in include the previously known input addresses ADDR0_in, ADDR1_in, and ADDR2_in of the memory cells, memory strings, memory pages, memory blocks, and / or memory faces for which multi-faceted read operations are to be performed. In some embodiments, the input addresses ADDR0_in, ADDR1_in, and ADDR2_in associated with the multi-faceted read operations MPR0, MPR1, and MPR2 point to different memory pages on different memory faces in the 3D NAND memory. In some embodiments, each of the input addresses ADDR0_in, ADDR1_in, and ADDR2_in may include a row address X-ADDR with a page index PD, a block index BD, and a face index PL. In some embodiments, each of the input addresses ADDR0_in, ADDR1_in, and ADDR2_in may also include a column address Y-ADDR. However, due to process variations, some of the memory cells / strings / pages / blocks / faces may be defective and need to be replaced with a predetermined set of redundant memory cells / strings / pages / blocks / faces located at new addresses. The remaining steps of method 1100 provide a processing flow for updating the input signals MPR0_in, MPR1_in, and MPR2_in accordingly.

[0124] At step S1120, the input signals MPR0_in, MPR1_in, and MPR2_in are compared with the first programming counter old_pc at comparators 854-1, 854-2, and 854-3, respectively. The first programming counter old_pc points to the first old address old_pc_0 (also referred to as the first address in the first set of mapped addresses) stored in the mapping table in CAM 850. In some embodiments, the mapping table may be stored in multiple CAM registers 852 inside CAM 850. The mapping table contains multiple old addresses (also referred to as the first set of mapped addresses) and multiple new addresses (also referred to as the second set of mapped addresses), wherein the old addresses (i.e., the first set of mapped addresses) provide the location of defective memory cells / strings / pages / blocks / faces, and the new addresses (i.e., the second set of mapped addresses) provide the location of redundant memory cells / strings / pages / blocks / faces intended to replace the defective memory cells / strings / pages / blocks / faces. In the mapping table, one new address corresponds to one old address. Although the old address can be stored in the first programming counter old_pc, the new address can be stored in the second programming counter new_pc.

[0125] At step S1130, it is determined whether the input signals MPR0_in, MPR1_in and MPR2_in have an address that matches the address stored in the first programming counter old_pc (e.g., the first old address old_pc_0).

[0126] If the input address ADDR0_in of the input signal MPR0_in matches the first old address old_pc_0, then at step S1140, comparator 854-1 can generate an output enable signal MPR0_out_en to indicate the matching state. Similarly, if the input address ADDR1_in of the input signal MPR1_in or the input address ADDR2_in of the input signal MPR2_in matches the first old address old_pc_0, then comparator 854-2 or 854-3 can generate an output enable signal MPR1_out_en or MPR2_out_en to indicate the matching state.

[0127] If the input address ADDR0_in of the input signal MPR0_in does not match the first old address old_pc_0, then the first old address old_pc_0 in the first programming counter old_pc can be replaced by the second old address (e.g., old_pc_1) in the mapping table, as shown in step S1150. The first programming counter old_pc can thus point to the second old address old_pc_1 (also referred to as the second address in the first set of mapped addresses). And at step S1130, the input signal MPR0_in can be compared again with the first programming counter to determine whether the input address ADDR0_in matches the second old address old_pc_1. A similar processing flow can be applied to the input signals MPR1_in and MPR2_in.

[0128] If all old addresses in the mapping table (i.e., all first-group mapped addresses) have been compared with the input address ADDR0_in in the input signal MPR0_in, and no matching address is found (see step S1145), then at step S1160, comparator 854-1 can generate the output enable signal MPR0_out_en to indicate NULL. Similarly, if no matching address is found in the mapping table, then at step S1160, comparators 854-2 and 854-3 can generate the output enable signals MPR1_out_en and MPR2_out_en to indicate NULL.

[0129] At step S1170, if the output enable signal MPR0_out_en indicates NULL, the output signal MPR0_out can be generated by the MUX 856-1 without changing the input address ADDR0_in. In other words, the multi-faceted read operation to be performed at the memory cell / string / page / block / face located at the input address ADDR0_in is not marked as defective by the memory system.

[0130] If the output enable signal MPR0_out_en indicates a matching state, an output signal MPR0_out with a new address ADDR0_new can be generated at step S1180. In other words, when memory cells / strings / pages / blocks / faces located at input address ADDR0_in are marked as defective by the storage system, they can be replaced by redundant memory cells / strings / pages / blocks / faces located at the new address ADDR0_new. The new address ADDR0_new can be determined based on the second programming counter new_pc, which returns the new address new_pc_0 (also referred to as the first address in the second set of mapped addresses) in the mapping table corresponding to the old address old_pc_0 (i.e., the first address in the first set of mapped addresses).

[0131] In summary, this disclosure provides a content-addressable memory (CAM) for repairing multi-faceted read operations in a flash memory device. The CAM includes a set of CAM registers configured as a memory mapping table. The mapping table includes multiple old addresses, each corresponding to a new address. The CAM also includes N comparators coupled to the set of CAM registers and configured to compare the old addresses with N input signals for performing multi-faceted read operations on N memory faces, where N is an integer greater than 1. The CAM also includes N multiplexers, each coupled to one of the N comparators and to the set of CAM registers, and configured to generate N output signals for the multi-faceted read operations. At least one of the N output signals includes a comparison based on the new address in the mapping table and the output of the comparators.

[0132] This disclosure also provides a flash memory device having M memory planes, where M is an integer greater than 1. The flash memory device further includes control circuitry coupled to the M memory planes via word line drivers and / or bit line drivers. The control circuitry includes M asynchronous multiple-plane (AMPI) read units with independent page addresses, each read unit configured to provide AMPI read control signals for a corresponding memory plane among the M memory planes to control AMPI read operations on the corresponding memory plane. The control circuitry also includes content-addressable memory (CAM) including a set of CAM registers shared by the M AMPI read units for firmware repair of AMPI read operations.

[0133] This disclosure also provides a memory storage system having a flash memory device. The flash memory device includes M memory planes and control circuitry, where M is an integer greater than 1. The control circuitry is coupled to the M memory planes via word line drivers and / or bit line drivers. The control circuitry includes M asynchronous multiple access (AMPI) read units with independent page addresses. Each read unit is configured to provide AMPI read control signals for a corresponding memory plane among the M memory planes to control AMPI read operations on the corresponding memory plane. The control circuitry also includes a content-addressable memory (CAM) having a set of CAM registers shared by the M AMPI read units for firmware repair of AMPI read operations.

[0134] This disclosure also provides a method for repairing firmware for multi-faceted read operations in a flash memory device. The method includes the steps of: receiving N input signals at a content-addressable memory (CAM) to perform multi-faceted read operations on N memory faces, where N is an integer greater than 1; comparing the N input signals with a first old address stored in a set of CAM registers by N comparators in the CAM; generating N output enable signals by the N comparators in the CAM to indicate whether a corresponding input signal includes an input address matching the first old address; and generating N output signals based on the N output enable signals by N multiplexers in the CAM, wherein at least one of the N output signals points to a new address stored in a set of CAM registers, where the new address corresponds to the first old address.

[0135] The foregoing description of the specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt these specific embodiments for various applications by applying knowledge of the art without excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive rather than limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on the disclosure and guidance.

[0136] The embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly performed.

[0137] The summary and abstract section may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0138] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A content-addressable memory (CAM), comprising: A CAM register stores a mapping table, wherein the mapping table includes a plurality of first addresses and a plurality of second addresses, each first address corresponding to a second address; N A comparator, the N A comparator is coupled to the CAM register, and each comparator is configured to compare a plurality of the first addresses with... N One of the input signals is compared, where... N It is an integer greater than 1, the stated N Each input signal comes from one of N microcontroller units; and N A multiplexer, the N Each multiplexer is coupled to the aforementioned N A comparator is coupled to the CAM register and configured to generate N One output signal, wherein the N At least one of the output signals is obtained according to the mapping table and the comparison output by the comparator.

2. The content-addressable memory according to claim 1, wherein, The N Each of the comparators is also configured as follows: Generate an output enable signal; and The output enable signal is sent to the N One of the multiplexers in a set of multiplexers.

3. The content-addressable memory according to claim 2, wherein, The N Each of the multiplexers is also configured to: Receive the output enable signal sent by the comparator; and Receive the second address stored in the mapping table.

4. The content-addressable memory according to claim 2, wherein, When the input address in the input signal matches one of the plurality of first addresses, the output enable signal indicates the matching state.

5. The content-addressable memory according to claim 4, wherein, When the input address in the input signal does not match any of the plurality of first addresses, the output enable signal indicates NULL.

6. The content-addressable memory according to claim 4, wherein, The N microcontroller units respectively control the N memory surface read operations in the flash memory device; the input address in the input signal identifies the memory cell, memory string, memory page, memory block or memory surface in the flash memory device.

7. The content-addressable memory according to claim 1, wherein, The N microcontroller units each control the N-sided memory surface read operation in the flash memory device.

8. The content-addressable memory according to claim 7, wherein, The plurality of first addresses stored in the mapping table identify defective memory cells, defective memory strings, defective memory pages, or defective memory blocks in the flash memory device.

9. The content-addressable memory according to claim 7, wherein, The second address stored in the mapping table identifies redundant memory cells, redundant memory strings, redundant memory pages, redundant memory blocks, or redundant memory planes in the flash memory device.

10. The content-addressable memory according to claim 7, wherein, The N microcontroller units and the content-addressable memory are all located in the peripheral circuitry of the flash memory device; wherein the flash memory includes a three-dimensional NAND flash memory.

11. A content-addressable memory (CAM), comprising: A CAM register stores a mapping table, wherein the mapping table includes a plurality of first addresses and a plurality of second addresses, each first address corresponding to a second address; A first comparator and a second comparator, both coupled to the CAM register, wherein the first comparator is configured to receive a first input signal from a first microcontroller and compare the first input signal with a plurality of first addresses; and the second comparator is configured to receive a second input signal from a second microcontroller and compare the second input signal with a plurality of first addresses; and A first multiplexer and a second multiplexer, the first multiplexer being coupled to the first comparator and the second multiplexer being coupled to the second comparator, and both the first multiplexer and the second multiplexer being coupled to the CAM register and configured to receive a plurality of the second addresses.

12. The content-addressable memory according to claim 11, wherein, The first input terminal of the first comparator and the first input terminal of the second comparator are both coupled to the CAM register, and the second input terminal of the first comparator is coupled to the first microcontroller unit, and the second input terminal of the second comparator is coupled to the second microcontroller unit; The control terminal of the first multiplexer is coupled to the output terminal of the first comparator, the control terminal of the second multiplexer is coupled to the output terminal of the second comparator, and the input terminals of both the first and second multiplexers are coupled to the CAM register.

13. A content-addressable memory (CAM) for a flash memory device, comprising: A set of CAM registers, shared by multiple microcontroller units of a flash memory device, the set of CAM registers being configured as a memory mapping table, the mapping table including multiple first addresses and second addresses, each first address corresponding to one second address; The CAM register and the plurality of microcontroller units are disposed in the control circuit of the flash memory device, and the set of CAM registers is coupled to the plurality of microcontroller units.

14. A memory comprising: M There are several memory surfaces, among which... M It is an integer greater than 1; and The control circuit, coupled to the word line driver and / or bit line driver, is connected to the... M A memory surface, wherein the control circuitry includes: M Each microcontroller unit is configured to provide for the... M The read control signals for the corresponding memory plane in each memory plane; and Content-addressable memory (CAM), the content-addressable memory comprising the... M The CAM register is shared by all microcontroller units.

15. The memory according to claim 14, wherein, The memory includes a flash memory device. M Each of the memory planes includes a plurality of memory strings extending vertically through a stack of alternating conductive and dielectric layers, wherein each of the plurality of memory strings comprises: A channel layer disposed on the sidewall of the core filling membrane; and A memory film is disposed on the sidewall of the channel layer.

16. The memory according to claim 14, wherein, The content-addressable memory also includes M Each comparator is coupled to the CAM register and configured to compare a plurality of first addresses stored in the CAM register with a read control signal of the microcontroller unit.

17. The memory according to claim 16, wherein, The plurality of first addresses identify defective memory cells, defective memory strings, defective memory pages, or defective memory blocks in the memory.

18. The memory according to claim 16, wherein, The content-addressable memory also includes M Each multiplexer is coupled to a corresponding comparator and the CAM register, and each multiplexer is configured to generate an output signal for reading operations on the corresponding memory surface.

19. The memory according to claim 18, wherein, The output signal includes a second address provided by the CAM register, the second address identifying a redundant memory cell, redundant memory string, redundant memory page, or redundant memory block in the memory.

20. The memory according to claim 18, wherein, Each comparator is also configured as follows: When the input address in the read control signal matches one of the plurality of first addresses, an output enable signal indicating the matching status is generated; and The output enable signal is sent to the corresponding multiplexer to generate the output signal for performing the read operation on the corresponding memory surface.

21. A memory comprising: First memory surface and second memory surface; A control circuit coupled to the first memory surface and the second memory surface, wherein the control circuit includes: A first microcontroller unit and a second microcontroller unit, wherein the first microcontroller unit is configured to output a first output signal and the second microcontroller unit is configured to output a second output signal; Content-addressable memory, the content-addressable memory being coupled to the first microcontroller unit and the second microcontroller unit, the content-addressable memory being the content-addressable memory as described in any one of claims 1-13.

22. The memory according to claim 21, wherein, The memory includes a flash memory device. Both the first memory surface and the second memory surface include multiple memory strings that extend vertically through a stack of alternating conductive and dielectric layers. Each of the multiple memory strings includes: A channel layer disposed on the sidewall of the core filling membrane; and A memory film is disposed on the sidewall of the channel layer.

23. A memory storage system, comprising: Memory, including: M There are several memory surfaces, among which... M It is an integer greater than 1; and The control circuit, coupled to the word line driver and / or bit line driver, is connected to the... M A memory surface, wherein the control circuitry includes: M Each microcontroller unit is configured to provide for the... M The read control signals for the corresponding memory plane in each memory plane; and Content-addressable memory (CAM), the content-addressable memory comprising the... M The CAM register is shared by all microcontroller units.

24. A method of operating a memory, comprising: The input signals of each of the N microcontroller units are input to the same content-addressable memory (CAM), where... N It is an integer greater than 1. The content-addressable memory stores a mapping table, wherein the mapping table includes a plurality of first addresses and a plurality of second addresses, and each first address corresponds to a second address; Compare each of the input signals with a plurality of the first addresses and output an enable signal; and N output signals are output according to the mapping table and each of the output enable signals.

25. The method of claim 24, further comprising: pass N Each comparator will... N Each input signal is compared with a first address; as well as pass N Each multiplexer is based on N The output enable signal generates the N One output signal, wherein the N At least one of the output signals points to the second address, wherein the second address corresponds to the first address.

26. The method of claim 24, further comprising: The corresponding comparator determines whether the input address of the corresponding input signal matches the first address.

27. The method of claim 26, further comprising: When the input address matches the first address, a corresponding output enable signal indicating the matching status is generated.

28. The method according to claim 27, wherein, Generate the N The output signals include: When the corresponding output enable signal indicates the matching state, a corresponding output signal including the second address is generated.

29. The method of claim 26, further comprising: When the input address does not match the first address, the input address of the corresponding input signal is compared with other first addresses stored in the content-addressable memory by the corresponding comparator.

30. The method of claim 29, further comprising: When the input address does not match any first address stored in the content-addressable memory, a corresponding output enable signal is generated to indicate NULL.

31. The method according to claim 30, wherein, Generate the N The output signals include: When the corresponding output enable signal indicates NULL, a corresponding output signal including the input address is generated.

32. The method of claim 29, further comprising: Receive an input enable signal to activate the content-addressable memory.

33. The method of claim 24, further comprising: The first address is stored in the content-addressable memory to identify a defective memory cell, defective memory page, or defective memory block in the memory.

34. The method of claim 24, further comprising: The second address is stored in the content-addressable memory to identify redundant memory cells, redundant memory pages, or redundant memory blocks in the memory.

35. The method of claim 24, further comprising: Fix firmware for multi-faceted read operations in a 3D NAND flash memory, wherein the 3D NAND flash memory includes: Multiple memory strings, the multiple memory strings extending vertically through a stack of alternating conductive and dielectric layers, wherein each of the multiple memory strings comprises: A channel layer disposed on the sidewall of the core filling membrane; and A memory film is disposed on the sidewall of the channel layer.

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