Semiconductor structure and method of forming the same, layout structure

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a layout structure and a forming method thereof. The method comprises: providing a substrate; the substrate comprises a first region and a second region arranged in a second direction in sequence, and T-shaped active pillars arranged in a first direction and a third direction in the first region and the second region; the first direction, the second direction and the third direction are perpendicular to each other, and the first direction and the second direction are parallel to the surface of the substrate; forming a T-shaped gate structure on the surface of the T-shaped active pillar and a bit line structure extending in the third direction in the first region; wherein a plurality of T-shaped gate structures in the first direction are connected to each other; forming a capacitor structure extending in the second direction in the second region, and the bit line structure and the capacitor structure are connected to the T-shaped gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its formation method and layout structure. Background Technology

[0002] Currently, 6F is widely used. 2 Dynamic Random Access Memory (DRAM) is fabricated using traditional layout methods and buried word line technology. However, miniaturization of DRAM becomes extremely difficult under this technology. There are also attempts to improve DRAM performance by using new materials, but this undoubtedly increases the process complexity and manufacturing cost of DRAM.

[0003] Based on this, in related technologies, 4F is fabricated using a full-ring gate or dual-gate process. 2 DRAM, 4F 2 DRAM requires the formation of bit line steps or word line steps. However, bit line steps have relatively large sensing noise in DRAM use, while word line steps have word line coupling and the interconnection of word lines on the same plane is difficult to achieve for multi-layer stacking. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, as well as a layout structure.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, including:

[0006] A substrate is provided; the substrate includes a first region and a second region arranged sequentially along a second direction, and T-shaped active pillars arranged in an array along the first direction and a third direction in the first region and the second region; the first direction, the second direction and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the substrate;

[0007] A T-shaped gate structure and a bit line structure extending along the third direction are formed in the first region on the surface of the T-shaped active pillar; wherein, a plurality of the T-shaped gate structures located in the first direction are interconnected.

[0008] A capacitor structure extending along the second direction is formed in the second region, and both the bit line structure and the capacitor structure are connected to the T-type gate structure.

[0009] In a second aspect, embodiments of this disclosure provide a semiconductor structure, which is formed by the above-described semiconductor structure formation method, and the semiconductor structure includes:

[0010] A semiconductor substrate and T-shaped active pillars located on the surface of the semiconductor substrate; the T-shaped active pillars are arranged in an array along a first direction and a third direction;

[0011] A T-shaped gate structure and a bit line structure are located on the surface of a portion of the T-shaped active pillars; wherein, a plurality of the T-shaped gate structures in the first direction are interconnected; the bit line structure extends along the third direction;

[0012] A capacitor structure extending along a second direction; both the bit line structure and the capacitor structure are connected to the T-type gate structure; the first direction, the second direction, and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate.

[0013] In some embodiments, the semiconductor substrate includes a first region and a second region arranged sequentially along a second direction;

[0014] The T-shaped active post includes a first active post and a second active post located in the first region and extending along the second direction, and a third active post and a fourth active post located in the first region and extending along the first direction; wherein the first active post is connected to the third active post; the bit line structure is formed on a portion of the fourth active post.

[0015] In some embodiments, the projections of the first active pillar and the third active pillar onto the surface of the semiconductor substrate are T-shaped.

[0016] Thirdly, embodiments of this disclosure provide a layout structure, including: the aforementioned semiconductor structures arranged at intervals along a second direction;

[0017] The semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; each memory cell includes a T-gate structure and a capacitor structure.

[0018] Wherein, two adjacent memory cells in the second direction are centrally symmetrical, and the capacitor structures of two adjacent memory cells in the second direction at least partially overlap in the projection area in the first direction.

[0019] The semiconductor structure and its formation method and layout structure provided in this disclosure form a T-type gate structure, and word lines can be formed on the outside of the T-type gate structure. In this way, not only can the interconnection of word lines on the same plane in the multi-layer stacked structure be realized, but also the size of the word lines can be controlled, thereby reducing the coupling effect between word line steps. Attached Figure Description

[0020] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0021] Figure 1 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0022] Figures 2a-2l , Figures 3a-3q This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0023] Figures 4a-4e This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0024] Figures 5a-5d This is a schematic diagram of a planar structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 6a and 6b A plan layout diagram of the layout structure provided in the embodiments of this disclosure;

[0026] The annotations in the attached figures are explained as follows:

[0027] 10—Semiconductor substrate; 11—Stacked structure; 111—First semiconductor layer; 112—Second semiconductor layer; 110—Initial active layer; 12—T-shaped active pillar; 121—First active pillar; 122—Second active pillar; 123—Third active pillar; 124—Fourth active pillar; 125—Fifth active pillar; 1251—First sub-pillar; 1252—Second sub-pillar; 1253—Third sub-pillar; 131—First sacrificial layer; 132—Second sacrificial layer; 14—Support structure; 141—The first active layer; 142—Second support layer; 15—Concave trench; 151—Isolation layer; 16—T-type gate structure; 161—Gate dielectric layer; 162—Gate conductive layer; 17—Bit line; 171—Bit line trench; 18—Capacitor structure; 181—First electrode layer; 182—Dielectric layer; 183—Second electrode layer; 184—Conductive layer; 19—Word line step; 191—Word line; 20—Third semiconductor layer; 21—Protective layer; 100—Semiconductor structure; 200—Layout structure. Detailed Implementation

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0029] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces of the substrate is defined as the third direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate is located), two intersecting (e.g., perpendicular) directions are defined. For example, the direction of the extension of the letter lines can be defined as the first direction, and the direction of the extension of the capacitor structure can be defined as the second direction. The planar orientation of the substrate can be determined based on the first and second directions. Here, the first direction, the second direction, and the third direction are perpendicular to each other. In the embodiments of this disclosure, the first direction is defined as the X-axis, the second direction is defined as the Y-axis, and the third direction is defined as the Z-axis.

[0034] This disclosure provides a method for forming a semiconductor structure. Figure 1 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0035] Step S101, providing a substrate; the substrate includes a first region and a second region arranged sequentially along a second direction, and T-shaped active pillars arranged in the first region and the second region along the first direction and a third direction array.

[0036] In this embodiment of the disclosure, the substrate includes at least a semiconductor substrate, which may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0037] In this embodiment of the disclosure, the first region and the second region can be used to form different functional structures, for example, the first region can be used to form a gate structure, a bit line structure and a stepped word line structure, and the second region can be used to form a capacitor structure.

[0038] Step S102: A T-type gate structure located on the surface of a T-type active pillar and a bit line structure extending along a third direction are formed in the first region; wherein, a plurality of T-type gate structures located in the first direction are interconnected.

[0039] In this embodiment of the disclosure, the T-gate structure is partly a dual-gate structure and partly a four-sided ring-gate structure. The T-gate structure covers the first and second surfaces of the T-type active pillar along the third direction, one side of the T-type active pillar along the first direction, and one side of the T-type active pillar along the second direction.

[0040] Since both the bit line structure and the T-type gate structure are formed on the surface of the T-type active pillar, the bit line structure and the T-type gate structure are connected through the T-type active pillar.

[0041] In this embodiment, since word lines can be formed on the outside of the T-type gate structure, not only can the interconnection of word lines on the same plane in the multi-layer stacked structure be realized, but the size of the word lines can also be controlled, thereby reducing the coupling effect between word line steps.

[0042] Step S103: A capacitor structure extending along the second direction is formed in the second region, and both the bit line structure and the capacitor structure are connected to the T-type gate structure.

[0043] The capacitor structure formed in this embodiment extends along a second direction, meaning it is arranged horizontally. This horizontal arrangement reduces the likelihood of tipping or breaking, thus improving stability. Furthermore, multiple horizontal capacitor structures and T-gate structures can be stacked to form a three-dimensional semiconductor structure, thereby increasing integration and enabling miniaturization.

[0044] Figures 2a-2l , Figures 3a-3q This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 2a-2l , Figures 3a-3q The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0045] First, you can refer to Figures 2a-2k Step S101 is executed, providing a substrate; the substrate includes a first region and a second region arranged sequentially along a second direction, and T-shaped active pillars arranged in an array along the first and third directions within the first and second regions. Figure 2a For 3D views, Figures 2b-2k This is a top view of the semiconductor structure formation process or a cross-sectional view along a-a', b-b', and c-c'.

[0046] In some embodiments, a T-shaped active pillar can be formed by the following steps: providing a semiconductor substrate 10; forming a stacked structure 11 on the surface of the semiconductor substrate 10 located in a first region A and a second region B; the stacked structure 11 includes a first semiconductor layer 111 and a second semiconductor layer 112 alternately stacked along a third direction; removing the first semiconductor layer 111 in the first region A to expose the second semiconductor layer 112 in the first region A; thinning the exposed second semiconductor layer 112 to form an initial active layer 110; and processing the initial active layer 110 to form a T-shaped active pillar 12.

[0047] like Figure 2a and 2b As shown, a stacked structure 11 located in a first region A and a second region B is formed on the surface of a semiconductor substrate 10; the stacked structure 11 includes a first semiconductor layer 111 and a second semiconductor layer 112 that are alternately stacked along a third direction.

[0048] In this embodiment of the disclosure, the material of the first semiconductor layer 111 may be germanium (Ge), silicon germanide (SiGe), or silicon carbide; it may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The second semiconductor layer 112 may be a silicon layer, or may include other semiconductor elements, such as germanium, or include semiconductor compounds, such as silicon carbide, gallium arsenide, gallium indium phosphide, indium arsenide, or indium antimonide, or include other semiconductor alloys, such as silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide or combinations thereof.

[0049] In this embodiment, the first semiconductor layer 111 and the second semiconductor layer 112 are made of different materials because the first semiconductor layer 111 needs to be removed later, while the second semiconductor layer 112 is retained. Therefore, the first semiconductor layer 111 has a larger selective etching ratio than the second semiconductor layer 112. For example, the etching selectivity ratio of the first semiconductor layer 111 to the second semiconductor layer 112 can be 5-15, so that the first semiconductor layer 111 is more easily etched away than the second semiconductor layer 112 during the etching process.

[0050] In this embodiment, the thickness of the first semiconductor layer 111 can be 5–30 nanometers (nm), for example, 10 nm or 25 nm; the thickness of the second semiconductor layer 112 can be 50–80 nm, for example, 60 nm or 75 nm. The number of the first semiconductor layer 111 and the second semiconductor layer 112 in the stacked structure 11 can be set according to the required capacitance density (or storage density). The more layers of the first semiconductor layer 111 and the second semiconductor layer 112, the higher the integration level and the greater the capacitance density of the formed semiconductor structure.

[0051] In this embodiment of the disclosure, the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, spin coating process, coating process, or thin film process, etc.

[0052] like Figure 2c As shown, the first semiconductor layer 111 in the first region A is removed to expose the second semiconductor layer 112 in the first region A.

[0053] In this embodiment of the present disclosure, the first semiconductor layer 111 in the first region A can be removed by a wet etching process (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or a dry etching process. Since the first semiconductor layer 111 has a high etching selectivity relative to the second semiconductor layer 112, the second semiconductor layer 112 can be removed without damaging it.

[0054] like Figure 2d As shown, the exposed second semiconductor layer 112 is thinned to form an initial active layer 110.

[0055] In this embodiment of the disclosure, the second semiconductor layer 112 can be thinned in the following two ways to form the initial active layer 110:

[0056] Method 1: Dry etching is performed directly on the second semiconductor layer 112 until the required thickness is formed, at which point the etching is stopped.

[0057] Method 2: In-situ oxidation of the second semiconductor layer 112, partially oxidizing the second semiconductor layer 112 into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching techniques.

[0058] In this embodiment, the second semiconductor layer 112 is thinned to 15-25 nm to form an initial active layer 110, for example, the thickness of the initial active layer 110 can be 20 nm. This allows the formation of a channel region from the fully depleted semiconductor layer, where holes are easily recombinated in the source region without accumulation, thus improving the floating body effect. Furthermore, the increased gap between adjacent initial active layers 110 allows for more space to be reserved for the formation of the gate structure and subsequent word line structure, reducing word line coupling and the complexity and cost of fabricating the gate and word line structures.

[0059] It should be noted that in other embodiments, the second semiconductor layer 112 may not be thinned. After removing the first semiconductor layer 111 in the first region A, the exposed second semiconductor layer 112 can be directly used as the initial active layer 110.

[0060] In some embodiments, processing the initial active layer 110 to form a T-shaped active pillar 12 may include the following steps: sequentially forming a first sacrificial layer 131 and a first support layer 141 on the surface of the initial active layer 110; wherein the first support layer 141 fills the spaces between the first sacrificial layers 131; removing a portion of the first support layer 141, a portion of the first sacrificial layer 131, a portion of the initial active layer 110 in the first region A, and a portion of the stacked structure 11 in the second region B to form a plurality of concave trenches 15 spaced apart along a first direction; removing a portion of the initial active layer in the second direction to form a first space, the remaining initial active layer constituting the T-shaped active pillar.

[0061] like Figure 2e and 2f As shown, a first sacrificial layer 131 and a first support layer 141 are sequentially formed on the surface of the initial active layer 110; a portion of the first support layer 141, a portion of the first sacrificial layer 131, a portion of the initial active layer 110, and a portion of the stacked structure 11 in the second region B are removed to form a plurality of concave trenches 15 spaced apart along the X-axis direction.

[0062] In this embodiment, the material of the first sacrificial layer 131 can be silicon oxide or other suitable materials. The material of the first support layer 141 can be silicon nitride or other suitable materials. Here, the materials of the first sacrificial layer 131 and the first support layer 141 should be different, and have different etching selectivity ratios under the same etching conditions. For example, the etching selectivity ratio between the first sacrificial layer 131 and the semiconductor substrate 10 is greater than the etching selectivity ratio between the first support layer 141 and the semiconductor substrate 10. Both the first sacrificial layer 131 and the first support layer 141 can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, coating process, or furnace tube process.

[0063] In this embodiment of the present disclosure, the first support layer 141 is used to support the second semiconductor layer 112. Since a T-type gate structure needs to be formed on the surface of the second semiconductor layer 112, the first support layer 141 can also be used to support the T-type gate structure. In this way, the stability of the formed semiconductor structure can be improved and the collapse of the formed semiconductor structure can be prevented.

[0064] In this embodiment of the disclosure, a portion of the first support layer 141, a portion of the first sacrificial layer 131, a portion of the initial active layer 110, and a portion of the stacked structure 11 in the first region A can be removed by dry etching technology to form a plurality of concave trenches 15 spaced apart along the first direction.

[0065] In this embodiment of the disclosure, each T-shaped active post is used to form a memory cell, and two adjacent memory cells in the X-axis direction are isolated by a concave trench 15.

[0066] In some embodiments, such as Figure 2g and 2h As shown, after forming the concave trench 15, the method for forming the semiconductor structure further includes filling the concave trench 15 with an isolation material to form an isolation layer 151. The isolation material can be a low dielectric constant (Low K) material, such as SiCON.

[0067] In this embodiment of the present disclosure, the etching selectivity between the isolation layer 151 and the semiconductor substrate 10 is greater than that between the first sacrificial layer 131 and the semiconductor substrate 10. That is, under the same etching conditions, the isolation layer 151 is easier to be etched away than the first sacrificial layer 131.

[0068] In this embodiment of the disclosure, Low K material is used as the isolation material, which can reduce the parasitic capacitance of the semiconductor structure, thereby reducing the capacitance resistance delay and improving the response time of the semiconductor structure.

[0069] like Figure 2i and 2jAs shown, a portion of the initial active layer 110 in the Y-axis direction is removed to form the first space C, and the remaining initial active layer 110 constitutes the T-shaped active column 12.

[0070] In this embodiment, a wet etching process can be used to laterally etch the initial active layer 110 to form a T-shaped active pillar 12. The etching solution used in the wet etching can be a hydrofluoric acid solution or a mixed solution of diluted hydrofluoric acid and ammonia.

[0071] In some embodiments, the T-shaped active column located in the first region A includes a first active column and a second active column extending along a second direction, and a third active column and a fourth active column extending along a first direction, wherein the first active column and the third active column are connected.

[0072] Figure 2l This is a three-dimensional structural diagram of a T-shaped active column 12 located in the first region A, as shown below. Figure 2k and 2l As shown, the first active pillar 121, the second active pillar 122, the third active pillar 123, and the fourth active pillar 124 can be formed by the following steps: removing a portion of the first sacrificial layer 131 in the X-axis and Y-axis directions, exposing a portion of the initial active layer 110, forming a second space D; wherein, the portions of the exposed initial active layer 110 extending along the X-axis and Y-axis directions respectively constitute the first active pillar 121 and the third active pillar 123 (e.g., ...). Figure 2l (As shown); the portions of the unexposed initial active layer 110 extending along the first and second directions respectively constitute the second active pillar 122 and the fourth active pillar 124 (as shown). Figure 2l (as shown); the second space D includes the first space C.

[0073] In this embodiment of the disclosure, since a T-type gate structure and a word line structure can be formed in the second space D, the interconnection of word lines on the same plane in a multi-layer stack can be achieved through the side-connected word lines.

[0074] Next, you can refer to Figures 3a-3h In step S102, a T-type gate structure located on the surface of the T-type active pillar and a bit line structure extending along a third direction are formed in the first region A; wherein, multiple T-type gate structures located in the first direction are interconnected. Figures 3a-3b 3d to 3h are top views or cross-sectional views along a-a', b-b', and c-c' of the semiconductor structure formation process. Figure 3c A 3D view of a T-gate structure.

[0075] like Figures 3a-3cAs shown, the T-type gate structure 16 can be formed by the following steps: a gate dielectric layer 161 and a gate conductive layer 162 are sequentially formed on the surfaces of the first active pillar 121 and the third active pillar 123 to form the T-type gate structure 16. The gate conductive layer 162 fills the second space D.

[0076] In this embodiment of the disclosure, the material used for the gate dielectric layer 161 may be silicon oxide or other suitable materials; the material used for the gate conductive layer 162 may include polysilicon, metals (e.g., tungsten, copper, aluminum, titanium, tantalum, ruthenium, etc.), metal alloys, metal silicides, titanium nitride, or any combination thereof.

[0077] In this embodiment, the gate dielectric layer 161 can be formed by in-situ steam generation (ISSG) and the thickness of the gate dielectric layer 161 can be 45-80 nm, for example, 50 nm or 70 nm. The gate conductive layer 162 can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0078] Please continue reading Figure 3c In this embodiment of the disclosure, along the Y-axis direction, a portion of the gate metal layer 162-1 located at the first end of the T-type gate structure 16 can subsequently be used as part of a word line structure connecting the same T-type gate structure.

[0079] In some embodiments, such as Figures 3d-3g As shown, the bitline structure 17 can be formed by the following steps: removing part of the first sacrificial layer 131 and part of the isolation layer 151 from the sidewall of the fourth active pillar 124 to form a bitline trench 171; wherein, the bitline trench 171 exposes the end of the fourth active pillar 124 away from the third active pillar 123, and part of the isolation layer 151 is retained between two adjacent T-shaped active pillars 12 in the X-axis direction; and bitline metal material is filled into the bitline trench 171 to form a bitline structure 17 extending along the Z-axis direction.

[0080] In this embodiment of the disclosure, the bit line metal material can be any material with good conductivity, such as tungsten, cobalt, copper, aluminum, titanium, titanium nitride, platinum, palladium, molybdenum, titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0081] In this embodiment, the bit line metal material is in direct contact with the second semiconductor layer 112. Subsequently, rapid thermal annealing can be used to allow the metal material to react directly with the second semiconductor layer 112 in situ to form a metal silicide. Since the metal silicide has a low resistance, the contact resistance between the bit line structure and the fourth active pillar can be reduced, thereby further reducing the power consumption of the semiconductor structure.

[0082] like Figure 3h and 3i As shown, after forming the bit line structure 17 and before forming the capacitor structure, the method for forming the semiconductor structure further includes: removing the isolation layer 151 and the first semiconductor layer 111 located in the second region B, exposing the second semiconductor layer 112 in the second region B; thinning the second semiconductor layer 112 in the second region B to form a fifth active pillar 125, wherein the fifth active pillar 125 is connected to the second active pillar 122.

[0083] Please continue reading Figure 3i In this embodiment of the present disclosure, the fifth active column 125 includes a first sub-column 1251, a second sub-column 1252 and a third sub-column 1253 arranged sequentially along the Y-axis direction.

[0084] In this embodiment, the isolation layer 151 can be removed using a dry etching process (e.g., plasma etching, reactive ion etching, or ion milling) or a wet etching process (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid). The gas used in dry etching can be one or any combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6). In this embodiment, because the first semiconductor layer 111 has a high etch selectivity relative to the second semiconductor layer 112, the second semiconductor layer 112 can be removed without damaging it.

[0085] In this embodiment of the disclosure, the methods for thinning the second semiconductor layer 112 in the second region B include the following two:

[0086] Method 1: Dry etching is performed directly on the second semiconductor layer 112 until the required thickness is formed, at which point the etching is stopped.

[0087] Method 2: In-situ oxidation of the second semiconductor layer 112, partially oxidizing the second semiconductor layer 112 into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching techniques.

[0088] In this embodiment of the present disclosure, by thinning the second semiconductor layer 112 to form a fifth active pillar 125, the gap between two adjacent fifth active pillars 125 is increased. In this way, the effective area between the electrodes of the formed capacitor structure can be increased, thereby increasing the capacitance of the formed capacitor structure.

[0089] It should be noted that in other embodiments, the second semiconductor layer 112 may not be thinned.

[0090] Finally, you can refer to Figures 3j-3qIn step S103, a capacitor structure extending along the second direction is formed in the second region. Both the bit line structure and the capacitor structure are connected to the T-type gate structure. Figures 3i-3p 3q is a top view of the semiconductor structure formation process or a cross-sectional view along a-a', b-b' and c-c', and 3q is a three-dimensional view of the formed semiconductor structure.

[0091] like Figure 3j As shown, the capacitor structure 18 can be formed by the following steps: forming a second support layer 142 on the surface of the first sub-pillar 1251; forming a second sacrificial layer 132 on the surface of the second sub-pillar 1252.

[0092] In this embodiment of the disclosure, the second support layer 142 is filled between the first sub-pillars 1251; the material of the second support layer 142 may be silicon nitride or silicon carbonitride; the first support layer 141 and the second support layer 142 together constitute the support structure 14 of the semiconductor structure.

[0093] In this embodiment of the disclosure, the second sacrificial layer 132 is filled between the second sub-pillars 1252, and the material of the second sacrificial layer 132 can be silicon oxide or silicon oxynitride.

[0094] like Figure 3k and 3l As shown, a third semiconductor layer 20 is formed on the surface of the third sub-pillar 1253; a first electrode layer 181 is formed on the surface of the third semiconductor layer 20 and the sidewall of the second sacrificial layer 132; and a protective layer 21 is formed on the surface of the first electrode layer 181 and in the gap between the first electrode layers 181.

[0095] In this embodiment, the third semiconductor layer 20 may be a metal silicide layer. In practice, a metal material, such as any one of cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), and palladium (Pd), can be deposited on the surface of the third sub-pillar 1253; subsequently, a rapid thermal annealing process is performed to allow the metal material to react with the third sub-pillar 1253, thereby forming a metal silicide on the surface of the third sub-pillar 1253. Since the metal silicide has a low resistance, the contact resistance between the lower electrode and the drain electrode can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0096] In this embodiment of the present disclosure, the first electrode layer 181 can be formed by any of the following deposition processes: selective atomic layer deposition, chemical vapor deposition, physical vapor deposition, and spin coating. The material of the first electrode layer 181 may include a metal or a metal nitride, such as ruthenium (Ru) or titanium nitride.

[0097] In some embodiments, the material of the protective layer 21 may be silicon nitride or any other suitable material. The protective layer 21 is used to protect the first electrode layer 181 from damage when the second sacrificial layer 132 is subsequently removed. Therefore, it is necessary to set the etching selectivity between the second sacrificial layer 132 and the second sub-pillar 1252 to be greater than the etching selectivity between the protective layer 21 and the second sub-pillar 1252.

[0098] like Figure 3m and 3n As shown, the second sacrificial layer and the first electrode layer 181 located on the sidewall of the second sub-pillar 1252 are removed, exposing the sidewalls of the second sub-pillar 1252 and the second support layer 142; the protective layer 21 is removed, exposing the remaining first electrode layer 181; a dielectric layer 182 is formed on the surface of the second sub-pillar 1252 and the first electrode layer 181; a second electrode layer 183 is formed on the sidewall of the second support layer 142 and the surface of the dielectric layer 182, and the first electrode layer 181, the dielectric layer 182 and the second electrode layer 183 constitute a capacitor structure 18.

[0099] In this embodiment of the disclosure, the protective layer 21 can be removed by wet etching (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or dry etching techniques.

[0100] In this embodiment, the dielectric layer 182 and the second electrode layer 183 can be formed by any of the following deposition processes: selective atomic layer deposition (SALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin coating. The material of the second electrode layer 183 may include a metal or a metal nitride, such as ruthenium (Ru) or titanium nitride. The material of the dielectric layer 182 may include a high-k dielectric material, such as one or any combination of lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), hafnium silicate (HfSiOx), or zirconium oxide (ZrO₂). In other embodiments, the materials of the first electrode layer and the second electrode layer may also be polycrystalline silicon.

[0101] In this embodiment of the disclosure, the capacitor structure 18 extends along the Y-axis direction, that is, each capacitor structure 18 is parallel to the semiconductor substrate, i.e., the capacitor structure 18 is horizontal. On the one hand, compared with the vertical capacitor structure 18 with a high aspect ratio (i.e., the ratio of height to width or diameter), the horizontal capacitor structure 18 can reduce the possibility of tipping over or breaking, thereby improving the stability of the capacitor structure 18. On the other hand, the stacked structure formed by stacking multiple capacitor structures in the vertical direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and realizing miniaturization.

[0102] In some embodiments, such as Figure 3o and 3pAs shown, the method for forming the semiconductor structure further includes: forming a conductive layer 184 on the surface of the second electrode layer 183, wherein the conductive layer 184 fills the space between adjacent third sub-pillars 1253.

[0103] In this embodiment of the disclosure, the material of the conductive layer 184 can be polycrystalline silicon or any other suitable conductive material, such as doped polycrystalline silicon.

[0104] In some embodiments, such as Figure 3q As shown, after forming the T-gate structure 16, the method for forming the semiconductor structure further includes: forming word line steps 19 stacked sequentially along the Z-axis direction; wherein each word line 191 in the word line steps 19 is electrically connected to a plurality of T-gate structures 16 arranged along the X-axis direction.

[0105] In some embodiments, the word line step 19 can be formed by the following steps: First, a photoresist layer with a first opening is formed on the surface of a first region A; the first opening exposes one end of the first region A; the first region A is etched by the photoresist layer with the first opening to form a first stepped structure; second, a photoresist layer with a second opening is formed on the surface of the first stepped structure, the second opening exposes a portion of the first stepped structure, the first stepped structure is etched by the photoresist layer with the second opening to form a second stepped structure, wherein the size of the second opening in the first direction is larger than the size of the first opening; third, a photoresist layer with a third opening is formed on the surface of the second stepped structure, the third opening exposes a portion of the second stepped structure, the second stepped structure is etched by the photoresist layer with the third opening to form a third stepped structure, wherein the size of the third opening in the first direction is larger than the size of the second opening; the above steps are repeated, and after multiple etching processes, the word line step 19 is finally formed, the word line step 19 having a progressively decreasing length from bottom to top along the Z-axis direction.

[0106] In other embodiments, the word line step 19 can also be formed by the following steps: First, a first word line of a first length is formed on the substrate surface of the first region A, wherein the first word line is electrically connected to the bottommost first layer T-gate structure 16 along the X-axis direction; Second, a first isolation unit of a second length is formed on the surface of the first word line; A second word line of a second length is formed on the surface of the first isolation unit, wherein the second word line is electrically connected to the bottommost second layer T-gate structure 16 along the first direction, wherein the first length is greater than the second length, and the first isolation unit is used to isolate adjacent first word lines and second word lines; Third, a second isolation unit of a third length is formed on the surface of the second word line; A third word line of a third length is formed on the surface of the second isolation unit, wherein the third word line is electrically connected to the bottommost third layer T-gate structure 16 along the X-axis direction, wherein the second length is greater than the third length, and the second isolation unit is used to isolate adjacent second word lines and third word lines; Repeating the above steps, after multiple formation processes, a word line step 19 composed of multiple word lines is formed.

[0107] In this embodiment of the disclosure, a T-type gate structure is formed and a word line side-connection method is adopted, which not only solves the problem that word line interconnection on the same plane is difficult to achieve for multi-layer stacking, but also reduces the coupling effect of word lines by controlling the size of the side-connected word lines.

[0108] This disclosure also provides a semiconductor structure, which is formed using the semiconductor structure formation method described in the above embodiments. Figures 4a-4e This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, wherein, Figure 4a A three-dimensional view of the semiconductor structure. Figure 4b This is a 3D view of a T-shaped active column. Figure 4c This is a three-dimensional view of the T-gate structure. Figure 4d for Figure 4a Top view, Figure 4e for Figure 4a A sectional view along a-a'.

[0109] like Figure 4a As shown, the semiconductor structure 100 includes at least: a semiconductor substrate 10 and T-shaped active pillars 12 located on the surface of the semiconductor substrate 10; the T-shaped active pillars 12 are arranged in an array along the X-axis and Z-axis directions; T-shaped gate structures 16 and bit line structures 17 are located on the surface of a portion of the T-shaped active pillars 12; wherein, a plurality of T-shaped gate structures 16 in the X-axis direction are interconnected; the bit line structure 17 extends along the Z-axis direction; and a capacitor structure 18 extends along the Y-axis direction; both the bit line structure 17 and the capacitor structure are connected to the T-shaped gate structure 16.

[0110] In some embodiments, such as Figure 4bAs shown, the semiconductor structure 100 further includes: a first region A and a second region B arranged sequentially along the Y-axis direction; the T-shaped active pillar 12 includes a first active pillar 121 and a second active pillar 122 located in the first region A and extending along the Y-axis direction, and a third active pillar 123 and a fourth active pillar 124 located in the first region A and extending along the X-axis direction; wherein the first active pillar 121 and the third active pillar 123 are connected; the bit line structure 17 is formed on a portion of the fourth active pillar 124.

[0111] In some embodiments, such as Figure 4c As shown, the T-type gate structure 16 includes a gate dielectric layer 161 located on the surfaces of the first active pillar 121 and the third active pillar 123, and a gate conductive layer 162 located on the surface of the gate dielectric layer 161.

[0112] In this embodiment of the disclosure, the projections of the first active pillar 121 and the third active pillar 123 onto the surface of the semiconductor substrate 10 are T-shaped.

[0113] In some embodiments, please continue to see Figure 4b The T-shaped active pillar 12 also includes a fifth active pillar 125 located in the second region B; the capacitor structure 18 is formed on a portion of the fifth active pillar 125.

[0114] like Figure 4e As shown, the capacitor structure 18 includes a first electrode layer 181, a dielectric layer 182, and a second electrode layer 183 located on the fifth active pillar 125.

[0115] In some embodiments, please continue to see Figure 4d and 4e The semiconductor structure 100 also includes a conductive layer 184 located between and on the surface of the second electrode layer 183, and a third semiconductor layer 20 located between the first electrode layer 181 and the fifth active pillar 125.

[0116] In some embodiments, the third semiconductor layer 20 may be a metal silicide layer, and the third semiconductor layer 20 is used to reduce the contact resistance between the capacitor structure 18 and the fifth active pillar 125.

[0117] In some embodiments, please continue to see Figure 4d The adjacent T-shaped active columns along the X-axis have concave grooves 15.

[0118] In some embodiments, please continue to see Figure 4a , 4dIn addition to 4e, the semiconductor structure 100 further includes: a support structure 14; the support structure 14 includes a first support layer 141 and a second support layer 142; wherein the first support layer 141 is located on the surface of the second active pillar 122 between the bit line structure 17 and the T-type gate structure 16; and the second support layer 142 is located on the surface of the fifth active pillar 125 between the capacitor structure and the T-type gate structure 16.

[0119] In some embodiments, please continue to see Figure 4a The semiconductor structure 100 further includes: word line steps 19; the word line steps 19 are stacked sequentially along the Z-axis direction, and each layer of word lines 191 in the word line steps 19 is electrically connected to a plurality of T-type gate structures 16 arranged along the X-axis direction.

[0120] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0121] The semiconductor structure provided in this embodiment has a T-type gate structure, and the word lines are led out through the outside of the T-type gate structure. In this way, not only can the interconnection of word lines on the same plane in the multi-layer stacked structure be realized, but the size of the word lines can also be controlled, thereby reducing the coupling effect between word lines.

[0122] Figures 5a-5d This is a schematic diagram of a planar structure of a semiconductor structure provided in an embodiment of this disclosure, such as... Figures 5a-5d As shown, the semiconductor structure 100 includes a T-type gate structure 16, a bit line structure 17, and a capacitor structure 18 arranged in an array along the X-axis and Z-axis directions; wherein the bit line structure 17 and the capacitor structure 18 are each connected to a T-type gate structure 16.

[0123] In this embodiment, a T-gate structure 16 and a capacitor structure 18 constitute a memory cell; adjacent memory cells along the X-axis have the same layout (e.g., Figure 5a , 5c (as shown in 5d), or, adjacent memory cells along the X-axis are axially symmetric (e.g., as shown in 5d). Figure 5b (As shown).

[0124] In some embodiments, please continue to refer to 5a-5d, the semiconductor structure 100 further includes word line steps 19 extending along the X-axis direction, wherein each word line in the word line steps 19 is electrically connected to a plurality of T-type gate structures 16 arranged along the X-axis direction.

[0125] In this embodiment of the disclosure, each layer of character lines in the character line step 19 can be rectangular (e.g., ...). Figures 5a-5c As shown), it can also be serrated (as shown). Figure 5d (As shown).

[0126] This disclosure also provides a layout structure. Figure 6a and 6b This is a planar layout diagram of the layout structure provided in an embodiment of the present disclosure. The layout structure 200 includes the aforementioned semiconductor structures 100 arranged at intervals along the Y-axis direction.

[0127] like Figure 6a and 6b As shown, the semiconductor structure 100 includes memory cells arranged in an array along the X-axis and Z-axis directions; each memory cell includes a T-gate structure 16 and a capacitor structure 18; wherein, two adjacent memory cells in the Y-axis direction are centrally symmetrical, and the projection areas of the capacitor structures 18 of two adjacent memory cells in the Y-axis direction at least partially overlap in the X-axis direction.

[0128] In some embodiments, please continue to see Figure 6a and 6b The semiconductor structure 100 also includes a bit line structure 17 and a word line step 19.

[0129] In some embodiments, please continue to see Figure 6a The layout of two adjacent storage cells in the X-axis direction is the same.

[0130] In some embodiments, please continue to see Figure 6b The layout of two adjacent storage cells along the X-axis is axially symmetrical.

[0131] The layout structure provided in this disclosure can effectively utilize the space in the semiconductor structure to achieve miniaturization of the semiconductor structure.

[0132] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0133] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0134] The above descriptions are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided; the substrate includes a first region and a second region arranged sequentially along a second direction, and T-shaped active pillars arranged in an array along the first direction and a third direction in the first region and the second region; the first direction, the second direction and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the substrate; A T-shaped gate structure and a bit line structure extending along the third direction are formed in the first region on the surface of the T-shaped active pillar; wherein, a plurality of the T-shaped gate structures located in the first direction are interconnected. A capacitor structure extending along the second direction is formed in the second region, and both the bit line structure and the capacitor structure are connected to the T-type gate structure.

2. The method according to claim 1, characterized in that, The T-shaped active pillar located in the first region includes a first active pillar and a second active pillar extending along a second direction, and a third active pillar and a fourth active pillar extending along the first direction, wherein the first active pillar is connected to the third active pillar; a T-shaped gate structure and a bit line structure are formed on the surface of the T-shaped active pillar in the first region, including: The T-shaped gate structure is formed on the surface of the first active pillar and the third active pillar; The bit line structure extending along the third direction is formed at the end of the fourth active post away from the third active post.

3. The method according to claim 2, characterized in that, The T-shaped active post is formed through the following steps: Provide semiconductor substrates; A stacked structure located in the first region and the second region is formed on the surface of the semiconductor substrate; the stacked structure includes a first semiconductor layer and a second semiconductor layer alternately stacked along a third direction; Remove the first semiconductor layer in the first region to expose the second semiconductor layer in the first region; The exposed second semiconductor layer is thinned to form an initial active layer; The initial active layer is processed to form the T-shaped active pillar.

4. The method according to claim 3, characterized in that, The process of processing the initial active layer to form the T-shaped active pillar includes: A first sacrificial layer and a first support layer are sequentially formed on the surface of the initial active layer; wherein the first support layer fills the spaces between the first sacrificial layers; A portion of the first support layer, a portion of the first sacrificial layer, a portion of the initial active layer, and a portion of the stacked structure in the second region are removed from the first region to form a plurality of concave trenches spaced apart along the first direction. A portion of the initial active layer in the second direction is removed to form a first space, and the remaining initial active layer constitutes the T-shaped active column.

5. The method according to claim 4, characterized in that, After forming the concave groove, the method further includes: An insulating material is filled into the concave groove to form an insulating layer.

6. The method according to claim 5, characterized in that, The first active post, the second active post, the third active post, and the fourth active post are formed through the following steps: A portion of the first sacrificial layer in the first direction and the second direction is removed to expose a portion of the initial active layer, forming a second space; wherein, the portions of the exposed initial active layer extending along the first direction and the second direction respectively constitute the first active pillar and the third active pillar; the portions of the unexposed initial active layer extending along the first direction and the second direction respectively constitute the second active pillar and the fourth active pillar; the second space includes the first space.

7. The method according to claim 6, characterized in that, The T-shaped gate structure is formed on the surfaces of the first active pillar and the third active pillar, including: A gate dielectric layer and a gate conductive layer are sequentially formed on the surfaces of the first active pillar and the third active pillar to form the T-type gate structure; wherein the gate conductive layer fills the second space.

8. The method according to claim 6, characterized in that, A bitline structure extending in the third direction is formed at the end of the fourth active post away from the third active post, including: A portion of the first sacrificial layer and a portion of the isolation layer on the sidewall of the fourth active post are removed to form a bit line trench; wherein, the bit line trench exposes the end of the fourth active post away from the third active post, and a portion of the isolation layer is retained between two adjacent T-shaped active posts in the first direction; The bit line structure is formed by filling the bit line trench with bit line metal material.

9. The method according to any one of claims 4 to 8, characterized in that, The second region includes a fifth active post extending along the second direction; the fifth active post is formed by the following steps: Remove the first semiconductor layer and the isolation layer located in the second region from the remaining stacked structure in the second region to expose the second semiconductor layer; The exposed second semiconductor layer is thinned to form the fifth active pillar, which is connected to the second active pillar.

10. The method according to claim 9, characterized in that, The fifth active pillar includes a first sub-pillar, a second sub-pillar, and a third sub-pillar arranged sequentially along the second direction; a capacitor structure is formed in the second region, including: A second support layer is formed on the surface of the first sub-pillar; wherein the second support layer fills the spaces between the first sub-pillars; the first support layer and the second support layer constitute the support structure of the semiconductor structure; A second sacrificial layer is formed on the surface of the second sub-pillar; wherein the second sacrificial layer fills the spaces between the second sub-pillars; A third semiconductor layer is formed on the surface of the third sub-pillar; A first electrode layer is formed on the surface of the third semiconductor layer and on the sidewall of the second sacrificial layer; A protective layer is formed on the surface of the first electrode layer and in the gaps between the first electrode layers; Remove the second sacrificial layer and the first electrode layer located on the sidewall of the second sub-pillar to expose the sidewall of the second sub-pillar and the second support layer; Remove the protective layer to expose the remaining first electrode layer; A dielectric layer is formed on the surface of the second sub-pillar and the first electrode layer; A second electrode layer is formed on the sidewall of the second support layer and the surface of the dielectric layer, and the first electrode layer, the dielectric layer and the second electrode layer constitute the capacitor structure.

11. The method according to claim 10, characterized in that, The etching selectivity between the second sacrificial layer and the second subpillar is greater than that between the protective layer and the second subpillar.

12. The method according to claim 10 or 11, characterized in that, The method further includes: A conductive layer is formed on the surface of the second electrode layer, and the conductive layer fills the space between adjacent third sub-pillars.

13. The method according to claim 12, characterized in that, After forming the T-type gate structure, the method for forming the semiconductor structure further includes: Forming word line steps stacked sequentially along the third direction; Each word line in the word line step is electrically connected to a plurality of T-shaped gate structures arranged along the first direction.

14. A semiconductor structure, characterized in that, The semiconductor structure includes at least: A semiconductor substrate and T-shaped active pillars located on the surface of the semiconductor substrate; the T-shaped active pillars are arranged in an array along a first direction and a third direction; A T-shaped gate structure and a bit line structure are located on the surface of a portion of the T-shaped active pillars; wherein, a plurality of the T-shaped gate structures in the first direction are interconnected; the bit line structure extends along the third direction; A capacitor structure extending along a second direction; both the bit line structure and the capacitor structure are connected to the T-type gate structure; the first direction, the second direction, and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate.

15. The semiconductor structure according to claim 14, characterized in that, The semiconductor substrate includes a first region and a second region arranged sequentially along a second direction; The T-shaped active post includes a first active post and a second active post located in the first region and extending along the second direction, and a third active post and a fourth active post located in the first region and extending along the first direction; wherein the first active post is connected to the third active post; the bit line structure is formed on a portion of the fourth active post.

16. The semiconductor structure according to claim 15, characterized in that, The projections of the first active pillar and the third active pillar onto the surface of the semiconductor substrate are T-shaped.

17. The semiconductor structure according to claim 16, characterized in that, The T-shaped active column also includes a fifth active column located in the second region; The capacitor structure is formed on a portion of the fifth active pillar.

18. The semiconductor structure according to claim 17, characterized in that, The adjacent T-shaped active posts along the first direction have concave grooves.

19. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure further includes: a support structure; The support structure includes a first support layer and a second support layer; wherein the first support layer is located on the surface of a portion of the second active pillar between the bit line structure and the T-type gate structure; and the second support layer is located on the surface of a portion of the fifth active pillar between the capacitor structure and the T-type gate structure.

20. The semiconductor structure according to any one of claims 14 to 19, characterized in that, The semiconductor structure further includes: word line steps; The word line steps are stacked sequentially along the third direction, and each layer of word lines in the word line steps is electrically connected to a plurality of T-shaped gate structures arranged along the first direction.

21. A layout structure, characterized in that, include: Semiconductor structures as described in any one of claims 14 to 20 are arranged sequentially at intervals along a second direction; The semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; each memory cell includes a T-gate structure and a capacitor structure. Wherein, two adjacent memory cells in the second direction are centrally symmetrical, and the capacitor structures of two adjacent memory cells in the second direction at least partially overlap in the projection area in the first direction.

22. The layout structure according to claim 21, characterized in that, The two adjacent storage cells in the first direction have the same layout or are axially symmetrical.

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