Semiconductor structure and its formation method, layout structure

Abstract

This disclosure provides a semiconductor structure and its formation method and layout structure. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region arranged sequentially along a second direction; the second region including active structures arranged in an array along a first direction and a third direction, the active structures including at least a channel structure; the first direction, the second direction and the third direction being mutually perpendicular, and the first direction and the second direction being parallel to the surface of the semiconductor substrate; forming a gate structure on the surface of the channel structure; forming a word line structure extending along the first direction on the first region; wherein the word line structure is connected to the gate structure located on the same layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and its formation method and layout structure. Background Technology

[0002] 3D Dynamic Random Access Memory (3D DRAM) often employs a horizontal word line structure; however, the manufacturing process for horizontal word line structures is highly complex. Furthermore, because word line transistors are very sensitive to device functionality, current 3D DRAM processes struggle to control the length and width of the gate. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, as well as a layout structure.

[0004] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region arranged sequentially along a second direction; the second region includes active structures arranged in an array along the first direction and a third direction, the active structures including at least a channel structure; the first direction, the second direction and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate; A gate structure is formed on the surface of the channel structure; A word line structure extending along the first direction is formed on the first region; wherein the word line structure is connected to the gate structure located on the same layer.

[0005] In some embodiments, the projection of the channel structure onto the surface of the semiconductor substrate is U-shaped or rectangular.

[0006] In some embodiments, the active structure further includes an active post; the active post and the channel structure are arranged sequentially along the second direction, and the channel structure connects the active post; the method further includes: A capacitor structure and a bit line structure are formed on the end face of the active pillar; The capacitor structure extends along the second direction, and the bit line structure extends along the third direction.

[0007] In some embodiments, the channel structure is formed by the following steps: A stacked structure is formed on the surface of the semiconductor substrate; the stacked structure includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a third direction; The stacked structure and a portion of the semiconductor substrate are etched to form a first isolation groove and a second isolation groove that extend along the second direction in the second region and are alternately spaced, and an etching trench that extends along the first direction in the first region; wherein the size of the first isolation groove in the second direction is smaller than the size of the second isolation groove in the second direction, and the second isolation groove communicates with the etching trench; The remaining stacked structure in the second region is processed to form the channel structure.

[0008] In some embodiments, the remaining stacked structure in the second region includes a first portion located on both sides of the first isolation groove along the first direction, and a second portion connected to the first portion along the second direction; processing the remaining stacked structure in the second region to form the channel structure includes: A first isolation layer is formed in the first isolation groove, the second isolation groove, and the etched trench; the surface of the first isolation layer is flush with the surface of the stacked structure. A first mask layer with a preset pattern is formed on the surface of the stacked structure and the first isolation layer; wherein the preset pattern exposes a portion of the first isolation layer located in the etched trench and a portion of the stacked structure that exposes the second portion, and the first mask layer is flush with both sides of the first isolation groove in the second direction; The first mask layer is used to remove the exposed portion of the first isolation layer and the exposed portion of the first semiconductor layer to form a gate trench; the remaining second semiconductor layer in the exposed portion constitutes the channel structure.

[0009] In some embodiments, the word line structure and the gate structure are formed by the following steps: A gate dielectric layer and a gate conductive layer covering the channel structure are sequentially formed on the inner wall of the gate trench to form an initial gate structure; A second isolation layer is formed in a gate trench having the gate dielectric layer and the gate conductive layer; the surface of the second isolation layer is flush with the surface of the stacked structure. Remove the remaining first isolation layer in the etched trench, as well as the gate dielectric layer and gate conductive layer located on the sidewall of the second isolation layer in the gate trench, to expose part of the etched trench; A third isolation layer is formed in the exposed etched trenches; The stacked structure of the first region, as well as the second and third isolation layers in the etched trenches, are processed to form the word line structure; The initial gate structure is processed to form the gate structure.

[0010] In some embodiments, processing the stacked structure of the first region, and the second and third isolation layers in the etched trenches to form the word line structure includes: Remove the second semiconductor layer in the first region, as well as the third and second isolation layers located in the projection region of the second semiconductor layer along the second direction, to form a word line trench; The character line structure is formed by filling the character line groove with character line metal material.

[0011] In some embodiments, after forming the word line structure, the method further includes: Remove the first semiconductor layer in the first region to form a third isolation groove; A fourth isolation layer is formed in the third isolation groove.

[0012] In some embodiments, processing the initial gate structure to form the gate structure includes: A second mask layer with a serrated pattern is formed on the surface of the word line structure and the initial gate structure; wherein the serrated pattern includes convex patterns and concave patterns arranged alternately along the first direction; the concave pattern exposes a portion of the initial gate structure; The exposed initial gate structure is removed through the second mask layer, forming the gate structure and the first space.

[0013] In some embodiments, the method further includes: The active pillar is formed simultaneously with the formation of the gate structure.

[0014] In some embodiments, the active post is formed by the following steps: The second semiconductor layer of the first portion and the first isolation layer located in the first portion are removed to form a second space, and a first sub-pillar and a second sub-pillar arranged alternately along the first direction; The first sub-pillar and the second sub-pillar constitute the active pillar; the second space includes the first space.

[0015] In some embodiments, the method further includes: A fifth isolation layer is formed in the second space.

[0016] In some embodiments, a capacitor structure and a bit line structure are formed on the surface of the active pillar, including: The capacitor structure is formed on the end face of the first sub-pillar away from the word line structure; The bit line structure is formed on the end face of the second sub-pillar away from the word line structure.

[0017] In a second aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged sequentially along a second direction; An active structure located on the second region and arranged in an array along a first direction and a third direction, the active structure including at least a channel structure; the first direction, the second direction and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate; The character line structure located in the first region and extending along the first direction; A gate structure located on the surface of the channel structure, wherein the word line structure is connected to the gate structure located on the same layer.

[0018] In some embodiments, the projection of the channel structure onto the surface of the semiconductor substrate is U-shaped, rectangular, L-shaped, or convex.

[0019] In some embodiments, the gate structure covers a first and second surface of the channel structure along the third direction, a third and a fourth surface of the channel structure along the first direction, and a fifth surface of the channel structure along the second direction, and the word line structure is connected to the gate structure located on the fifth surface; The gate structure includes a gate dielectric layer and a gate conductive layer stacked together.

[0020] In some embodiments, the semiconductor structure further includes a capacitor structure and a bit line structure located in the second region; The capacitor structure extends along the second direction, and the bit line structure extends along the third direction.

[0021] In some embodiments, the active structure further includes an active post; the active post and the channel structure are arranged sequentially along the second direction; the active post includes a first sub-post and a second sub-post; The capacitor structure is formed on the end face of the first sub-pillar; the bit line structure is formed on the end face of the second sub-pillar.

[0022] In some embodiments, a first isolation groove is provided between the first sub-post and the second sub-post of the same active post; and a second isolation groove is provided between adjacent active posts along the first direction; Wherein, the dimension of the second isolation groove in the second direction is greater than or equal to the dimension of the first isolation groove in the second direction.

[0023] Thirdly, embodiments of this disclosure provide a layout structure, including: the aforementioned semiconductor structures arranged at intervals along a second direction; The semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; each memory cell includes a gate structure and a capacitor structure. Wherein, two adjacent memory cells in the second direction are centrally symmetrical, and the capacitor structures of two adjacent memory cells in the second direction at least partially overlap in the projection area in the first direction.

[0024] In some embodiments, the projection of the gate structure onto the third direction is U-shaped, rectangular, L-shaped, or convex.

[0025] In some embodiments, two adjacent storage cells in the first direction have the same layout or are axially symmetrical.

[0026] The semiconductor structure formation method provided in this disclosure can control the length and width of the gate, and the formed word line structure is horizontal. The horizontal word line structure can be directly filled and formed, which reduces the complexity of the fabrication process of the horizontal word line structure, thereby reducing the manufacturing cost of the semiconductor structure. Attached Figure Description

[0027] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0028] Figure 1 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure; Figures 2a-2l , Figures 3a-3k This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure; Figures 4a-4c This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure; Figures 5a-5f This is a schematic diagram of a planar structure of a semiconductor structure provided in an embodiment of the present disclosure; Figure 6a and 6b A plan layout diagram of the layout structure provided in the embodiments of this disclosure; The annotations in the attached figures are explained as follows: 10—Semiconductor substrate; 11—Stacked structure; 111—First semiconductor layer; 112—Second semiconductor layer; 12—First isolation trench; 13—Second isolation trench; 14—Etched trench; 15—First isolation layer; 161—First mask layer; 162—Second mask layer; 17—Gate trench; 18 / 18a—Channel structure; 171—Gate dielectric layer; 172—Gate conductive layer; 19—Second isolation layer; 20—Third isolation layer; 21—Word line trench; 22—Word line structure; 23—Third isolation trench; 24—Fourth isolation layer; 25—Active pillar; 251—First sub-pillar Column; 252—Second sub-column; 26—Fourth isolation layer; 27—Capacitor structure; 271—First electrode layer; 272—Dielectric layer; 273—Second electrode layer; 28—Bit line structure; 29—Initial gate structure; 30—Gate structure; 311—First contact structure; 312—Second contact structure; 100—Semiconductor structure; 200—Layout structure; A—First region; B—Second region; B-1—First part; B-2—Second part; I—Zigzag pattern; G—Convex pattern; H—Concave pattern; c—First space; d—Second space; E—Preset pattern; F—Rounded corner. Detailed Implementation

[0029] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0030] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0031] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. The semiconductor substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the third direction. In the direction of the top and bottom surfaces of the semiconductor substrate (i.e., the plane in which the semiconductor substrate lies), two intersecting (e.g., perpendicular) directions are defined. For example, the direction of word line extension can be defined as the first direction, and the direction of capacitor structure extension can be defined as the second direction. Based on the first and second directions, the planar orientation of the semiconductor substrate can be determined. Here, the first direction, the second direction, and the third direction are mutually perpendicular. In the embodiments of this disclosure, the first direction is defined as the X-axis, the second direction as the Y-axis, and the third direction as the Z-axis.

[0035] This disclosure provides a method for forming a semiconductor structure. Figure 1 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming a semiconductor structure includes the following steps: Step S101: Provide a semiconductor substrate, the semiconductor substrate including a first region and a second region arranged sequentially along a second direction; the second region includes active structures arranged in an array along the first direction and a third direction, the active structures including at least a channel structure.

[0036] In this embodiment of the disclosure, the semiconductor substrate may be a silicon substrate, or it may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0037] In this embodiment of the disclosure, the first region and the second region can be used to form different functional structures, for example, the first region can be used to form a word line structure, and the second region can be used to form a gate structure, a capacitor structure, and a bit line structure.

[0038] In this embodiment of the disclosure, the active structure includes at least a channel structure. In other embodiments, the active structure also includes an active post. The active post and the channel structure are arranged sequentially along a second direction, and the channel structure is connected to the active post.

[0039] In this embodiment of the disclosure, the cross-section of the active column along a third direction can be circular, square, or any polygonal.

[0040] In this embodiment of the disclosure, the projection of the channel structure onto the surface of the semiconductor substrate is U-shaped or rectangular.

[0041] In other embodiments, the projection of the channel structure onto the surface of the semiconductor substrate can also be convex or L-shaped.

[0042] Step S102: Form a gate structure on the surface of the channel structure.

[0043] In this embodiment of the disclosure, the gate structure includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer; the gate structure may be a five-sided ring gate structure, for example, the gate structure covers the first and second surfaces of the channel structure along the third direction, covers the third and fourth surfaces of the channel structure along the first direction, and covers the fifth surface of the channel structure along the second direction.

[0044] Step S103: Form a word line structure extending in a first direction on the first region; wherein the word line structure is connected to the gate structure located on the same layer.

[0045] In this embodiment of the disclosure, the word line structure extends along a first direction, that is, the word line structure is horizontal. This not only enables the interconnection of word lines on the same plane in a multi-layer stacked structure, but also enables the control of the size of the word lines, thereby reducing the coupling effect between word line steps.

[0046] The semiconductor structure formation method provided in this disclosure can control the length and width of the gate, and the formed word line structure is horizontal. The horizontal word line structure can be directly filled and formed, which reduces the complexity of the fabrication process of the horizontal word line structure, thereby reducing the manufacturing cost of the semiconductor structure.

[0047] Figures 2a-2l , Figures 3a-3k This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 2a-2l , Figures 3a-3k The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0048] First, you can refer to Figures 2a-2g In step S101, a semiconductor substrate 10 is provided. The semiconductor substrate 10 includes a first region A and a second region B arranged sequentially along the Y-axis direction. The second region B includes active structures arranged in an array along the X-axis and Z-axis directions, and the active structures include at least a channel structure 18. Figure 2a For 3D views, Figures 2b-2g This is a top view or a cross-sectional view along a-a' of the semiconductor structure formation process.

[0049] In some embodiments, the channel structure 18 can be formed by the following steps: forming a stacked structure 11 on the surface of a semiconductor substrate 10; the stacked structure 11 includes a first semiconductor layer 111 and a second semiconductor layer 112 alternately stacked along a third direction; etching the stacked structure 11 and a portion of the semiconductor substrate 10 to form a first isolation groove 12 and a second isolation groove 13 located in the second region B and extending along a second direction and arranged alternately, and an etching trench 14 located in the first region A and extending along a first direction; processing the remaining stacked structure 11 in the second region B to form the channel structure 18.

[0050] like Figure 2a and 2b As shown, a stacked structure 11 located in a first region A and a second region B is formed on the surface of a semiconductor substrate 10; the stacked structure 11 includes a first semiconductor layer 111 and a second semiconductor layer 112 that are alternately stacked along the Y-axis direction.

[0051] In this embodiment, the material of the first semiconductor layer 111 may be germanium (Ge), silicon germanide (SiGe), or silicon carbide; it may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI). The second semiconductor layer 112 may be a silicon layer, or may include other semiconductor elements, such as germanium, or include semiconductor compounds, such as silicon carbide, gallium arsenide, gallium indium phosphide, indium arsenide, or indium antimonide, or include other semiconductor alloys, such as silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide or combinations thereof.

[0052] In this embodiment, the first semiconductor layer 111 and the second semiconductor layer 112 are made of different materials because the first semiconductor layer 111 in the stacked structure 11 needs to be removed subsequently, while the second semiconductor layer 112 is retained. Therefore, the first semiconductor layer 111 has a larger selective etching ratio than the second semiconductor layer 112. For example, the etching selectivity ratio of the first semiconductor layer 111 to the second semiconductor layer 112 can be 5 to 15, making it easier for the first semiconductor layer 111 to be etched away than the second semiconductor layer 112 during the etching process.

[0053] In this embodiment of the disclosure, the number of the first semiconductor layer 111 and the second semiconductor layer 112 in the stacked structure 11 can be set according to the required capacitance density (or storage density). The more layers the first semiconductor layer 111 and the second semiconductor layer 112 have, the higher the integration of the semiconductor structure and the greater the capacitance density.

[0054] In this embodiment of the present disclosure, the first semiconductor layer 111 and the second semiconductor layer 112 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, spin coating process, coating process, or thin film process, etc.; for example, the first semiconductor layer 111 and the second semiconductor layer 112 can be sequentially formed on the semiconductor substrate 10 by an epitaxial process.

[0055] like Figure 2cAs shown, the etched stacked structure 11 and a portion of the semiconductor substrate 10 form a first isolation groove 12 and a second isolation groove 13 located in the second region B, extending along the Y-axis and arranged alternately, and an etch trench 14 located in the first region A, extending along the X-axis. The first isolation groove 12, the second isolation groove 13, and the etch trench 14 all expose the semiconductor substrate 10. The dimension L1 of the first isolation groove 12 in the Y-axis direction is smaller than the dimension L2 of the second isolation groove 13 in the Y-axis direction, and the second isolation groove 13 is connected to the etch trench 14.

[0056] In this embodiment of the disclosure, the remaining stacked structure 11 in the second region is defined as a first part B-1 and a second part B-2; wherein, the first part B-1 is located on both sides of the first isolation groove 12 along the first direction, and the second part B-2 is connected to the first part B-1 along the second direction.

[0057] In this embodiment of the disclosure, the first isolation groove 12 can be rectangular.

[0058] In other embodiments, the first isolation groove 12 may also be L-shaped.

[0059] In this embodiment of the disclosure, the stacked structure 11 and part of the semiconductor substrate 10 can be etched by wet etching process (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) or dry etching process (e.g., plasma etching process, reactive ion etching process, or ion milling process).

[0060] like Figure 2d~2g As shown, processing the remaining stacked structure 11 in the second region B to form the channel structure 18 may include the following steps: forming a first isolation layer 15 in the first isolation groove 12, the second isolation groove 13, and the etching trench 14; the surface of the first isolation layer 15 is flush with the surface of the stacked structure 11; forming a first mask layer 161 with a preset pattern E on the surfaces of the stacked structure 11 and the first isolation layer 15; wherein the preset pattern E exposes a portion of the first isolation layer 15 located in the etching trench and exposes a portion of the stacked structure 11 in the second region B-2, and is located in The first mask layer 161 of the second region B (first part B-1 and second part B-2) is flush with both sides of the first isolation groove in the second direction. The projection of the first mask layer 161 in the first region A along the Z-axis direction coincides with the projection of the etching trench along the Z-axis direction. Through the first mask layer 161, the exposed portion of the first isolation layer 15 and the exposed first semiconductor layer 111 in the second part B-2 are removed to form a gate trench 17. The remaining second semiconductor layer 112 in the exposed second part B-2 constitutes the channel structure 18.

[0061] like Figure 2dAs shown, a first isolation material is filled into the first isolation groove, the second isolation groove, and the etched trench to form a first isolation layer 15. The surface of the first isolation layer 15 is flush with the surface of the stacked structure 11. The first isolation material can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0062] like Figure 2e As shown, a first mask layer 161 with a preset pattern E is formed on the surface of the stacked structure 11 and the first isolation layer 15; the preset pattern E exposes the first isolation layer 15 located in the etched trench and exposes the stacked structure 11 in the second part B-2, and the first mask layer 161 is flush with both sides of the first isolation groove in the Y-axis direction.

[0063] In this embodiment of the disclosure, the material used for the first mask layer 161 may be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the first mask layer 161 may be formed by any suitable deposition process.

[0064] like Figure 2f As shown, the first isolation layer 15 exposed in the first part A and the first semiconductor layer 111 in the second part B-2 are removed sequentially through the first mask layer 161 to form a gate trench 17; the remaining second semiconductor layer 112 in the second part B-2 constitutes the channel structure 18a.

[0065] In this embodiment of the present disclosure, a dry etching process or a wet etching process can be used to remove the exposed portion of the first isolation layer 15 and the first semiconductor layer 111 in the second portion B-2. The gas used for dry etching can be one or any combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6).

[0066] In some embodiments, the method for forming a semiconductor structure further includes thinning the channel structure 18a. The thinned structure can also serve as the channel structure 18 in the embodiments of this disclosure (e.g., Figure 2g (as shown); for example, the channel structure 18a can be thinned in the following two ways: Method 1: Dry etching is performed directly on the channel structure 18a until the required thickness is achieved, at which point the etching is stopped.

[0067] Method 2: In-situ oxidation of the channel structure 18a, partially oxidizing the channel structure 18a into a silicon oxide layer, and removing the silicon oxide layer by wet etching or dry etching techniques.

[0068] It should be noted that during the thinning process of the channel structure 18a, the junction between the channel structure 18a and the first part B-1 has a rounded corner F. In Method 1, the rounded corner F is formed due to incomplete removal of residues during the thinning process. In Method 2, the rounded corner F is formed because, during the oxidation of the channel structure 18a, the oxidation rates of different silicon phases are different, and during the removal of the silicon oxide layer, the rounded corner is located at the innermost part, resulting in uneven etching of the internal silicon oxide by the etching gas flow.

[0069] In this embodiment of the disclosure, by thinning the channel structure, a channel structure formed by a fully depleted semiconductor layer can be formed. At this time, holes are easily recombinated in the source region without accumulation, thus improving the floating body effect. In addition, since the gap between two adjacent channel structures becomes larger, more space can be reserved for the subsequent formation of the gate structure, reducing the complexity of the gate structure fabrication process and the manufacturing cost.

[0070] It should be noted that in other embodiments, the channel structure 18a may not be thinned.

[0071] Next reference Figure 2h~2l Steps S102 and S103 are executed to form a gate structure 30 on the surface of the channel structure 18; a word line structure 22 extending along the X-axis is formed on the first region A; wherein the word line structure 22 is connected to the gate structure 30 located on the same layer.

[0072] In this embodiment of the present disclosure, the gate structure 30 can be formed by the following steps: a gate dielectric layer 171 and a gate conductive layer 172 covering the channel structure 18 are sequentially formed on the inner wall of the gate trench 17 to form an initial gate structure 29; a second isolation layer 19 is formed in the gate trench 17 having the gate dielectric layer 171 and the gate conductive layer 172; the surface of the second isolation layer 19 is flush with the surface of the stacked structure 11; the remaining first isolation layer 15 in the etching trench 14, as well as the gate dielectric layer 171 and the gate conductive layer 172 located on the sidewall of the second isolation layer 19 in the gate trench 17, are removed to expose part of the etching trench 14; a third isolation layer 20 is formed in the exposed etching trench 14; the stacked structure 11 of the first region A, as well as the second isolation layer 19 and the third isolation layer 20 in the etching trench 14, are processed to form a word line structure 22; and the initial gate structure 29 is processed to form the gate structure 30.

[0073] like Figure 2h and 2i As shown, a gate dielectric material and a gate conductive material are sequentially deposited on the inner wall of the gate trench 17 to form a gate dielectric layer 171 and a gate conductive layer 172 covering the channel structure 18, thereby forming an initial gate structure 29.

[0074] In this embodiment of the disclosure, the gate dielectric material may be silicon oxide or other suitable materials; the gate conductive material may include one or any combination of polysilicon, metals (e.g., tungsten, copper, aluminum, titanium, tantalum, ruthenium, etc.), metal alloys, metal silicides, titanium nitride, etc.

[0075] In this embodiment of the present disclosure, the gate dielectric layer 171 and the gate conductive layer 172 can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0076] It is worth noting that during the formation of the initial gate, not only are gate dielectric material and gate conductive material deposited on the inner wall of the gate trench 17, but also on the sidewall of the first isolation layer 15 and the surface of the first mask layer 161.

[0077] like Figure 2j As shown, a second isolation material is filled in the gate trench having a gate dielectric layer 171 and a gate conductive layer 172 to form a second isolation layer 19; the surface of the second isolation layer 19 is flush with the surface of the stacked structure 11.

[0078] In this embodiment, the second insulating material can be a low dielectric constant (Low K) material, such as SiCON. Using a Low K material as the insulating material provides better insulation performance, thus reducing gate leakage in the current leakage path and improving the performance of the semiconductor structure.

[0079] In this embodiment of the disclosure, after forming the second isolation layer 19, the method for forming the semiconductor structure further includes: removing the first mask layer 161, and the gate dielectric material and gate conductive material located on the surface and sidewalls of the first mask layer 161.

[0080] like Figure 2k As shown, the remaining first isolation layer in the etching trench 14, as well as the gate dielectric layer and gate conductive layer located on the sidewall of the first isolation layer in the gate trench, can be removed sequentially by wet etching or dry etching process, exposing part of the etching trench 14.

[0081] like Figure 2l As shown, a third isolation material is deposited in the exposed etched trenches to form a third isolation layer 20. In this embodiment, the third isolation material may be a low dielectric constant material, such as SiCON.

[0082] Using Low K material as the insulating material provides good insulation performance, which can reduce crosstalk between subsequent word line structures and thus improve the performance of the semiconductor structure.

[0083] In some embodiments, processing the stacked structure 11 of the first region A and the second isolation layer 19 and the third isolation layer 20 in the etched trench 14 to form a word line structure 22 may include the following steps: sequentially removing the second semiconductor layer 112 in the first region A, and the third isolation layer 20 and the second isolation layer 19 located in the projection region of the second semiconductor layer 112 along the second direction to form a word line trench; filling the word line trench 21 with word line metal material to form a word line structure 22.

[0084] like Figure 3a As shown, a self-aligned process is used to remove the second semiconductor layer 112 in the first region A to form a self-aligned opening. Then, using the remaining first semiconductor layer 111 in the first region A as a mask, the third isolation layer 20 located in the projection area of ​​the second semiconductor layer 112 along the Y-axis direction and located in the first region A, and the second isolation layer 19 located in the projection area of ​​the second semiconductor layer 112 along the Y-axis direction and located in the first region A are removed to form a word line trench 21.

[0085] In this embodiment of the disclosure, the number of photomasks used in the formation of word line trench 21 can be reduced by self-aligned lateral etching, thereby reducing the manufacturing cost and process complexity of the word line structure, and thus reducing the manufacturing cost and process complexity of the final semiconductor structure.

[0086] like Figure 3b As shown, word line metal material is filled into the word line trench 21 to form word line structure 22. The word line metal material can be cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), platinum (Pt), palladium (Pd), or any other suitable conductive metal material. The word line structure 22 can be formed by any suitable deposition process.

[0087] In this embodiment, the formed word line structure is horizontal, and the horizontal word line structure can be directly filled to form, reducing the complexity of the fabrication process of the horizontal word line structure and thus reducing the manufacturing cost of the semiconductor structure. In addition, the word line structure formed by the side-connection method not only realizes the interconnection of word line structures on the same plane in the multi-layer stacked structure, but also allows control of the size of the side-connected word lines, thereby realizing the control of word line coupling by controlling the size of the side-connected word lines.

[0088] In some embodiments, such as Figure 3c and 3d As shown, after forming the word line structure 22, the method further includes: removing the first semiconductor layer 111 of the first region A to form a third isolation groove 23; and filling the third isolation groove 23 with a fourth isolation material to form a fourth isolation layer 26.

[0089] In this embodiment of the disclosure, the fourth isolation material can be a low dielectric constant material, such as SiCON, and the fourth isolation layer 26 can be formed by any suitable deposition process.

[0090] In this embodiment of the disclosure, the first isolation material, the second isolation material, the third isolation material and the fourth isolation material can all be the same or any two of them can be the same, or they can all be different.

[0091] In some embodiments, processing the initial gate structure 29 to form the gate structure 30 includes the following steps: forming a second mask layer 162 with a serrated pattern on the surface of the word line structure 22 and the initial gate structure 29; removing the exposed initial gate structure 29 through the second mask layer 162 to form the gate structure 30 and the first space c.

[0092] like Figures 3e~3h As shown, a second mask layer 162 with a serrated pattern is formed on the surfaces of the word line structure 22 and the initial gate structure 29. Through the second mask layer 162, the exposed initial gate structure 29 is removed, forming the gate structure 30 and the first space c. Figure 3f A three-dimensional view of the formed gate structure 30.

[0093] In this embodiment, the second mask layer 162 has a sawtooth pattern, wherein the sawtooth pattern I includes convex patterns G and concave patterns H arranged alternately along the X-axis direction; the concave pattern H exposes a portion of the initial gate structure 29. The exposed initial gate structure 29 is removed through the second mask layer 162, forming a structure as shown below. Figure 3f The gate structure 30 is shown. In this embodiment, the gate structure 30 is a five-sided ring gate structure. The gate structure 30 covers the first and second surfaces of the channel structure 18 along the Z-axis, the third and fourth surfaces of the channel structure 18 along the X-axis, and the fifth surface of the channel structure 18 along the Y-axis. The word line structure 22 is connected to the gate structure 30 located on the fifth surface, and the sixth surface of the channel structure 18 along the Y-axis is used to connect to the active pillar and is electrically connected to the bit line structure and the capacitor structure.

[0094] In this embodiment of the disclosure, the material used for the second mask layer 162 can be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride, and the second mask layer 162 can be formed by any suitable deposition process.

[0095] In some embodiments, an active pillar 25 is formed concurrently with the formation of the gate structure 30.

[0096] Please continue to refer to 3g~3h, remove the second semiconductor layer 112 of the first part B-1, and remove the first isolation layer 15 located in the first part B-1 to form the second space d, and the first sub-pillar 251 and the second sub-pillar 252 arranged alternately along the X-axis direction; wherein, the first sub-pillar 251 and the second sub-pillar 252 constitute the active pillar 25; the second space d includes the first space c.

[0097] In this embodiment, the length L3 of the first sub-post 251 along the Y-axis is greater than the length L4 of the second sub-post 252 along the Y-axis, and the second sub-post 252 and the first sub-post 251 are arranged alternately in the first direction. In other embodiments, the lengths of the first sub-post 251 and the second sub-post 252 may also be equal.

[0098] In this embodiment, a dry etching process or a wet etching process can be used to remove the exposed initial gate structure 29 and the first isolation layer 15 located in the first portion B-1 to form the gate structure 30, the first sub-pillar 251, and the second sub-pillar 252. The gas used in the dry etching process can be one or any combination of trifluoromethane, carbon tetrafluoride, difluoromethane, hydrobromic acid, chlorine, or sulfur hexafluoride.

[0099] In this embodiment of the disclosure, since the sawtooth pattern of the second mask layer includes convex and concave patterns arranged alternately along the first direction, the formed gate structure 30 is U-shaped, such as... Figure 3f As shown.

[0100] In other embodiments, when the size of the concave pattern in the second direction of the sawtooth pattern of the second mask layer is reduced to 0, that is, when the second mask layer does not have a sawtooth pattern, a gate structure with a rectangular projection in the Z-axis direction can also be formed.

[0101] The gate structure 30 provided in this embodiment can be a five-sided gate structure. The five-sided gate structure has a large channel region. On the one hand, it can enhance the gate control capability, thereby further reducing the size of the gate structure and overcoming the physical scaling ratio and performance limitations of the current technology. On the other hand, since the five-sided gate structure can further reduce the size of the gate structure, the size of the semiconductor structure can be further reduced.

[0102] In this embodiment of the disclosure, after forming the gate structure 30, the method for forming the semiconductor structure further includes: removing the second mask layer 162.

[0103] In some embodiments, after removing the second mask layer, the method of forming the semiconductor structure may further include: forming word line steps stacked sequentially along a third direction; wherein each word line in the word line steps is electrically connected to a corresponding gate structure arranged along a first direction.

[0104] In this embodiment, the word line step can be formed in two ways. Method 1: First, a photoresist layer with a first opening is formed on the surface of a first region A; the first opening exposes the end of the first region A away from the gate structure; the first region A is etched by the photoresist layer with the first opening to form a first stepped structure; second, a photoresist layer with a second opening is formed on the surface of the first stepped structure, the second opening exposing a portion of the first stepped structure; the first stepped structure is etched by the photoresist layer with the second opening to form a second stepped structure, wherein the size of the second opening in the first direction is larger than the size of the first opening; third, a photoresist layer with a third opening is formed on the surface of the second stepped structure, the third opening exposing a portion of the second stepped structure; the second stepped structure is etched by the photoresist layer with the third opening to form a third stepped structure, wherein the size of the third opening in the first direction is larger than the size of the second opening; repeating the above steps, after multiple etching processes, a word line step is finally formed, the word line step having a progressively decreasing length from bottom to top along the Z-axis.

[0105] Method 2: First, a first word line of a first length is formed on the surface of the semiconductor substrate in the first region A, wherein the first word line is electrically connected to the bottommost word line structure along the first direction; second, a first isolation unit of a second length is formed on the surface of the first word line; a second word line of a second length is formed on the surface of the first isolation unit, wherein the second word line is electrically connected to the next bottommost second layer word line structure along the first direction, wherein the first length is greater than the second length, and the first isolation unit is used to isolate adjacent first and second word lines; third, a second isolation unit of a third length is formed on the surface of the second word line; a third word line of a third length is formed on the surface of the second isolation unit, wherein the third word line is electrically connected to the third layer word line structure from bottom to top along the first direction, wherein the second length is greater than the third length, and the second isolation unit is used to isolate adjacent second and third word lines; repeating the above steps, after multiple formation processes, a word line step composed of multiple word lines is formed.

[0106] In some embodiments, before forming the capacitor structure 27 and the bit line structure 28, the method for forming the semiconductor structure further includes: performing ion implantation on the second semiconductor layer near the gate structure in the second portion B-2 to form the source S and the drain D (e.g., Figure 3i (as shown); forming a first contact structure and a second contact structure that are in contact with the capacitor structure 27 and the bit line structure 28, respectively.

[0107] In some embodiments, please refer to Figures 3i~3kAfter forming the first sub-pillar 251 and the second sub-pillar 252, the method for forming the semiconductor structure further includes: forming a capacitor structure 27 on the end face of the first sub-pillar 251 away from the word line structure 22; and forming a bit line structure 28 on the end face of the second sub-pillar 252 away from the word line structure 22. The capacitor structure 27 extends along a second direction, and the bit line structure 22 extends along a third direction.

[0108] In this embodiment of the disclosure, the capacitor structure 27 can be formed by the following steps: depositing a first electrode material, a dielectric material, and a second electrode material sequentially on the surface of the first sub-pillar 251 to form a first electrode layer 271, a dielectric layer 272, and a second electrode layer 273, wherein the first electrode layer 271, the dielectric layer 272, and the second electrode layer 273 constitute the capacitor structure 27.

[0109] In this embodiment, the first electrode layer 271, dielectric layer 272, and dielectric layer 273 can be formed by any of the following deposition processes: chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The first electrode material and the second electrode material can include metal nitrides or metal silicides, such as titanium nitride. The dielectric material can include high-k dielectric materials, such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), and hafnium silicate (HfSiO2). x The material may be one or any combination of zirconium oxide (ZrO2) or zirconia. In other embodiments, the materials of the first electrode layer 271 and the dielectric layer 273 may also be polycrystalline silicon.

[0110] In some embodiments, a metal silicide layer may be formed on the surface of the first sub-pillar 251 before the formation of the first electrode layer 271. In practice, a metal material, such as any one of cobalt, titanium, tantalum, nickel, tungsten, platinum, and palladium (Pd), may be deposited on the surface of the first sub-pillar 251; subsequently, a rapid thermal annealing process is performed to allow the metal material to react with the first sub-pillar 251, thereby forming a metal silicide on the surface of the first sub-pillar 251. Since the metal silicide has a low resistance, the contact resistance between the first electrode layer 271 and the drain electrode can be reduced, thereby reducing the power consumption of the semiconductor structure.

[0111] In this embodiment, the formed capacitor structure extends along the Y-axis direction, that is, the formed capacitor structure is horizontal. Compared with the vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure can reduce the possibility of tipping or breaking, thereby improving the stability of the capacitor structure. Furthermore, the stacked structure formed by stacking multiple capacitor structures in the Z-axis direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and realizing miniaturization.

[0112] In this embodiment of the disclosure, please refer to Figure 3i and 3k The bit line structure 28 can be formed by the following steps: depositing bit line metal material on the end face of the second sub-pillar 252 away from the word line structure to form the bit line structure 28.

[0113] In this embodiment of the disclosure, the bit line metal material can be any material with good conductivity, such as tungsten, cobalt, copper, aluminum, titanium, titanium nitride, platinum, palladium, molybdenum, titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0114] In some embodiments, a metal silicide layer may be formed between the second sub-pillar 252 and the bit line structure to reduce the contact resistance between the bit line structure 28 and the second sub-pillar 252, thereby further reducing the power consumption of the semiconductor structure.

[0115] In some embodiments, after forming the capacitor structure 27 and the bit line structure 28, the method for forming the semiconductor structure further includes forming a fifth isolation layer (not shown) in the second space.

[0116] In this embodiment of the disclosure, the material of the fifth isolation layer can be polycrystalline silicon or any other suitable material.

[0117] The semiconductor structure formation method provided in this disclosure can control the length and width of the gate, and the formed word line structure is horizontal. The horizontal word line structure can be directly filled and formed, which reduces the complexity of the fabrication process of the horizontal word line structure, thereby reducing the manufacturing cost of the semiconductor structure.

[0118] This disclosure also provides a semiconductor structure. Figures 4a-4c This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure, such as... Figures 4a-4c As shown, the semiconductor structure 100 includes at least: a semiconductor substrate 10, which includes a first region A and a second region B arranged sequentially along a second direction (Y-axis direction); an active structure located on the second region B and arranged in an array along a first direction (X-axis direction) and a third direction (Z-axis direction), the active structure including at least a channel structure 18; a word line structure 22 located in the first region A and extending along the first direction; and a gate structure 30 located on the surface of the channel structure 18, wherein the word line structure 22 is connected to the gate structure 30 located on the same layer. The second region B includes a first portion B-1 and a second portion B-2.

[0119] In some embodiments, the projection of the channel structure 18 onto the surface of the semiconductor substrate 10 is U-shaped; in other embodiments, the projection of the channel structure 18 onto the surface of the semiconductor substrate 10 can be rectangular, L-shaped, or convex.

[0120] In some embodiments, please continue to see Figure 4c The gate structure 30 covers the first and second surfaces of the channel structure 18 along the Z-axis, the third and fourth surfaces of the channel structure 18 along the X-axis, and the fifth surface of the channel structure along the Y-axis. The word line structure 22 is connected to the gate structure 30 located on the fifth surface. The gate structure 30 includes a gate dielectric layer 171 and a gate conductive layer 172 stacked together.

[0121] In some embodiments, please refer to Figure 4a The semiconductor structure also includes a capacitor structure 27 and a bit line structure 28 located in the second region B; wherein the capacitor structure 27 extends along the Y-axis direction and the bit line structure 28 extends along the Z-axis direction.

[0122] In some embodiments, please refer to Figure 4b and Figure 4c The active structure also includes active pillars; the active pillars and the channel structure 18 are arranged sequentially along the second direction; the active pillars include a first sub-pillar 251 and a second sub-pillar 252; the capacitor structure 27 is formed on the end face of the first sub-pillar 251; and the bit line structure 28 is formed on the end face of the second sub-pillar 252.

[0123] In some embodiments, please refer to Figures 4a-4c A first isolation groove 12 is provided between the first sub-post 251 and the second sub-post 252 of the same active post; a second isolation groove 13 is provided between adjacent active posts along the first direction; wherein the dimension L2 of the second isolation groove 13 in the second direction is greater than the dimension L1 of the first isolation groove 12 in the second direction.

[0124] In this embodiment of the disclosure, the first isolation groove 12 can be L-shaped or rectangular.

[0125] In this embodiment of the disclosure, please refer to Figure 4a The semiconductor structure also includes: source (S) and drain (D).

[0126] In some embodiments, please continue to see Figure 4b and 4c The capacitor structure 27 is located on the first sub-pillar 251; the bit line structure 28 is located on the second sub-pillar 252; wherein, the capacitor structure 24 includes a first electrode layer 271, a dielectric layer 272, and a second electrode layer 273.

[0127] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding, and will not be repeated here.

[0128] The semiconductor structure provided in this disclosure uses a self-aligned process to form word line trenches. By filling word line material, a horizontal word line structure can be directly formed, which can control the length and width of the gate. Therefore, the fabrication process complexity of the horizontal word line structure is reduced, thereby reducing the manufacturing cost of the semiconductor structure.

[0129] Figures 5a-5f This is a schematic diagram of a planar structure of a semiconductor structure provided in an embodiment of this disclosure, such as... Figures 5a-5f As shown, the semiconductor structure 100 includes: a gate structure 30, a bit line structure 28, and a capacitor structure 27 arranged in an array along the X-axis and Z-axis directions; wherein the bit line structure 28 and the capacitor structure 27 are each connected to a gate structure 30.

[0130] In this embodiment, a gate structure 30 and a capacitor structure 27 constitute a memory cell; adjacent memory cells along the X-axis have the same layout (e.g., ...). Figures 5a-5e (as shown), or, adjacent memory cells along the X-axis are axially symmetric (e.g. Figure 5f (As shown).

[0131] In some embodiments, please continue to refer to 5a-5f, the semiconductor structure 100 further includes word line structures 22 extending along the X-axis direction, wherein each word line structure 22 is connected to a plurality of gate structures 30 arranged along the X-axis direction.

[0132] In this embodiment of the disclosure, please continue to refer to 5a~5f. The semiconductor structure 100 also includes a source S, a drain D, a first contact structure 311 connected to the drain D, and a second contact structure 312 connected to the source S.

[0133] In this embodiment of the disclosure, the gate structure 30 can be U-shaped (e.g., Figure 5a As shown), rectangle (as shown) Figure 5e and 5f as shown), convex type (such as Figure 5b (As shown), or it can be L-shaped (such as...) Figure 5c and 5d (As shown).

[0134] This disclosure also provides a transistor structure, which includes a source, a drain, and a gate structure surrounding a channel structure.

[0135] The gate structure can be a five-sided ring gate structure. The projection of the gate structure onto the semiconductor substrate surface (or third-party upward) can be rectangular, convex, U-shaped, or L-shaped. The drain and capacitor structure are connected through a first contact structure, and the source and bit line structure are connected through a second contact structure.

[0136] The transistor structure provided in this disclosure is similar to the transistor structure in the semiconductor structure in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding, and will not be repeated here.

[0137] In this embodiment of the disclosure, the shape of the gate structure can be freely controlled as needed, thus effectively utilizing the space in the semiconductor structure to achieve miniaturization.

[0138] In addition, this disclosure also provides a layout structure. Figure 6a and 6b This is a planar layout diagram of the layout structure provided in an embodiment of the present disclosure. The layout structure 200 includes the aforementioned semiconductor structures 100 arranged at intervals along the Y-axis direction.

[0139] like Figure 6a and 6b As shown, the semiconductor structure 100 includes memory cells arranged in an array along the X-axis and Z-axis directions; each memory cell includes a gate structure 30 and a capacitor structure 27; wherein, two adjacent memory cells in the Y-axis direction are centrally symmetrical, and the projection areas of the capacitor structures 27 of two adjacent memory cells in the Y-axis direction at least partially overlap in the X-axis direction.

[0140] In some embodiments, please continue to see Figure 6a and 6b The semiconductor structure 100 also includes a bit line structure 28 and a word line structure 22.

[0141] In some embodiments, please continue to see Figure 6a The layout of two adjacent storage cells in the X-axis direction is the same.

[0142] In some embodiments, please continue to see Figure 6b The layout of two adjacent storage cells along the X-axis is axially symmetrical.

[0143] The layout structure provided in this disclosure can effectively utilize the space in the semiconductor structure to achieve miniaturization of the semiconductor structure.

[0144] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0145] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0146] The above descriptions are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region arranged sequentially along a second direction; the second region includes active structures arranged in an array along the first direction and a third direction, the active structures including at least a channel structure; the first direction, the second direction and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate; A gate structure is formed on the surface of the channel structure; A word line structure extending along the first direction is formed on the first region; wherein the word line structure is connected to the gate structure located on the same layer.

2. The method according to claim 1, characterized in that, The projection of the channel structure onto the surface of the semiconductor substrate is U-shaped or rectangular.

3. The method according to claim 2, characterized in that, The active structure further includes an active post; the active post and the channel structure are arranged sequentially along the second direction, and the channel structure connects the active post; the method further includes: A capacitor structure and a bit line structure are formed on the end face of the active pillar; The capacitor structure extends along the second direction, and the bit line structure extends along the third direction.

4. The method according to claim 3, characterized in that, The channel structure is formed through the following steps: A stacked structure is formed on the surface of the semiconductor substrate; the stacked structure includes a first semiconductor layer and a second semiconductor layer that are alternately stacked along a third direction; The stacked structure and a portion of the semiconductor substrate are etched to form a first isolation groove and a second isolation groove that extend along the second direction in the second region and are alternately spaced, and an etching trench that extends along the first direction in the first region; wherein the size of the first isolation groove in the second direction is smaller than the size of the second isolation groove in the second direction, and the second isolation groove communicates with the etching trench; The remaining stacked structure in the second region is processed to form the channel structure.

5. The method according to claim 4, characterized in that, The remaining stacked structure in the second region includes a first portion located on both sides of the first isolation groove along the first direction, and a second portion connected to the first portion along the second direction; The process of processing the remaining stacked structure in the second region to form the channel structure includes: A first isolation layer is formed in the first isolation groove, the second isolation groove, and the etched trench; the surface of the first isolation layer is flush with the surface of the stacked structure. A first mask layer with a preset pattern is formed on the surface of the stacked structure and the first isolation layer; wherein the preset pattern exposes a portion of the first isolation layer located in the etched trench and a portion of the stacked structure that exposes the second portion, and the first mask layer is flush with both sides of the first isolation groove in the second direction; The first mask layer is used to remove the exposed portion of the first isolation layer and the exposed portion of the first semiconductor layer to form a gate trench; the remaining second semiconductor layer in the exposed portion constitutes the channel structure.

6. The method according to claim 5, characterized in that, The word line structure and the gate structure are formed through the following steps: A gate dielectric layer and a gate conductive layer covering the channel structure are sequentially formed on the inner wall of the gate trench to form an initial gate structure; A second isolation layer is formed in the gate trench having the gate dielectric layer and the gate conductive layer; The surface of the second isolation layer is flush with the surface of the stacked structure; Remove the remaining first isolation layer in the etched trench, as well as the gate dielectric layer and gate conductive layer located on the sidewall of the second isolation layer in the gate trench, to expose part of the etched trench; A third isolation layer is formed in the exposed etched trenches; The stacked structure of the first region, as well as the second and third isolation layers in the etched trenches, are processed to form the word line structure; The initial gate structure is processed to form the gate structure.

7. The method according to claim 6, characterized in that, The process of processing the stacked structure of the first region, and the second and third isolation layers in the etched trenches, to form the word line structure includes: Remove the second semiconductor layer in the first region, as well as the third and second isolation layers located in the projection region of the second semiconductor layer along the second direction, to form a word line trench; The character line structure is formed by filling the character line groove with character line metal material.

8. The method according to claim 7, characterized in that, After forming the word line structure, the method further includes: Remove the first semiconductor layer in the first region to form a third isolation groove; A fourth isolation layer is formed in the third isolation groove.

9. The method according to claim 6, characterized in that, The process of processing the initial gate structure to form the gate structure includes: A second mask layer with a serrated pattern is formed on the surface of the word line structure and the initial gate structure; wherein the serrated pattern includes convex patterns and concave patterns arranged alternately along the first direction; the concave pattern exposes a portion of the initial gate structure; The exposed initial gate structure is removed through the second mask layer, forming the gate structure and the first space.

10. The method according to claim 9, characterized in that, The method further includes: The active pillar is formed simultaneously with the formation of the gate structure.

11. The method according to claim 10, characterized in that, The active column is formed through the following steps: The second semiconductor layer of the first portion and the first isolation layer located in the first portion are removed to form a second space, and a first sub-pillar and a second sub-pillar arranged alternately along the first direction; The first sub-pillar and the second sub-pillar constitute the active pillar; the second space includes the first space.

12. The method according to claim 11, characterized in that, The method further includes: A fifth isolation layer is formed in the second space.

13. The method according to claim 11, characterized in that, A capacitor structure and a bit line structure are formed on the surface of the active pillar, including: The capacitor structure is formed on the end face of the first sub-pillar away from the word line structure; The bit line structure is formed on the end face of the second sub-pillar away from the word line structure.

14. A semiconductor structure, characterized in that, At least including: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region arranged sequentially along a second direction; An active structure located on the second region and arranged in an array along a first direction and a third direction, the active structure including at least a channel structure; the first direction, the second direction and the third direction are mutually perpendicular, and the first direction and the second direction are parallel to the surface of the semiconductor substrate; The character line structure located in the first region and extending along the first direction; A gate structure located on the surface of the channel structure, wherein the word line structure is connected to the gate structure located on the same layer.

15. The semiconductor structure according to claim 14, characterized in that, The projection of the channel structure onto the surface of the semiconductor substrate is U-shaped, rectangular, L-shaped, or convex.

16. The semiconductor structure according to claim 15, characterized in that, The gate structure covers a first and second surface of the channel structure along the third direction, a third and a fourth surface of the channel structure along the first direction, and a fifth surface of the channel structure along the second direction, and the word line structure is connected to the gate structure located on the fifth surface; The gate structure includes a gate dielectric layer and a gate conductive layer stacked together.

17. The semiconductor structure according to any one of claims 14 to 16, characterized in that, The semiconductor structure further includes a capacitor structure and a bit line structure located in the second region; The capacitor structure extends along the second direction, and the bit line structure extends along the third direction.

18. The semiconductor structure according to claim 17, characterized in that, The active structure further includes active pillars; the active pillars and the channel structure are arranged sequentially along the second direction; the active pillars include a first sub-pillar and a second sub-pillar; The capacitor structure is formed on the end face of the first sub-pillar; the bit line structure is formed on the end face of the second sub-pillar.

19. The semiconductor structure according to claim 18, characterized in that, A first isolation groove is provided between the first sub-post and the second sub-post of the same active post; a second isolation groove is provided between adjacent active posts along the first direction; The second isolation groove has a larger dimension in the second direction than the first isolation groove has in the second direction.

20. A layout structure, characterized in that, include: Semiconductor structures as described in any one of claims 14 to 19 are arranged sequentially at intervals along a second direction; The semiconductor structure includes memory cells arranged in an array along a first direction and a third direction; each memory cell includes a gate structure and a capacitor structure. Wherein, two adjacent memory cells in the second direction are centrally symmetrical, and the capacitor structures of two adjacent memory cells in the second direction at least partially overlap in the projection area in the first direction.

21. The layout structure according to claim 20, characterized in that, The projection of the gate structure in the third direction is U-shaped, rectangular, L-shaped, or convex.

22. The layout structure according to claim 20 or 21, characterized in that, The two adjacent storage cells in the first direction have the same layout or are axially symmetrical.

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