Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of existing holes in an interconnection structure. The preparation method of the semiconductor structure comprises the following steps: forming a first dielectric layer with a first thickness on a target layer, wherein the first thickness is less than a preset thickness; forming a first conductive via in the first dielectric layer, wherein the first conductive via comprises a first hole section and a second hole section, the second hole section is located below the first hole section and communicates with the first hole section, and the diameter of the second hole section is less than the diameter of the first hole section; forming a second dielectric layer in the first conductive via, wherein the second dielectric layer extends to outside the first conductive via and covers the first dielectric layer; removing the second dielectric layer on the inner wall of the first conductive via, and the remaining second dielectric layer surrounds a second conductive via which communicates with the first conductive via; and forming an interconnection structure in the conductive via. The present disclosure is used to prevent the formation of holes in the interconnection structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In the semiconductor fabrication process, interconnect structures are an indispensable part of the semiconductor structure. For example, Dynamic Random Access Memory (DRAM) typically includes a storage area and a peripheral circuit area. The storage area is used to set up multiple storage cells for storing data information. The storage area and the peripheral circuit area usually include interconnect structures to realize the storage, retrieval and connection of data information.

[0003] In related technologies, a dielectric layer with conductive vias is typically formed on a semiconductor structure, and then conductive material is deposited within the vias to form an interconnect structure. However, the presence of voids within the formed interconnect structure can degrade the performance of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a semiconductor structure and its fabrication method to prevent the formation of holes in the interconnect structure and improve the performance of the semiconductor structure.

[0005] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0006] A first dielectric layer with a first thickness is formed on the target layer, the first thickness being less than a preset thickness; wherein, the target layer contains a semiconductor device;

[0007] A first conductive via is formed within the first dielectric layer to expose the semiconductor device. The first conductive via includes a first segment and a second segment. The second segment is located below the first segment and communicates with the first segment. The diameter of the second segment is smaller than the diameter of the first segment.

[0008] A second dielectric layer is formed inside the first conductive via, and the second dielectric layer extends outside the first conductive via and covers the first dielectric layer;

[0009] Remove the second dielectric layer located on the inner wall of the first conductive via. The remaining second dielectric layer forms a second conductive via that is connected to the first conductive via. The second conductive via and the first conductive via together form a conductive via.

[0010] An interconnect structure is formed within the conductive via.

[0011] In some embodiments, the step of forming a first conductive via within the first dielectric layer to expose the semiconductor device includes:

[0012] A portion of the first dielectric layer is removed using a first etching process to form a first initial conductive via within the first dielectric layer;

[0013] The top of the first initial conductive via is enlarged using a second etching process, so that the diameter of the top of the first initial conductive via is larger than the diameter of the bottom of the first initial conductive via. The enlarged first initial conductive via forms a first segment, and the unenlarged first initial conductive via forms a second segment.

[0014] In some embodiments, the target layer has a first region and a second region connected to the first region, and both the first region and the second region have semiconductor devices.

[0015] The steps of enlarging the top of the first initial conductive via using a second etching process include:

[0016] A second etching process is used to form a filling hole on the first dielectric layer located in the first region, wherein the bottom of the filling hole does not expose the bottom surface of the first dielectric layer.

[0017] In some embodiments, the step of enlarging the top of the first initial conductive via using a second etching process includes:

[0018] A first mask layer with a first mask opening is formed on the first dielectric layer, a portion of the first mask opening is located on the second region and directly above the first initial conductive via, and a portion of the first mask opening is located on the first region; wherein, the width of the first mask opening is greater than the diameter of the first initial conductive via.

[0019] Using the first mask layer as a mask, a portion of the thickness of the first dielectric layer is removed using a second etching process to form a filling hole in the first region and a first hole segment in the second region.

[0020] In some embodiments, the first etching process and the second etching process each independently include dry etching.

[0021] In some embodiments, the etching rates of the first etching process and the second etching process are each independently 3-8 nm / s.

[0022] In some embodiments, there are multiple first conductive vias, which are spaced apart within a first dielectric layer; wherein each first conductive via has the same size.

[0023] In some embodiments, the second dielectric layer has a second thickness, which is less than the first thickness.

[0024] In some embodiments, the first thickness is 480nm to 520nm; the second thickness is 260nm to 300nm.

[0025] In some embodiments, the step of removing the second dielectric layer located on the inner wall of the first conductive via includes:

[0026] The second dielectric layer located on the sidewall of the first hole segment and the second dielectric layer with at least a partial thickness located on the bottom wall of the first hole segment are removed using a third etching process.

[0027] The second dielectric layer located on the sidewalls and bottom of the second hole segment is removed using a fourth etching process.

[0028] In some embodiments, the third etching process and the fourth etching process each independently include dry etching.

[0029] In some embodiments, the etching rates of the third etching process and the fourth etching process are each independently 3-8 nm / s.

[0030] In some embodiments, the step of forming an interconnect structure within the conductive via includes:

[0031] A copper seed layer is formed on the inner wall of the conductive via;

[0032] A conductive layer is formed on the copper seed layer, and the conductive layer fills the area enclosed by the copper seed layer.

[0033] In some embodiments, a conductive layer is formed in the area enclosed by the copper seed layer by an electroplating process, wherein the conductive layer is made of copper.

[0034] In some embodiments, both the first dielectric layer and the second dielectric layer are made of silicon oxide.

[0035] A second aspect of this disclosure provides a semiconductor structure formed by the method for fabricating the semiconductor structure described in the first aspect.

[0036] In the semiconductor structure and its fabrication method provided in this disclosure, a first dielectric layer is first formed on the target layer. The thickness of the first dielectric layer is less than the preset thickness of the dielectric layer. This reduces the aspect ratio of the first conductive via in the first dielectric layer, ensuring that a relatively regular stepped first conductive via can be formed. Then, a second dielectric layer of a certain thickness is formed, and the second dielectric layer located on the inner wall of the first conductive via is removed to form a second conductive via communicating with the first conductive via. The second conductive via and the first conductive via constitute a conductive via. This ensures that the conductive via is a relatively regular stepped shape, thereby avoiding the formation of interconnect structures with holes and improving the performance of the semiconductor structure.

[0037] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0040] Figure 2 This is a schematic diagram of the target layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0041] Figure 3 This is a schematic diagram of the structure for forming the first dielectric layer in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0042] Figure 4 A schematic diagram of the structure for forming the second mask layer in the method for fabricating a semiconductor structure provided in this embodiment of the present disclosure;

[0043] Figure 5 A schematic diagram of the structure for forming a first initial conductive via in the method for fabricating a semiconductor structure provided in this embodiment of the present disclosure;

[0044] Figure 6A schematic diagram of the structure for forming the first conductive via in the method for fabricating a semiconductor structure provided in this embodiment of the present disclosure;

[0045] Figure 7 A schematic diagram of the structure for forming the second dielectric layer in the method for fabricating a semiconductor structure provided in this embodiment of the present disclosure;

[0046] Figure 8 A schematic diagram of a semiconductor structure fabrication method with partial removal of the second dielectric layer provided in this embodiment of the disclosure;

[0047] Figure 9 A schematic diagram of the formation of the second conductive via in the method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0048] Figure 10 This is a schematic diagram of the structure for forming a copper seed layer in the method for preparing a semiconductor structure provided in this embodiment of the disclosure;

[0049] Figure 11 This is a schematic diagram of the structure in which a conductive layer is formed in the method for preparing a semiconductor structure according to an embodiment of this disclosure.

[0050] Figure label:

[0051] 100: Target layer; 110: Conductive plug; 120: Insulating layer; 130: First region; 140: Second region;

[0052] 200: Dielectric layer; 210: First dielectric layer; 211: First initial conductive via; 220: Second dielectric layer; 230: First conductive via; 231: First via segment; 232: Second via segment; 233: Step surface; 240: Filling via; 250: Second conductive via;

[0053] 300: Second mask layer; 310: First opening; 400: Copper seed layer; 500: Conductive layer. Detailed Implementation

[0054] As described in the background section, the inventors have discovered that the interconnect structure in the related technology has the problem of having holes. The reason for this problem is that the dielectric layer used to support the interconnect structure is relatively high. As a result, the conductive vias formed in the dielectric layer have a high aspect ratio and are difficult to present a regular step shape. Instead, they present a serrated or other irregular shape. When the interconnect structure is formed in the conductive via, it is easy to form a void in the interconnect structure, which reduces the performance of the semiconductor structure.

[0055] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and its fabrication method. First, a first dielectric layer is formed on a target layer. The thickness of the first dielectric layer is less than the preset thickness of dielectric layers in related technologies. This reduces the aspect ratio of the subsequent first conductive via within the first dielectric layer, ensuring the formation of a relatively regular stepped first conductive via. Then, a second dielectric layer of a certain thickness is formed, and the second dielectric layer located on the inner wall of the first conductive via is removed to form a second conductive via communicating with the first conductive via. The second conductive via and the first conductive via constitute a conductive via. This ensures that the conductive via is a relatively regular stepped shape, thereby avoiding the formation of interconnect structures with holes and improving the performance of the semiconductor structure.

[0056] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0057] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0058] Please refer to the attached document. Figure 1 The present disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0059] Step S100: A first dielectric layer is formed on the target layer. The first dielectric layer has a first thickness, which is less than a preset thickness. The target layer contains a semiconductor device.

[0060] Please refer to the attached document. Figure 2The target layer 100 may consist solely of a substrate, or it may include a substrate and semiconductor devices formed within or on the substrate. The substrate supports the semiconductor devices formed within or on it, and can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. Semiconductor devices include N-type metal-oxide-semiconductor (NMOS) transistors, P-type metal-oxide-semiconductor (PMOS) transistors, conductive plugs, resistors, capacitors, inductors, etc. For ease of description, the following description uses the example of a semiconductor device including conductive plugs.

[0061] Please refer to the attached document. Figure 3 The first dielectric layer 210 can be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), to form the first dielectric layer 210 on the target layer 100.

[0062] The first dielectric layer 210 has a first thickness, which is less than a preset thickness. The preset thickness can be understood as the thickness of the dielectric layer in related technologies, for example, a range of 740nm to 820nm. Thus, a first dielectric layer 210 of relatively small thickness can be deposited first, and then a first conductive via 230 can be formed within the first dielectric layer 210 (see appendix). Figure 6 When this is done, the aspect ratio of the first conductive via can be reduced, allowing for better control over its shape. To clearly determine the thickness of the first dielectric layer 210, consider the attached... Figure 3 H1 is used as the first thickness.

[0063] For example, the first thickness H1 ranges from 480nm to 520nm. If the value of the first thickness H1 is less than 480nm, the thickness of the first dielectric layer 210 will be too small, making it difficult to form the inverted U-shaped first conductive via 230 (please refer to the appendix). Figure 6 This, in turn, hinders the formation of subsequent interconnection structures.

[0064] If the value of the first thickness H1 is greater than 520nm, the thickness of the first dielectric layer 210 will be too large, making it impossible to reduce the aspect ratio of the subsequently formed first conductive via 230, and thus making it difficult to ensure that the inner wall of the first conductive via 230 has a regular shape.

[0065] Therefore, this embodiment limits the thickness of the first dielectric layer 210 to avoid both excessively thin and excessively thick first dielectric layer 210. In this way, the shape of the first conductive via 230 can be guaranteed to be an inverted convex shape with a larger top and a smaller bottom as much as possible.

[0066] It should be noted that, before forming the first dielectric layer 210, an insulating layer 120 may be formed on the target layer 100 so that the interconnect structure subsequently formed can be selectively connected to the semiconductor devices in the target layer 100. The insulating layer 120 may be made of silicon nitride, but is not limited to this.

[0067] Step S200: A first conductive via is formed in the first dielectric layer to expose a semiconductor device. The first conductive via includes a first segment and a second segment. The second segment is located below the first segment and communicates with the first segment. The diameter of the second segment is smaller than the diameter of the first segment.

[0068] Please refer to the attached document. Figure 6 The first dielectric layer 210 is patterned, and a portion of the first dielectric layer 210 is removed to form a first conductive via 230 within the first dielectric layer 210, exposing the semiconductor device. For example, the bottom wall of the first conductive via 230 is the top surface of the conductive plug 110; or, for another example, the bottom wall of the first conductive via 230 is located inside the conductive plug 110, that is, when a portion of the first dielectric layer 210 is removed, a portion of the conductive plug 110 is also removed, causing the first conductive via 230 to extend into the conductive plug 110.

[0069] It should be noted that the first conductive via 230 can be formed by a single etching process or by multiple etching processes. A single etching process refers to etching the first dielectric layer 210 to a certain depth in one step; multiple etching processes refer to etching in multiple steps or in stages, etching the first dielectric layer 210 to a certain depth through at least two etching processes. The type and / or process parameters of the at least two etching processes can be the same or different.

[0070] In some possible examples, the first conductive via 230 is formed through a two-etching process. For example:

[0071] Step S210: A portion of the first dielectric layer is removed using a first etching process to form a first initial conductive via within the first dielectric layer. The structure of this via can be referenced in the attached diagram. Figure 5 .

[0072] For example, please refer to the appendix. Figure 4 A second mask layer 300 is formed on the first dielectric layer 210. The second mask layer 300 can be a photoresist layer, that is, a photoresist layer can be formed on the surface of the first dielectric layer 210 away from the target layer 100 by coating.

[0073] A patterned photoresist layer is formed to create a plurality of spaced-apart first masking portions on the photoresist layer, with a first opening 310 formed between adjacent first masking portions. That is, by means of exposure, development or etching, a portion of the photoresist layer is removed, and the remaining photoresist layer forms a plurality of first masking portions.

[0074] Next, please refer to the appendix. Figure 5 The first dielectric layer 210 exposed in the first opening 310 is removed by the first etching process to form a first initial conductive via 211 in the first dielectric layer 210.

[0075] In this step, the process parameters of the first etching process can be controlled to make the sidewalls of the first initial conductive via 211 as straight as possible. In other words, the diameter of the first initial conductive via 211 should be kept as constant as possible from top to bottom, so that the subsequently formed first conductive via 230 has a stepped surface 233 (see Appendix). Figure 6 ).

[0076] Step S220: The top of the first initial conductive via is enlarged using a second etching process, so that the diameter of the top of the first initial conductive via is larger than the diameter of the bottom of the first initial conductive via. The enlarged first initial conductive via forms a first segment, and the unenlarged first initial conductive via forms a second segment. See the attached diagram for its structure. Figure 6 .

[0077] In this embodiment, a portion of the first dielectric layer 210 is removed using a first etching process to form a first initial conductive via 211 extending in a direction perpendicular to the target layer 100 within the first dielectric layer 210. Because the first thickness of the first dielectric layer 210 is relatively small, the first initial conductive via 211 can be formed quickly. Furthermore, the small first thickness of the first dielectric layer 210 also allows the sidewalls of the first initial conductive via 211 to be approximately or strictly perpendicular to the target layer 100, ensuring that the shape of the first initial conductive via 211 reaches an ideal state.

[0078] Subsequently, a second etching process is used to enlarge the top of the first initial conductive via 211, so that the top of the first initial conductive via 211 quickly forms the first segment 231, while the bottom of the first initial conductive via 211 retains its original shape, forming the second segment 232. A stepped surface 233 is formed between the first segment 231 and the second segment 232.

[0079] In this embodiment, the first dielectric layer 210 is etched in two steps, which can reduce or avoid damage to the corner of the step surface 233 and ensure that the final first conductive via 230 is an inverted convex-shaped hole with a larger top and a smaller bottom.

[0080] In this setup, the first and second etching processes are identical; both can be dry etching, or both can be wet etching. In one example, the first and second etching processes each independently include dry etching. This configuration utilizes the good consistency of dry etching, which can improve the accuracy of the pattern.

[0081] It should be noted that the first etching process and the second etching process can also be different. For example, the first etching process can be dry etching, and the second etching process can be wet etching. This setup can better utilize the better consistency of dry etching and the better etching selectivity of wet etching, reducing damage to the pattern and thus forming a more regular first conductive via.

[0082] In this embodiment, the etching gas for dry etching includes at least one of C2F2, CF4, CH2F2, CHF3, and C4F6; wherein the atomic ratio of carbon to fluorine in the etching gas is 1:2 to 2:3. In a preferred embodiment, the etching gas for dry etching may include CF4 and CHF3.

[0083] Thus, by reasonably adjusting the volume or flow rate ratio of each gas in the etching gas, the etching rates of the first and second etching processes can be controlled. For example, the proportion of C can be appropriately increased to increase the etching rate, thereby ensuring that the sidewalls of the formed first conductive via 230 are as straight as possible, thereby improving the performance of the subsequent interconnect structure formed in the first conductive via 230, and thus improving the performance of the semiconductor structure.

[0084] In some embodiments, if the etching rate of the first etching process and the second etching process is greater than 8 nm / s, the etching rate will be too fast. On the one hand, it can damage the step surface 233 between the first hole segment 231 and the second hole segment 232, causing irregular sawtooth shape to form at the position that should be the step surface. On the other hand, it can also damage the conductive plug 110, reducing the yield of the semiconductor structure.

[0085] If the etching rate of the first and second etching processes is less than 3nm / s, the etching rate will be too slow, resulting in an increase in etching time and thus an increase in the cost of the etching process.

[0086] Therefore, in this embodiment, the etching rates of the first etching process and the second etching process are controlled so that the etching rates of the first etching process and the second etching process are each independently located at 3-8 nm / s, thereby avoiding damage to the step surface between the first hole segment 231 and the second hole segment 232, and also reducing the production cost of the etching process.

[0087] In this embodiment, the etching rates of the first etching process and the second etching process are each independently located in the range of 3-8 nm / s. This can be understood as the etching rates of the first etching process and the second etching process being the same or different. However, the etching rates of both the first etching process and the second etching process are located in the range of 3-8 nm / s.

[0088] It should be noted that, in this embodiment, the target layer 100 may include a first region 130 and a second region 140 connected to the first region 130. The first region 130 and the second region 140 are connected, which can be understood as the first region 130 and the second region 140 being arranged side-by-side in a certain direction. Their structure can be found in the attached diagram. Figure 6 It can also be understood that the first region 130 is set around the second region 140; or it can be understood that the second region 140 is set around the first region 130.

[0089] Both the first region 130 and the second region 140 have semiconductor devices. For example, the first region 130 can serve as an array region, where the semiconductor devices located in the first region 130 can be memory cells, bit lines, and various conductive plugs. The second region 140 can serve as a peripheral circuit region, where the semiconductor devices are logic transistors. Each memory cell includes a control transistor and a capacitor. The lower electrode of the capacitor is connected to the source or drain region of the control transistor via a capacitive contact structure. The capacitive contact structure includes a contact plug located within the substrate and a connecting pad located on the substrate. The longitudinal section of the connecting pad is perpendicular to the substrate. The longitudinal cross-sectional shape of the connecting pad can be I-shaped or Z-shaped, thereby increasing the contact area between the contact plug and the connecting pad, improving the connection accuracy between the capacitor and the source or drain region of the control transistor, and thus improving the yield of the semiconductor structure.

[0090] Furthermore, in this embodiment, the control transistor can be a buried transistor, that is, the gate and source / drain regions of the transistor are both located within the substrate. This reduces the size of the semiconductor structure, facilitating the development of semiconductor structures towards smaller dimensions. Therefore, when the top of the first initial conductive via 211 is enlarged using the second etching process, the first dielectric layer 210 located on the first region 130 is also patterned.

[0091] It should be noted that the semiconductor devices in the array area and peripheral circuit area are of conventional structure; therefore, the structure of the memory cell and logic transistor is not shown in the accompanying drawings.

[0092] Please continue to refer to the appendix. Figure 6 For example, a second etching process is used to form a filling hole 240 on the first dielectric layer 210 located in the first region 130. The bottom of the filling hole 240 does not expose the bottom surface of the first dielectric layer 210, that is, the depth of the filling hole 240 is less than the thickness of the first dielectric layer 210.

[0093] Specifically, a first mask layer (not shown in the figure) with a first mask opening is formed on the first dielectric layer. Part of the first mask opening is located on the second region 140 and directly above the first initial conductive via 211, and part of the first mask opening is located on the first region 130. The width of the first mask opening is greater than the diameter of the first initial conductive via 211.

[0094] Please continue reading the appendix. Figure 6 Using the first mask layer as a mask, a portion of the thickness of the first dielectric layer 210 is removed by a second etching process to form a filling hole 240 in the first region 130 and a first hole segment 231 in the second region 140.

[0095] It should be noted that in this step, the first dielectric layer 210 located on the first region 130 is a full-surface structure, and the first initial conductive via 211 has been formed in the first dielectric layer 210 located on the second region 140. Therefore, under the same etching process, the etching rate of the first dielectric layer 210 on the first region 130 is less than the etching rate of the first dielectric layer 210 on the second region 140, so that the depth of the formed filling hole 240 is less than the depth of the first hole segment 231.

[0096] Furthermore, the diameter of the filling hole 240 can be the same as or different from the diameter of the first hole segment 231.

[0097] In this embodiment, the first mask layer is used as a mask to form the first hole segment 231 on the second region 140, while simultaneously forming the filling hole 240 in the first region 130. This reduces the difficulty of mask fabrication and lowers the manufacturing cost of the semiconductor structure.

[0098] In this embodiment, there are multiple first conductive vias 230, which are spaced apart within the first dielectric layer 210. The dimensions of each first conductive via 230 can be the same or different. For example, the size of the photomask and / or the etching parameters of the photolithography process can be adjusted so that the dimensions of each first mask opening in the first mask layer are the same, thereby making the dimensions of each first conductive via 230 the same (including the dimensions of the first hole segment and the second hole segment being the same) to maintain pattern consistency.

[0099] Step S300: A second dielectric layer is formed inside the first conductive via, and the second dielectric layer extends outside the first conductive via and covers the first dielectric layer.

[0100] Please refer to the attached document. Figure 7 For example, an atomic layer deposition process is used to form a second dielectric layer 220 on the first dielectric layer 210. In other words, the second dielectric layer 220 covers the inner wall of the first conductive via 230 and the top surface of the first dielectric layer 210.

[0101] The first dielectric layer 210 and the second dielectric layer 220 constitute the dielectric layer 200. The material of the first dielectric layer 210 is the same as that of the second dielectric layer 220. For example, the materials of the first dielectric layer 210 and the second dielectric layer 220 both include silicon oxide, but are not limited to this.

[0102] The second dielectric layer 220 has a second thickness, which is less than the first thickness. To clearly determine the thickness of the second dielectric layer 220, let's consider the attached... Figure 7 H2 is used as the second thickness.

[0103] For example, the second thickness H2 is in the range of 260nm to 300nm. This avoids the second dielectric layer 220 being too thick and completely filling the first conductive via 230, thus reducing the difficulty of removing the second dielectric layer 220 from the first conductive via 230.

[0104] In addition, it can prevent the thickness of the second dielectric layer 220 from being too small, thereby preventing the depth of the subsequently formed conductive vias from being too small and improving the conductivity of the interconnect structure.

[0105] Step S400: Remove the second dielectric layer located on the inner wall of the first conductive via. The remaining second dielectric layer forms a second conductive via that is connected to the first conductive via. The second conductive via and the first conductive via together form a conductive via, the structure of which is shown in the attached figure. Figure 9 As shown.

[0106] In this embodiment, a first dielectric layer 210 is first formed on the target layer 100, and the thickness of the first dielectric layer 210 is less than the preset thickness of the dielectric layer in related technologies. In this way, the aspect ratio of the subsequent first conductive via 230 in the first dielectric layer 210 can be reduced, so as to ensure that a more regular stepped first conductive via 230 can be formed.

[0107] Next, a second dielectric layer 220 of a certain thickness is formed, and the inner wall of the first conductive via 230 and the second dielectric layer 220 on the first conductive via 230 are removed to form a second conductive via 250 communicating with the first conductive via 230. The second conductive via 250 and the first conductive via 230 constitute a conductive via. In this way, the conductive via can be ensured to be a relatively regular stepped shape, thereby avoiding the formation of interconnect structures with holes and improving the performance of the semiconductor structure.

[0108] It should be noted that, in this embodiment, the second dielectric layer located in the first conductive via can be removed by a single etching process, or it can be formed by multiple etching processes.

[0109] Please refer to the attached document. Figure 8 For example, a third etching process is used to remove the second dielectric layer 220 located on the sidewall of the first hole segment 231 and the second dielectric layer 220 with at least a partial thickness located on the bottom wall of the first hole segment 231.

[0110] Please refer to the attached document. Figure 9 The second dielectric layer 220 located on the sidewall of the second hole segment 232 and the second dielectric layer 220 at the bottom of the second hole segment 232 are removed using a fourth etching process, so that the second dielectric layer 220 remaining on the first dielectric layer 210 forms a second conductive via 250. The second conductive via 250 communicates with the first hole segment 231, and their axes are collinear. Furthermore, the retained first dielectric layer 210 and second dielectric layer 220 constitute dielectric layer 200.

[0111] The etching process for forming the second conductive via 250 is dry etching. That is, the third and fourth etching processes can also be different. For example, the third and fourth etching processes can each independently include dry etching. Furthermore, the etching rates of the third and fourth etching processes are each independently 3-8 nm / s.

[0112] In this embodiment, the etching gas for dry etching may include at least one of C2F2, CF4, CH2F2, CHF3, and C4F6; wherein the atomic ratio of carbon to fluorine in the etching gas is 1:2 to 2:3. In a preferred embodiment, the etching gas for dry etching may include CF4 and CHF3.

[0113] In this embodiment, the etching gas used to etch the second conductive via 250 can be the same as the etching gas used to form the first conductive via 230, only the etching time is different. This simplifies the fabrication process of the conductive via.

[0114] In this embodiment, the first dielectric layer 210 and the second dielectric layer 220 are formed by two deposition processes, respectively, so that the thickness of the first dielectric layer 210 and the second dielectric layer 220 is smaller than the thickness of the dielectric layer in related technologies. In this way, the aspect ratio of the first conductive via 230 formed in the first dielectric layer 210 and the aspect ratio of the second conductive via 250 formed in the second dielectric layer 220 can be reduced, so as to ensure that the formed conductive vias are regular step-shaped.

[0115] Furthermore, the etching of the first conductive via 230 and the second conductive via 250 are both formed by two etching processes. That is, the dielectric layer 200 in this embodiment is formed by two depositions and conductive vias are formed in the dielectric layer 200 by four etching processes. In this way, the uniformity of etching the first conductive via 230 and the second conductive via 250 can be ensured, and damage to the step surface 233 between the first hole segment 231 and the second hole segment 232 can be reduced or avoided, thus maintaining the consistency of the pattern.

[0116] After this step, the dielectric layer remaining in the conductive via can be removed by sputtering to clean the inner wall of the conductive via and ensure the electrical performance of the interconnect structure formed subsequently.

[0117] Step S500: Form an interconnect structure within the conductive via. The interconnect structure can be formed by deposition or electroplating, and the material of the interconnect structure can include copper, tungsten, or a mixture thereof.

[0118] Please refer to the attached document. Figure 10 For example, a copper seed layer 400 (Cu Seed) is formed on the inner wall of a conductive via by a deposition process. Since the conductive via formed by the above process is a regular inverted convex shape with a larger top and a smaller bottom, the deposition process can ensure that the copper seed layer 400 adheres better to the inner wall of the conductive via, avoiding the formation of undulating morphology on the surface of the copper seed layer 400, thereby preventing the copper seed layer 400 from blocking the top of the second hole segment.

[0119] Next, please refer to the appendix. Figure 11 Conductive material is electroplated onto the copper seed layer using an electroplating process to form a conductive layer 500, wherein the conductive layer 500 fills the area enclosed by the copper seed layer 400. The conductive layer 500 and the copper seed layer 400 constitute an interconnect structure, and the material of the conductive layer 500 includes copper.

[0120] Given that the above process improves the shape of the conductive via, avoids the copper seed layer 400 from blocking the top of the second via segment, and thus avoids the formation of voids in the conductive layer 500, the resistance of the interconnect structure is reduced, and the performance of the semiconductor structure is improved.

[0121] In this process, the self-annealing effect of electroplating can be utilized to make the grains of the interconnect structure larger, which is beneficial to reducing the resistivity of the interconnect structure.

[0122] After the interconnect structure is formed, chemical mechanical polishing (CMP) can be performed on the top surface of the interconnect structure to planarize the top surface of the interconnect structure so that other components can be formed on the interconnect structure.

[0123] This disclosure also provides a semiconductor structure, which is formed by the semiconductor structure preparation method provided in the above embodiments. Therefore, the semiconductor structure has the beneficial effects of the above embodiments, and this embodiment will not be further limited here.

[0124] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0125] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0126] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A first dielectric layer with a first thickness is formed on the target layer, the first thickness being less than a preset thickness, the preset thickness being in the range of 740nm to 820nm; wherein, a semiconductor device is present within the target layer; A first conductive via is formed within the first dielectric layer to expose the semiconductor device. The first conductive via includes a first segment and a second segment. The second segment is located below the first segment and communicates with the first segment. The diameter of the second segment is smaller than the diameter of the first segment. A second dielectric layer is formed inside the first conductive via, and the second dielectric layer extends outside the first conductive via and covers the first dielectric layer; Remove the second dielectric layer located on the inner wall of the first conductive via. The remaining second dielectric layer forms a second conductive via that is connected to the first conductive via. The second conductive via and the first conductive via together form a conductive via. An interconnect structure is formed within the conductive via.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming a first conductive via within the first dielectric layer to expose the semiconductor device includes: A portion of the first dielectric layer is removed using a first etching process to form a first initial conductive via within the first dielectric layer; The top of the first initial conductive via is enlarged using a second etching process, so that the diameter of the top of the first initial conductive via is larger than the diameter of the bottom of the first initial conductive via. The enlarged first initial conductive via forms a first segment, and the unenlarged first initial conductive via forms a second segment.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The target layer has a first region and a second region connected to the first region, and both the first region and the second region have semiconductor devices. The steps of enlarging the top of the first initial conductive via using a second etching process include: A second etching process is used to form a filling hole on the first dielectric layer located in the first region, wherein the bottom of the filling hole does not expose the bottom surface of the first dielectric layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The steps of enlarging the top of the first initial conductive via using a second etching process include: A first mask layer with a first mask opening is formed on the first dielectric layer, a portion of the first mask opening is located on the second region and directly above the first initial conductive via; a portion of the first mask opening is located on the first region; wherein the width of the first mask opening is greater than the diameter of the first initial conductive via. Using the first mask layer as a mask, a portion of the thickness of the first dielectric layer is removed using a second etching process to form a filling hole in the first region and a first hole segment in the second region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The first etching process and the second etching process each independently include dry etching.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The etching rates of the first etching process and the second etching process are each 3-8 nm / s independently.

7. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, There are multiple first conductive vias, which are spaced apart within the first dielectric layer; wherein each first conductive via has the same size.

8. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, The second dielectric layer has a second thickness, which is less than the first thickness.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The first thickness is 480nm to 520nm; the second thickness is 260nm to 300nm.

10. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, The step of removing the second dielectric layer located on the inner wall of the first conductive via includes: The second dielectric layer located on the sidewall of the first hole segment and the second dielectric layer with at least a partial thickness located on the bottom wall of the first hole segment are removed using a third etching process. The second dielectric layer located on the sidewalls and bottom of the second hole segment is removed using a fourth etching process.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The third etching process and the fourth etching process each independently include dry etching.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The etching rates of the third and fourth etching processes are each independently 3-8 nm / s.

13. The method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, The step of forming an interconnect structure within the conductive via includes: A copper seed layer is formed on the inner wall of the conductive via; A conductive layer is formed on the copper seed layer, and the conductive layer fills the area enclosed by the copper seed layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, A conductive layer is formed within the area enclosed by the copper seed layer using an electroplating process, wherein the conductive layer is made of copper.

15. A semiconductor structure, characterized in that, The semiconductor structure is formed by the method for preparing the semiconductor structure according to any one of claims 1-14.

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