Semiconductor device including alignment pattern

Abstract

Semiconductor devices are provided. A semiconductor includes a bottom layer, a lower core layer spaced apart from the bottom layer in a vertical direction from a top surface of the bottom layer, wherein the lower core layer extends in a horizontal direction parallel to the top surface of the bottom layer, and wherein the lower core layer includes a plurality of lower segments spaced apart from each other in the horizontal direction, an upper core layer spaced apart from the lower core layer in the vertical direction, wherein the upper core layer extends in the horizontal direction, and wherein the upper core layer includes a plurality of upper segments spaced apart from each other in the horizontal direction, a pillar pattern penetrating the upper core layer and the lower core layer perpendicularly, a passivation layer surrounding the lower core layer, the upper core layer, and the pillar pattern, a coating layer surrounding the passivation layer, and a support pattern extending in the vertical direction and passing through the lower core layer, the upper core layer, the passivation layer, and the coating layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2022-0080451, filed on July 30, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention discloses a semiconductor device including an aligned pattern and a method for manufacturing the semiconductor device. Background Technology

[0003] As the integration level of semiconductor devices gradually increases, alignment patterns are also being improved, which brings challenges to manufacturing operations. Summary of the Invention

[0004] The embodiments disclosed in this invention provide an alignment pattern with a support pattern.

[0005] One aspect of this invention relates to a semiconductor device comprising an alignment pattern having a support pattern.

[0006] Another aspect of the present invention discloses a method for forming an alignment pattern having a support pattern.

[0007] Another aspect of the present invention discloses a method for manufacturing a semiconductor device including an alignment pattern having a support pattern.

[0008] According to some embodiments disclosed in this invention, a semiconductor device includes: a substrate; a lower core layer spaced apart from the substrate in a direction perpendicular to the top surface of the substrate, wherein the lower core layer extends in a horizontal direction parallel to the top surface of the substrate, and wherein the lower core layer includes a plurality of lower segments spaced apart from each other in the horizontal direction; an upper core layer spaced apart from the lower core layer in the vertical direction, wherein the upper core layer extends in the horizontal direction, and wherein the upper core layer includes a plurality of upper segments spaced apart from each other in the horizontal direction; a pillar pattern perpendicularly penetrating the upper core layer and the lower core layer; a passivation layer surrounding the lower core layer, the upper core layer and the pillar pattern; a coating layer surrounding the passivation layer; and a support pattern extending in the vertical direction and passing through the lower core layer, the upper core layer, the passivation layer and the coating layer.

[0009] According to some embodiments disclosed in this invention, a semiconductor device includes: an alignment pattern comprising: a bottom layer; a core layer including segments spaced apart from the bottom layer in a vertical direction, wherein the segments are individually divided in a horizontal direction; a passivation layer surrounding a surface of the core layer; a coating layer surrounding a surface layer of the passivation layer; a support pattern perpendicularly passing through the core layer, the passivation layer, and the coating layer; an overhang region between the bottom layer and the core layer; and a gap between the segments of the coating layer. The support pattern perpendicularly passes through the gap.

[0010] According to some embodiments disclosed in this invention, a semiconductor device includes an alignment pattern comprising sub-alignment patterns. The sub-alignment patterns are arranged in a pinwheel shape. Each sub-alignment pattern includes a plurality of unit alignment patterns arranged side-by-side. At least one unit alignment pattern includes a support pattern disposed therein.

[0011] According to some embodiments disclosed in this invention, a semiconductor device includes an underlayer; a barrier layer on the underlayer; a passivation layer on the barrier layer; a lower core layer formed within the passivation layer, the lower core layer including a plurality of lower segments extending in a horizontal direction parallel to the barrier layer and the underlayer; an upper core layer formed within the passivation layer, the upper core layer including a plurality of spaced-apart upper segments extending in the horizontal direction; at least one pillar pattern penetrating the upper core layer, the lower core layer and the passivation layer to expose the barrier layer, the at least one pillar pattern being configured to support at least one of the upper segments and the lower segments; a coating layer surrounding the surface of the passivation layer; and a support pattern including a plurality of lower support patterns and a plurality of upper support patterns perpendicularly passing through the lower core layer, the upper core layer, the passivation layer and the coating layer. Attached Figure Description

[0012] Figures 1A to 1D This is a plan view illustrating the alignment pattern of a semiconductor device according to an embodiment disclosed in the present invention.

[0013] Figures 2A to 2D It is along Figure 1A The longitudinal cross-sectional view taken by line I-I' is used to illustrate the alignment pattern of a semiconductor device according to some embodiments disclosed in the present invention.

[0014] Figures 3A to 3I It is along Figure 1A The longitudinal cross-sectional view taken by line I-I' is used to describe a method for forming an alignment pattern according to some embodiments disclosed in the present invention.

[0015] Figure 4A and Figure 4B It is along Figure 1A The longitudinal cross-sectional view taken by line I-I' is used to describe a method for forming an alignment pattern according to some embodiments disclosed in the present invention.

[0016] Figure 5A and Figure 5B It is along Figure 1A The longitudinal cross-sectional view taken by line I-I' is used to describe a method for forming an alignment pattern of a semiconductor device according to some embodiments disclosed in the present invention. Detailed Implementation

[0017] Various embodiments of the invention will be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same portions in the various drawings and embodiments of the invention.

[0018] It is understood that although the terms "first" and / or "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the teachings of this invention. Similarly, a second element may also be referred to as a first element.

[0019] Other expressions explaining the relationship between elements, such as “between…”, “directly between…”, “adjacent to…”, or “directly adjacent to…”, should be interpreted in the same way.

[0020] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the case where the first layer is formed directly on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or the substrate.

[0021] Figures 1A to 1D This is a plan view illustrating the alignment patterns 100A to 100D of a semiconductor device according to an embodiment of the present invention. See also Figures 1A to 1DThe alignment patterns 100A to 100D of the semiconductor device according to embodiments of the present invention may include four sub-alignment patterns 21 to 24, which are arranged in a pinwheel shape in a first direction D1 and a second direction D2, respectively. The four sub-alignment patterns 21 to 24 may be arranged in a clockwise order. For example, the first sub-alignment pattern 21 may be located in the upper right position, the second sub-alignment pattern 22 in the lower right position, the third sub-alignment pattern 23 in the lower left position, and the fourth sub-alignment pattern 24 in the upper left position. Each of the sub-alignment patterns 21 to 24 may include a plurality of rectangular frame-type unit alignment patterns 31 arranged side-by-side. In each of the sub-alignment patterns 21 to 24, the unit alignment patterns 31 may be arranged parallel to each other. For example, the first sub-alignment pattern 21 may include a plurality of unit alignment patterns 31, each unit alignment pattern 31 having a rectangular frame (the long side extending in the second direction D2) and arranged parallel to each other in the first direction D1. The second sub-alignment pattern 22 may include a plurality of cell alignment patterns 31, each cell alignment pattern 31 having a rectangular frame (its long side extending in the first direction D1) and arranged parallel to each other in the second direction D2. The third sub-alignment pattern 23 may include a plurality of cell alignment patterns 31, each cell alignment pattern 31 having a rectangular frame (its long side extending in the second direction D2) and arranged parallel to each other in the first direction D1. The fourth sub-alignment pattern 24 may include a plurality of cell alignment patterns 31, each cell alignment pattern 31 having a rectangular frame (its long side extending in the first direction D1) and arranged parallel to each other in the second direction D2. The first direction D1 and the second direction D2 may be perpendicular to each other. For example, the first direction D1 may be a direction toward a cell region of the semiconductor chip, and the second direction D2 may be a direction extending along a scribe line. Alignment patterns 100A to 100D may be disposed in a scribe line of a semiconductor wafer. In some embodiments, alignment patterns 100A to 100D may include a vernier key pattern.

[0022] See Figure 1AAccording to an embodiment of the present invention, the unit alignment pattern 31 of the sub-alignment patterns 21 to 24 of the alignment pattern 100A of the semiconductor device may include a strip support pattern 35a. The strip support patterns 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 may be formed in the unit alignment pattern 31. The strip support patterns 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 may be arranged side-by-side in a first direction D1. The strip support patterns 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 may have an elongated shape, having a long side extending in a second direction D2. That is, the short side direction of the strip support patterns 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 may extend in the first direction D1, and the long direction of the strip support patterns 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 may extend in the second direction D2.

[0023] The strip support patterns 35a of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 can be formed in the unit alignment pattern 31. The strip support patterns 35a of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 can be arranged side by side in the second direction D2. The strip support patterns 35a of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 can have an elongated shape, with a long side extending in the first direction D1. That is, the short side direction of the strip support patterns 35a of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 can extend in the second direction D2, and the long direction of the strip support patterns 35a of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 can extend in the first direction D1.

[0024] See Figure 1BAccording to some embodiments of the semiconductor device disclosed herein, the unit alignment pattern 31 of the sub-alignment patterns 21 to 24 of the alignment pattern 100B may optionally include one of a strip support pattern 35a and a square support pattern 35b. The strip support pattern 35a may have an elongated shape, having a long side and a short side, and the square support pattern 35b may have four sides of similar length. For example, the unit alignment pattern 31 of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 may include the strip support pattern 35a. The second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 of the unit alignment pattern 31 may include the square support pattern 35b. The strip support pattern 35a may be formed to extend in a second direction D2 in the unit alignment pattern 31 of the first sub-alignment pattern 21 and the third sub-alignment pattern 23. The square support pattern 35b may be arranged in the unit alignment pattern 31 to be spaced apart from each other in an island structure. The square support pattern 35b may be formed in the unit alignment pattern 31 of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 and arranged in a first direction D1. The strip support pattern 35a can substantially completely fill the interior of the unit alignment pattern 31, and the square support pattern 35b can partially fill the interior of the unit alignment pattern 31. In some embodiments, the strip support pattern 35a can partially fill the interior of the unit alignment pattern 31.

[0025] See Figure 1C According to some embodiments of the semiconductor device disclosed herein, the alignment pattern 31 of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 of the alignment pattern 100C may include a strip support pattern 35a. Figure 1A and Figure 1B In contrast, any of the support patterns 35a and 35b may not be formed in the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24.

[0026] Figures 1A to 1C The strip support pattern 35a can block and mitigate cracks. For example, the strip support pattern 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 can be perpendicular to the first direction D1 (i.e., the cell region direction of the semiconductor chip). Therefore, as described above, the strip support pattern 35a of the first sub-alignment pattern 21 and the third sub-alignment pattern 23 can block and mitigate cracks toward the cell region of the semiconductor chip, and the strip support pattern 35a of the second sub-alignment pattern 22 and the fourth sub-alignment pattern 24 can block and mitigate cracks along the scribe lines of the semiconductor chip.

[0027] See Figure 1D According to some embodiments of the present invention, the cell alignment pattern 31 in the sub-alignment patterns 21 to 24 of the alignment pattern 100D of the semiconductor device may include a square support pattern 35b. Figure 1B and Figure 1DThe square support pattern 35b shown can prevent the unit alignment pattern 31 from collapsing.

[0028] Figures 2A to 2D It is along Figure 1A A longitudinal cross-sectional view taken along line I-I' is shown to illustrate the alignment pattern of a semiconductor device according to some embodiments disclosed in the present invention. See also Figure 2A The alignment pattern of a semiconductor device according to some embodiments of the present invention may include: a bottom layer 40, a barrier layer 45, a core layer 50, a pillar pattern 60, a passivation layer 70, a coating layer 75, a support pattern 80A, and a covering insulating layer 90. The alignment pattern may also include suspended regions S1 and S2 therein. The suspended regions S1 and S2 may be spatially defined as being surrounded by the coating layer 75 and the support pattern 80A.

[0029] The bottom layer 40 may include one of a semiconductor substrate, an interlayer insulating layer, an etch stop layer, a planarization layer, or other insulating material layers. In some embodiments, the bottom layer 40 may include a conductive layer, such as a metal layer or a metal composite layer. In some embodiments, the bottom layer 40 may be disposed at the same level as the memory contact or landing pad of a DRAM cell.

[0030] The barrier layer 45 may be formed on the base layer 40 and is planar. The barrier layer 45 may include at least one barrier metal layer or barrier insulating layer. In some embodiments, the barrier metal layer may include at least one of a titanium (Ti) layer, a titanium nitride (TiN) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, or a tungsten nitride (WN) layer. In some embodiments, the barrier insulating layer may include an inorganic layer, such as a silicon nitride (SiN) layer or an oxygen-free silicon carbon nitride (SiCN) layer.

[0031] The core layer 50 may include a lower core layer 51 and an upper core layer 52 located on the lower core layer. The lower core layer 51 and the upper core layer 52 may extend horizontally and may be spaced apart from each other vertically. The barrier layer 45 and the lower core layer 51 may be spaced apart from each other vertically. A lower slack region S1 may be formed between the barrier layer 45 and the lower core layer 51. The lower core layer 51 and the upper core layer 52 may also be spatially separated. An upper slack region S2 may be formed between the lower core layer 51 and the upper core layer 52. In one embodiment, the lower core layer 51 and the upper core layer 52 may be discontinuous. For example, the lower core layer 51 may have a plurality of lower segments spaced apart from each other horizontally. The lower core layer 51 and the upper core layer 52 may each have a plurality of upper segments spaced apart from each other horizontally. The core layer 50 may include an inorganic layer, such as a silicon nitride (SiN) layer. The lower core layer 51 and the upper core layer 52 may have substantially the same planar structure. The core layer 50 may include an opaque material.

[0032] The pillar pattern 60 can vertically penetrate the core layer 50 and the passivation layer 70. The pillar pattern 60 can support the core layer 50 to prevent it from collapsing. The pillar pattern 60 can include a material with etch selectivity relative to the core layer 50 and silicon oxide (SiO2). For example, the pillar pattern 60 can include polysilicon, silicon germanium (SiGe), silicon nitride (SiN), or a metal-based material. The pillar pattern 60 can be pillar-shaped. In some embodiments, the pillar pattern 60 can be formed into a wall shape. The pillar pattern 60 can be opaque.

[0033] A passivation layer 70 may be conformally formed on the surfaces of the barrier layer 45, the core layer 50, and the pillar pattern 60. The passivation layer 70 may comprise polysilicon. The passivation layer 70 may provide spacing between the core layers 50. The passivation layer 70 may provide volume for the empty regions S1 and S2. The passivation layer 70 may comprise silicon germanium (SiGe). By controlling the volume of the passivation layer 70, the spacing between the core layers 50 can be adjusted. Furthermore, by controlling the volume of the passivation layer 70, the volumes of the empty regions S1 and S2 can also be adjusted. The passivation layer 70 may be opaque.

[0034] The coating layer 75 may be conformally formed on the surface of the passivation layer 70. The coating layer 75 may reflect light. For example, the coating layer 75 may include a metal layer or a metal nitride layer. In some embodiments, the coating layer 75 may include tungsten nitride (WN). In some embodiments, the coating layer 75 may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten (W). A plurality of gaps G1 and G2 may be defined by the passivation layer 70 and the coating layer 75. For example, the horizontal width of the lower gap G1 may be defined by the coating layer 75 surrounding a segment of the passivation layer 70 spaced apart from each other in the horizontal direction of the lower core layer 51. The horizontal width of the upper gap G2 may be defined by the coating layer 75 surrounding a segment of the passivation layer 70 spaced apart from each other in the horizontal direction of the upper core layer 52. The lower gap G1 may be located at the same level as the lower core layer 51. The upper gap G2 may be located at the same level as the upper core layer 52.

[0035] The support pattern 80A can pass vertically through the upper gap G2 and the lower gap G1 to be located on the barrier layer 45 of the bottom layer 40. That is, the support pattern 80A can pass vertically through the lower core layer 51, the upper core layer 52, the passivation layer 70, and the coating layer 75. The support pattern 80A may include a plurality of lower support patterns 81, a plurality of intermediate support patterns 82, and an upper support pattern 83A.

[0036] Each lower support pattern 81 may include a lower part and an upper part. The lower part of each lower support pattern 81 may spatially and horizontally separate the lower support area S1. The upper part of each lower support pattern 81 may be located in the lower gap G1.

[0037] Each lower support pattern 81 may be in the shape of a column or wall extending from the lower overhead area S1 to the lower gap G1. The lower portion of each lower support pattern 81 may have a relatively wide width, and the upper portion may have a relatively narrow width. That is, the horizontal width of the lower portion of each lower support pattern 81 may be wider than the horizontal width of the upper portion. For example, each lower support pattern 81 may have a trapezoidal longitudinal cross-section. Each lower support pattern 81 may contact the coating layer 75 surrounding the passivation layer 70 of the lower core layer 51 in the lower gap G1.

[0038] Each intermediate support pattern 82 may include a lower portion located in the lower gap G1 and an upper portion located in the upper gap G2. Each intermediate support pattern 82 may have a column shape or a wall shape extending from the upper portion of the lower gap G1 to the lower portion of the upper gap G2. Each intermediate support pattern 82 may be cross-shaped in a side view. Each intermediate support pattern 82 may have a wall shape extending from the front side to the rear side of the figure. For example, each intermediate support pattern 82 may have a wall shape extending from the left side to the right side in the left side of the right side view. Each intermediate support pattern 82 may spatially and horizontally divide the overhead area S2. The lower portion of each intermediate support pattern 82 may be located in the lower gap G1. The upper portion of each intermediate support pattern 82 may be located in the upper gap G2. Each intermediate support pattern 82 may have a convex central portion. For example, each intermediate support pattern 82 may have a side portion that laterally protrudes into the upper overhead area S2. The lower portion of each intermediate support pattern 82 may contact the coating layer 75 surrounding the passivation layer 70 of the lower core layer 51 in the lower gap G1. The upper portion of each intermediate support pattern 82 may contact the coating layer 75 surrounding the passivation layer 70 of the upper core layer 52 in the upper gap G2. The lower support pattern 81 and the intermediate support pattern 82 may comprise the same material. Therefore, an interface may actually exist between the lower support pattern 81 and the intermediate support pattern 82. That is, the lower support pattern 81 and the intermediate support pattern 82 may substantially continue.

[0039] The upper support pattern 83A may include a lower portion located in the upper gap G2 and an upper portion on the upper surface of the coating layer 75 disposed around the passivation layer 70 surrounding the upper core layer 52. The lower portion of the upper support pattern 83A may have a column shape or a wall shape, and the upper portion of the upper support pattern 83A may have a bridge shape or a plate shape, extending horizontally over the coating layer 75 surrounding the passivation layer 70 surrounding the upper core layer 52. The intermediate support pattern 82 and the upper support pattern 83A may include the same material. Therefore, an interface may actually exist between the intermediate support pattern 82 and the upper support pattern 83A. That is, the intermediate support pattern 82 and the upper support pattern 83A may be substantially continuous.

[0040] An insulating layer 90 may be formed on the upper support pattern 83A and the coating layer 75 to cover the upper support pattern 83A. The insulating layer 90 may include an inorganic insulating material layer, such as a silicon oxide (SiO2) layer.

[0041] See Figure 2B The alignment pattern of a semiconductor device according to some embodiments of the present invention may include: a bottom layer 40, a barrier layer 45, a core layer 50, a pillar pattern 60, a passivation layer 70, a coating layer 75, a support pattern 80B, and a covering insulating layer 90. The alignment pattern may also include overhead regions S1 and S2 therein. The support pattern 80B may include: a plurality of lower support patterns 81, a plurality of intermediate support patterns 82, and a plurality of upper support patterns 83B. The upper support pattern 83B may have a pillar shape or a wall shape. The upper support pattern 83B may include a plurality of lower portions and a plurality of upper portions, each lower portion having a narrow horizontal width and each upper portion having a wide horizontal width. The lower portions of the upper support pattern 83B may be located in the upper gap G2. Figure 2A In contrast, in the top or side view, the upper support pattern 83B can have the shape of multiple islands or multiple squares, arranged in a lattice shape that does not extend in any horizontal direction. Therefore, the support pattern 80B can have multiple pillars or walls extending downward to the bottom layer 40 through the upper gap G2 and the lower gap G1.

[0042] Referring to 2C, the alignment pattern of a semiconductor device according to some embodiments of the present invention may include: a bottom layer 40, a barrier layer 45, a core layer 50, a pillar pattern 60, a passivation layer 70, a coating layer 75, a support pattern 80C, and a covering insulating layer 90. The alignment pattern may also include overhead regions S1 and S2 therein. The support pattern 80C may include a plurality of lower support patterns 81 and a plurality of intermediate support patterns 82. Figure 2A and Figure 2B In contrast, the upper support patterns 83A and 83B can be omitted. The covering insulating layer 90 can completely fill the upper gap G2.

[0043] Referring to 2D, the alignment pattern of a semiconductor device according to some embodiments of the present invention may include: a bottom layer 40, a barrier layer 45, a core layer 50, a pillar pattern 60, a passivation layer 70, a coating layer 75, a support pattern 80C, and a covering insulating layer 90. The support pattern 80C may include a plurality of lower support patterns 81 and a plurality of intermediate support patterns 82. Figure 2C In contrast, multiple gaps V can be formed between the middle support pattern 82 and the upper end of the covering insulation layer 90.

[0044] Figures 3A to 3I It is along Figure 1A The longitudinal cross-sectional view taken by line I-I' is used to describe a method for forming an alignment pattern according to some embodiments disclosed in the present invention.

[0045] See Figure 3A According to some embodiments of the present invention, a method for forming an alignment pattern may include: forming a barrier layer 45 on a bottom layer 40, forming a lower sacrificial layer 46 on the barrier layer 45, forming a lower core layer 51 on the lower sacrificial layer 46, forming an upper sacrificial layer 47 on the lower core layer 51, and forming an upper core layer 52 on the upper sacrificial layer 47. The bottom layer 40 may include one of a semiconductor substrate, an interlayer insulating layer, an etch stop layer, a planarization layer, a metal layer, or other insulating material layer. Forming the barrier layer 45 may include forming a barrier metal layer or a barrier insulating layer on the bottom layer 40 by performing a deposition process. The barrier metal layer may include forming a titanium (Ti) layer, a titanium nitride (TiN) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, or a tungsten nitride (WN) layer. The barrier insulating layer may include an oxygen-free inorganic material, such as silicon nitride (SiN) or silicon carbonitride (SiCN). Forming the lower sacrificial layer 46, lower core layer 51, upper sacrificial layer 47, and upper core layer 52 may include forming inorganic layers by performing a deposition process such as chemical vapor deposition (CVD). The lower sacrificial layer 46 and upper sacrificial layer 47 may include the same material. For example, the lower sacrificial layer 46 and upper sacrificial layer 47 may include silicon oxide layers. The lower core layer 51 and upper core layer 52 may include the same material. For example, the lower core layer 51 and upper core layer 52 may include silicon nitride. The sacrificial layers 46 and 47 may have etch selectivity relative to the core layers 51 and 52.

[0046] See Figure 3B The method may further include forming an aperture H. The aperture H can be formed by performing photolithography and etching processes. The aperture H can vertically penetrate sacrificial layers 46 and 47 and core layers 51 and 52 to expose the barrier layer 45. In a top view, the aperture H can have a trench shape extending in a horizontal direction. In some embodiments, in a top view, the aperture H can have a circular shape. In some embodiments, in a top view, the aperture H can have a polygonal shape.

[0047] See Figure 3C The method may further include forming a pillar pattern 60 in the H-holes. Forming the pillar pattern 60 may include performing a deposition process and a planarization process. The planarization process may include an etch-back process or a CMP (chemical mechanical process) process. The pillar pattern 60 may include a material with etch selectivity relative to the sacrificial layers 46 and 47 and the core layers 51 and 52. For example, the pillar pattern 60 may include polysilicon (polysilicon), silicon-germanium (SiGe), or a metal-based material.

[0048] See Figure 3D The method may further include forming slots SL. Forming slots SL may include performing a selective etching process. Slots SL may penetrate vertically through sacrificial layers 46 and 47 and core layers 51 and 52 to expose barrier layer 45. In a top view, each slot SL may have a strip shape. Core layers 51 and 52 may be divided and formed into multiple segments, which are horizontally spaced apart from each other by slots.

[0049] See Figure 3E The method may further include removing sacrificial layers 46 and 47 through gaps SL. Removing sacrificial layers 46 and 47 may include performing a wet etching process to form slack regions S1 and S2 and first initial gaps G1p1 and G2p1. The surfaces of segments of core layers 51 and 52 and the surface of pillar pattern 60 may be exposed in slack regions S1 and S2. Slack regions S1 and S2 may include a lower slack region S1 between a barrier layer 45 on the bottom layer 40 and a lower core layer 51, and an upper slack region S2 between a segment of the lower core layer 51 and a segment of the upper core layer 52. The first initial gaps G1p1 and G2p1 may include a first lower initial gap G1p1 between segments of the lower core layer 51 and a first upper initial gap G2p1 between segments of the upper core layer 52. In other words, the first lower initial gap G1p1 can each have a horizontal width defined by a segment of the lower core layer 51, and the horizontal width of the first upper initial gap G2p1 can be defined by a segment of the upper core layer 52. For example, the first lower initial gap G1p1 can have a horizontal width defined by the distance between consecutive lower segments of the lower core layer 51, and the horizontal width of the first upper initial gap G2p1 can be defined by the distance between consecutive upper segments of the upper core layer 52.

[0050] See Figure 3FThe method may further include forming a passivation layer 70 on the surface of the segments of core layers 51 and 52 exposed in the overhead regions S1 and S2, and on the surface of the pillar pattern 60. Forming the passivation layer 70 may include performing a deposition process to form a silicon layer or a silicon-germanium layer, such as CVD or atomic layer deposition (ALD). The passivation layer 70 may be formed on the surface of the barrier layer 45, the pillar pattern 60, the segments of the lower core layer 51, and the segments of the core layer 52 on the bottom layer 40. The first lower initial gap G1p1 may be changed to a second lower initial gap G1p2 narrowed by the passivation layer 70 surrounding the lower segment, and the first upper initial gap G2p1 may be changed to a second upper initial gap G2p2 narrowed by the passivation layer 70 surrounding the upper segment. That is, the horizontal width of the second lower initial gap G1p2 may be defined by the passivation layer 70 on the surface of the lower core layer 51, and the horizontal width of the second upper initial gap G2p2 may be defined by the passivation layer 70 on the surface of the upper core layer 52.

[0051] See Figure 3G The method may further include conformally forming a coating layer 75 on the surface of the passivation layer 70. Forming the coating layer 75 may include performing a deposition process such as CVD or ALD to form at least one of a tungsten (W) layer, a tungsten nitride (WN) layer, a titanium (Ti) layer, a titanium nitride (TiN) layer, or a layer of various metal nitrides. A second lower initial gap G1p2 may be formed as a lower gap G1 narrowed by the coating layer 75, and a second upper initial gap G2p2 may be formed as an upper gap G2 narrowed by the coating layer 75. That is, the horizontal width of the lower gap G1 may be defined by the coating layer 75 on the surface of the passivation layer 70 (on the surface of the lower core layer 51), and the horizontal width of the upper gap G2 may be defined by the coating layer 75 on the surface of the passivation layer 70 (on the surface of the upper core layer 52).

[0052] See Figure 3H The method may further include forming a mask pattern M having an opening Op exposing the upper gap G2. Forming the mask pattern M may include forming an inorganic pattern, such as a silicon oxide (SiO2) pattern or a silicon nitride (SiN) pattern, by performing photolithography and etching processes. In some embodiments, the mask pattern M may include a polymeric organic material, such as a photoresist.

[0053] See Figure 3IThe method may further include forming a support pattern 80A through an opening Op. Forming the support pattern 80A may include filling the voids S1 and S2 and the gaps G1 and G2 with metal by performing a deposition process such as PVD. For example, the support pattern 80A may include a metal such as tungsten (W). In some embodiments, the support pattern 80A may include an inorganic insulating material such as silicon nitride (SiN). The support pattern 80A may partially fill the lower void S1 and the upper void S2. The support pattern 80A may completely fill the lower gap G1 and the upper gap G2. The mask pattern M may then be removed. In some embodiments, the mask pattern M may be retained instead of being removed. See hereafter. Figure 2A The method may also include forming a covering insulating layer 90. Forming the covering insulating layer 90 may include forming an inorganic material, such as silicon oxide (SiO2), by performing a deposition process.

[0054] Figure 4A and Figure 4B It is along Figure 1A The longitudinal cross-sectional view taken along line I-I' is used to describe a method for forming an alignment pattern according to some embodiments disclosed in the present invention. See also Figure 4A The method for forming an alignment pattern for a semiconductor device according to some embodiments of the present invention may include performing a reference... Figures 3A to 3H The process described is to form a mask pattern M with an opening Op, thereby exposing the upper gap G2.

[0055] See Figure 4B The method may further include forming a support pattern 80B through an opening Op. The support pattern 80B may have a column shape or a wall shape extending from the front to the rear of the figure. The support pattern 80B may have a wall shape extending from the left to the right in the left side of the right-hand view. The support pattern 80B may include a plurality of lower support patterns 81, a plurality of intermediate support patterns 82, and a plurality of upper support patterns 83B. Each lower support pattern 81 may include a lower portion with a wider horizontal width and an upper portion with a narrower horizontal width. Each intermediate support pattern 82 may have a convex central portion.

[0056] Figure 5A and Figure 5B It is along Figure 1A A longitudinal cross-sectional view taken along line I-I' is provided to illustrate a method for forming an alignment pattern for a semiconductor device according to an embodiment of the present invention. See also Figure 5A The method for forming an alignment pattern for a semiconductor device according to some embodiments of the present invention may include performing a reference... Figures 3A to 3H The described process forms a support pattern 80C. The support pattern 80C may include a plurality of lower support patterns 81 and a plurality of intermediate support patterns 82. Forming the support pattern 80C may include performing a reference... Figure 3I The process described involves forming a mask pattern M with an opening Op exposing the upper gap G, and ensuring that the uppermost end of the intermediate support pattern 82 of the support pattern 80C is positioned at the same or lower level as the upper core layer 52. See thereafter. Figure 2C The method may also include forming a covering insulating layer 90.

[0057] See Figure 5B The method for forming an alignment pattern for a semiconductor device according to some embodiments of the present invention may include performing a reference... Figures 3A to 3H and Figure 4A The described process forms a support pattern 80C. The support pattern 80C may include a plurality of lower support patterns 81 and a plurality of intermediate support patterns 82. Forming the support pattern 80C may include performing a reference... Figure 3I The process involves forming a mask pattern M with multiple openings Op that respectively expose the upper gap G, and positioning the uppermost end of the intermediate support pattern 82 of the support pattern 80C at the same or lower level as the upper core layer 52. See thereafter. Figure 2D The method may further include forming a covering insulating layer 90. A void V may be formed between the upper end of the support pattern 80C and the covering insulating layer 90.

[0058] According to the embodiments disclosed in this invention, since the semiconductor device includes an alignment pattern with a support pattern, physical damage to the alignment pattern can be prevented.

[0059] The support pattern disclosed in the embodiments of the present invention can prevent crack formation, slow crack propagation and expansion, or prevent cracks from forming at the source of a semiconductor chip.

[0060] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various other embodiments or variations and modifications thereof can be made without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: Alignment pattern, the alignment pattern including: bottom layer; A lower core layer, which is spaced apart from the bottom layer in a direction perpendicular to the top surface of the bottom layer, wherein the lower core layer extends in a horizontal direction parallel to the top surface of the bottom layer, and wherein the lower core layer includes a plurality of lower segments spaced apart from each other in the horizontal direction. An upper core layer, which is spaced apart from the lower core layer in the vertical direction, wherein the upper core layer extends in the horizontal direction, and wherein the upper core layer includes a plurality of upper segments spaced apart in the horizontal direction; A column pattern that vertically penetrates the upper core layer and the lower core layer; A passivation layer surrounding the lower core layer, the upper core layer, and the column pattern; A coating layer surrounding the passivation layer; and A support pattern extends in the vertical direction and passes through the lower core layer, the upper core layer, the passivation layer, and the coating layer.

2. The semiconductor device according to claim 1, wherein, The alignment pattern further includes: The lower overhead area is defined between the bottom layer and the lower core layer; The upper elevated area is defined between the lower core layer and the upper core layer; A lower gap, disposed between the plurality of lower segments of the lower core layer, wherein the lower gap is defined by a coating layer surrounding the passivation layer of the lower core layer; and An upper gap is disposed between the plurality of upper segments of the upper core layer, wherein the upper gap is defined by the coating layer surrounding the passivation layer of the upper core layer.

3. The semiconductor device according to claim 2, in, The support pattern includes: Lower support pattern, located in the lower overhead area and extending into the lower gap; and An intermediate support pattern is located on the lower support pattern and extends into the upper gap.

4. The semiconductor device according to claim 3, in, The lower support pattern includes: The lower part, which is located in the lower overhead area; and The upper part, which is located in the lower gap, The intermediate support pattern includes: The lower part, which is located in the lower gap; and The upper part is located in the upper gap.

5. The semiconductor device according to claim 3, wherein, The lower support pattern and the middle support pattern are made of the same material.

6. The semiconductor device according to claim 3, wherein, The alignment pattern further includes: Upper support pattern, including: The lower part, which is located in the upper gap; and The upper part is located on the coating layer surrounding the passivation layer of the upper core layer and extends in the horizontal direction.

7. The semiconductor device according to claim 2, The horizontal width of the lower gap is defined by the coating layer surrounding the passivation layer of the lower segment of the lower core layer, and The horizontal width of the upper gap is defined by the coating layer surrounding the passivation layer of the upper segment of the upper core layer.

8. The semiconductor device according to claim 1, wherein, The alignment pattern further includes: A barrier layer, which is on the underlying layer, in: The underlying layer comprises at least one metal and a metal compound, and The barrier layer includes at least one of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, and silicon nitride.

9. The semiconductor device according to claim 1, wherein, The lower core layer and the upper core layer comprise silicon nitride.

10. The semiconductor device according to claim 1, wherein, The column pattern comprises a material with etching selectivity relative to the lower core layer and the upper core layer.

11. The semiconductor device according to claim 1, wherein, The coating layer includes a reflective material.

12. The semiconductor device according to claim 1, wherein, At least one of the lower core layer, the upper core layer, and the passivation layer comprises an opaque material.

13. The semiconductor device according to claim 1, wherein, The alignment pattern further includes: An insulating layer is applied over the coating layer surrounding the support pattern and the passivation layer of the upper core layer.

14. The semiconductor device according to claim 13, wherein, The alignment pattern further includes: The gap is located between the upper end of the support pattern and the covering insulation layer.

15. A semiconductor device, comprising: Alignment pattern, the alignment pattern including: bottom layer; The core layer includes segments that are vertically spaced from the bottom layer, wherein the segments are separately divided in the horizontal direction; A passivation layer that surrounds the surface of the core layer; A coating layer that surrounds the surface of the passivation layer; A support pattern that extends vertically through the core layer, the passivation layer, and the coating layer; An elevated area, located between the bottom layer and the core layer; and The gaps, which are between sections of the coating layer, The support pattern passes vertically through the gap.

16. A semiconductor device, comprising: Alignment pattern, the alignment pattern including: bottom layer; A barrier layer, which is on the underlying layer; A passivation layer on the barrier layer; A lower core layer is formed inside the passivation layer, the lower core layer comprising a plurality of lower segments extending in a horizontal direction parallel to the barrier layer and the bottom layer; An upper core layer is formed inside the passivation layer, the upper core layer comprising a plurality of spaced upper segments extending in the horizontal direction; At least one column pattern that penetrates the upper core layer, the lower core layer and the passivation layer to expose the barrier layer, and the at least one column pattern is configured to support at least one of the upper segment and the lower segment; A coating layer surrounding the surface of the passivation layer; and The support pattern includes a plurality of lower support patterns and a plurality of upper support patterns that pass vertically through the lower core layer, the upper core layer, the passivation layer and the coating layer.

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