Vertical charge transfer imaging sensor and method of forming the same

Abstract

The present application relates to a kind of vertical charge transfer imaging sensor and its forming method.In the vertical charge transfer imaging sensor, deep trench isolation penetrates substrate and defines first number of pixel region and second number of common substrate region between pixel region in substrate, polysilicon layer conformal covers substrate and deep trench isolation from substrate back, the polysilicon layer is electrically connected with the substrate of each pixel region and common substrate region, gate structure is formed on the surface of pixel region, and it is with the pixel region below and constitutes MOS capacitor, the substrate end voltage of MOS capacitor is applied to common substrate region from substrate front side, it is transmitted to the substrate of each pixel region by common substrate region and polysilicon layer, so that metal electrode does not need to be formed on substrate back, can avoid the problem of high interface defect and large contact resistance when metal electrode is formed on substrate back, and the thickness uniformity of polysilicon layer is good, it is helpful to the voltage of the substrate of each pixel region balancedly applied.

Description

Technical Field

[0001] This invention relates to the field of photosensitive technology, and more particularly to a vertical charge transfer imaging sensor and a method for forming a vertical charge transfer imaging sensor. Background Technology

[0002] Vertically charge-transferring pixel sensors are image sensors that use a substrate and a floating gate transistor structure to achieve imaging. Figure 1 This is a planar schematic diagram of a vertical charge transfer imaging sensor. Figure 2 It is along Figure 1 A schematic cross-sectional view of the vertical charge transfer imaging sensor in the XX' direction. (Refer to...) Figure 1 and Figure 2 A vertical charge transfer imaging sensor typically includes multiple pixels formed on a substrate 10. Each pixel includes a photosensitive region 11 and a charge readout region 12 formed in the substrate 10 and separated by a shallow trench isolation (STI). It also includes a gate structure formed on the photosensitive region 11 and the charge readout region 12. The gate structure includes a gate dielectric layer, a floating gate FG, an inter-gate dielectric layer, and a control gate CG stacked sequentially on the substrate 10. Each pixel also includes a source region S and a drain region D formed on the charge readout region 12 and located on either side of the control gate (CG). In this vertical charge transfer imaging sensor, the gate structure and the photosensitive region 11 below it constitute a MOS capacitor, where the control gate (CG) and the substrate 10 of the photosensitive region 11 are the two electrodes of the MOS capacitor. The gate structure, along with the source region S and the drain region D, constitute a readout transistor. The photosensitive mechanism of the vertical charge transfer imaging sensor is as follows: light enters the substrate 10 from the side away from the gate structure and collides with the substrate lattice to generate photoelectrons. When a suitable bias voltage is applied to the MOS capacitor, the photoelectrons can move toward the control gate CG and gather on the surface of the photosensitive area 11 or cross the potential barrier to enter the floating gate (FG), thereby causing a change in the drain current and / or threshold voltage of the readout transistor. By detecting this change, photoelectric sensing and imaging can be realized.

[0003] Compared to traditional photodiode-based sensors (such as CMOS image sensors), vertical charge transfer imaging sensors can achieve higher full-well charge at the same pixel size, resulting in a higher signal-to-noise ratio and a significant advantage in pixel miniaturization.

[0004] To avoid crosstalk between different pixels, such as Figure 2As shown, currently, adjacent pixels are physically isolated by forming a deep trench isolation (DTI) that penetrates through the substrate 10. In order to facilitate the application of voltage to the substrate 10, which serves as the electrode of the MOS capacitor, a metal electrode 13 is embedded in the region between the pixels on the back side of the substrate 10. Part of the surface of the metal electrode 13 is in direct contact with the substrate 10, and another part of the surface is covered by a high dielectric constant layer 14. The high dielectric constant layer 14 is also formed on the back side of the substrate 10 around the metal electrode 13.

[0005] However, the surface of the metal electrode 13 disposed on the back side of the substrate 10 is in direct contact with the substrate 10, resulting in high interface defects and high contact resistance. Moreover, the process of forming the back side structure of the substrate is complex, which will increase the manufacturing cost of the vertical charge transfer imaging sensor. Summary of the Invention

[0006] In order to achieve effective isolation between pixels while avoiding the problems of high interface defects and high contact resistance that exist when forming metal electrodes on the back side of the substrate, the present invention provides a vertical charge transfer imaging sensor and a method for forming the same.

[0007] On one hand, the present invention provides a vertical charge transfer imaging sensor, the vertical charge transfer imaging sensor comprising:

[0008] A substrate having a first doping type and including a front side and a back side opposite to each other, wherein deep trench isolation and shallow trench isolation are formed in the substrate, wherein the cross-section of the deep trench isolation is a grid structure, at least a portion of the deep trench isolation is exposed on the back side of the substrate, the deep trench isolation defines a first number of pixel regions and a second number of common substrate regions located between the first number of pixel regions in the substrate, and the shallow trench isolation is formed on the front side of the substrate of each pixel region and defines a photosensitive area and a charge readout area;

[0009] A polysilicon layer conformally covers the substrate from the back side of the substrate and isolates it from the deep trench; the polysilicon layer is electrically connected to the substrate of each pixel region and the common substrate region; and

[0010] A gate structure is formed on the surface of the pixel region, and the gate structure and the pixel region below it constitute a MOS capacitor, wherein the substrate voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

[0011] Optionally, the gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surfaces of the photosensitive area and the charge readout area, wherein the floating gate, the inter-gate dielectric layer, and the control gate extend from the photosensitive area to the charge readout area; the vertical charge transfer imaging sensor further includes a source region and a drain region formed in the charge readout area and respectively located on both sides of the gate structure, wherein the gate structure, the source region, and the drain region constitute a readout transistor.

[0012] Optionally, a portion of the lower end of the deep trench isolation is exposed from the back side of the substrate, while another portion is not exposed; or, the entire lower end of the deep trench isolation is exposed from the back side of the substrate, and the cross-section of the deep trench isolation exposed from the back side of the substrate has a mesh structure.

[0013] Optionally, in the mesh structure, the distance between the lower end region of the deep trench isolation corresponding to each point on the mesh line and the front side of the substrate is the same or varies within a range.

[0014] Optionally, in the mesh structure, the lower end region of the deep trench isolation corresponding to each point on the mesh line protrudes beyond the back surface of the substrate or is flush with the back surface of the substrate; or, the lower end region of the deep trench isolation corresponding to each point on the mesh line partially protrudes beyond the back surface of the substrate and partially is flush with the back surface of the substrate.

[0015] Optionally, in the mesh structure, the lower region of the deep trench isolation corresponding to each intersection of the mesh lines is further away from the back side of the substrate than the lower region of the deep trench isolation corresponding to the non-intersections of the mesh lines.

[0016] Optionally, the vertical charge transfer imaging sensor further includes:

[0017] An interlayer dielectric layer is formed on one side of the front side of the substrate and covers the substrate and the gate structure;

[0018] Substrate electrode plugs, penetrating the interlayer dielectric layer and electrically connected to the common substrate region; and

[0019] A metal interconnect layer is formed on the surface of the interlayer dielectric layer and electrically connects to the substrate electrode plug.

[0020] Optionally, the substrate further includes a peripheral region formed around the first number of pixel regions and the second number of common substrate regions, and the metal interconnect layer extends to the peripheral region.

[0021] Optionally, the vertical charge transfer imaging sensor further includes:

[0022] At least one via is located in the peripheral region and penetrates the substrate, the via being electrically connected to the metal interconnect layer; and

[0023] At least one metal connection pad is formed in the peripheral region and located on the back side of the substrate, the metal connection pad being electrically connected to a corresponding via, wherein the substrate electrode plug is electrically connected to the corresponding metal connection pad through the metal interconnect layer and the via.

[0024] Optionally, the vertical charge transfer imaging sensor further includes a high dielectric constant layer covering the polycrystalline silicon layer.

[0025] On one hand, the present invention provides a method for forming a vertical charge transfer imaging sensor, the method comprising:

[0026] A substrate is provided, the substrate having a first doping type and including a front side and a back side opposite to each other;

[0027] Deep trench isolation and shallow trench isolation are formed on the front side of the substrate, the deep trench isolation and the shallow trench isolation extend from the front side into the substrate, the cross-section of the deep trench isolation is a grid structure to define a first number of pixel areas and a second number of common substrate areas located between the pixel areas in the substrate, and the shallow trench isolation defines a photosensitive area and a charge readout area in the pixel areas.

[0028] A gate structure is formed on the surface of the pixel region, and a source region and a drain region are formed in the charge readout region, wherein the source region and the drain region are respectively located on both sides of the gate structure;

[0029] The substrate is thinned from the back side to expose at least a portion of the deep trench isolation;

[0030] A polysilicon layer is formed, which conformally covers the substrate from the back side of the substrate and isolates it from the deep trench. The polysilicon layer is electrically connected to the substrate of each pixel region and the common substrate region. The gate structure and the pixel region below it constitute a MOS capacitor. The substrate terminal voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

[0031] Optionally, in the mesh structure, the lower region of the deep trench isolation corresponding to each intersection of the mesh lines is further away from the front side of the substrate than the lower region of the deep trench isolation corresponding to the non-intersections of the mesh lines; after thinning the substrate from the back side to expose at least part of the deep trench isolation, at least the lower region of the deep trench isolation corresponding to each intersection of the mesh lines is exposed from the back side of the substrate.

[0032] Optionally, when thinning the substrate from the back side, the substrate is first thinned to a first thickness that does not expose the deep trench isolation using a CMP process, and then the substrate is thinned to a second thickness that exposes at least part of the deep trench isolation using a wet etching process.

[0033] Optionally, forming the polycrystalline silicon layer includes:

[0034] An amorphous silicon layer is conformally coated on the back side of the substrate; and

[0035] A laser crystallization process is performed to convert the amorphous silicon layer into the polycrystalline silicon layer.

[0036] In the vertical charge transfer imaging sensor and its formation method provided by the present invention, a first number of pixel regions and a second number of common substrate regions are defined in the substrate by means of a deep trench isolation. The deep trench isolation forms effective isolation between the pixel regions, which helps to avoid photoelectric crosstalk between different pixels. Furthermore, the gate structure and the pixel regions below it constitute a MOS capacitor. In order to apply a voltage to the substrate, which serves as an electrode in the MOS capacitor, a polysilicon layer electrically connected to the substrates of each pixel region and the common substrate region is formed on the back side of the substrate. The substrate voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate. This substrate voltage is transmitted to the substrate of each pixel region through the common substrate region and the polysilicon layer, thereby eliminating the need to form a metal electrode on the back side of the substrate and avoiding the problems of high interface defects and high contact resistance that exist when forming a metal electrode on the back side of the substrate. Attached Figure Description

[0037] Figure 1 This is a planar schematic diagram of a vertical charge transfer imaging sensor.

[0038] Figure 2 It is along Figure 1 A schematic cross-sectional view of a vertical charge transfer imaging sensor in the XX' direction.

[0039] Figure 3 This is a cross-sectional schematic diagram of a vertical charge transfer imaging sensor according to an embodiment of the present invention.

[0040] Figure 4 This is a schematic flowchart of a method for forming a vertical charge transfer imaging sensor according to an embodiment of the present invention.

[0041] Figures 5A to 5K This is a cross-sectional schematic diagram of a method for forming a vertical charge transfer imaging sensor according to an embodiment of the present invention. Detailed Implementation

[0042] The vertical charge transfer imaging sensor and its formation method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, only to facilitate and clarify the illustration of the embodiments of the present invention. The embodiments of the present invention should not be considered as limited to the specific shapes of the areas shown in the figures, but may include actual shapes, such as those caused by manufacturing deviations.

[0043] Reference Figure 3 According to an embodiment of the present invention, a vertical charge transfer imaging sensor includes a substrate 10, a gate structure formed on the front side 10a of the substrate 10, and a polysilicon layer 110a formed on the back side 10b of the substrate 10.

[0044] The substrate 10 can be any suitable substrate in the art, and its material may include silicon, germanium, silicon-germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide, etc. The substrate 10 has a first doping type, such as p-type or n-type; this embodiment uses p-type as an example. The substrate 10 is, for example, a silicon substrate doped with boron or boron difluoride. The substrate 10 has a front side 10a and a back side 10b that are opposite to each other.

[0045] Deep trench isolation (DTI) and shallow trench isolation (STI) are formed within substrate 10. Shallow trench isolation (STI) includes shallow trenches formed from the front side 10a of substrate 10 and an isolation medium (such as silicon oxide or silicon nitride) filling the shallow trenches. Deep trench isolation (DTI) includes deep trenches formed within substrate 10 and an isolation medium (such as silicon oxide or silicon nitride) filling the deep trenches. Figure 3 Optionally, the deep trench isolation DTI includes a deep trench that penetrates at least a portion of the substrate 10, a linear dielectric layer 105 filled within the deep trench, a trench electrode 106, and a capping layer 107. The linear dielectric layer 105 and the capping layer 107 are isolation media filled within the deep trench, and they enclose the trench electrode 106, isolating it from the substrate 10 and the polysilicon layer 110a. The trench electrode 106 provides an operable electrode for the vertical charge transfer imaging sensor. Combined with other electrodes in the sensor, it allows for diverse operating methods. For example, by applying a positive bias voltage between the substrate 10 and the trench electrode 106, the potential barrier at the interface between the deep trench isolation DTI and the substrate 10 can be increased, reducing the probability of photoelectrons being trapped at the interface, thus improving photoelectric conversion efficiency and mitigating dark current and white pixel issues. The trench electrode 106 can extend to the peripheral region of the substrate 10 for connection to external electrical signals.

[0046] According to an embodiment of the present invention, the cross-section of the deep trench isolation DTI is a mesh structure to define a first number of pixel regions A1 and a second number of common substrate regions A2 located between the first number of pixel regions A1 in the substrate 10. The second number is greater than or equal to 1. The first number is, for example, greater than or equal to the second number. Each common substrate region A2 is, for example, adjacent to at least two pixel regions A1 so as to be shared by at least two pixel regions A1.

[0047] Depending on the specific fabrication process, in the grid structure formed by the cross-section of the deep trench isolation DTI, the distance between the lower end region of the deep trench isolation DTI corresponding to each point on the grid line and the front side 10a of the substrate 10 is the same or varies within a certain range.

[0048] The back surface 10b of the substrate 10 exposes at least a portion of the deep trench isolation DTI. Specifically, in one embodiment, the back surface 10b of the substrate 10 exposes a portion of the lower end region of the deep trench isolation DTI ("lower end" refers to the end away from the front surface 10a of the substrate 10, the same below), that is, from the perspective of the grid structure formed by the cross-section of the deep trench isolation DTI, the lower end region of the deep trench isolation DTI corresponding to each point on the grid line is partially exposed from the back surface 10b of the substrate 10 and partially not exposed. In another embodiment, the back surface 10b of the substrate 10 exposes the entire lower end region of the deep trench isolation DTI, that is, in the grid structure, the lower end region of the deep trench isolation DTI corresponding to each point on the grid line is completely exposed from the back surface 10b of the substrate 10, that is, the cross-section of the deep trench isolation DTI exposed from the back surface 10b of the substrate 10 has a grid structure.

[0049] In the described mesh structure, the lower end region of the deep trench isolation DTI corresponding to each point on the mesh line may all protrude beyond the back surface 10b of the substrate 10 or be flush with the back surface 10b of the substrate 10; or, the lower end region of the deep trench isolation DTI corresponding to each point on the mesh line may partially protrude beyond the back surface 10b of the substrate 10 and partially be flush with the back surface 10b of the substrate 10. The invention is not limited thereto. In another embodiment, in the mesh structure, the lower end region of the deep trench isolation DTI corresponding to each point on the mesh line is partially exposed beyond the back surface 10b of the substrate 10 (specifically, it may protrude beyond the back surface 10b of the substrate 10 or be flush with the back surface 10b of the substrate 10), and partially located inside the substrate 10.

[0050] like Figure 3As shown, in this embodiment, the deep trench isolation DTI completely penetrates the substrate 10. From the perspective of the grid structure formed by the cross-section of the deep trench isolation DTI, the lower end region of the deep trench isolation DTI corresponding to each point on the grid line penetrates the substrate 10 and is exposed on the back surface 10b of the substrate 10. The cross-section of the deep trench isolation DTI exposed on the back surface 10b of the substrate 10 is a grid structure. Furthermore, in the grid structure, the distance between the lower end region of the deep trench isolation DTI corresponding to each point on the grid line and the back surface 10b of the substrate 10 can be the same or vary within a range. As an example, the distance between the lower end region of the deep trench isolation DTI corresponding to each point on the grid line and the back surface 10b of the substrate 10 varies within a range. The lower end region of the deep trench isolation DTI corresponding to each point on the grid line can all protrude from the back surface 10b of the substrate 10, or a portion of the lower end region protrudes from the back surface 10b of the substrate 10 and a portion of the lower end region is flush with the back surface 10b of the substrate 10. Optionally, in the grid structure formed by the cross-section of the deep trench isolation DTI, the lower region of the deep trench isolation DTI corresponding to each intersection of the grid lines is further away from the back surface 10b of the substrate 10 than the lower region of the deep trench isolation DTI corresponding to the non-intersection of the grid lines.

[0051] Shallow trench isolation (STI) is formed on the front side 10a of the substrate 10 in each pixel region A1 to define the photosensitive area and charge readout area in the vertical charge transfer imaging sensor pixel. For example... Figure 3 As shown, each pixel region A1 is separated by shallow trench isolation (STI) to form a photosensitive region 11 and a charge readout region 12. It can be understood that, with the front side 10a of the substrate 10 as a reference, the depth of the shallow trench isolation (STI) in the substrate 10 is less than the depth of the deep trench isolation (DTI) in the substrate 10.

[0052] The gate structure is located on the front side 10a of the substrate 10 and formed on the surface of each pixel region A1. For example... Figure 3 As shown, the gate structure includes a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 109, and a control gate CG stacked on the surfaces of the photosensitive area 11 and the charge readout area 12 of the corresponding pixel area A1. In this embodiment, the floating gate FG, the inter-gate dielectric layer 109, and the control gate CG in the gate structure extend from the photosensitive area 11 of the lower pixel area A1 to the charge readout area 12. The control gates CG on multiple pixel areas A1 can be connected to form a word line WL. Furthermore, the gate structure can also be formed on a common substrate area A2. The control gate CG in the gate structure on the common substrate area A2 is connected to the control gate CG in the gate structure on the adjacent pixel area A1, and thus connected to the word line WL. The word line WL can span the common substrate area A2.

[0053] The gate structure and the pixel region A1 below it (i.e., the pixel region A1 on the surface where the gate structure is formed) constitute a MOS capacitor. In the MOS capacitor, the control gate CG constitutes one electrode, and the substrate 10 of the pixel region A1 constitutes the other electrode.

[0054] The gate structure formed on the surface of pixel region A1 exposes a portion of the charge readout region 12 in the corresponding pixel region A1 on both sides of the extension direction. The vertical charge transfer imaging sensor also includes a source region S and a drain region D formed on the charge readout region 12 and located on both sides of the gate structure (the positional relationship between the source region S and the drain region D and the gate structure can be referred to...). Figure 1 The gate structure, along with the source region S and drain region D, constitutes a readout transistor, which is used for charge readout. During photosensitive processing by the vertical charge transfer imaging sensor, pressure is applied to the two electrodes of the MOS capacitor, causing the control gate CG to be positively biased relative to the substrate 10 of the pixel region A1, resulting in a depletion region in the substrate 10. When light enters from the back surface 10b of the substrate 10, it collides with the substrate lattice to generate photoelectrons. Under the influence of the electric field in the depletion region, the photoelectrons accumulate on the surface of the photosensitive region 11 or cross the potential barrier to enter the floating gate FG. Since the photosensitive region 11 and the floating gate FG of the charge readout region 12 are connected, the accumulation of photoelectrons causes a change in the state of the floating gate FG of the charge readout region 12, which in turn causes a change in the drain current and / or threshold voltage of the readout transistor. The vertical charge transfer imaging sensor detects this change to achieve photoelectric sensing and imaging. This paper uses an N-type device as an example to illustrate this, where the source region S and drain region D are n-type doped. It is understandable that, in the case where the read transistor is a p-type device, the source region S and the drain region D are p-type doped.

[0055] like Figure 3 As shown, the vertical charge transfer imaging sensor also includes a polysilicon layer 110a, which conformally covers the substrate 10 from the back surface 10b side of the substrate 10 and the deep trench isolation DTI exposed on the back surface 10b of the substrate 10. The polysilicon layer 110a is conductive, for example, having the same doping type as the substrate 10. In this embodiment, the polysilicon layer 110a contacts the substrate 10 of each pixel region A1 and the common substrate region A2, thereby electrically connecting to the substrate 10 of each pixel region A1 and the common substrate region A2.

[0056] In this embodiment, the substrate voltage of the MOS capacitor is applied from the front side 10a of the substrate 10 to the common substrate region A2. This substrate voltage is transmitted along the thickness direction of the substrate 10 to the polysilicon layer 110a. Since the polysilicon layer 110a is electrically connected to the substrate 10 of each pixel region A1, the purpose of applying voltage to the substrate 10 of multiple pixel regions A1 is achieved. The voltage transmission path is as follows: Figure 3As indicated by the dashed arrow.

[0057] The common substrate region A2 may have a substrate contact region (pick-up, not shown) formed near the front side 10a of the substrate 10, wherein the substrate contact region has a first doping concentration greater than that of the surrounding substrate region. The substrate terminal voltage of the MOS capacitor can be applied to the common substrate region A2 through the substrate contact region, and the higher doping concentration of the substrate contact region helps to reduce contact resistance.

[0058] To avoid significant differences in voltage applied to the substrate 10 of each pixel region A1 due to varying distances between the applied voltage location and the pixel region A1, thus affecting photosensitivity, multiple common substrate regions A2 can be distributed within the substrate 10, depending on the number of pixel regions A1. Therefore, when applying voltage to the substrate 10 of each pixel region A1 using the common substrate regions A2 and the polysilicon layer 110a, applying voltage from multiple common substrate regions A2 helps to balance the voltage at different locations on the polysilicon layer 110a, i.e., to achieve voltage balance across the substrate 10 of each pixel region A1. As an example, the ratio of the first quantity to the second quantity is approximately 100:1 to 200:1.

[0059] The thickness of the polysilicon layer 110a can be set according to the isolation and conductivity requirements of the pixel area A1. Specifically, if the thickness of the polysilicon layer 110a is too large, the polysilicon layer 110a connecting adjacent pixel areas A1 will be too thick, which may increase the risk of crosstalk. If the thickness of the polysilicon layer 110a is too small, the resistance of the polysilicon layer 110a will increase, resulting in increased voltage loss. As an example, the thickness of the polysilicon layer 110a is in the range of 0.1 micrometers to 0.5 micrometers, and more specifically, for example, in the range of 0.2 micrometers to 0.3 micrometers.

[0060] On the back side 10b of the substrate 10, the vertical charge transfer imaging sensor may further include a high-dielectric-constant layer 111 covering a polycrystalline silicon layer 110a. The high-dielectric-constant layer 111 is formed using a material with a high dielectric constant (e.g., greater than 3.9) (such as Al₂O₃, Ta₂O₅, ZrO₂, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO₃(BST), or TiO₂, etc.). Utilizing the high-dielectric-constant layer 111 increases the potential barrier on the back side 10b of the substrate 10, reducing the probability of photoelectrons being trapped near the back side 10b of the substrate 10, thus contributing to improved photoelectric conversion efficiency.

[0061] To apply a substrate voltage to the common substrate region A2, an electrode structure electrically connected to the common substrate region A2 can be formed on the front side 10a of the substrate 10. This electrode structure includes, for example, a substrate electrode plug and a metal interconnect layer (not shown) electrically connected to the common substrate region A2. Specifically, the vertical charge transfer imaging sensor may include an interlayer dielectric layer, a substrate electrode plug, and a metal interconnect layer formed on the front side 10a of the substrate 10. The interlayer dielectric layer covers the substrate 10 and the gate structure. The substrate electrode plug penetrates the interlayer dielectric layer and is electrically connected to the common substrate region A2. The metal interconnect layer is formed on the surface of the interlayer dielectric layer and is electrically connected to the substrate electrode plug. The interlayer dielectric layer may also form conductive plugs electrically connected to the control gate CG, source region (S), and drain region (D) of the aforementioned readout transistor. The metal interconnect layer can be electrically connected to each of these conductive plugs.

[0062] The substrate 10 may also include a peripheral region located around the first number of pixel regions A1 and the second number of common substrate regions A2, the peripheral region being used to form part of the circuitry of the vertical charge transfer imaging sensor.

[0063] In one embodiment, an interconnect structure and a front metal pad connected to the interconnect structure are formed on the front side 10a of the substrate 10. The front metal pad serves as an input port for the substrate terminal voltage. The interconnect structure may include multiple patterned conductive layers isolated by a dielectric material and conductive plugs. The aforementioned metal interconnect layer is the bottom metal layer of the interconnect structure. In another embodiment, the vertical charge transfer imaging sensor includes at least one via formed in the peripheral region and at least one back metal pad formed in the peripheral region of the back side 10b of the substrate 10. The via penetrates the substrate 10 and is electrically connected to the metal interconnect layer. The back metal pad is electrically connected to the corresponding via to be electrically connected to the metal interconnect layer through the corresponding via, and then electrically connected to the common substrate region A2 and the polysilicon layer 110a. The back metal pad serves as an input port for the substrate terminal voltage. It should be noted that the input port for applying the substrate voltage can be located on the front side 10a or the back side 10b of the substrate 10, depending on the need. However, according to the embodiment of the present invention, the transmission path of the substrate voltage applied through the input port is to first apply it to the common substrate area A2 from the front side 10a of the substrate 10, then transmit it to the polysilicon layer 110a, and then apply it to the substrate 10 of each pixel area A1 through the polysilicon layer 110a.

[0064] This invention also relates to a method for forming a vertical charge transfer imaging sensor, which can be used to fabricate the vertical charge transfer imaging sensor described in the above embodiments. The following refers to... Figure 4 and Figures 5A to 5K The method for forming the vertical charge transfer imaging sensor will be described.

[0065] Reference Figure 4 as well as Figure 5A Step S1 is performed, providing a substrate 10 having a first doping type and including a front side 10a and a back side 10b facing opposite directions. As an example, the substrate 10 is, for example, a silicon substrate and has p-type doping.

[0066] Reference Figure 4 Step S2 is performed to form a deep trench isolation (DTI) and a shallow trench isolation (STI) on the front side 10a of the substrate 10 (see reference). Figure 5F The deep trench isolation (DTI) and the shallow trench isolation (STI) extend from the front side 10a into the substrate 10. The cross-section of the deep trench isolation (DTI) is a mesh structure to define a first number of pixel regions A1 and a second number of common substrate regions A2 located between the first number of pixel regions A1 in the substrate 10. The shallow trench isolation (STI) defines a photosensitive region 11 and a charge readout region 12 within the pixel regions A1.

[0067] Optionally, in one embodiment, the shallow trench isolation (STI) may include a shallow trench formed from one side of the front side 10a of the substrate 10 and an isolation medium filling the shallow trench. The deep trench isolation (DTI) may include a deep trench formed from one side of the front side 10a of the substrate 10 and an isolation medium filling the deep trench. The isolation medium in the deep trench isolation (DTI) and the shallow trench isolation (STI) may include silicon oxide or silicon nitride, etc. The shallow trench isolation (STI) and the deep trench isolation (DTI) may be formed separately using conventional trench isolation fabrication processes, and this application does not impose any special restrictions on the formation order of the shallow trench isolation (STI) and the deep trench isolation (DTI). In this embodiment, the deep trench isolation (DTI) includes a deep trench formed on the front side 10a of the substrate 10, an isolation medium filling the deep trench, and a trench electrode, wherein the trench electrode provides an operable electrode terminal for the vertical charge transfer imaging sensor. The following description of step S2 is based on the example of forming shallow trench isolation (STI) first and then deep trench isolation (DTI). In other embodiments, deep trench isolation (DTI) can be formed first and then shallow trench isolation (STI), or they can be formed simultaneously.

[0068] As an example, step S2 includes the following process:

[0069] First, refer to Figure 5AA pad oxide layer 101 and a first hard mask layer 102 are stacked on the front side 10a of the substrate 10 and etched to form a shallow trench that penetrates the first hard mask layer 102, the pad oxide layer 101 and part of the substrate 10. Then, a dielectric material is deposited in the shallow trench and on the substrate 10, and a CMP process is performed to expose the first hard mask layer 102. The shallow trench and the dielectric material therein constitute shallow trench isolation (STI). The pad oxide layer 101 is, for example, silicon oxide, and the first hard mask layer 102 is, for example, silicon nitride. The shallow trench extends from the front side 10a to a depth of about 100 nm to 400 nm in the substrate 10.

[0070] Then, refer to Figure 5B A second hard mask layer 103 (the second hard mask layer 104 is, for example, a silicon nitride layer) is formed on the front side 10a of the substrate 10, covering the shallow trench isolation STI and the first hard mask layer 102. Then, the position of the deep trench isolation is defined by photolithography and etching is performed to form a deep trench DT that penetrates the second hard mask layer 103, the first hard mask layer 102, the pad oxide layer 101 and part of the substrate 10. The deep trench DT extends from the front side 10a to a depth of about 1.5 μm to 2.5 μm in the substrate 10. The cross-section of the deep trench DT is a grid structure (the "cross-section" is parallel to the front side 10a of the substrate 10) to define a first number of pixel areas A1 in the substrate 10 and a second number of common substrate areas A2 located between the pixel areas A1. The shallow trench isolation STI is formed in each pixel area A1. Each pixel area A1 includes a photosensitive area 11 and a charge readout area 12 separated by the shallow trench isolation STI.

[0071] Then, refer to Figure 5C A linear dielectric layer 105 is formed on the inner surface of the deep trench DT. Before this, the top of the deep trench DT can be widened to improve the isolation performance. After the linear dielectric layer 105 is formed, annealing can be performed to repair the defects on the surface of the deep trench DT. The linear dielectric layer 105 may include silicon oxide or silicon nitride, etc. In this embodiment, silicon nitride is used for example.

[0072] Then, refer to Figure 5D Conductive material is deposited in the deep trench DT and on the second hard mask layer 103. Using CMP and etching processes, the upper surface of the conductive material around each pixel area A1 is lowered to below the front side 10a of the substrate 10, forming a trench electrode 106 in the deep trench DT. In this embodiment, the deep trench DT and the trench electrode 106 can extend to the peripheral area of ​​the substrate 10. The peripheral area is located around the pixel area A1 and the common substrate area A2. For easy lead-out, the upper surface of the trench electrode 106 in the deep trench DT in the peripheral area can exceed the front side 10a of the substrate 10.

[0073] Then, refer to Figure 5E A dielectric material is deposited on the front side 10a of the substrate 10 and a CMP process is performed to expose the second hard mask layer 103. Then, a capping layer 107 is formed in the deep trench DT. The linear dielectric layer 105 and the capping layer 107 are the isolation dielectrics filling the deep trench DT. The trench electrode 106 is wrapped by the linear dielectric layer 105 and the capping layer 107 to insulate it from the substrate 10. The deep trench DT and the linear dielectric layer 105, the capping layer 107 and the trench electrode 106 located in the deep trench DT constitute a deep trench isolation DTI.

[0074] Then, refer to Figure 5F Remove the second hard mask layer 103 and the first hard mask layer 102.

[0075] Reference Figure 4 and Figure 5G In step S3, a gate structure is formed on the surface of pixel region A1, and a source region and a drain region are formed in the charge readout region 12 of pixel region A1, respectively located on both sides of the gate structure. The positional relationship between the source region, the drain region and the gate structure can be referenced. Figure 1 .

[0076] In this embodiment, the gate structure includes a gate dielectric layer 108, a floating gate FG, an inter-gate dielectric layer 109, and a control gate CG stacked on the surfaces of the photosensitive region 11 and the charge readout region 12. It may also include sidewalls covering the sides of the floating gate FG, the inter-gate dielectric layer 109, and the control gate CG. The floating gate FG, the inter-gate dielectric layer 109, the control gate CG, and the sidewalls extend from the photosensitive region 11 to the charge readout region 12. Optionally, the control gates CG in the plurality of gate structures can be connected to form a word line WL, and, as... Figure 5G As shown, at least a portion of the word line WL spans the common substrate region A2. The gate structure, as well as the source and drain regions, can be formed using processes known in the art. For example, the gate dielectric layer 108 can be formed on the front side 10a of the substrate 10 by a thermal oxidation process after removing the pad oxide layer 101. To fabricate the source and drain regions of the readout transistors in the vertical charge transfer imaging sensor pixels, a portion of the charge readout region 12 is exposed on the side of the sidewall away from the control gate CG, and the source and drain regions are formed respectively in the charge readout regions 12 on both sides of the extension direction of the gate structure by ion implantation. Further details are omitted here.

[0077] After forming the gate structure, the following process (not shown) can further be performed on the front side 10a of the substrate 10:

[0078] An interlayer dielectric layer is formed, which covers the substrate 10 after the above-described gate structure is formed from the front side 10a.

[0079] Multiple conductive plugs are formed in the interlayer dielectric layer, and a metal interconnect layer is formed on the surface of the interlayer dielectric layer. The conductive plugs penetrate the interlayer dielectric layer. Some of the conductive plugs are electrically connected to the control gate CG, some are electrically connected to the source region, some are electrically connected to the drain region, and some are substrate electrode plugs. The substrate electrode plugs penetrate the interlayer dielectric layer and are electrically connected to the common substrate region A2. In this embodiment, a gate structure is formed on the common substrate region A2, so the substrate electrode plugs also penetrate the gate structure to be electrically connected to the common substrate region A2. When forming the substrate electrode plugs, a dielectric layer can be formed in the corresponding plug holes to isolate the substrate electrode plugs from the gate structure. The metal interconnect layer is electrically connected to each of the conductive plugs.

[0080] After completing the process on the front side 10a of substrate 10, refer to Figure 4 Step S4 is performed to thin the substrate 10 from the back side to expose at least a portion of the deep trench isolation DTI. Before thinning the substrate 10, a carrier plate may be bonded to the front side 10a of the substrate 10 as a support.

[0081] As an example, firstly, as Figure 5H As shown, using CMP technology, the substrate 10 is thinned from the back side 10b to a first thickness. This first thickness can be set as needed; for example, when the substrate 10 is at the first thickness, the lower ends of the deep trench isolation (DTI) are not exposed. Then, as... Figure 5I As shown, the substrate 10 is further thinned from the back side 10b to a second thickness using a wet etching process, so that at least part of the deep trench isolation DTI is exposed.

[0082] In this embodiment, after completing the CMP and wet etching processes, in the mesh structure formed by the deep trench isolation DTI, the lower end (i.e., the end furthest from the front side 10a of the substrate 10) of the deep trench isolation DTI corresponding to each point on the mesh line is exposed from the back side 10b of the substrate 10 and protrudes beyond the back side 10b of the substrate 10. However, this is not limited to this. In another embodiment, after completing the CMP and wet etching processes, the lower end region of the deep trench isolation DTI corresponding to each point on the mesh line is partially exposed from the back side 10b of the substrate 10 (specifically, it may protrude beyond the back side 10b of the substrate 10 or be flush with the back side 10b of the substrate 10) and partially not exposed; or, after completing the CMP and wet etching processes, the lower end region of the deep trench isolation DTI corresponding to each point on the mesh line is exposed from the back side 10b of the substrate 10 and is flush with the back side 10b of the substrate 10. The trench electrode 106 is not exposed by the protection of the isolation medium within the deep trench.

[0083] In this embodiment, before step S4 to thin the substrate 10, the depth of the deep trench isolation DTI in the substrate 10 is the depth of the corresponding deep trench extending from the front side 10a of the substrate 10 into the substrate 10. The depth of the deep trench extending into the substrate 10 at different locations can be the same or different. According to the actual manufacturing process, in the grid structure of the deep trench isolation DTI cross-section, the depth of the lower end region of the deep trench isolation DTI corresponding to different points on the grid lines in the substrate 10 is not completely consistent, but varies within a range. For example, in the grid structure, the lower end region of the deep trench isolation DTI corresponding to each intersection point of the grid lines is farther from the front side 10a of the substrate 10 than the lower end region of the deep trench isolation DTI corresponding to the non-intersection points of the grid lines. As a result, the distance from the lower end of the deep trench isolation DTI to the back side of the substrate 10 also varies within a range, making the substrate 10 thickness uneven in each pixel area A1 and the common substrate area A2, and also uneven in the substrate 10 thickness between the lower end of the deep trench isolation DTI and the back side 10b of the substrate 10.

[0084] In this embodiment, in the mesh structure, the lower region of the deep trench isolation DTI corresponding to each intersection of the mesh lines is farther away from the front side 10a of the substrate 10 than the lower region of the deep trench isolation DTI corresponding to the non-intersection of the mesh lines. After thinning the substrate 10 from the back side 10b in step S4 to expose at least part of the deep trench isolation, the substrate 10 becomes thinner overall, and at least the lower region of the deep trench isolation DTI corresponding to each intersection of the mesh lines is exposed from the back side 10b of the substrate 10.

[0085] Step S4 removes the entire substrate 10 between the lower end of the deep trench isolation DTI and the back surface 10b of the substrate 10. This eliminates the influence of depth differences in the deep trench isolation DTI on the thickness of the substrate 10 in each pixel region A1 and the common substrate region A2, resulting in a more uniform thickness. This eliminates the influence of depth differences in the deep trench isolation DTI on the thickness of different areas of the substrate 10. After step S4 removes the entire substrate 10 between the lower end of the deep trench isolation DTI and the back surface 10b of the substrate 10, the lower end of the deep trench isolation DTI is fully exposed. The distance between the lower end region of the deep trench isolation DTI corresponding to each point on the grid line and the back surface 10b of the substrate 10 varies within a certain range. The lower end region of the deep trench isolation DTI corresponding to each point on the grid line can all protrude beyond the back surface 10b of the substrate 10, or a portion of the lower end region can protrude beyond the back surface 10b of the substrate 10 while another portion is flush with the back surface 10b of the substrate 10. Optionally, in the mesh structure, the lower region of the deep trench isolation DTI corresponding to each intersection of the mesh lines is further away from the back surface 10b of the substrate 10 than the lower region of the deep trench isolation DTI corresponding to the non-intersections of the mesh lines.

[0086] Reference Figure 4 Step S5 is executed to form a polysilicon layer. The polysilicon layer conformally covers the substrate 10 and the deep trench isolation DTI from the back side 10b of the substrate 10. The polysilicon layer is electrically connected to the substrate 10 of each pixel region A1 and the common substrate region A2.

[0087] To protect the structure already formed on the front side 10a of the substrate 10, the process for forming the polycrystalline silicon layer uses a low-temperature process as much as possible to avoid high temperatures. Since the temperature for forming monocrystalline silicon is usually higher than the temperature for forming amorphous silicon by chemical vapor deposition or epitaxy, this embodiment adopts a method of first forming an amorphous silicon layer and then converting it into a polycrystalline silicon layer.

[0088] Specifically, firstly, referring to Figure 5I An amorphous silicon layer 110 is formed on the back side 10b of the substrate 10. The amorphous silicon layer 110 conformally covers the substrate 10 and the deep trench isolation DTI from one side of the back side 10b of the substrate 10. The growth temperature of the amorphous silicon layer 110 is controlled, for example, below 450 degrees Celsius. Before forming the amorphous silicon layer 110, it can be determined whether a natural oxide layer has formed on the back side of the substrate 10 based on the exposure time of the back side 10b after the substrate 10 is thinned. If no natural oxide layer has formed, the amorphous silicon layer 110 can be deposited directly by chemical vapor deposition or epitaxy. If a natural oxide layer exists, it is preferable to remove the natural oxide layer first (e.g., using a SiCoNi etching process) and then deposit the amorphous silicon layer 110 by chemical vapor deposition or epitaxy.

[0089] Next, refer to Figure 5J A laser crystallization process is performed to convert the amorphous silicon layer 110 into a polycrystalline silicon layer 110a. In other embodiments, other techniques may also be used to convert the amorphous silicon layer 110 into a polycrystalline silicon layer 110a.

[0090] In this embodiment, the polysilicon layer 110a conformally covers the back side 10b of the substrate 10 and the deep trench isolation DTI surface exposed by the back side 10b of the substrate 10. The thickness of the polysilicon layer 110a is not affected by the height difference of the deep trench isolation DTI, thus the thickness of the polysilicon layer 110a in contact with each pixel region A1 and the common substrate region A2 is substantially the same. When a substrate voltage is applied from the front side 10a of the substrate 10 to the common substrate region A2, the substrate voltage is transmitted to the substrate 10 of each pixel region A1 through the common substrate region A2 and the polysilicon layer 110a. Since the polysilicon layer 110a formed on the back side 10b of the substrate 10 has good thickness uniformity, it is easy to control the voltage loss caused by the resistance of the polysilicon layer 110a, which helps to balance the voltage applied to the substrate 10 of each pixel region A1.

[0091] Reference Figure 5K Optionally, after completing step S5 above, a high dielectric constant layer 111 can be further formed on the surface of the polysilicon layer 110a.

[0092] In the vertical charge transfer imaging sensor and the method for forming the vertical charge transfer imaging sensor described in the above embodiments, the deep trench isolation (DTI) that penetrates the substrate 100 defines a first number of pixel regions A1 and a second number of common substrate regions A2 located between the pixel regions A1 in the substrate 10. The deep trench isolation (DTI) can effectively isolate the pixel regions A1 and avoid crosstalk. Furthermore, the gate structure formed on the surface of the pixel region A1 constitutes a MOS capacitor with the corresponding pixel region A1. In order to apply a substrate terminal voltage to the substrate 10, which serves as an electrode in the MOS capacitor, a polysilicon layer 110a is covered on the back side 10b of the substrate 10. The polysilicon layer 110a is electrically connected to the substrate 10 of each pixel region A1 and the common substrate region A2. The substrate terminal voltage applied to the common substrate region A2 from the front side 10a of the substrate 10 can be transmitted to the substrate 10 of each pixel region A1 through the common substrate region A2 and the polysilicon layer 110a. Using the method for forming a vertical charge transfer imaging sensor described in the above embodiments, applying the substrate terminal voltage to the substrate 10, which serves as an electrode in the MOS capacitor, does not require forming a metal electrode on the back side 10b of the substrate 10 to contact the substrate 10. This avoids the problems of high interface defects and high contact resistance that exist when forming such a metal electrode. Furthermore, compared to applying voltage directly from the peripheral region of the substrate 10 to each pixel region A1, applying the substrate terminal voltage from the front side 10a of the substrate 10 to the common substrate region A2 can reduce voltage loss and help to balance the substrate terminal voltage corresponding to each pixel region A1.

[0093] It should be noted that the embodiments in this specification are described in a progressive manner, with each part focusing on the differences from the preceding parts, and the similarities and similarities between the parts can be referred to each other.

[0094] The above description is merely a description of preferred embodiments of the present invention and is not intended to define the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A vertical charge transfer imaging sensor, characterized in that, include: A substrate having a first doping type and including a front side and a back side opposite to each other, wherein deep trench isolation and shallow trench isolation are formed in the substrate, wherein the cross-section of the deep trench isolation is a grid structure, at least a portion of the deep trench isolation is exposed on the back side of the substrate, the deep trench isolation defines a first number of pixel regions and a second number of common substrate regions located between the first number of pixel regions in the substrate, and the shallow trench isolation is formed on the front side of the substrate of each pixel region and defines a photosensitive area and a charge readout area; A polysilicon layer conformally covers the substrate from the back side of the substrate and isolates it from the deep trench; the polysilicon layer is electrically connected to the substrate of each pixel region and the common substrate region; and A gate structure is formed on the surface of the pixel region, and the gate structure and the pixel region below it constitute a MOS capacitor, wherein the substrate voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

2. The vertical charge transfer imaging sensor as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate stacked on the surfaces of the photosensitive area and the charge readout area, wherein the floating gate, the inter-gate dielectric layer, and the control gate extend from the photosensitive area to the charge readout area; the vertical charge transfer imaging sensor also includes a source region and a drain region formed in the charge readout area and respectively located on both sides of the gate structure, and the gate structure, the source region, and the drain region constitute a readout transistor.

3. The vertical charge transfer imaging sensor as described in claim 1, characterized in that, In the mesh structure, the lower end region of the deep trench isolation corresponding to each point on the mesh line is partially exposed from the back side of the substrate and partially not exposed; or, in the mesh structure, the lower end region of the deep trench isolation corresponding to each point on the mesh line is completely exposed from the back side of the substrate, and the cross-section of the deep trench isolation exposed from the back side of the substrate is a mesh structure.

4. The vertical charge transfer imaging sensor as described in claim 1, characterized in that, In the mesh structure, the distance between the lower end region of the deep trench isolation corresponding to each point on the mesh line and the front side of the substrate is the same or varies within a certain range.

5. The vertical charge transfer imaging sensor as described in claim 1, characterized in that, In the mesh structure, the lower end region of the deep trench isolation corresponding to each point on the mesh line either protrudes from the back of the substrate or is flush with the back of the substrate; or, the lower end region of the deep trench isolation corresponding to each point on the mesh line partially protrudes from the back of the substrate and partially is flush with the back of the substrate.

6. The vertical charge transfer imaging sensor as described in claim 1, characterized in that, In the mesh structure, the lower region of the deep trench isolation corresponding to each intersection of the mesh lines is farther away from the back side of the substrate than the lower region of the deep trench isolation corresponding to the non-intersections of the mesh lines.

7. The vertical charge transfer imaging sensor as described in any one of claims 1 to 6, characterized in that, Also includes: An interlayer dielectric layer is formed on one side of the front side of the substrate and covers the substrate and the gate structure; A substrate electrode plug penetrates the interlayer dielectric layer and is electrically connected to the common substrate region; as well as A metal interconnect layer is formed on the surface of the interlayer dielectric layer and electrically connects to the substrate electrode plug.

8. The vertical charge transfer imaging sensor as described in claim 7, characterized in that, The substrate further includes a peripheral region formed around the first number of pixel regions and the second number of common substrate regions, and the metal interconnect layer extends to the peripheral region.

9. The vertical charge transfer imaging sensor as described in claim 8, characterized in that, Also includes: At least one via is located in the peripheral region and penetrates the substrate, and the via is electrically connected to the metal interconnect layer; as well as At least one metal connection pad is formed in the peripheral region and located on the back side of the substrate, the metal connection pad being electrically connected to a corresponding via, wherein the substrate electrode plug is electrically connected to the corresponding metal connection pad through the metal interconnect layer and the via.

10. The vertical charge transfer imaging sensor according to any one of claims 1 to 6, characterized in that, It also includes a high dielectric constant layer covering the polycrystalline silicon layer.

11. A method for forming a vertical charge transfer imaging sensor, characterized in that, The forming method includes: A substrate is provided, the substrate having a first doping type and including a front side and a back side opposite to each other; Deep trench isolation and shallow trench isolation are formed on the front side of the substrate, the deep trench isolation and the shallow trench isolation extend from the front side into the substrate, the cross-section of the deep trench isolation is a grid structure to define a first number of pixel areas and a second number of common substrate areas located between the pixel areas in the substrate, and the shallow trench isolation defines a photosensitive area and a charge readout area in the pixel areas. A gate structure is formed on the surface of the pixel region, and a source region and a drain region are formed in the charge readout region, wherein the source region and the drain region are respectively located on both sides of the gate structure; The substrate is thinned from the back side to expose at least a portion of the deep trench isolation; A polysilicon layer is formed, which conformally covers the substrate from the back side of the substrate and isolates it from the deep trench. The polysilicon layer is electrically connected to the substrate of each pixel region and the common substrate region. The gate structure and the pixel region below it constitute a MOS capacitor. The substrate terminal voltage of the MOS capacitor is applied to the common substrate region from the front side of the substrate.

12. The forming method as described in claim 11, characterized in that, In the mesh structure, the lower region of the deep trench isolation corresponding to each intersection of the mesh lines is further away from the front side of the substrate than the lower region of the deep trench isolation corresponding to the non-intersection of the mesh lines. After the substrate is thinned from the back side to expose at least a portion of the deep trench isolation, the lower end region of the deep trench isolation corresponding to at least each intersection of the grid lines is exposed from the back side of the substrate.

13. The forming method as described in claim 11, characterized in that, When thinning the substrate from the back side, the substrate is first thinned to a first thickness that does not expose the deep trench isolation using a CMP process, and then the substrate is thinned to a second thickness that exposes at least part of the deep trench isolation using a wet etching process.

14. The forming method as described in claim 11, characterized in that, Forming the polycrystalline silicon layer includes: An amorphous silicon layer is conformally coated on the back side of the substrate; and A laser crystallization process is performed to convert the amorphous silicon layer into the polycrystalline silicon layer.

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