Fabrication method and application of P+ local tunneling passivation contact structure

Abstract

The application relates to the technical field of solar cells, and discloses a manufacturing method of a P+ local tunneling passivation contact structure and application. The manufacturing method comprises the following steps: preparing a tunneling oxide layer on the front surface of a silicon substrate after texturing; locally opening holes in the tunneling oxide layer to expose the front surface of the silicon substrate in a non-metallized area; preparing an amorphous silicon layer on the whole surface; diffusing boron to the amorphous silicon layer to form a P+ emitter, a p+ polysilicon layer and a borosilicon glass layer; after removing the borosilicon glass layer in the hole non-metallized area, alkali cleaning is performed on the hole area to remove the p+ polysilicon layer in the non-metallized area and wash away part of the doped silicon substrate in the hole area, so as to control the boron doping amount of the silicon substrate in the hole area; and the borosilicon glass layer in the metallized area is removed. The manufacturing method can simultaneously manufacture the P+ emitter and the local tunneling passivation contact structure through one-time doping, can control the alkali concentration and cleaning time of alkali cleaning to control the doping amount of the silicon substrate, can improve the P+ emitter, and can simplify the manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a method for fabricating and applying a P+ local tunneling passivation contact structure. Background Technology

[0002] In the field of solar cells, fabricating patterned, selective, localized tunneling passivation contact structures (polyfin structures) is an effective means to reduce metal recombination on the front side of solar cells and improve the passivation effect and overall cell conversion efficiency. This technology is commonly used on the front side of PERC, TOPCon, and other solar cells to achieve the effect of metallized passivation contacts.

[0003] Currently, there are publicly available methods for fabricating p+poly fingers, such as the method for fabricating a passivation structure provided in publication number CN110634996A. This method includes: sequentially forming a tunneling oxide layer and an intrinsic polysilicon layer on the front side of a silicon wafer; then performing boron doping on a target portion of the intrinsic polysilicon layer to obtain locally boron-doped polysilicon, and removing the portion of the intrinsic polysilicon layer other than the target portion; then removing the portion of the tunneling oxide layer other than the portion covered by the boron-doped polysilicon; and performing boron diffusion on the uncovered portion of the silicon wafer to obtain a boron diffusion layer, thereby obtaining a passivation structure.

[0004] The existing method for fabricating this passivation structure (CN110634996A) employs a boron slurry doping process and a boron diffusion process to separately dope the polyfin and non-polyfin regions with boron. Furthermore, it requires the separate use of an organic cleaning agent (such as diethylene glycol butyl ether) to clean the organic shell formed by the boron-doped slurry. Therefore, this method cannot simultaneously dope the polyfin and non-polyfin regions using a single boron diffusion process, and it lacks precise control over the boron doping amount in the non-polyfin regions. Consequently, it is difficult to form a high-quality boron diffusion layer, and the fabrication process is complex and involves numerous steps. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for fabricating and applying a P+ local tunneling passivation contact structure.

[0006] Based on this, the present invention discloses a method for fabricating a P+ local tunneling passivation contact structure, comprising the following fabrication steps:

[0007] S1. Prepare a tunneling oxide layer on the front side of the texturized silicon substrate;

[0008] S2. Localize the tunnel oxide layer to expose the front side of the silicon substrate in the non-metallized region, while retaining the tunnel oxide layer on the front side of the silicon substrate in the metallized region.

[0009] S3. An amorphous silicon layer is prepared on the front side of the tunneling oxide layer and the exposed silicon substrate.

[0010] S4. Boron diffusion doping is performed on the entire amorphous silicon layer to form a p+ polycrystalline silicon layer. The boron doping source in the non-metallized region will pass through the amorphous silicon layer to dope the silicon substrate to form a P+ emitter, and a full borosilicate glass layer will be formed on the front side of the p+ polycrystalline silicon layer.

[0011] S5. After opening the borosilicate glass layer in the non-metallized region, perform alkaline cleaning on the opening region to remove the p+ polysilicon layer in the non-metallized region and wash away some of the doped silicon substrate in the opening region, so as to control the boron doping amount of the silicon substrate in the opening region and improve the P+ emitter in the opening region.

[0012] S6. Then remove the borosilicate glass layer in the metallized area.

[0013] Preferably, in steps S2 and S5, laser is used to create the opening.

[0014] More preferably, in steps S2 and S5, an ultraviolet laser is used to make the opening, and the laser power for opening is 5-15W.

[0015] Preferably, in step S4, the thickness of the borosilicate glass layer is 50nm-120nm.

[0016] Preferably, in step S4, the boron diffusion doping is tubular boron diffusion doping, and the diffusion process is a two-step through-source method; the sheet resistance of the obtained p+ polysilicon layer is 150-400Ω / □, and the sheet resistance of the doped P+ emitter is 30-100Ω / □.

[0017] More preferably, in step S5, the alkaline cleaning uses a NaOH solution with a NaOH to water volume ratio of 1%-3.5%, and the cleaning time is 2-5 minutes, so that the sheet resistance of the P+ emitter in the improved pore region is 70-150 Ω / □ and the maximum surface concentration is 4.2e19-5.0e19 cm⁻¹. 3 The junction depth of the PN junction is 0.49-0.70um.

[0018] More preferably, in step S5, the volume ratio of NaOH to water in the NaOH solution is 3%, and the washing time is 4 minutes, so that the sheet resistance of the P+ emitter in the improved pore region is 140 Ω / □ and the maximum surface concentration is 4.2e19 cm⁻¹. 3The junction depth of the PN junction is 0.49um.

[0019] Preferably, in step S6, an HF solution is used for cleaning to remove the borosilicate glass layer in the metallized region.

[0020] Preferably, in step S3, the amorphous silicon layer is prepared by low-pressure chemical vapor deposition to form an amorphous silicon layer with a thickness of 100nm-150nm.

[0021] This invention also discloses an application of a method for fabricating a P+ local tunneling passivation contact structure, namely: applying the method for fabricating a P+ local tunneling passivation contact structure described above in this invention to the preparation of TOPCon batteries.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects:

[0023] This invention provides a simple method for fabricating a p+ polyfin structure on an N-type silicon substrate: This method combines the steps prior to doping, and through a single doping process (such as boron diffusion doping), it can simultaneously achieve boron doping of the amorphous silicon layer in the polyfin region (corresponding to the metallization region) and the silicon substrate in the non-polyfin region (corresponding to the non-metallization region), and achieve crystallization of the amorphous silicon layer, thereby forming a p+ poly layer (i.e., a p+ polycrystalline silicon layer) and a P+ emitter in one step, and forming a BSG layer located on the front side of the p+ poly layer and the P+ emitter. Therefore, compared with CN110634996A, the fabrication process of the method of this invention is simplified.

[0024] Furthermore, the method of the present invention, combined with subsequent BSG layer local opening and alkaline cleaning steps, removes the p+ poly layer in the non-metallized region. At the same time, by controlling the alkaline cleaning time and alkaline concentration, the doping amount of the silicon substrate can be controlled to obtain a P+ emitter with maximum surface concentration, junction depth, and moderate sheet resistance on the silicon substrate in the non-metallized region, thereby improving the quality of the P+ emitter and contributing to the improvement of battery conversion efficiency. Moreover, the alkaline cleaning process uses the BSG layer retained in the metallized region after opening as a protective layer, eliminating the need for an additional protective film. Therefore, compared with other existing methods that use masking to fabricate polyfin structures, this method does not involve a subsequent process of removing the protective film, further simplifying the fabrication process. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure after step (1) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0026] Figure 2This is a schematic diagram of the structure after step (2) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0027] Figure 3 This is a schematic diagram of the structure after step (3) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0028] Figure 4 This is a schematic diagram of the structure after step (4) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0029] Figure 5 This is a schematic diagram of the structure after step (5) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0030] Figure 6 This is a schematic diagram of the structure after step (6) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0031] Figure 7 This is a schematic diagram of the structure after step (7) of the fabrication method of the P+ local tunneling passivation contact structure in this embodiment.

[0032] Reference numerals: 1. Silicon substrate; 2. P+ emitter; 3. Tunneling oxide layer; 4. Amorphous silicon layer; 41. P+ poly layer; 5. BSG layer; 6. Opening area. Detailed Implementation

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Example 1

[0035] This embodiment describes a method for fabricating a P+ local tunneling passivation contact structure. See [link to relevant documentation]. Figure 1-7 The production process includes the following steps:

[0036] (1) First, the silicon substrate 1 is textured on both sides to form a pyramidal textured surface on the front and back sides of the silicon substrate 1. Then, a tunneling oxide layer 3 is prepared on the front side of the silicon substrate 1. The silicon wafer structure after step (1) is as follows. Figure 1 As shown.

[0037] It should be noted that in this embodiment, the silicon substrate 1 is processed so that the surface of the silicon substrate 1 is also provided with other layered structures such as the tunneling oxide layer 3. At this time, the silicon substrate 1 and other layered structures are collectively referred to as silicon wafers.

[0038] In step (1), the silicon substrate 1 is selected as an N-type silicon substrate with a thickness ranging from 130-180 μm (preferably 150 μm), a size of 182*182 mm, and a resistivity of 1-9 Ω·cm. After double-sided texturing, a pyramidal textured surface of 0.5 μm-3 μm is formed on both the front and back sides of the silicon substrate 1.

[0039] Taking NaOH solution as the reagent for double-sided texturing as an example, the process conditions for double-sided texturing are as follows: the texturing temperature is 60-90℃ (preferably 75℃), the time is 380-420s (preferably 410s), and the volume fraction of NaOH solution is 2.50%-3.50% (preferably 3%).

[0040] Of course, other alkaline solutions can also be used as reagents for double-sided flocking; NaOH solution is preferred because the pyramidal flocking surface obtained by flocking with NaOH solution is more uniform.

[0041] In step (1), the tunneling oxide layer 3 is prepared by thermal oxidation, preferably by Popaid (plasma-assisted oxidation and plasma-assisted in-situ doping deposition) method; the thickness of the tunneling oxide layer 3 is 0.5 nm-2.5 nm (e.g., 0.6-2 nm), and the material is SiO2. x .

[0042] Taking the preparation of tunneling oxide layer 3 using the Popaid method as an example, the process conditions of the Popaid method are: temperature of 400-450℃ (preferably 420℃), oxygen of 5SLM, plasma-enhanced oxidation, and the carrier speed in the Popaid equipment is 5-10cm / s (preferably 5cm / s).

[0043] (2) After step (1), the tunneling oxide layer 3 in the non-metallized region (corresponding to the non-polyfinger region) is opened, exposing the front side of the silicon substrate 1 in the non-polyfinger region, while retaining the tunneling oxide layer 3 in the metallized region (corresponding to the polyfinger region). The silicon wafer structure after step (2) is as follows. Figure 2 As shown.

[0044] In step (2), it is preferable to use a laser to open the hole, and the width of the hole is 500μm-1500μm (e.g., 800μm).

[0045] Specifically, an ultraviolet laser is used for hole opening, and the opening is performed at a low power of 5-15W; the laser power is preferably 5W, which can not only complete the opening well, but also cause less damage to the silicon substrate 1.

[0046] Moreover, compared with traditional drilling methods (wet drilling, screen printing), laser drilling has higher precision, is easier to control, and is more operable.

[0047] (3) After step (2), an amorphous silicon layer 4 is fabricated on the entire front side of the silicon wafer (including the front side of the tunneling oxide layer 3 retained in the non-polyfin regions and the front side of the silicon substrate 1 exposed in the polyfin regions). The silicon wafer structure after step (3) is as follows: Figure 3 As shown.

[0048] In step (3), the amorphous silicon layer 4 is prepared by LPCVD (low-pressure chemical vapor deposition) or other existing deposition methods. The thickness of the amorphous silicon layer 4 is 100nm-150nm (e.g., 120-130nm).

[0049] Taking the preparation of amorphous silicon layer 4 by LPCVD as an example, the process conditions are as follows: deposition temperature 400-500℃ (preferably 450℃, at which temperature the deposition is more uniform), deposition time 12-15min (preferably 13min, to make the deposition thickness better), deposition pressure 50-60Pa (preferably 55Pa, to make the deposition more stable), and SiH4 flow rate 800-850sccm (preferably 830sccm).

[0050] (4) Boron diffusion doping is performed on the amorphous silicon layer 4 to form a p+poly layer 41 (i.e., a p+ polycrystalline silicon layer). The boron doping source in the non-poly finger region will penetrate the amorphous silicon layer 4 to simultaneously dope the silicon substrate 1. This boron diffusion doping process will also grow a BSG (i.e., borosilicate glass) layer on the surface (e.g., the front side) of the p+poly layer 41. The silicon wafer structure after step (4) is as follows: Figure 4 As shown.

[0051] In step (4), during the boron diffusion doping process: (a) the amorphous silicon layer 4 can form a p+poly layer 41. (b) since there is no tunneling oxide layer 3 in the non-poly finger region, the boron doping source in the non-poly finger region can directly pass through the amorphous silicon layer 4 to perform good boron doping on the silicon substrate 1; while because of the tunneling oxide layer 3, the amount of boron doping on the silicon substrate 1 located in the poly finger region is relatively small; thus, only one step of boron diffusion doping is needed to achieve good boron doping on the silicon substrate 1 in the non-poly finger region and a small amount of doping on the silicon substrate 1 in the poly finger region, thereby initially forming a P+ emitter 2 on the silicon substrate 1. (c) the boron diffusion doping process will also form a BSG layer 5 with a thickness of 50nm-120nm (e.g., 80-100nm) on the surface of the p+poly layer 41.

[0052] In step (4), the boron diffusion doping is tubular high-temperature boron diffusion doping, and the diffusion process is a two-step through-source method: the deposition temperature is 750-890℃ (preferably 800℃), the deposition time is 15-35min (preferably 30min); the drive temperature is 850-1000℃ (preferably 900℃, to achieve better doping while ensuring junction depth), and the drive time is 10-50min (preferably 40min). The sheet resistance of the p+poly layer 41 after doping is 150-400Ω / □ (e.g., 280-330Ω / □), and the sheet resistance of the P+ emitter 2 in the non-poly finger region is 30-100Ω / □ (e.g., 50-80Ω / □).

[0053] (5) After step (4), holes are made in the BSG layer 5 in the non-polyfinger region to expose the front side of the p+poly layer 41 in the non-polyfinger region, while retaining the BSG layer 5 in the polyfinger region. The silicon wafer structure after step (5) is as follows. Figure 5 As shown.

[0054] In step (5), laser is preferably used to create the opening. Specifically, an ultraviolet laser is used to create the opening in the BSG layer 5. The opening is performed at a low power of 5-15W (preferably 12W, which ensures that the BSG layer 5 in the non-polyfinger region is completely removed).

[0055] (6) After step (5), the opening region 6 is cleaned to remove the p+poly layer 41 of the non-poly finger region (corresponding to the opening region 6), and the boron-doped silicon substrate 1 located in the opening region 6 is washed away, while the boron-doped silicon substrate 1 in the opening region 6 is retained, so as to control the boron doping amount of the silicon substrate 1 in the opening region 6, so that the maximum surface concentration of the P+ emitter 2 and the junction depth of the PN junction in the opening region 6 are appropriate. The silicon wafer structure after step (6) is as follows. Figure 6 As shown.

[0056] In step (6), a dilute alkaline solution (referred to as alkaline solution) is used to clean the opening area 6. Taking the cleaning of the opening area 6 with NaOH solution as an example, the cleaning process conditions are as follows: the alkaline solution is a NaOH solution with a volume ratio of NaOH to water of 1%-3.5% (preferably 3%), and the cleaning time is 2-5 min (preferably 4 min); after cleaning, the sheet resistance of the P+ emitter 2 increases from 30-100Ω / □ (e.g., 50-80Ω / □) to 70-150Ω / □ (100-150Ω / □).

[0057] (7) After step (6), the silicon wafer is cleaned with HF solution to remove the BSG layer 5 in the polyfin region, thus obtaining the p+ polyfin structure. After step (7), a P+ local tunneling passivation contact structure with a P+ emitter 2 can be formed on the silicon substrate 1, as shown in the figure. Figure 7 As shown.

[0058] In step (7), a typical cleaning condition is: the volume ratio of HF solution is 2%-5% (e.g., 3%), and the cleaning time is 3-5 min (e.g., 4 min).

[0059] The fabrication method described in steps (1) to (7) of this embodiment is particularly suitable for application in TOPCon batteries to improve the passivation contact effect of the front metallization of the battery, avoid direct contact between the front metal grid lines of the battery and the silicon substrate 1, reduce metal recombination and resistivity, and at the same time achieve the absence of the p+poly layer 41 blocking the non-metallized area, eliminate the parasitic absorption caused by the front p+poly layer 41, and increase the J of the battery. SC (Short-circuit current density).

[0060] Performance testing

[0061] In step (6) of test example 1, the effects of different NaOH to water volume ratios and different cleaning times on the doping performance of the open-pore region (corresponding to the non-polyfin region or non-metallized region) were investigated.

[0062] Table 1

[0063]

[0064] The sheet resistance (Rs) of the P+ emitter affects the cell's Voc (open-circuit voltage) and FF (fill factor). Generally, increasing Rs increases Voc while decreasing FF. To ensure good conversion efficiency, Rs cannot be too high or too low. A shallow PN junction depth places higher demands on minority carrier lifetime. The maximum surface concentration of the ECV (electrochemical capacitance voltage) curve measured at the P+ emitter affects contact resistance and Auger recombination. Doping level is characterized by both the PN junction depth and the maximum surface concentration of the ECV curve at the P+ emitter.

[0065] In Table 1, sample 5, when the volume ratio of NaOH to water is 3% and the cleaning time is 4 min, can achieve a suitable maximum surface concentration of P+ emitter and a suitable junction depth of PN junction in the open area, so as to control the boron doping amount of silicon substrate in the open area. Therefore, the sheet resistance of P+ emitter is more suitable, and the effect of P+ emitter is the best.

[0066] Therefore, the method for fabricating the P+ local tunneling passivation contact structure of the present invention, while achieving the fabrication of the P+ emitter and p+ poly finger structure through a single doping process, also removes the p+ poly layer in the non-poly finger region (thus forming the local tunneling passivation contact structure) by controlling the concentration of the alkaline solution and the cleaning time during the alkaline cleaning process. This not only achieves the purpose of controlling the doping amount of the silicon substrate, but also obtains a P+ emitter with the maximum surface concentration, junction depth and moderate sheet resistance on the silicon substrate in the non-metallized region, improves the quality of the P+ emitter, helps to improve the battery conversion efficiency, and greatly simplifies the fabrication process and reduces costs.

[0067] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0068] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for fabricating a P+ local tunneling passivation contact structure, characterized in that, The production steps include the following: S1. Prepare a tunneling oxide layer on the front side of the texturized silicon substrate; S2. Localize the tunnel oxide layer to expose the front side of the silicon substrate in the non-metallized region, while retaining the tunnel oxide layer on the front side of the silicon substrate in the metallized region. S3. An amorphous silicon layer is prepared on the front side of the tunneling oxide layer and the exposed silicon substrate. S4. Boron diffusion doping is performed on the entire amorphous silicon layer to form a p+ polycrystalline silicon layer. The boron doping source in the non-metallized region will pass through the amorphous silicon layer to dope the silicon substrate to form a P+ emitter, and a full borosilicate glass layer will be formed on the front side of the p+ polycrystalline silicon layer. S5. After opening the borosilicate glass layer in the non-metallized region, perform alkaline cleaning on the opening region to remove the p+ polysilicon layer in the non-metallized region and wash away some of the doped silicon substrate in the opening region, so as to control the boron doping amount of the silicon substrate in the opening region and improve the P+ emitter in the opening region. S6. Then remove the borosilicate glass layer in the metallized area.

2. The method for fabricating a P+ local tunneling passivation contact structure according to claim 1, characterized in that, In steps S2 and S5, laser is used to create the opening.

3. The method for fabricating a P+ local tunneling passivation contact structure according to claim 2, characterized in that, In steps S2 and S5, an ultraviolet laser is used to make the opening, and the laser power for opening is 5-15W.

4. The method for fabricating a P+ local tunneling passivation contact structure according to claim 1, characterized in that, In step S4, the thickness of the borosilicate glass layer is 50nm-120nm.

5. The method for fabricating a P+ local tunneling passivation contact structure according to claim 1, characterized in that, In step S4, the boron diffusion doping is tubular boron diffusion doping, and the diffusion process is a two-step through-source method; the sheet resistance of the obtained p+ polysilicon layer is 150-400Ω / □, and the sheet resistance of the doped P+ emitter is 30-100Ω / □.

6. A method for fabricating a P+ local tunneling passivation contact structure according to claim 1 or 5, characterized in that, In step S5, the alkaline cleaning uses a NaOH solution with a NaOH to water volume ratio of 1%-3.5%, and the cleaning time is 2-5 minutes, so that the sheet resistance of the P+ emitter in the improved pore region is 70-150 Ω / □ and the maximum surface concentration is 4.2e19-5.0e19 cm⁻¹. 3 The junction depth of the PN junction is 0.49-0.70um.

7. The method for fabricating a P+ local tunneling passivation contact structure according to claim 6, characterized in that, In step S5, the volume ratio of NaOH to water in the NaOH solution is 3%, and the washing time is 4 minutes, so that the sheet resistance of the P+ emitter in the improved pore region is 140 Ω / □ and the maximum surface concentration is 4.2e19 cm⁻¹. 3 The junction depth of the PN junction is 0.49um.

8. The method for fabricating a P+ local tunneling passivation contact structure according to claim 1, characterized in that, In step S6, an HF solution is used for cleaning to remove the borosilicate glass layer in the metallized area.

9. The method for fabricating a P+ local tunneling passivation contact structure according to claim 1, characterized in that, In step S3, the amorphous silicon layer is prepared by low-pressure chemical vapor deposition to form an amorphous silicon layer with a thickness of 100nm-150nm.

10. An application of a method for fabricating a P+ local tunneling passivation contact structure, characterized in that, The method for fabricating a P+ local tunneling passivation contact structure according to any one of claims 1-9 is applied to the preparation of TOPCon cells.

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