Dual decision under-voltage protection circuit of GaN driving chip

Abstract

This invention discloses a dual-decision undervoltage protection circuit for a GaN driver chip, comprising: a bandgap reference module for generating a low-temperature drift reference voltage; a decision voltage module for outputting a first reference voltage and a second reference voltage, comparing the first and second reference voltages with the low-temperature drift reference voltage to generate a comparison result, and determining the state of the undervoltage protection circuit based on the comparison result; and a logic control module for generating a drive signal based on a clock signal and the output signal of the decision voltage module when the undervoltage protection circuit is in a deactivated state. The drive signal is used to drive the GaN transistor in the switching circuit. This invention employs a dual comparison reference circuit, performing two logical decisions on the output result. If both decisions pass, the voltage is output to the GaN gate, improving the accuracy of the comparator comparison result.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a dual-decision undervoltage protection circuit for a GaN driver chip. Background Technology

[0002] Driven by the new energy vehicle electronics industry, higher demands are being placed on power systems. Wide-bandgap semiconductor materials, represented by GaN, have overcome the problems of traditional Si-based materials, such as low melting point, high power consumption, slow electron drift at high frequencies, and inability to withstand high voltage. They have become the mainstream devices for automotive electronic power devices, key core components supporting the construction of "new infrastructure," and a current research hotspot for automotive drive chips.

[0003] However, GaN-based devices are exceptionally sensitive at their gates, with voltages typically not exceeding 6V (5V is the optimal design). This low threshold voltage characteristic leads to a low gate voltage premature power-on, causing overall system malfunction (and in GaN-based driver circuits, malfunctions are generally irreversible). Therefore, to address the challenges of using GaN devices in driver circuits, a high-performance undervoltage protection circuit is needed to prioritize power supply analysis, determine normality through logic, and then output the protection signal to the GaN gate. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the present invention provides a dual-decision undervoltage protection circuit for GaN driver chips to solve the above-mentioned technical problems.

[0005] This invention provides a dual-decision undervoltage protection circuit for a GaN driver chip, comprising:

[0006] The bandgap reference module is used to generate a low-temperature drift reference voltage;

[0007] The decision voltage module is used to output a first reference voltage and a second reference voltage, compare the first reference voltage and the second reference voltage with the low temperature drift reference voltage respectively to generate a comparison result, and determine the state of the undervoltage protection circuit based on the comparison result. The state includes: undervoltage protection state and undervoltage protection deactivated state.

[0008] The logic control module, when the undervoltage protection circuit is in the state of being deactivated, generates a drive signal based on the clock signal and the output signal of the decision voltage module. The drive signal is used to drive the GaN transistor in the switching circuit.

[0009] In one embodiment of the present invention, the bandgap reference module includes: a current mirror circuit, a low temperature drift reference voltage generation circuit, and a startup circuit.

[0010] In one embodiment of the present invention, the current mirror circuit includes:

[0011] First transistor to fourth transistor;

[0012] The gate of the first transistor is connected to the source and the gate of the first transistor, respectively. The drain of the first transistor is grounded to the drain of the first transistor, respectively. The source of the first transistor is connected to the source of the third transistor, and the source of the first transistor is connected to the drain of the fourth transistor. The drain of the third transistor is connected to the drain of the fourth transistor to form a first electrical node. An input voltage is applied to the first electrical node.

[0013] In one embodiment of the present invention, the low-temperature drift reference voltage generation circuit includes:

[0014] The first resistor to the fourth resistor is used for transistors five through seven.

[0015] The gate of the fifth transistor is connected to the source of the first transistor. The source of the fifth transistor is connected to the source of the sixth transistor to form a second electrical junction. The drain of the fifth transistor is grounded. The gate of the fourth transistor is connected to the gate of the sixth transistor to form a third electrical junction. The gate of the fourth transistor is connected to the second electrical junction. The drain of the seventh transistor is connected to an external power supply. The gate of the seventh transistor is connected to an external bias voltage. The source of the seventh transistor is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor. The other end of the second resistor is connected to the third electrical junction. One end of the third resistor is connected to the third electrical junction. The other end of the third resistor is grounded. The drain of the sixth transistor is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to the source of the seventh transistor. The connection between the first and second resistors outputs a low-temperature drift reference voltage.

[0016] In one embodiment of the present invention, the current mirror circuit further includes a seventh resistor, which is connected between the source of the seventh transistor and the first electrical node.

[0017] In one embodiment of the present invention, the startup circuit includes:

[0018] The eighth transistor, the ninth transistor, the first transistor, the second transistor, the fifth resistor, and the sixth resistor;

[0019] The gate of the eighth transistor is connected to the source of the eighth transistor and the gate of the ninth transistor, respectively. The drain of the eighth transistor and the drain of the ninth transistor are grounded, respectively. The source of the eighth transistor is connected to the emitter of the first transistor. The emitter of the first transistor is connected to the source of the ninth transistor. The base of the first transistor is connected to the second electrical junction, respectively. The collector of the first transistor is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to one end of the sixth resistor. The collector of the second transistor is connected to one end of the sixth resistor. The other end of the sixth resistor is connected to the source of the seventh transistor.

[0020] In one embodiment of the present invention, the decision voltage module includes:

[0021] Eighth to tenth resistors, first transmission gate, second transmission gate, first inverter, comparator;

[0022] The eighth, ninth, and tenth resistors are connected in series. The eighth resistor is connected to a power supply voltage, and the tenth resistor is grounded.

[0023] The connection terminals of the eighth and ninth resistors are connected to the input terminal of the first transmission gate. The output terminal of the first transmission gate is connected to the non-inverting input terminal of the comparator. The first output terminal of the comparator is connected to the first gate control signal terminal of the first transmission gate via the first inverter. The second output terminal of the comparator is connected to the input terminal of the logic control module. The power supply terminal of the comparator is connected to the source of the seventh transistor.

[0024] The connection terminals of the ninth and tenth resistors are connected to the input terminal of the second transmission gate. The output terminal of the second transmission gate is connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the low temperature drift reference voltage.

[0025] In one embodiment of the present invention, the logic control module includes:

[0026] Second inverter to fifth inverter, NAND gate, first AND gate to fourth AND gate, first delay circuit to fourth delay circuit, first OR gate to fourth OR gate;

[0027] The output of the decision voltage module is connected to one of the inputs of a NAND gate after passing through the second inverter, and the other input of the NAND gate is connected to the clock signal;

[0028] The first delay circuit, the first OR gate, the first AND gate, the second delay circuit, and the second OR gate are arranged in sequence; the third delay circuit, the third OR gate, the third AND gate, the fourth delay circuit, and the fourth OR gate are arranged in sequence. The output of the NAND gate is connected to the input of the first delay circuit, one input of the first OR gate, one input of the third AND gate, and the input of the third inverter, respectively. The output of the first delay circuit is connected to the other input of the first OR gate, and the output of the first OR gate is connected to one input of the first AND gate. The output of the third inverter is connected to the other input of the first AND gate, the input of the third delay circuit, and one input of the third OR gate, respectively. The output of the third delay circuit is connected to the other input of the third OR gate, and the output of the third OR gate is connected to the other input of the third AND gate, respectively. The first AND gate has its input terminals connected; the output terminal of the first AND gate is connected to the input terminal of the fourth inverter, the input terminal of the second delay circuit, and one of the input terminals of the second OR gate. The output terminal of the second delay circuit is connected to the other input terminal of the second OR gate. The output terminal of the second OR gate and the output terminal of the fourth inverter are each connected to one input terminal of the second AND gate. The output terminal of the second AND gate is used to connect to the GaN transistor in the switching circuit. The third AND gate has its output terminal connected to the input terminal of the fifth inverter, the input terminal of the fourth delay circuit, and one of the input terminals of the fourth OR gate. The output terminal of the fourth delay circuit is connected to the other input terminal of the fourth OR gate. The output terminal of the fourth OR gate and the output terminal of the fifth inverter are each connected to one input terminal of the fourth AND gate. The output terminal of the fourth AND gate is used to connect to the GaN transistor in the switching circuit.

[0029] In one embodiment of the present invention, the first transistor N1, the fifth transistor, the eighth transistor, and the ninth transistor are NMOS transistors; the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor are PMOS transistors; and the first transistor Q1 and the second transistor Q2 are PNP transistors.

[0030] The beneficial effects of this invention are:

[0031] This invention discloses a dual-decision undervoltage protection circuit for a GaN driver chip, comprising: a bandgap reference module for generating a low-temperature drift reference voltage; a decision voltage module for outputting a first reference voltage and a second reference voltage, comparing the first and second reference voltages with the low-temperature drift reference voltage to generate a comparison result, and determining the state of the undervoltage protection circuit based on the comparison result, the state including: undervoltage protection state and undervoltage protection deactivated state; and a logic control module for generating a drive signal based on a clock signal and the output signal of the decision voltage module when the undervoltage protection circuit is in the undervoltage protection deactivated state, the drive signal being used to drive the GaN transistor in the switching circuit. This invention employs a dual comparison reference circuit, comparing the low-temperature drift reference voltage with the first and second reference voltages, performing a second logic decision on the output result, and outputting the voltage to the GaN gate terminal if both decisions pass, thereby improving the accuracy of the comparator comparison result and widening the hysteresis voltage to prevent the chip system from being accidentally turned on and burned out due to repeated power-frequency switching, thus improving the circuit's anti-interference capability.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0034] Figure 1 This is a schematic diagram of a dual-decision undervoltage protection circuit for a GaN driver chip according to an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of a dual-decision undervoltage protection circuit for a GaN driver chip according to another embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of a bandgap reference module in one embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of a decision voltage module in one embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of a logic control module in one embodiment of the present invention;

[0039] Figure 6 This is a schematic circuit layout diagram according to one embodiment of the present invention;

[0040] Figure 7 This is a simulation diagram of the enhanced anti-interference undervoltage protection process of a GaN driver chip according to an embodiment of the present invention. Detailed Implementation

[0041] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0042] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0044] Driven by the new energy vehicle electronics industry, higher demands are being placed on power systems. Wide-bandgap semiconductor materials, represented by GaN, have overcome the problems of traditional Si-based materials, such as low melting point, high power consumption, slow electron drift at high frequencies, and inability to withstand high voltage. They have become the mainstream devices for automotive electronic power devices, key core components supporting the construction of "new infrastructure," and a current research hotspot for automotive drive chips.

[0045] However, GaN-based devices, due to their exceptionally sensitive gate voltage (typically not exceeding 6V, with 5V being the optimal design), exhibit low threshold voltage characteristics. This leads to a low gate voltage premature power-on before the power supply reaches its normal operating state, resulting in overall system malfunction (GaN-based driver circuits typically exhibit irreversible malfunctions). Therefore, to address the aforementioned challenges of using GaN devices in driver circuits, a high-performance undervoltage protection circuit is needed to prioritize power supply analysis, determine normality through logic, and then output the protection signal to the GaN gate. Based on this, an embodiment of the present invention proposes an undervoltage protection circuit to solve the aforementioned technical problem.

[0046] Please see Figure 1 , Figure 1 This is a block diagram illustrating the principle of a dual-decision undervoltage protection circuit for a GaN driver chip according to an embodiment of this application. Figure 1 The undervoltage protection circuit includes:

[0047] Bandgap reference module 110 is used to generate a low-temperature drift reference voltage;

[0048] The decision voltage module 120 is used to output a first reference voltage and a second reference voltage, compare the first reference voltage and the second reference voltage with the low temperature drift reference voltage respectively to generate a comparison result, and determine the state of the undervoltage protection circuit based on the comparison result. The state includes: undervoltage protection state and undervoltage protection deactivated state.

[0049] The logic control module 130, when the undervoltage protection circuit is in the state of being deactivated, generates a drive signal based on the clock signal and the output signal of the decision voltage module. The drive signal is used to drive the GaN transistor in the switching circuit.

[0050] Therefore, the present invention employs a dual comparison reference circuit, which compares the low-temperature drift reference voltage with the first reference voltage and the second reference voltage, performs a second logic decision on the output result, and outputs the voltage to the GaN gate terminal if both decisions pass, thereby improving the accuracy of the comparator comparison result. At the same time, it widens the hysteresis voltage to prevent the chip system from being accidentally turned on and burned out due to repeated power-frequency switching, thus improving the circuit's anti-interference capability.

[0051] Please see Figure 2 , Figure 2 This is a block diagram illustrating the principle of a dual-decision undervoltage protection circuit for a GaN driver chip according to an embodiment of this application. Figure 2 The system includes a bandgap reference module, a decision voltage module, a clock module, and a logic control module. The decision voltage module includes a voltage divider network consisting of K resistors, a MUX circuit, and a high-speed comparator.

[0052] The bandgap reference module receives the first power supply voltage and generates a low temperature drift reference voltage and a second power supply voltage. The low temperature drift reference voltage is input to the negative phase input terminal of the comparator, and the second power supply voltage is connected to the power supply terminal of the comparator.

[0053] The voltage divider network takes a first reference voltage and a second reference voltage as inputs. The first reference voltage and the second reference voltage are used as inputs to the MUX circuit. The first reference voltage and the second reference voltage are compared with the low temperature drift reference voltage to generate a comparison result. The comparison result is input to the non-inverting input of the comparator. One output of the comparator is connected to the MUX circuit, and the other output of the comparator is connected to the logic control module. The logic control module generates a drive signal based on the clock signal and the output signal of the decision voltage module to drive the GaN transistor in the switching circuit.

[0054] The following provides a detailed description of each circuit / module in the dual-decision undervoltage protection circuit of the GaN driver chip.

[0055] Please see Figure 3 , Figure 3 This is a circuit diagram of a bandgap reference module according to one embodiment of this application. Figure 3 As shown, the bandgap reference module includes: a current mirror circuit, a low-temperature drift reference voltage generation circuit, and a startup circuit.

[0056] In one embodiment, the current mirror circuit includes:

[0057] First transistor N1, first transistor N2, third transistor P1, fourth transistor P2;

[0058] The gate of the first transistor N1 is connected to the source of the first transistor N1 and the gate of the first transistor N2. The drain of the first transistor N1 and the drain of the first transistor N2 are grounded. The source of the first transistor N1 is connected to the source of the third transistor P1. The source of the first transistor N2 is connected to the drain of the fourth transistor P2. The drain of the third transistor P1 and the drain of the fourth transistor P2 are connected to form a first electrical node. An input voltage is applied to the first electrical node.

[0059] In one embodiment, the low-temperature drift reference voltage generation circuit includes:

[0060] Fifth transistor N3, sixth transistor P3, seventh transistor P4, first resistor R6, second resistor R7, third resistor R8, fourth resistor R 10 ;

[0061] The gate of the fifth transistor N3 is connected to the source of the first transistor N2. The source of the fifth transistor N3 is connected to the source of the sixth transistor P3, forming a second electrical junction. The drain of the fifth transistor N3 is grounded. The gate of the fourth transistor P2 is connected to the gate of the sixth transistor P3, forming a third electrical junction. The gate of the fourth transistor P2 is connected to the second electrical junction. The drain of the seventh transistor P4 is connected to an external power supply. The gate of the seventh transistor P4 is connected to an external bias voltage. The source of the seventh transistor P4 is connected to one end of the first resistor R6. The other end of the first resistor R6 is connected to one end of the second resistor R7. The other end of the second resistor R7 is connected to the third electrical junction. One end of the third resistor R8 is connected to the third electrical junction. The other end of the third resistor R8 is grounded. The drain of the sixth transistor P3 is connected to the fourth resistor R6. 10 One end is connected to the fourth resistor R. 10 The other end is connected to the source of the seventh transistor P4, and the connection between the first resistor R6 and the second resistor R7 outputs a low temperature drift reference voltage.

[0062] In one embodiment, the current mirror circuit further includes a seventh resistor R9, which is connected between the source of the seventh transistor P4 and the first electrical node.

[0063] In one embodiment, the startup circuit includes:

[0064] The eighth transistor N4, the ninth transistor N5, the first transistor Q1, the second transistor Q2, the fifth resistor R5, and the sixth resistor R4;

[0065] The gate of the eighth transistor N4 is connected to the source of the eighth transistor N4 and the gate of the ninth transistor N5. The drain of the eighth transistor N4 and the drain of the ninth transistor N5 are grounded. The source of the eighth transistor N4 is connected to the emitter of the first transistor Q1. The emitter of the first transistor N2 is connected to the source of the ninth transistor N5. The base of the first transistor N1 and the base of the first transistor N2 are connected to the second electrical junction. The collector of the first transistor N1 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to one end of the sixth resistor R4. The collector of the second transistor Q2 is connected to one end of the sixth resistor R4. The other end of the sixth resistor R4 is connected to the source of the seventh transistor P4.

[0066] In one embodiment, the first transistor N1, the first transistor N2, the fifth transistor N3, the eighth transistor N4, and the ninth transistor N5 are NMOS transistors; the third transistor P1, the fourth transistor P2, the sixth transistor P3, and the seventh transistor P4 are PMOS transistors; and the first transistor Q1 and the second transistor Q2 are PNP transistors.

[0067] The main function of the bandgap reference module is to provide a high-precision reference voltage, allowing the PNP transistors to be designed in a 1:8 ratio. Under perfect current mirror adaptation, after the bandgap reference module is fully powered on, the collector currents flowing through the first transistor Q1 and the second transistor Q2 are the same, i.e.:

[0068] I C1 =I C2

[0069] At this moment, the current flowing through resistor R5 is:

[0070]

[0071] The formulas for collector current are:

[0072]

[0073]

[0074] In the formula, Is is the reverse saturation current of the transistor, and V T Since the voltage is thermal, it has a positive temperature coefficient. Therefore, the following equation can be derived:

[0075]

[0076] The voltage V1 is derived as follows:

[0077]

[0078] Taking the partial derivative (absolute value) of the reference voltage with respect to temperature in the above equation, we have:

[0079]

[0080] Where m is a dimensionless quantity = -1.5; E is the bandgap energy = 1.12 eV; Q is the charge quantity. Simulations were performed based on the operating point theory. After device debugging, V was obtained. BE1 =0.7V, when T=300K, then:

[0081]

[0082] To meet the requirements, the transistor area ratio is 8, therefore:

[0083]

[0084] Where K / Q = 0.087mv / K, substituting this into R4 / R5 = 4.477, we can satisfy the low temperature drift design.

[0085] Please see Figure 4 , Figure 4This is a circuit diagram of a decision voltage module according to an embodiment of this application. Figure 4 As shown, the decision voltage module includes:

[0086] The circuit consists of resistors R1 (eighth), R2 (ninth), and R3 (tenth), along with transmission gates T1 and T2, an inverter A1, and a comparator. Resistors R1, R2, and R3 are used to construct a voltage divider network and power supply V based on the circuit's decision requirements. S The outputs V1 and V2, the first transmission gate T1 and the second transmission gate T2 are connected to the positive input of comparator COMP1, and the negative input of comparator COMP1 is connected to the output V of the bandgap reference module. ref The comparator COMP1 output S is connected to the first transmission gate T1 and the second transmission gate T2 via the first inverter A1.

[0087] Specifically, the eighth resistor R1, the ninth resistor R2, and the tenth resistor R3 are connected in series. The eighth resistor R1 is connected to a power supply voltage, and the tenth resistor R3 is grounded.

[0088] The connection terminals of the eighth resistor R1 and the ninth resistor R2 are connected to the input terminal of the first transmission gate T1. The output terminal of the first transmission gate T1 is connected to the non-inverting input terminal of the comparator. The first output terminal of the comparator is connected to the first gate control signal terminal of the first transmission gate T1 via the first inverter. The second output terminal of the comparator is connected to the input terminal of the logic control module. The power supply terminal of the comparator is connected to the source of the seventh transistor P4.

[0089] The connection terminals of the ninth resistor R2 and the tenth resistor R3 are connected to the input terminal of the second transmission gate T2. The output terminal of the second transmission gate T2 is connected to the positive input terminal of the comparator, and the negative input terminal of the comparator is connected to the low temperature drift reference voltage.

[0090] Please see Figure 5 , Figure 5 This is a circuit diagram of a logic control module according to an embodiment of this application. Figure 5 As shown, the logic control module includes:

[0091] Second inverter A2 to fifth inverter A5, NAND gate B1, first AND gate C1 to fourth AND gate C4, first delay circuit D1 to fourth delay circuit D4, first OR gate E1 to fourth OR gate E4;

[0092] The decision output Z of comparator COMP1 is connected to the second inverter A2, and the output of the second inverter A2 is connected to the external clock V. clk Connected to NAND gate B1, then sequentially connected to the first delay circuit D1, the first OR gate E1, and the first AND gate C1, and connected to the input of the second AND gate C2 via the fourth inverter A4. Simultaneously, the first AND gate C1 is connected to the second OR gate E2 via the second delay circuit D2, and the second E2 outputs V through the second AND gate C2.up It operates at the high-side GaN switch gate, with the low-side connection method being the same as the high-side, and ultimately outputs V through the fourth gate C4. down It is applied to the low-side GaN switch gate.

[0093] Specifically, the output of the decision voltage module is connected to one input of NAND gate B1 after passing through the second inverter A2, and the other input of NAND gate B1 is connected to the clock signal; the first delay circuit D1, the first OR gate E1, the first AND gate C1, the second delay circuit D2, and the second OR gate E2 are arranged in sequence, and the third delay circuit D3, the third OR gate E3, the third AND gate C3, the fourth delay circuit D4, and the fourth OR gate E4 are arranged in sequence; the output of NAND gate B1 is connected to the input of the first delay circuit D1, one input of the first OR gate E1, one input of the third AND gate C3, and the input of the third inverter A3, respectively; the output of the first delay circuit D1 is connected to the other input of the first OR gate E1, and the output of the first OR gate E1 is connected to one input of the first AND gate C1; the output of the third inverter A3 is connected to the other input of the first AND gate C1, the input of the third delay circuit D3, and one input of the third OR gate E3, respectively; the output of the third delay circuit D3 is connected to the clock signal. The other input of the third OR gate E3 is connected, and the output of the third OR gate E3 is connected to the other input of the third AND gate C3. The output of the first AND gate C1 is connected to the input of the fourth inverter A4, the input of the second delay circuit D2, and one of the inputs of the second OR gate E2. The output of the second delay circuit D2 is connected to the other input of the second OR gate E2. The output of the second OR gate E2 and the output of the fourth inverter A4 are respectively connected to one input of the second AND gate C2. The output of the second AND gate C2 is used to connect to the GaN transistor in the switching circuit. The output of the third AND gate C3 is connected to the input of the fifth inverter A5, the input of the fourth delay circuit D4, and one of the inputs of the fourth OR gate E4. The output of the fourth delay circuit D4 is connected to the other input of the fourth OR gate E4. The output of the fourth OR gate E4 and the output of the fifth inverter A5 are respectively connected to one input of the fourth AND gate C4. The output of the fourth AND gate C4 is used to connect to the GaN transistor in the switching circuit.

[0094] For this invention, during power-on, the operational amplifier is at a low voltage (S=0), at which time the reference voltage V2 is output to the comparator input, and V3 < V ref Z outputs "1", indicating undervoltage protection; when V3 > V ref When the input voltage V2 is selected, the source (S) terminal of the operational amplifier (comparator) switches to "1" first, selecting the reference voltage V2 as the input of the comparator. After two comparisons, both V2 and V3 are greater than V2. refWhen the decision takes effect, Z outputs a "0" potential, thus releasing the undervoltage protection state. After the undervoltage protection state is released, the input clock passes through the logic control module, such as... Figure 4 As shown, it is converted into a pulse signal, used to drive the GaN half-bridge switch, and outputs a pulse voltage V. up V down Control the high-side and low-side GaN driving circuits.

[0095] Please see Figure 6 , Figure 6 This is a schematic circuit layout diagram of an embodiment of this application, which satisfies the high-voltage isolation island design of BCD process. Figure 7 To extract Figure 6 The simulation diagram shows the results of process corner simulation verification based on the parasitic parameters of the layout. The 0.5V hysteresis voltage requirement is met under various process corners, verifying the feasibility of the invention and demonstrating excellent anti-interference capability.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A dual-decision undervoltage protection circuit for a GaN driver chip, characterized in that, The undervoltage protection circuit includes: The bandgap reference module is used to generate a low-temperature drift reference voltage; The decision voltage module is used to output a first reference voltage and a second reference voltage, compare the first reference voltage and the second reference voltage with the low temperature drift reference voltage respectively to generate a comparison result, and determine the state of the undervoltage protection circuit based on the comparison result. The state includes: undervoltage protection state and undervoltage protection deactivated state. The logic control module, when the undervoltage protection circuit is in the state of de-undervoltage protection, generates a drive signal based on the clock signal and the output signal of the decision voltage module. The drive signal is used to drive the GaN transistor in the switching circuit. The bandgap reference module includes: a current mirror circuit, a low-temperature drift reference voltage generation circuit, and a startup circuit; The current mirror circuit includes: First transistor to fourth transistor; The gate of the first transistor is connected to the source and drain of the first transistor and the gate of the second transistor, respectively. The source of the first transistor and the source of the second transistor are grounded, respectively. The drain of the first transistor is connected to the drain of the third transistor. The drain of the second transistor is connected to the drain of the fourth transistor. The source of the third transistor and the source of the fourth transistor are connected to form a first electrical node. An input voltage is connected to the first electrical node. The low-temperature drift reference voltage generation circuit includes: Transistors five through seven, resistors one through four; The gate of the fifth transistor is connected to the drain of the second transistor. The drain of the fifth transistor is connected to the drain of the sixth transistor to form a second electrical junction. The source of the fifth transistor is grounded. The gate of the fourth transistor is connected to the gate of the sixth transistor to form a third electrical junction. The gate of the fourth transistor is connected to the third electrical junction. The source of the seventh transistor is connected to an external power supply. The gate of the seventh transistor is connected to an external bias voltage. The source of the seventh transistor is connected to one end of the first resistor. The other end of the first resistor is connected to one end of the second resistor. The other end of the second resistor is connected to the third electrical junction. One end of the third resistor is connected to the third electrical junction. The other end of the third resistor is grounded. The source of the sixth transistor is connected to one end of the fourth resistor. The other end of the fourth resistor is connected to the drain of the seventh transistor. The connection between the first and second resistors outputs a low temperature drift reference voltage. The current mirror circuit further includes a seventh resistor, which is connected between the drain of the seventh transistor and the first electrical node; The startup circuit includes: The eighth transistor, the ninth transistor, the first transistor, the second transistor, the fifth resistor, and the sixth resistor; The gate of the eighth transistor is connected to the drain of the eighth transistor and the gate of the ninth transistor, respectively. The source of the eighth transistor and the source of the ninth transistor are grounded, respectively. The drain of the eighth transistor is connected to the collector of the first transistor. The collector of the second transistor is connected to the drain of the ninth transistor. The base of the first transistor and the base of the second transistor are connected to the second electrical junction, respectively. The emitter of the first transistor is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to one end of the sixth resistor. The emitter of the second transistor is connected to one end of the sixth resistor. The other end of the sixth resistor is connected to the drain of the seventh transistor.

2. The dual-decision undervoltage protection circuit for the GaN driver chip according to claim 1, characterized in that, The decision voltage module includes: Eighth to tenth resistors, first transmission gate, second transmission gate, first inverter, comparator; The eighth, ninth, and tenth resistors are connected in series. The eighth resistor is connected to a power supply voltage, and the tenth resistor is grounded. The connection terminals of the eighth and ninth resistors are connected to the input terminal of the first transmission gate. The output terminal of the first transmission gate is connected to the non-inverting input terminal of the comparator. The first output terminal of the comparator is connected to the first gate control signal terminal of the first transmission gate via the first inverter. The second output terminal of the comparator is connected to the input terminal of the logic control module. The power supply terminal of the comparator is connected to the drain of the seventh transistor. The connection terminals of the ninth and tenth resistors are connected to the input terminal of the second transmission gate. The output terminal of the second transmission gate is connected to the positive input terminal of the comparator. The negative input terminal of the comparator is connected to the low temperature drift reference voltage.

3. The dual-decision undervoltage protection circuit for the GaN driver chip according to claim 2, characterized in that, The logic control module includes: Second inverter to fifth inverter, NAND gate, first AND gate to fourth AND gate, first delay circuit to fourth delay circuit, first OR gate to fourth OR gate; The output of the decision voltage module is connected to one of the inputs of a NAND gate after passing through the second inverter, and the other input of the NAND gate is connected to the clock signal; The first delay circuit, the first OR gate, the first AND gate, the second delay circuit, and the second OR gate are arranged in sequence; the third delay circuit, the third OR gate, the third AND gate, the fourth delay circuit, and the fourth OR gate are arranged in sequence. The output of the NAND gate is connected to the input of the first delay circuit, one input of the first OR gate, one input of the third AND gate, and the input of the third inverter, respectively. The output of the first delay circuit is connected to the other input of the first OR gate, and the output of the first OR gate is connected to one input of the first AND gate. The output of the third inverter is connected to the other input of the first AND gate, the input of the third delay circuit, and one input of the third OR gate, respectively. The output of the third delay circuit is connected to the other input of the third OR gate, and the output of the third OR gate is connected to the other input of the third AND gate, respectively. One input terminal is connected; the output terminal of the first AND gate is connected to the input terminal of the fourth inverter, the input terminal of the second delay circuit, and one of the input terminals of the second OR gate, respectively. The output terminal of the second delay circuit is connected to the other input terminal of the second OR gate, and the output terminal of the second OR gate is connected to the input terminal of the second AND gate, respectively, and the output terminal of the second AND gate is used to connect to the GaN transistor in the switching circuit; the output terminal of the third AND gate is connected to the input terminal of the fifth inverter, the input terminal of the fourth delay circuit, and one of the input terminals of the fourth OR gate, respectively. The output terminal of the fourth delay circuit is connected to the other input terminal of the fourth OR gate, and the output terminal of the fourth OR gate is connected to the input terminal of the fourth AND gate, respectively, and the output terminal of the fourth AND gate is used to connect to the GaN transistor in the switching circuit.

4. The dual-decision undervoltage protection circuit for the GaN driver chip according to claim 3, characterized in that, The first transistor, the second transistor, the fifth transistor, the eighth transistor, and the ninth transistor are NMOS transistors; the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor are PMOS transistors; and the first transistor Q1 and the second transistor Q2 are PNP transistors.

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