Class-c capacitance inductance voltage controlled oscillator for satellite communication in x-band and ku-band

Abstract

The application discloses an X-band and Ku-band Class-C capacitance inductance voltage-controlled oscillator applied to satellite communication, which comprises a gate bias circuit, a capacitance inductance resonant cavity, a cross-coupled negative resistance circuit, a switch capacitance array, two MOS transistors and two tail capacitors. The gate bias circuit is used for adjusting the oscillator to work in a Class-C mode. The capacitance inductance resonant cavity is used for forming a stable oscillation waveform. The cross-coupled negative resistance circuit is used for offsetting the energy consumed by a parasitic resistance in the resonant cavity to keep equal-amplitude oscillation. The switch capacitance array is used for realizing a wide-band tuning range. The two MOS transistors are used for increasing the transconductance of cross-coupled transistors. The two tail capacitors are used for accommodating parasitic capacitance and filtering high-frequency noise. The application can be divided into an N-type cross-coupled capacitance inductance voltage-controlled oscillator structure and a P-type cross-coupled capacitance inductance voltage-controlled oscillator structure according to different types of negative resistance structures. The Class-C capacitance inductance voltage-controlled oscillator provided by the application overcomes the difficulty in starting and does not need to make two inductances into a coupling form of a transformer, thereby avoiding the problems of low coupling degree and large coupling attenuation of a transformer in a CMOS process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to an X-band and Ku-band Class-C capacitor-inductor voltage-controlled oscillator for satellite communications. Background Technology

[0002] In modern communication systems, satellite communication plays an increasingly important role. X-band and Ku-band technologies were developed earlier and are therefore widely used. The voltage-controlled oscillator (VCO) is a key component of an RF transceiver, providing the local clock signal for the system; therefore, its performance requirements are extremely stringent. Under low supply voltage conditions, Class-C VCOs exhibit better phase noise performance than VCOs with other architectures.

[0003] Traditional Class-C voltage-controlled oscillators have the following disadvantages: 1. Due to the influence of PVT characteristics and low gate bias, the circuit is not easy to start oscillating robustly; 2. Transformer-based Class-C voltage-controlled oscillators require the two inductors to be coupled in a transformer-like manner, but the coupling degree is low and the coupling attenuation is large in CMOS technology. Summary of the Invention

[0004] To address the aforementioned problems, the purpose of this invention is to provide a Class-C capacitor-inductor voltage-controlled oscillator for X-band and Ku-band satellite communications. This voltage-controlled oscillator overcomes the shortcomings of traditional Class-C voltage-controlled oscillators, making it easy to start oscillating and eliminating the need to couple the two inductors in a transformer-like manner, thus possessing practicality.

[0005] The specific technical solution for achieving the objective of this invention is as follows:

[0006] A Class-C capacitor-inductor voltage-controlled oscillator for X-band and Ku-band satellite communications includes: an N-type cross-coupled capacitor-inductor voltage-controlled oscillator structure and a P-type cross-coupled capacitor-inductor voltage-controlled oscillator structure;

[0007] The N-type cross-coupled capacitor-inductor voltage-controlled oscillator structure includes: a gate bias circuit composed of an adjustable resistor R1 and a first inductor L1, which adjusts the oscillator to operate in Class-C mode by controlling the gate bias voltage of the cross-coupled pair; a capacitor-inductor resonant cavity composed of variable capacitors C3, C4, C5, C6, C7, and L2, which forms a stable oscillation waveform through energy transfer; an N-type cross-coupled negative resistance circuit composed of a first NMOS transistor M1 and a second NMOS transistor M2, used to offset the energy consumed by parasitic resistance in the resonant cavity to maintain constant amplitude oscillation; a switched capacitor array for achieving a wide-band tuning range; a third PMOS transistor M3 and a fourth PMOS transistor M4 for increasing the transconductance of the cross-coupled transistors; and two tail capacitors, C1 and C2, used to accommodate parasitic capacitance and filter high-frequency noise. One end of the adjustable resistor R1 is connected to the power supply voltage V. DD One end is connected to the center tap of the first inductor L1; one end of the first capacitor C1 and the second capacitor C2 are both connected to the power supply voltage V. DD One end is connected to the first inductor L1, and the other end is connected to the two ends of the first inductor L1 respectively; one end of each of the variable capacitors C3 and C4 is connected to the input tuning voltage V. ctrl One end is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the first NMOS transistor M1, respectively; the two ends of the switched capacitor array are connected to the gates of the second NMOS transistor M2 and the first NMOS transistor M1, respectively; the gate of the first NMOS transistor M1 is connected to the second output port V. out2 The connection is made between the drain of the first NMOS transistor M1 and the first output port V. out1 The source of the first NMOS transistor M1 is connected to the source of the third PMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the first output port V. out1 The connection is made between the drain of the second NMOS transistor M2 and the second output port V. out2 The connections are as follows: the source of the second NMOS transistor M2 is connected to the source of the fourth PMOS transistor M4; one end of the fifth capacitor C5 is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the third PMOS transistor M3; one end of the sixth capacitor C6 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the fourth PMOS transistor M4; one end of the seventh capacitor C7 is connected to the gate of the third PMOS transistor M3, and the other end is connected to the gate of the fourth PMOS transistor M4; one end of the second inductor L2 is connected to the gate of the third PMOS transistor M3, and the other end is connected to the gate of the fourth PMOS transistor M4, with its center tap connected to ground; the drains of both the third PMOS transistor M3 and the fourth PMOS transistor M4 are connected to ground.

[0008] The P-type cross-coupled capacitor-inductor voltage-controlled oscillator structure includes: a gate bias circuit composed of an adjustable resistor R1 and a second inductor L2, which adjusts the oscillator to operate in Class-C mode by controlling the gate bias voltage of the cross-coupled pair; a capacitor-inductor resonant cavity composed of a first inductor L1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a variable capacitor C4, and a variable capacitor C5, which forms a stable oscillation waveform through energy transfer; a P-type cross-coupled negative resistance circuit composed of a third PMOS transistor M3 and a fourth PMOS transistor M4, used to offset the energy consumed by parasitic resistance in the resonant cavity to maintain constant amplitude oscillation; a switched capacitor array for achieving a wide-bandwidth tuning range; a first NMOS transistor M1 and a second NMOS transistor M2 for increasing the transconductance of the cross-coupled transistors; and a sixth capacitor C6 and a seventh capacitor C7 as two tail capacitors for accommodating parasitic capacitance and filtering high-frequency noise; wherein the drains of the first NMOS transistor M1 and the second NMOS transistor M2 are both connected to the power supply voltage V. DD Connections: One end of the first inductor L1 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the second NMOS transistor M2. The center tap is connected to the power supply voltage V. DD Connections: One end of the first capacitor C1 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the second NMOS transistor M2; one end of the second capacitor C2 is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the third PMOS transistor M3; one end of the third capacitor C3 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the fourth PMOS transistor M4; the gate of the third PMOS transistor M3 is connected to the second output port V. out2 The drain of the third NMOS transistor M3 is connected to the first output port V. out1 The source of the third NMOS transistor M3 is connected to the source of the first NMOS transistor M1; the gate of the fourth PMOS transistor M4 is connected to the first output port V. out1 The connection is made between the drain of the fourth NMOS transistor M4 and the second output port V. out2 The source of the fourth NMOS transistor M4 is connected to the source of the second NMOS transistor M2; one end of each of the variable capacitors C4 and C5 is connected to the input tuning voltage V. ctrl One end of the capacitor is connected to the gate of the fourth PMOS transistor M4, and the other end is connected to the gate of the third PMOS transistor M3, respectively. The two ends of the switched capacitor array are connected to the gate of the fourth PMOS transistor M4 and the gate of the third PMOS transistor M3, respectively. One end of the sixth capacitor C6 and the seventh capacitor C7 are both connected to ground, and the other end is connected to the two ends of the second inductor L2, respectively. One end of the adjustable resistor R1 is connected to ground, and the other end is connected to the center tap of the second inductor L2.

[0009] The beneficial effects of this invention are as follows: This X-band and Ku-band Class-C capacitor-inductor voltage-controlled oscillator for satellite communication uses a bias circuit composed of an inductor and an adjustable resistor to control the additional bias of the gate of the cross-coupled transistor, and adds two MOS transistors to increase the transconductance of the cross-coupled transistor, overcoming the disadvantage of low gate bias voltage of traditional Class-C voltage-controlled oscillators. Therefore, it is easy to start oscillation, and it does not require the two inductors to be coupled in the form of a transformer, avoiding the problems of low coupling and large coupling attenuation in CMOS process. Attached Figure Description

[0010] Figure 1 This is the N-type cross-coupled capacitor-inductor voltage-controlled oscillator structure of this invention.

[0011] Figure 2 This is the P-type cross-coupled capacitor-inductor voltage-controlled oscillator structure of the present invention;

[0012] Figure 3 This is a waveform diagram of the start-up of an N-type cross-coupled capacitor-inductor voltage-controlled oscillator structure in an embodiment of the present invention.

[0013] Figure 4 This is the start-up waveform diagram of the voltage-controlled oscillator structure with P-type cross-coupled capacitor-inductor in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] like Figure 1The diagram shows a schematic of a Class-C capacitor-inductor voltage-controlled oscillator (VCO) structure for X-band and Ku-band satellite communications. Specifically, it is an N-type cross-coupled capacitor-inductor VCO structure, comprising: a gate bias circuit consisting of an adjustable resistor R1 and a first inductor L1, which adjusts the oscillator to operate in Class-C mode by controlling the gate bias voltage of the cross-coupled pair, making it easier to start oscillation; a capacitor-inductor resonant cavity consisting of variable capacitors C3, C4, C5, C6, C7, and L2, which forms a stable oscillation waveform through energy transfer; an N-type cross-coupled negative resistance circuit consisting of a first NMOS transistor M1 and a second NMOS transistor M2, used to offset the energy consumed by parasitic resistance in the resonant cavity to maintain constant amplitude oscillation; a switched capacitor array for achieving a wide-band tuning range; a third PMOS transistor M3 and a fourth PMOS transistor M4 for increasing the transconductance of the cross-coupled transistors; and a first capacitor C1 and a second capacitor C2 as two tail capacitors used to accommodate parasitic capacitance and filter high-frequency noise. Specifically, this includes: one end of the adjustable resistor R1 connected to the power supply voltage V. DD One end is connected to the center tap of the first inductor L1; one end of the first capacitor C1 and the second capacitor C2 are both connected to the power supply voltage V. DD One end is connected to the first inductor L1, and the other end is connected to the two ends of the first inductor L1 respectively; one end of each of the variable capacitors C3 and C4 is connected to the input tuning voltage V. ctrl One end is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the first NMOS transistor M1, respectively; the two ends of the switched capacitor array are connected to the gates of the second NMOS transistor M2 and the first NMOS transistor M1, respectively; the gate of the first NMOS transistor M1 is connected to the second output port V. out2 The connection is made between the drain of the first NMOS transistor M1 and the first output port V. out1 The source of the first NMOS transistor M1 is connected to the source of the third PMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the first output port V. out1 The connection is made between the drain of the second NMOS transistor M2 and the second output port V. out2 The connections are as follows: the source of the second NMOS transistor M2 is connected to the source of the fourth PMOS transistor M4; one end of the fifth capacitor C5 is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the third PMOS transistor M3; one end of the sixth capacitor C6 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the fourth PMOS transistor M4; one end of the seventh capacitor C7 is connected to the gate of the third PMOS transistor M3, and the other end is connected to the gate of the fourth PMOS transistor M4; one end of the second inductor L2 is connected to the gate of the third PMOS transistor M3, and the other end is connected to the gate of the fourth PMOS transistor M4, with its center tap connected to ground; the drains of both the third PMOS transistor M3 and the fourth PMOS transistor M4 are connected to ground.

[0016] like Figure 2 The diagram shows a schematic of a Class-C capacitor-inductor voltage-controlled oscillator (VCO) structure for X-band and Ku-band satellite communications. Specifically, it is a P-type cross-coupled capacitor-inductor VCO structure, comprising: a gate bias circuit composed of an adjustable resistor R1 and a second inductor L2, which adjusts the oscillator to operate in Class-C mode by controlling the gate bias voltage of the cross-coupled pair, making it easier to start oscillation; a capacitor-inductor resonant cavity composed of a first inductor L1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a variable capacitor C4, and a variable capacitor C5, which forms a stable oscillation waveform through energy transfer; a P-type cross-coupled negative resistance circuit composed of a third PMOS transistor M3 and a fourth PMOS transistor M4, used to offset the energy consumed by parasitic resistance in the resonant cavity to maintain constant amplitude oscillation; a switched capacitor array for achieving a wide-band tuning range; a first NMOS transistor M1 and a second NMOS transistor M2 for increasing the transconductance of the cross-coupled transistors; and a sixth capacitor C6 and a seventh capacitor C7 as two tail capacitors for accommodating parasitic capacitance and filtering high-frequency noise. Specifically, this includes: the drain of the first NMOS transistor M1 and the drain of the second NMOS transistor M2 are both connected to the power supply voltage V. DD Connections: One end of the first inductor L1 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the second NMOS transistor M2. The center tap is connected to the power supply voltage V. DD Connections: One end of the first capacitor C1 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the second NMOS transistor M2; one end of the second capacitor C2 is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the third PMOS transistor M3; one end of the third capacitor C3 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the fourth PMOS transistor M4; the gate of the third PMOS transistor M3 is connected to the second output port V. out2 The drain of the third NMOS transistor M3 is connected to the first output port V. out1 The source of the third NMOS transistor M3 is connected to the source of the first NMOS transistor M1; the gate of the fourth PMOS transistor M4 is connected to the first output port V. out1 The connection is made between the drain of the fourth NMOS transistor M4 and the second output port V. out2 The source of the fourth NMOS transistor M4 is connected to the source of the second NMOS transistor M2; one end of each of the variable capacitors C4 and C5 is connected to the input tuning voltage V. ctrlOne end of the capacitor is connected to the gate of the fourth PMOS transistor M4, and the other end is connected to the gate of the third PMOS transistor M3, respectively. The two ends of the switched capacitor array are connected to the gate of the fourth PMOS transistor M4 and the gate of the third PMOS transistor M3, respectively. One end of the sixth capacitor C6 and the seventh capacitor C7 are both connected to ground, and the other end is connected to the two ends of the second inductor L2, respectively. One end of the adjustable resistor R1 is connected to ground, and the other end is connected to the center tap of the second inductor L2.

[0017] For traditional Class-C voltage-controlled oscillators, in order to ensure that the cross-coupled transistor operates in the saturation region, the following must be satisfied:

[0018] V D >V G -V th

[0019] The most stringent conditions are:

[0020] V D-min =V DD -A tank

[0021] V G-max =V gbias +kA tank

[0022] That is:

[0023]

[0024] In the formula, V th A is the threshold voltage of the cross-coupled transistor. tank V is the single-end amplitude of the resonant cavity. gbias V is the gate bias voltage of the cross-coupled transistor, k is the AC voltage feedback factor from the resonant cavity to the gate of the cross-coupled transistor, and V is the gate bias voltage of the cross-coupled transistor. DD Let V be the power supply voltage, and assume k = 1. Also, since V... gbias >V th +V od V od Because this is the overdrive voltage of the cross-coupled transistor, the maximum output amplitude is as follows:

[0025]

[0026] The output amplitude is relatively small, so traditional Class-C voltage-controlled oscillators have the problem of difficulty in starting up.

[0027] In this invention, a bias circuit consisting of an inductor and an adjustable resistor is used to control the gate bias voltage of the cross-coupled transistor, and two MOSFETs are added to increase the transconductance of the cross-coupled transistor. This overcomes the shortcomings of traditional Class-C voltage-controlled oscillators, making oscillation easier to start. Figure 3 and Figure 4 The oscillation waveform diagram of the embodiment is given, showing that both Class-C capacitor-inductor voltage-controlled oscillators can stably output waveforms within 14ns. Furthermore, it eliminates the need to make the two inductors into a transformer-like coupling form, avoiding the problems of low coupling and large coupling attenuation in CMOS processes.

[0028] The foregoing describes the basic principles, main features, and advantages of this invention, but it should not be construed that the specific implementation of this invention is limited to these descriptions. For those skilled in the art, various changes and modifications can be made without departing from the concept of this invention, and these all fall within the scope of protection of this invention. Therefore, the scope of protection of this invention is defined by the claims.

Claims

1. A Class-C capacitor-inductor voltage-controlled oscillator for X-band and Ku-band satellite communications, characterized in that, include: N-type cross-coupled capacitor-inductor voltage-controlled oscillator structure and P-type cross-coupled capacitor-inductor voltage-controlled oscillator structure; The N-type cross-coupled capacitor-inductor voltage-controlled oscillator structure includes: a gate bias circuit composed of an adjustable resistor R1 and a first inductor L1, which adjusts the oscillator to operate in Class-C mode by controlling the gate bias voltage of the cross-coupled pair; a capacitor-inductor resonant cavity composed of variable capacitors C3, C4, C5, C6, C7, and L2, which forms a stable oscillation waveform through energy transfer; an N-type cross-coupled negative resistance circuit composed of a first NMOS transistor M1 and a second NMOS transistor M2, used to offset the energy consumed by parasitic resistance in the resonant cavity to maintain constant amplitude oscillation; a switched capacitor array for achieving a wide-band tuning range; a third PMOS transistor M3 and a fourth PMOS transistor M4 for increasing the transconductance of the cross-coupled transistors; and two tail capacitors, C1 and C2, used to accommodate parasitic capacitance and filter high-frequency noise. One end of the adjustable resistor R1 is connected to the power supply voltage V. DD One end is connected to the center tap of the first inductor L1; one end of the first capacitor C1 and the second capacitor C2 are both connected to the power supply voltage V. DD One end is connected to the first inductor L1, and the other end is connected to the two ends of the first inductor L1 respectively; one end of each of the variable capacitors C3 and C4 is connected to the input tuning voltage V. ctrl The variable capacitor C3 is connected to the gate of the second NMOS transistor M2 and the other end of the first capacitor C1, respectively. The variable capacitor C4 is connected to the gate of the first NMOS transistor M1 and the other end of the second capacitor C2, respectively. The two ends of the switched capacitor array are connected to the gates of the second NMOS transistor M2 and the first NMOS transistor M1, respectively. The gate of the first NMOS transistor M1 is connected to the second output port V. out2 The connection is made between the drain of the first NMOS transistor M1 and the first output port V. out1 The source of the first NMOS transistor M1 is connected to the source of the third PMOS transistor M3; the gate of the second NMOS transistor M2 is connected to the first output port V. out1 The connection is made between the drain of the second NMOS transistor M2 and the second output port V. out2 The connections are as follows: the source of the second NMOS transistor M2 is connected to the source of the fourth PMOS transistor M4; one end of the fifth capacitor C5 is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the third PMOS transistor M3; one end of the sixth capacitor C6 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the fourth PMOS transistor M4; one end of the seventh capacitor C7 is connected to the gate of the third PMOS transistor M3, and the other end is connected to the gate of the fourth PMOS transistor M4; one end of the second inductor L2 is connected to the gate of the third PMOS transistor M3, and the other end is connected to the gate of the fourth PMOS transistor M4, with its center tap connected to ground; the drains of both the third PMOS transistor M3 and the fourth PMOS transistor M4 are connected to ground. The P-type cross-coupled capacitor-inductor voltage-controlled oscillator structure includes: a gate bias circuit composed of an adjustable resistor R1 and a second inductor L2, which adjusts the oscillator to operate in Class-C mode by controlling the gate bias voltage of the cross-coupled pair; a capacitor-inductor resonant cavity composed of a first inductor L1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a variable capacitor C4, and a variable capacitor C5, which forms a stable oscillation waveform through energy transfer; a P-type cross-coupled negative resistance circuit composed of a third PMOS transistor M3 and a fourth PMOS transistor M4, used to offset the energy consumed by parasitic resistance in the resonant cavity to maintain constant amplitude oscillation; a switched capacitor array for achieving a wide-bandwidth tuning range; a first NMOS transistor M1 and a second NMOS transistor M2 for increasing the transconductance of the cross-coupled transistors; and a sixth capacitor C6 and a seventh capacitor C7 as two tail capacitors for accommodating parasitic capacitance and filtering high-frequency noise; wherein the drains of the first NMOS transistor M1 and the second NMOS transistor M2 are both connected to the power supply voltage V. DD Connections: One end of the first inductor L1 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the second NMOS transistor M2. The center tap is connected to the power supply voltage V. DD Connections: One end of the first capacitor C1 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the second NMOS transistor M2; one end of the second capacitor C2 is connected to the gate of the second NMOS transistor M2, and the other end is connected to the gate of the third PMOS transistor M3; one end of the third capacitor C3 is connected to the gate of the first NMOS transistor M1, and the other end is connected to the gate of the fourth PMOS transistor M4; the gate of the third PMOS transistor M3 is connected to the second output port V. out2 The drain of the third NMOS transistor M3 is connected to the first output port V. out1 The source of the third NMOS transistor M3 is connected to the source of the first NMOS transistor M1; the gate of the fourth PMOS transistor M4 is connected to the first output port V. out1 The connection is made between the drain of the fourth NMOS transistor M4 and the second output port V. out2 The source of the fourth NMOS transistor M4 is connected to the source of the second NMOS transistor M2; one end of each of the variable capacitors C4 and C5 is connected to the input tuning voltage V. ctrl The variable capacitor C4 is connected to the gate of the fourth PMOS transistor M4 and the other end of the sixth capacitor C6. The variable capacitor C5 is connected to the gate of the third PMOS transistor M3 and the other end of the seventh capacitor C7. The two ends of the switched capacitor array are connected to the gate of the fourth PMOS transistor M4 and the gate of the third PMOS transistor M3, respectively. One end of the sixth capacitor C6 and the seventh capacitor C7 are both connected to ground, and the other end is connected to the two ends of the second inductor L2, respectively. One end of the adjustable resistor R1 is connected to ground, and the other end is connected to the center tap of the second inductor L2.

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