A single-loop network dual-band doherty power amplifier

Abstract

The application relates to the technical field of wireless communication, in particular to a single-loop network double-band Doherty power amplifier which comprises a power divider, a first input matching network, a second input matching network, a carrier power amplifier, a peak power amplifier, a first output matching network, a second output matching network, a loop network and a post-matching network; input power is evenly divided into two signals by the power divider, one of which reaches the carrier power amplifier through the first input matching network, and the other reaches the peak power amplifier through the second input matching network, and then is output through the first output matching network and the second output matching network respectively and is power-combined in the loop network, and finally is output through the post-matching network. The application optimizes the load modulation structure of the Doherty power amplifier, and realizes different load modulation routes in different working frequency bands by setting the characteristics of the loop network at different frequency points.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and specifically to a single-ring network dual-band Doherty power amplifier. Background Technology

[0002] With the improvement and development of modern wireless communication technology, the efficiency of wireless communication technology is becoming increasingly higher, but spectrum resources are extremely scarce. To improve spectrum efficiency, modem wireless communication systems often employ modulation signals with a high peak-to-average power ratio (PAPR). Simultaneously, the coverage of high-performance base stations is expanding, necessitating a reduction in the implementation and operation costs of base stations. These requirements have driven the development of power amplifiers. The performance of traditional power amplifiers is no longer sufficient to meet these demands. Doherty power amplifiers (DPAs) have gained favor among researchers due to their simple and easy-to-implement architecture and ability to maintain high efficiency even in the power back-off region. However, the limitations of quarter-wavelength impedance inverters result in a relatively narrow bandwidth for traditional DPAs. Therefore, solving the bandwidth problem of DPAs has become a pressing technical challenge in this field. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a single-ring network dual-band Doherty power amplifier, and to propose a new solution for the load modulation structure of the Doherty power amplifier. By setting the characteristics of the ring network at different frequency points, a Doherty power amplifier with different load modulation paths in different operating frequency bands can be realized.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A single-ring network dual-band Doherty power amplifier, connected from the signal input terminal, includes a power divider, a first input matching network, a second input matching network, a carrier power amplifier, a peak power amplifier, a first output matching network, a second output matching network, a ring network, and a post-matching network. The power divider is connected to the input terminal. The first and second input matching networks are connected in parallel from the power divider. The input terminals of the carrier power amplifier and the peak power amplifier are respectively connected to the output terminals of the first and second input matching networks. The output terminals of the carrier power amplifier and the peak power amplifier are respectively connected to the input terminals of the first and second output matching networks. The input terminal of the ring network is connected to the output terminals of the first and second output matching networks. The output terminal of the ring network is connected to the input terminal of the post-matching network.

[0006] The input power at the signal input terminal is divided into two output signals by a power divider. One signal goes through the first input matching network to the carrier power amplifier, and the other signal goes through the second input matching network to the peak power amplifier. The two signals are then output through the first and second output matching networks respectively and combined in a ring network. The combined signal is then output through the matching network.

[0007] Furthermore, the ring network includes a ring-connected network A1, network A2, and network A3. Node a is provided between network A1 and network A2, node b is provided between network A2 and network A3, and node c is provided between network A3 and network A1. The output end of the first output matching network is connected to node a, the output end of the second output matching network is connected to node b, and the input end of the subsequent matching network is connected to node c.

[0008] Furthermore, when the amplitude of the imaginary part of the impedance at both ends of network A1 is greater than 30dB, and the reflection coefficient of the two ports of network A1 is greater than -0.5dB, the characteristic of network A1 is open circuit. The signals output by the first output matching network and the second output matching network pass through network A2 and network A3 respectively, and then are combined at node b, and finally output through the post-matching network.

[0009] When the phase of network A1 is set to 180° or 360° and the reflection coefficient of the two ports of network A1 is less than -10dB, the signals output by the first output matching network and the second output matching network are combined at node a or node c. The combined signal is then split into two paths and transmitted simultaneously in parallel networks A2 and A3. Finally, it is input to the matching network and output.

[0010] Furthermore, networks A1, A2, and A3 are composed of one or more microstrip lines, or of a combination of multiple lumped elements.

[0011] Furthermore, the power divider is connected to the first output matching network via a first phase compensation line and to the second output matching network via a second phase compensation line.

[0012] Furthermore, the power divider includes a microstrip line M1, microstrip lines M2 and M3 connected in parallel with microstrip line M1, microstrip lines M4 and M5 connected in series with microstrip line M2, and microstrip lines M6 and M7 connected in series with microstrip line M3. A resistor R1 is connected in series between the nodes of microstrip lines M2 and M4 and between microstrip lines M3 and M6. A resistor R2 is connected in series between the nodes of microstrip lines M4 and M5 and between microstrip lines M6 and M7. Microstrip line M1 is connected to the input terminal.

[0013] Furthermore, the first input matching network includes microstrip line M8, capacitor C1, microstrip line M9, microstrip line M10, microstrip line M11, microstrip line M12 and microstrip line M13 connected in series. A resistor R3 is connected between the nodes of microstrip line M12 and microstrip line M13. A microstrip line M14 is connected to the resistor R3. A capacitor C2 is connected to the microstrip line M14. The capacitor C2 is grounded. Microstrip line M8 is connected to microstrip line M5 or microstrip line M7.

[0014] The second input matching network includes microstrip line M15, capacitor C3, microstrip line M16, microstrip line M17, microstrip line M18, microstrip line M19 and microstrip line M20 connected in series. A resistor R4 is connected between the nodes of microstrip line M19 and microstrip line M20. A microstrip line M21 is connected to resistor R4. A capacitor C4 is connected to microstrip line M21. Capacitor C4 is grounded. Microstrip line M15 is connected to microstrip line M7 or microstrip line M5.

[0015] Furthermore, the carrier power amplifier is a transistor CGH40010F, the peak power amplifier is a transistor CGH40045F, the base b of the transistor CGH40010F is connected to microstrip line M13, and the base b of the transistor CGH40045F is connected to microstrip line M20.

[0016] Further, the first output matching network includes microstrip lines M22 and M23 connected in series, with microstrip line M22 connected to the carrier power amplifier; the second output matching network includes microstrip lines M24 and M25 connected in series, with microstrip line M24 connected to the peak power amplifier; network A1 includes microstrip line M27 connected between the nodes of microstrip lines M23 and M26, microstrip line M28 connected between the nodes of microstrip lines M25 and M30 and connected to microstrip line M27, and microstrip line M29 connected between the nodes of microstrip lines M27 and M28.

[0017] Furthermore, the post-matching network includes microstrip lines M32, M33, M34, M35, and M36 connected in series. The node between microstrip lines M32 and M33 is connected to microstrip line M31. Microstrip line M31 is connected to microstrip lines M26 and M30. Microstrip line M32 is connected to capacitor C5, and capacitor C5 is grounded.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] This invention features a simple structure, a scientific and reasonable design, and ease of use. Based on the theory of traditional Doherty power amplifiers, the load modulation structure of the Doherty power amplifier has been optimized. By setting the characteristics of the loop network at different frequency points, Doherty power amplifiers with different load modulation paths in different operating frequency bands can be realized. Attached Figure Description

[0020] Figure 1 This is a structural diagram of the present invention.

[0021] Figure 2 This is a schematic diagram of the invention's architecture.

[0022] Figure 3 This is a schematic diagram of a frequency point architecture.

[0023] Figure 4 This is a schematic diagram of a frequency point two-architecture.

[0024] Figure 5 This is a circuit structure diagram of the present invention.

[0025] Figure 6 A simplified diagram of the Doherty power amplifier.

[0026] Figure 7 The result of the frequency point test is shown in the figure.

[0027] Figure 8 The result of the frequency point 2 test is shown in the figure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] The terms "first," "second," etc., used in this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] If we respectively treat the two transistors of the carrier power amplifier and the peak power amplifier as two current sources, we can obtain the simplified schematic of the Doherty power amplifier, as shown below. Figure 6 As shown, Ac represents the carrier power amplifier, and Ap represents the peak power amplifier. The main principle of the Doherty power amplifier is to modulate the impedance Zp of the current source section of the peak power amplifier through the current Ic1 of the carrier power amplifier. That is, when Ip is constant, an increase in Ic1 will cause the impedance Zp to gradually increase as well. Similarly, the current Ip of the peak power amplifier will also modulate the impedance Zc1 at the power combining point of the carrier power amplifier, and further modulate the Zc of the current source section of the carrier power amplifier through a quarter-wavelength line. That is, when Ic1 is constant, an increase in Ip will lead to an increase in Zc1 and a decrease in Zc. This principle realizes the two efficiency peak states of the Doherty power amplifier.

[0032] The Doherty power amplifier operates in three main states. In the low-power region, only the carrier power amplifier is active, while the peak power amplifier is off, and the current Ip is zero. At this point, there is no load modulation. The load RL at the power combining point converts the impedance of the current source terminal to 2Ropt through a quarter-wavelength line. Ropt is the optimal impedance for the power amplifier to operate under Class B bias. In a traditional Doherty power amplifier, the characteristic impedance of the quarter-wavelength line, the load RL, and the optimal impedance Ropt satisfy the following relationship: Ropt = ZT = 2RL. The impedance of the current source being 2Ropt causes VC to saturate prematurely, resulting in the first peak efficiency point of the Doherty power amplifier, with a theoretical efficiency of 78.5% (Class B power amplifier efficiency). As the input power increases, the peak power amplifier gradually turns on, and the current Ip gradually increases. Due to the load modulation effect, the value of Zc1 begins to increase, leading to a decrease in the value of Zc. When the value of Ip increases to equal the value of Ic1, the value of Zc becomes Ropt, and the impedance value of Zp also modulates from infinity to Ropt, thus enabling the Doherty's second theoretical peak efficiency point to reach 78.5%. Under such load modulation, a conventional Doherty power amplifier can maintain high efficiency within a 6dB output power back-off range. However, the bandwidth characteristics of the quarter-impedance inverter greatly limit the operating bandwidth of the Doherty power amplifier. Furthermore, due to the parasitic parameters and packaging parameters of actual transistors, the Doherty power amplifier is more sensitive to frequency changes, further limiting its bandwidth.

[0033] This invention reconstructs the load modulation network architecture of a traditional Doherty power amplifier. The new ring network can be flexibly configured according to the optimal impedance required at different frequencies. By setting the phase and impedance characteristics of the ring network at different operating frequencies, the power of the two power amplifiers can be combined at different nodes.

[0034] One embodiment of the present invention, such as Figure 1 As shown, the signal output includes a power divider, a first input matching network, a second input matching network, a carrier power amplifier, a peak power amplifier, a first output matching network, a second output matching network, a ring network, and a post-matching network. The power divider is connected to the input terminal. The first and second input matching networks are connected in parallel from the power divider. The input terminals of the carrier power amplifier and the peak power amplifier are respectively connected to the output terminals of the first and second input matching networks. The output terminals of the carrier power amplifier and the peak power amplifier are respectively connected to the input terminals of the first and second output matching networks. The input terminal of the ring network is connected to the output terminals of the first and second output matching networks. The output terminal of the ring network is connected to the input terminal of the post-matching network. The input power at the signal input terminal is evenly split into two signals by the power divider. One signal goes through the first input matching network to the carrier power amplifier, and the other goes through the second input matching network to the peak power amplifier. Both signals are then output through the first and second output matching networks and combined in the ring network. The combined signal is then output through the post-matching network.

[0035] In some embodiments, such as Figure 2 As shown, the ring network includes a ring-connected network A1, network A2 and network A3. Node a is provided between network A1 and network A2, node b is provided between network A2 and network A3, and node c is provided between network A3 and network A1. The output end of the first output matching network is connected to node a, the output end of the second output matching network is connected to node b, and the input end of the subsequent matching network is connected to node c.

[0036] Am1 and Ap1 are the output matching networks of the carrier power amplifier and the peak power amplifier, respectively, i.e., the first output matching network and the second output matching network. By setting the phase and impedance characteristics of the sub-networks (networks A1, A2, and A3) in the ring network, and combining the voltage and current relationships between the sub-networks, the load modulation theory of the entire ring network can be derived, and it can be expressed by a Y matrix in a way similar to the traditional Doherty load modulation characteristics. Intuitively, the degree of power combining in network A1 changes gradually during frequency variation, so this architecture also has the potential for wideband and high efficiency. However, since the active load modulation network is a ring-shaped multi-node network, general circuit characteristic analysis can only fix the network parameter values ​​first, and then calculate the equivalent impedance modulation of the two paths using the active superposition theorem. This brings great inconvenience and difficulty to the exploration and design of the characteristics of the ring active load modulation network. To facilitate the explanation of the feasibility of this invention, two relatively special ring networks are used to illustrate the invention. When the phase characteristics at both ends of the A1 network are controlled at 180° or 360°, the connection of the nodes at both ends of the A1 network is similar to a differential connection. These two special cases have voltage inverse mode and voltage in-phase mode at nodes a and c, respectively. It has the same equivalent impedance form as the traditional single-synthetic node. Under the action of this special network, the analysis method is consistent with the traditional DPA analysis method.

[0037] like Figure 3 As shown, at frequency point 1, when the amplitude of the imaginary part of the impedance at both ends of network A1 is greater than 30dB and the reflection coefficient of the two ports of network A1 is greater than -0.5dB, the characteristic of network A1 is open circuit, so that there is no microstrip line connection between node a and node c. At this time, the signals output by the first output matching network and the second output matching network pass through network A2 and network A3 respectively, and then perform power combining at node b. The load modulation network of the single-loop network is the same as the load modulation of the traditional DPA due to the characteristics of the special phase network A1.

[0038] At frequency point one, the operating frequency band is low frequency 1.65-1.9GHz. Networks A2 and A3 also serve as part of the output matching networks of the carrier power amplifier and the peak power amplifier, respectively.

[0039] like Figure 4As shown, at frequency point two, when the phase of network A1 is set to 180° or 360° and the reflection coefficient of the two ports of network A1 is less than -10dB, the characteristic of network A1 is a path, making network A1 similar to a microstrip line with an electrical length of 0. The signals output by the first output matching network and the second output matching network are combined at node a or node c in the same way. Then the combined signal is split into two paths and transmitted simultaneously in parallel networks A2 and A3. Finally, it is input to the matching network and output.

[0040] In the case of frequency point two, nodes a and c are equivalent to the same point. The two output signals are synthesized at this equivalent point (point a or point c). The synthesized signal then passes through parallel networks A2 and A3 and is synthesized again at node b. After synthesis, it is output to the post-matching network.

[0041] At frequency point two, the operating frequency band is high frequency 2.65-2.75GHz. The parallel network of network A2 and network A3 also serves as part of the post-matching network and realizes the conversion of 50Ω impedance to the load impedance of node a or node c.

[0042] In a single-ring dual-band Doherty architecture, the input power is split into two output signals by a power divider. One signal reaches the carrier power amplifier through a first input matching network, while the other reaches the peak power amplifier through a second input matching network. These two input matching networks ensure the gain of the Doherty power amplifier in the small-signal region and absorb the gate bias circuit into the input matching networks, thus ensuring the stability of the Doherty power amplifier. However, because the Doherty power amplifier uses an asymmetrical design, the two power amplifiers will employ different input matching networks, and a phase compensation network needs to be added before the input matching networks.

[0043] In some embodiments, the power divider is connected to the first output matching network by a first phase compensation line and to the second output matching network by a second phase compensation line, thereby ensuring that the two current phases at the power combining node b at one frequency point and the power combining node a or c at the second frequency point are aligned when Doherty is operating in saturation. Finally, the parasitic and packaging parameter networks of the transistor will also be absorbed into the output matching networks of the carrier power amplifier and the peak power amplifier, respectively.

[0044] In some embodiments, such as Figure 5As shown, the first input matching network includes microstrip line M8, capacitor C1, microstrip line M9, microstrip line M10, microstrip line M11, microstrip line M12 and microstrip line M13 connected in series. A resistor R3 is connected between the nodes of microstrip line M12 and microstrip line M13. A microstrip line M14 is connected to resistor R3. A capacitor C2 is connected to microstrip line M14. The capacitor C2 is grounded. Microstrip line M14 is connected to an externally applied voltage. Microstrip line M8 is connected to microstrip line M5 or microstrip line M7.

[0045] The second input matching network includes microstrip line M15, capacitor C3, microstrip line M16, microstrip line M17, microstrip line M18, microstrip line M19 and microstrip line M20 connected in series. A resistor R4 is connected between the nodes of microstrip line M19 and microstrip line M20. A microstrip line M21 is connected to resistor R4. A capacitor C4 is connected to microstrip line M21 and grounded. Microstrip line M21 is connected to an externally applied voltage. Microstrip line M15 is connected to microstrip line M7 or microstrip line M5.

[0046] The carrier power amplifier is a commercially available GaN high electron mobility transistor CGH40010F, and the peak power amplifier is a commercially available GaN high electron mobility transistor CGH40045F. The drain bias voltage is 28V. The dielectric substrate used in the power amplifier circuit is Rogers 4350b with a thickness of 20 mil and a relative permittivity of 3.66. The base (b) of transistor CGH40010F is connected to microstrip line M13, and the base (b) of transistor CGH40045F is connected to microstrip line M20.

[0047] The first output matching network includes microstrip lines M22 and M23 connected in series, with microstrip line M22 connected to the carrier power amplifier; the second output matching network includes microstrip lines M24 and M25 connected in series, with microstrip line M24 connected to the peak power amplifier; network A1 includes microstrip line M27 connected between the nodes of microstrip lines M23 and M26, microstrip line M28 connected between the nodes of microstrip lines M25 and M30 and connected to microstrip line M27, and microstrip line M29 connected between the nodes of microstrip lines M27 and M28. However, the ring network is also considered in both output matching networks (the first output matching network and the second output matching network) during operation.

[0048] The post-matching network includes microstrip lines M32, M33, M34, M35, and M36 connected in series. The node between microstrip lines M32 and M33 is connected to microstrip line M31. Microstrip line M31 is connected to microstrip lines M26 and M30. Microstrip line M32 is connected to capacitor C5, which is grounded. Microstrip line M32 is connected to an externally applied voltage.

[0049] The results of testing the physical circuit are as follows: Figure 7 and Figure 8 The figures shown correspond to the test results for frequency points one and two, respectively. When the Doherty operating frequency band is 1.65-1.9GHz, the drain efficiency at the saturation point is 42.3-62.0%, and the drain efficiency at a 9.5dB backoff is 63.7-69.5%, exhibiting very obvious Doherty characteristics. When the Doherty operating frequency band is 2.65-2.75GHz, the drain efficiency at the saturation point is 55.7-57.9%, and the drain efficiency at a 9.5dB backoff is 47.3-49.6%, also exhibiting very obvious Doherty characteristics.

[0050] Finally, it should be noted that the above embodiments are merely preferred embodiments of the present invention used to illustrate the technical solutions of the present invention, and are not intended to limit the invention, nor are they intended to limit the patent scope of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention. That is to say, any changes or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but whose technical problems are still consistent with the present invention, should be included within the protection scope of the present invention. In addition, the direct or indirect application of the technical solutions of the present invention to other related technical fields are similarly included within the patent protection scope of the present invention.

Claims

1. A single-ring network dual-band Doherty power amplifier, characterized in that, The system includes a power divider, a first input matching network, a second input matching network, a carrier power amplifier, a peak power amplifier, a first output matching network, a second output matching network, a ring network, and a post-matching network. The power divider is connected to the input terminals. The first and second input matching networks are connected out of the power divider. The input terminals of the carrier power amplifier and the peak power amplifier are respectively connected to the output terminals of the first and second input matching networks. The output terminals of the carrier power amplifier and the peak power amplifier are respectively connected to the input terminals of the first and second output matching networks. The input terminal of the ring network is connected to the output terminals of the first and second output matching networks. The output terminal of the ring network is connected to the input terminal of the post-matching network. The input power at the signal input terminal is divided into two output signals by a power divider. One signal goes through the first input matching network to the carrier power amplifier, and the other signal goes through the second input matching network to the peak power amplifier. The two signals are then output through the first output matching network and the second output matching network, and are combined in a ring network. The combined signal is then output through the matching network. The ring network includes a ring-connected network A1, network A2 and network A3. Node a is provided between network A1 and network A2, node b is provided between network A2 and network A3, and node c is provided between network A3 and network A1. The output end of the first output matching network is connected to node a, the output end of the second output matching network is connected to node b, and the input end of the subsequent matching network is connected to node c. When the magnitude of the imaginary part of the impedance at both ends of network A1 is greater than 30dB, and the reflection coefficient of the two ports of network A1 is greater than -0.5dB, the characteristic of network A1 is open circuit. The signals output by the first output matching network and the second output matching network pass through network A2 and network A3 respectively, and then are combined at node b, and finally output through the post-matching network. When the phase of network A1 is set to 180° or 360° and the reflection coefficient of the two ports of network A1 is less than -10dB, the signals output by the first output matching network and the second output matching network are combined at node a or node c. The combined signal is then split into two paths and transmitted simultaneously in parallel networks A2 and A3. Finally, it is input to the matching network and output. Networks A1, A2, and A3 consist of one or more microstrip lines, or a combination of multiple lumped elements.

2. The single-ring network dual-band Doherty power amplifier according to claim 1, characterized in that, The power divider is connected to the first output matching network by a first phase compensation line and to the second output matching network by a second phase compensation line.

3. The single-ring network dual-band Doherty power amplifier according to claim 1, characterized in that, The power divider includes a microstrip line M1, microstrip lines M2 and M3 connected in parallel to microstrip line M1, microstrip lines M4 and M5 connected in series with microstrip line M2, and microstrip lines M6 and M7 connected in series with microstrip line M3. A resistor R1 is connected in series between the nodes of microstrip lines M2 and M4 and between microstrip lines M3 and M6. A resistor R2 is connected in series between the nodes of microstrip lines M4 and M5 and between microstrip lines M6 and M7. Microstrip line M1 is connected to the input terminal.

4. A single-ring network dual-band Doherty power amplifier according to claim 3, characterized in that, The first input matching network includes microstrip line M8, capacitor C1, microstrip line M9, microstrip line M10, microstrip line M11, microstrip line M12 and microstrip line M13 connected in series. A resistor R3 is connected between the nodes of microstrip line M12 and microstrip line M13. A microstrip line M14 is connected to resistor R3. A capacitor C2 is connected to microstrip line M14. Capacitor C2 is grounded. Microstrip line M8 is connected to microstrip line M5 or microstrip line M7. The second input matching network includes microstrip line M15, capacitor C3, microstrip line M16, microstrip line M17, microstrip line M18, microstrip line M19 and microstrip line M20 connected in series. A resistor R4 is connected between the nodes of microstrip line M19 and microstrip line M20. A microstrip line M21 is connected to resistor R4. A capacitor C4 is connected to microstrip line M21. Capacitor C4 is grounded. Microstrip line M15 is connected to microstrip line M7 or microstrip line M5.

5. A single-ring network dual-band Doherty power amplifier according to claim 4, characterized in that, The carrier power amplifier is a transistor CGH40010F, the peak power amplifier is a transistor CGH40045F, the base b of transistor CGH40010F is connected to microstrip line M13, and the base b of transistor CGH40045F is connected to microstrip line M20.

6. A single-ring network dual-band Doherty power amplifier according to claim 5, characterized in that, The first output matching network includes microstrip lines M22 and M23 connected in series, with microstrip line M22 connected to the carrier power amplifier; the second output matching network includes microstrip lines M24 and M25 connected in series, with microstrip line M24 connected to the peak power amplifier; network A1 includes microstrip line M27 connected between the nodes of microstrip lines M23 and M26, microstrip line M28 connected between the nodes of microstrip lines M25 and M30 and connected to microstrip line M27, and microstrip line M29 connected between the nodes of microstrip lines M27 and M28.

7. A single-ring network dual-band Doherty power amplifier according to claim 6, characterized in that, The post-matching network includes microstrip lines M32, M33, M34, M35, and M36 connected in series. The node between microstrip lines M32 and M33 is connected to microstrip line M31. Microstrip line M31 is connected to microstrip lines M26 and M30. Microstrip line M32 is connected to capacitor C5, which is grounded.

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