A general-purpose fiber optic network interface tester

Abstract

This invention relates to the field of interface testing technology, specifically to a general-purpose fiber optic network interface tester, comprising: a data acquisition and storage board, on which fiber optic interface units and network interface units are mounted for connecting to the device under test (DUT); the data acquisition and storage board is used for interface data simulation stimulation, data transmission and reception, received data verification, and data storage; a main control board, communicatively connected to the data acquisition and storage board, used for configuring interface parameters, controlling data transmission and reception, managing data, and performing statistical analysis; and a power supply module for supplying power to the main control board and the data acquisition and storage board. This invention enables simultaneous testing of fiber optic interfaces and network interfaces, overcoming, to some extent, the limitations of interface data transmission and reception testing.

Description

Technical Field

[0001] This invention relates to the field of interface testing technology, and more specifically to a general-purpose fiber optic network interface tester. Background Technology

[0002] An interface tester is a tool used to test and verify the interfaces between different devices. It is used to test the physical connection, communication protocols, and data transmission between devices, and is mainly used in the fields of computers, communications, and electronics.

[0003] Currently, most computer systems primarily use high-speed serial bus fiber optic interfaces and network interfaces. However, existing interface testers can only perform fiber optic interface testing or network interface testing separately. Furthermore, as system complexity increases, the number of interfaces that interface testers need to support is also constantly increasing.

[0004] Secondly, for testing fiber optic interfaces on high-speed serial buses, if the device under test (DUT) has many interfaces, existing interface testers typically employ three solutions: The first is to fully test only a portion of the device's interfaces, leaving the testing of other interfaces limited to simple link establishment tests. However, this leaves the data transmission and reception tests unsatisfactory, failing to guarantee the correctness, integrity, and stability of the interface transmission. The second is to use the DUT's own multi-channel interfaces for external self-loopback data transmission and reception tests. However, this cannot perform full-load data reception or transmission tests on all interface channels, resulting in insufficient interface testing. Finally, a professional high-speed serial bus fiber optic tester is used, but this requires multiple professional testers to perform tests simultaneously and cannot simultaneously support single-mode and dual-mode interface transmission and reception.

[0005] For network interface testing, most existing interface testers use high-configuration x86 computers for data transmission and reception verification. However, this method is limited by CPU resources and local data disk bandwidth, resulting in performance deficiencies and limited channel support. Specifically, network interface testing requires processing a large number of data packets and network traffic. High-configuration x86 computers may not be able to meet the requirements of high load and high-speed data processing, leading to performance deficiencies, especially in multi-threaded concurrent testing, where CPU resource limitations can restrict test speed. Network interface testing typically requires loading test cases or data from local storage and writing test results to local storage. If the local data disk bandwidth is limited, the data read / write speed may become a performance bottleneck, affecting test speed and efficiency. Some high-configuration x86 computers may not have enough network interfaces or channels to test multiple interfaces simultaneously, which limits the ability of existing interface testers to perform multi-interface tests concurrently, resulting in limited channel support. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention proposes a universal fiber optic network interface tester, which aims to simultaneously perform fiber optic interface testing and network interface testing, while overcoming, to some extent, the limitations of interface data transmission and reception testing.

[0007] Therefore, the present invention adopts the following technical solution: a universal fiber optic network interface tester, comprising:

[0008] The acquisition and storage board is equipped with an optical fiber interface unit and a network interface unit. The optical fiber interface unit and the network interface unit are used to connect to the device under test. The acquisition and storage board is used for interface data simulation stimulation, data transmission and reception, received data verification and data storage.

[0009] The main control board is communicatively connected to the acquisition and storage board. The main control board is used to configure interface parameters, control data transmission and reception, manage data, and perform statistical analysis on the acquisition and storage board.

[0010] The power module is used to supply power to the main control board and the data acquisition and storage board.

[0011] This invention, by setting up fiber optic interface units and network interface units on the acquisition and storage board, allows the device under test (DUT) to be directly connected to the acquisition and storage board via these units. The acquisition and storage board then directly generates stimulus data and sends it to the various interfaces of the DUT through the corresponding fiber optic and network interface units. Alternatively, it can directly receive data sent by the DUT through these units and send it to the acquisition and storage board, performing verification and data storage according to a specified format. This enables full-load data reception or transmission testing of all interface channels of the DUT. It not only supports simultaneous testing of both fiber optic and network interfaces but also, because all interfaces are directly connected to the acquisition and storage board rather than the main control board, it is not limited by CPU resources or local data disk bandwidth, thus overcoming to some extent the problems of insufficient performance and limited channel support.

[0012] Preferably, the acquisition and storage board includes an acquisition unit, a timing control unit, a data interaction unit, and a storage unit. The fiber optic interface unit and the network interface unit are directly connected to the acquisition unit. The acquisition unit is used for interface data simulation excitation, data transmission and reception, and received data verification. One end of the timing control unit is connected to the acquisition unit, and the other end is communicatively connected to the main control board. The acquisition unit, the main control board, and the storage unit are all communicatively connected to the data interaction unit.

[0013] Preferably, the optical fiber interface unit includes a multimode optical unit and a single-mode optical unit, both of which are directly connected to the acquisition and storage board. The multimode optical unit is used to provide a multimode optical fiber channel to the outside world, and the single-mode optical unit is used to provide a single-mode optical fiber channel to the outside world.

[0014] Preferably, the network interface unit includes two QSFG+ interfaces and four SFP+ interfaces, both of which are directly connected to the acquisition and storage board.

[0015] Preferably, the network interface unit includes several PHY chips and several RJ45 interfaces. The number of PHY chips is the same as the number of RJ45 interfaces. One end of each PHY chip is connected to the acquisition unit, and the other end is connected to the RJ45 interface.

[0016] Preferably, the main control board includes a system disk, a graphics card, a CPLD, and a processor. The system disk is equipped with an operating system and a control system. The operating system is used to manage the control system, and the control system is used to configure interface parameters, control data transmission and reception, manage data, and perform statistical analysis on the acquisition and storage board. The system disk is connected to the graphics card, and both the graphics card and the CPLD are connected to the processor.

[0017] Preferably, the processor is equipped with a gigabit Ethernet port and a 10-gigabit Ethernet port, both of which extend out of the side panel of the fiber optic network interface tester and are located on the same side of the main control board.

[0018] Preferably, the graphics card is provided with an HDMI external display interface and several USB interfaces. The HDMI external display interface and the USB interfaces extend out of the side panel of the fiber optic network interface tester and are located on the same side of the main control board.

[0019] Preferably, the fiber optic network interface tester includes a display screen, the graphics card is provided with an eDP internal display interface, and the display screen is connected to the eDP internal display interface.

[0020] Preferably, the main control board includes a microcontroller, and the fiber optic network interface tester includes an indicator light button board and an input module. The indicator light button board, the input module, the graphics card, and the CPLD are all connected to the microcontroller.

[0021] The beneficial technical effects of this invention include at least the following: It employs a universal fiber optic network interface tester. By setting fiber optic interface units and network interface units on the acquisition and storage board, the device under test (DUT) is directly connected to the acquisition and storage board through these units. The acquisition and storage board then directly generates excitation data and sends it to each interface of the DUT through the corresponding fiber optic and network interface units. Alternatively, it directly receives data sent by the DUT through these units and sends it to the acquisition and storage board, performing verification and data storage according to a specified format. This enables full-load data reception or transmission testing of all interface channels of the DUT. It not only supports simultaneous testing of fiber optic and network interfaces but also, because all interfaces are directly connected to the acquisition and storage board rather than the main control board, it is not limited by CPU resources or local data disk bandwidth. Therefore, it overcomes the problems of insufficient performance and limited channel support to a certain extent, and has high practical value.

[0022] Other features and advantages of the present invention will be disclosed in detail in the following detailed description and accompanying drawings. Attached Figure Description

[0023] The invention will be further described below with reference to the accompanying drawings:

[0024] Figure 1 This is a schematic diagram of the structure of a general-purpose fiber optic network interface tester according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the hardware structure of the data acquisition and storage board according to an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of the hardware structure of the main control board in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be explained and described below with reference to the accompanying drawings. However, the following embodiments are only preferred embodiments of the present invention and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments in the implementation methods without creative effort are all within the protection scope of the present invention.

[0028] In the following description, terms such as “inner,” “outer,” “upper,” “lower,” “left,” and “right” are used only to indicate orientation or positional relationship for the convenience of describing the embodiments and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0029] This application provides a universal fiber optic network interface tester. Please refer to the appendix. Figure 1 ,include:

[0030] The acquisition and storage board is equipped with a fiber optic interface unit and a network interface unit. The fiber optic interface unit and the network interface unit are used to connect the device under test. The acquisition and storage board is used for interface data simulation stimulation, data transmission and reception, received data verification and data storage.

[0031] The main control board communicates with the acquisition and storage board. The main control board is used to configure the interface parameters of the acquisition and storage board, control data transmission and reception, manage data, and perform statistical analysis.

[0032] The power module is used to supply power to the main control board and the data acquisition and storage board.

[0033] For example, the power module is powered by an AC 220V to DC 24V power adapter, which then powers the main control board and the data acquisition and storage board via a DC power module. With conductive cooling, it can output 160W. The power adapter and power module are connected via a 4-core power cable.

[0034] This embodiment of the specification sets up fiber optic interface units and network interface units on the acquisition and storage board. The device under test (DUT) is directly connected to the acquisition and storage board through the fiber optic interface units and network interface units. The acquisition and storage board directly generates excitation data and sends it to the various interfaces of the DUT through the corresponding fiber optic interface units and network interface units. Alternatively, it directly receives data sent by the DUT through the fiber optic interface units and network interface units and sends it to the acquisition and storage board. The data is then verified and stored according to a specified format. This enables full-load data reception or transmission testing of all interface channels of the DUT. It not only supports simultaneous testing of fiber optic interfaces and network interfaces, but also, because all interfaces are directly connected to the acquisition and storage board rather than the main control board, it is not limited by CPU resources and local data disk bandwidth, thus overcoming to some extent the problems of insufficient performance and limited channel support.

[0035] In one embodiment of this specification, the acquisition and storage board includes an acquisition unit, a timing control unit, a data interaction unit, and a storage unit. The fiber optic interface unit and the network interface unit are directly connected to the acquisition unit. The acquisition unit is used for interface data simulation excitation, data transmission and reception, and received data verification. One end of the timing control unit is connected to the acquisition unit, and the other end is communicatively connected to the main control board. The acquisition unit, the main control board, and the storage unit are all communicatively connected to the data interaction unit.

[0036] For example, please refer to the appendix. Figure 2 In this embodiment, the acquisition unit is selected from the Fudan Micro V7 FPGA chip (i.e., the attached chip). Figure 2 The FPGA chip is JFM7VX690T80, and the timing control unit is an A7 FPGA chip (i.e., the one attached). Figure 2The data interaction unit uses the PCIe Switch PEX8764 chip (A7 JFMK50-AS chip), and the storage unit uses four NVMe industrial-grade electronic disks mounted on the acquisition and storage board (i.e., attached). Figure 2 The four M.2 interfaces correspond to electronic disks. Specifically, the fiber optic interface unit and the network interface unit are directly connected to the V7 FPGA. One end of the A7 FPGA is connected to the V7 FPGA, and the other end communicates with the main control board via PCIe 3.0. Both the V7 FPGA and the main control board communicate with the PCIe Switch PEX8764 via PCIe 3.0. The electronic disks corresponding to the four M.2 interfaces communicate with the PCIe Switch PEX8764 via PCIe 3.0 x4, thereby providing a high-speed read / write bandwidth of 5GB / s to realize high-speed data reception and transmission of the acquisition interface.

[0037] In one embodiment of this specification, the optical fiber interface unit includes a multimode optical unit and a single-mode optical unit. Both the multimode optical unit and the single-mode optical unit are directly connected to the acquisition and storage board. The multimode optical unit is used to provide a multimode optical fiber channel to the outside world, and the single-mode optical unit is used to provide a single-mode optical fiber channel to the outside world.

[0038] For example, please refer to the appendix. Figure 2 In this embodiment, a 48-core HTG8515 multimode optical module is selected as the multimode optical unit, and an 8-core HTA3102 single-mode optical module is selected as the single-mode optical unit. The 48-core HTG8515 multimode optical module communicates with the V7 FPGA via GTX and provides 24 multimode fiber channels. The 8-core HTA3102 single-mode optical module communicates with the V7 FPGA via GTX and provides 4 single-mode fiber channels. The fiber channels are led out in the form of aviation plugs and can be connected to the MPO interface with guide pins of the device under test through optical cable assemblies.

[0039] This embodiment, through the built-in single-mode optical unit and multi-mode optical unit, can simultaneously support data transmission and reception tests of single-mode and dual-mode fiber optic interfaces.

[0040] In one embodiment of this specification, the network interface unit includes two QSFG+ interfaces and four SFP+ interfaces, all of which are directly connected to the acquisition and storage board.

[0041] Among them, QSFP+ and SFP+ interfaces support high-speed transmission, enabling higher data transfer rates. QSFP+ interfaces are typically used for 40G or 100G Ethernet connections, while SFP+ interfaces are typically used for 10G Ethernet connections. These high-speed interfaces make data transmission faster and more efficient.

[0042] Specifically, please refer to the appendix. Figure 2In this embodiment, the network interface unit provides two QSFP+ (40G) interfaces for direct communication with the V7 FPGA via GTX, providing two 40G channels externally. These interfaces can be connected to the device under test (DUT) via 40G QSPF+ high-speed cables, or downgraded to four 10G interfaces via 40G QSPF+ to 4x10G LC cables, achieving 10G physical interface expansion. Specifically, the QSFG+ interfaces can provide single-mode / multi-mode 40G Ethernet channels by equipping different 40GBase optical modules and fiber optic patch cords, or each 40G channel can be split into four 10G Ethernet channels for 10G physical network port expansion.

[0043] On the other hand, in this embodiment, the network interface unit provides four SFP+ (10G) external interfaces. These can be used to achieve single-mode or multi-mode 10G Ethernet data transmission by replacing the matching optical modules, and to communicate directly with the V7 FPGA via GTX. Alternatively, by replacing the optoelectronic conversion module, they can be downgraded to four RJ45 interfaces, enabling gigabit physical interface expansion. Specifically, the SFP+ interfaces can provide four single-mode / multi-mode 10G Ethernet channels by equipping different 10GBase optical modules and fiber optic patch cords; or by equipping an optoelectronic conversion module, the four 10G Ethernet channels can be downgraded to 1000Base RJ45 channels for gigabit physical network port expansion.

[0044] The network interface unit in this embodiment adopts QSFG+ and SFP+ interfaces. By replacing the single-mode and dual-mode fiber modules, it can flexibly support single-mode and dual-mode interface transmission and reception as needed. Moreover, each interface can support multi-channel data transmission and reception testing, providing greater flexibility and scalability.

[0045] In one embodiment of this specification, the network interface unit includes several PHY chips and several RJ45 interfaces. The number of PHY chips is the same as the number of RJ45 interfaces. One end of the PHY chip is connected to the acquisition unit, and the other end is connected to the RJ45 interface.

[0046] For example, please refer to the appendix. Figure 2 In this embodiment, the V7 FPGA connects to four YT8541 PHY chips via GTX and provides four RJ45 Ethernet channels to the outside world.

[0047] This embodiment provides common Ethernet connectivity options via an RJ45 interface, suitable for connecting to standard Ethernet devices and networks. This gives the network interface unit broader compatibility and allows it to connect to many common network devices and infrastructures.

[0048] In one embodiment of this specification, the main control board includes a system disk, a graphics card, a CPLD, and a processor. The system disk contains an operating system and a control system. The operating system is used to manage the control system, and the control system is used to configure interface parameters, control data transmission and reception, manage data, and perform statistical analysis on the acquisition and storage board. The system disk is connected to the graphics card, and both the graphics card and the CPLD are connected to the processor.

[0049] A graphics card, also known as a display adapter or graphics card, is a crucial component in a computer used for processing graphics and images. It is responsible for converting the graphics signals generated by the computer into images that can be displayed on the monitor. A CPLD (Complex Programmable Logic Device) is a programmable logic device used to implement the functions of digital logic circuits. It is a medium-sized programmable logic device, falling between FPGA (Field-Programmable Gate Array) and PAL (Programmable Array Logic). The operating system manages the control system, including monitoring and controlling its operational status, resource usage, and permission allocation to ensure the normal operation and security of the control system.

[0050] For example, please refer to the appendix. Figure 3 In this embodiment, the main control board consists of a Phytium D2000 / 8 (processor), a Phytium X100 (graphics card), an mSATA disk (system disk), a CPLD, and peripheral circuitry. The system disk connects to the X100 via the mSATA interface, and the X100 interacts with the D2000 / 8 via PCIe 3.0 x8. The CPLD is also connected to the D2000 / 8. The main control board communicates with the acquisition and storage board via PCIe 3.0, with reserved I2C, UART, and GPIO interfaces for sensor acquisition and status control information. Specifically, the main control board and the acquisition and storage board are connected via a snap-on design using a high-speed connector (i.e., an attached...). Figure 3 The PCIe high-speed slot (10147613-121406LF) supports up to 32Gb / s.

[0051] In one embodiment of this specification, the processor is provided with a gigabit Ethernet port and a 10-gigabit Ethernet port, both of which extend out of the side panel of the fiber optic network interface tester and are located on the same side of the main control board.

[0052] For example, please refer to the appendix. Figure 1 and attached Figure 3In this embodiment, the D2000 / 8 is connected to the 10 Gigabit Ethernet wx1820 via PCIE 3.0 x8, providing one 10 Gigabit SPF interface (i.e., 10 Gigabit Ethernet port) to the outside. The D2000 / 8 also provides one RJ45 interface to the outside via the PHY chip, which is used for remote network control of the tester and for importing and exporting data.

[0053] By extending the gigabit and 10-gigabit Ethernet ports directly to the side panel of the tester and placing them on the same side of the main control board, the connection distance can be shortened, signal attenuation and interference during signal transmission can be reduced, and the stability and reliability of network control and data import / export can be improved to a certain extent. At the same time, the circuit layout and appearance of the tester can be optimized.

[0054] In one embodiment of this specification, the graphics card is provided with an HDMI external display interface and several USB interfaces. The HDMI external display interface and the USB interfaces extend out of the side panel of the fiber optic network interface tester and are located on the same side of the main control board.

[0055] The USB interface can be used to connect external USB peripherals such as keyboards and mice, and can also be used for data import and export.

[0056] For example, please refer to the appendix. Figure 1 and attached Figure 3 In this embodiment, the Phytium X100, in addition to having a dedicated graphics card, also features high-speed expansion interfaces such as PCIe 3.0, SATA 3.0, and USB 3.1, as well as low-speed expansion interfaces such as QSPI, PS / 2, UART, and GPIO. It provides two USB 3.0 ports (i.e., additional ports). Figure 3 It includes a 3.0 commercial port and one HDMI port (i.e., one HDMI port is included). Figure 3 (HDMI commercial dock in the middle).

[0057] The tester's external expansion capabilities are achieved through the HDMI external display interface and several USB interfaces set on the main control board.

[0058] In one embodiment of this specification, please refer to the appendix. Figure 1 The fiber optic network interface tester includes a display screen, and the graphics card is equipped with an eDP internal display interface, which is connected to the display screen.

[0059] Both the eDP internal display interface and the aforementioned HDMI external display interface can be set as the main screen, or as a duplicate screen or extended screen.

[0060] For example, in this embodiment, the display screen mainly consists of an LCD screen, shielding glass, and adhesive backing. The LCD screen and shielding glass are bonded together using a full lamination process and fixed by adhesive backing. The screen interface uses an eDP standard interface and is connected to the graphics card of the main control board via an eDP signal cable. On the other hand, in this embodiment, the display screen can also reserve a backlight interface, allowing dynamic adjustment of the display screen brightness via a combination of buttons.

[0061] This embodiment uses a display screen to show the input and output of the device's operating system and control system, providing a good human-computer interaction and visual display.

[0062] In one embodiment of this specification, please refer to the appendix. Figure 1 and attached Figure 3 The main control board includes a microcontroller, and the fiber optic network interface tester includes an indicator light button board and an input module. The indicator light button board, input module, graphics card, and CPLD are all connected to the microcontroller.

[0063] The indicator light keypad is a device or panel equipped with multiple indicator lights and buttons to display the device's status and provide operational control. Optionally, the indicator light keypad may include, but is not limited to: a power button, a power indicator, a ready indicator, a data transmission indicator, a data reception indicator, an import / export indicator, a fault indicator, a Caps Lock indicator, and a Num Lock indicator. The input module includes a keyboard and a touchpad. The keyboard may be an 86-key membrane keyboard used with the main control board's operating system, primarily for parameter configuration input in the device control software. The touchpad may be a high-sensitivity integrated touchpad to provide mouse-like input.

[0064] For example, please refer to the appendix. Figure 3 In this embodiment, the microcontroller is a GD32 chip. The main control board communicates with the GD32 via a USB interface to implement functions such as a row and column keyboard, power on / off, and indicator lights. A CPLD is used for status management and timing control. For example, the power switch controls the power on / off of the entire tester, and the GD32 controls the "Power" light to indicate the power status. The keyboard control indicator lights include "Num Lock" and "Caps Lock" indicators, which are controlled by the GD32 based on the Num Lock and Caps Lock key values. The working status indicator lights include "Ready," "Import / Export," "Data Send," and "Data Receive" indicators. The timing control unit A7 FPGA in the data acquisition and storage board controls the working status indicator lights of the tester based on the overall initialization status, interface data transmission and reception status, and data interaction status between the main control board and the data acquisition and storage board.

[0065] The above description is merely a preferred embodiment disclosed in this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this disclosure.

[0066] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

Claims

1. A universal fiber optic network interface tester, characterized in that, include: The acquisition and storage board is equipped with an optical fiber interface unit and a network interface unit. The optical fiber interface unit and the network interface unit are used to connect to the device under test. The acquisition and storage board is used for interface data simulation stimulation, data transmission and reception, received data verification and data storage. The main control board is used to configure interface parameters, control data transmission and reception, manage data, and perform statistical analysis on the acquisition and storage board. The power module is used to power the main control board and the data acquisition and storage board; The acquisition and storage board includes an acquisition unit, a timing control unit, a data interaction unit, and a storage unit. The fiber optic interface unit and the network interface unit are directly connected to the acquisition unit. The acquisition unit is used for interface data simulation excitation, data transmission and reception, and received data verification. One end of the timing control unit is connected to the acquisition unit, and the other end is communicatively connected to the main control board. The acquisition unit, the main control board, and the storage unit are all communicatively connected to the data interaction unit.

2. The universal fiber optic network interface tester as described in claim 1, characterized in that, The optical fiber interface unit includes a multimode optical unit and a single-mode optical unit. Both the multimode optical unit and the single-mode optical unit are directly connected to the acquisition and storage board. The multimode optical unit is used to provide a multimode optical fiber channel to the outside world, and the single-mode optical unit is used to provide a single-mode optical fiber channel to the outside world.

3. The universal fiber optic network interface tester as described in claim 1, characterized in that, The network interface unit includes two QSFG+ interfaces and four SFP+ interfaces, all of which are directly connected to the acquisition and storage board.

4. A universal fiber optic network interface tester as described in claim 3, characterized in that, The network interface unit includes several PHY chips and several RJ45 interfaces. The number of PHY chips is the same as the number of RJ45 interfaces. One end of each PHY chip is connected to the acquisition unit, and the other end is connected to the RJ45 interface.

5. A universal fiber optic network interface tester as described in claim 1, characterized in that, The main control board includes a system disk, a graphics card, a CPLD, and a processor. The system disk contains an operating system and a control system. The operating system is used to manage the control system, and the control system is used to configure interface parameters, control data transmission and reception, manage data, and perform statistical analysis on the acquisition and storage board. The system disk is connected to the graphics card, and both the graphics card and the CPLD are connected to the processor.

6. A universal fiber optic network interface tester as described in claim 5, characterized in that, The processor is equipped with a gigabit Ethernet port and a 10-gigabit Ethernet port, both of which extend out of the side panel of the fiber optic network interface tester and are located on the same side of the main control board.

7. A universal fiber optic network interface tester as described in claim 5, characterized in that, The graphics card is equipped with an HDMI external display interface and several USB interfaces. The HDMI external display interface and the USB interfaces extend out of the side panel of the fiber optic network interface tester and are located on the same side of the main control board.

8. A universal fiber optic network interface tester as described in claim 5, characterized in that, The fiber optic network interface tester includes a display screen, and the graphics card is equipped with an eDP internal display interface, which is connected to the display screen.

9. A universal fiber optic network interface tester as described in claim 5, characterized in that, The main control board includes a microcontroller, and the fiber optic network interface tester includes an indicator light button board and an input module. The indicator light button board, input module, graphics card, and CPLD are all connected to the microcontroller.

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