A multi-power unit parallel carrier synchronization method, system and medium

Abstract

The application provides a multi-power-unit parallel carrier synchronization method, system and medium, which comprises the following steps: frame transmission is performed when the starting bits of each frame fall on the same edge of a carrier, that is, a master sends a synchronization frame to a power unit, receives a response frame of the synchronization frame returned by the power unit, then sends an acknowledgement frame of the response frame, and the power unit receives the acknowledgement frame; the master carrier count and the power unit carrier count are calculated according to the time instants of sending and receiving the synchronization frame and the response frame, the carrier count variation ΔC1 based on the master carrier count in the frame transmission stage and the deviation ΔC2 of the master carrier count and the power unit carrier count are calculated; the power unit re-calculates the power unit carrier count Cpowercell at the time instant when the power unit receives the acknowledgement frame according to the master carrier count Ct2 at the time instant when the master sends the acknowledgement frame and the carrier offset ΔC3 generated in the process of analyzing Ct2.

Description

Technical Field

[0001] This invention belongs to the fields of power electronic converters and frequency converters, and specifically relates to a method, system and medium for parallel carrier synchronization of multiple power units. Background Technology

[0002] Multi-power unit parallel carrier synchronization technology is a technique applied in the power electronics industry, primarily in power electronic converters and frequency converters. Its purposes are typically twofold: firstly, to facilitate the "tailoring" of equipment power, enabling rapid development of solutions for different customer power requirements; and secondly, to meet equipment redundancy needs. When a power unit fails, it can be automatically or manually bypassed while still meeting the power requirements of the consuming equipment, activating other backup power units for rapid recovery from the fault.

[0003] like Figure 1 As shown, carrier synchronization is an essential technique for multi-unit parallel operation because it effectively suppresses circulating currents between power units, reduces losses, and lowers the temperature rise of power units. The carrier generally refers to a triangular wave, and carrier synchronization aims to ensure that the carrier in all power units has the same value at the same time. A common method for carrier synchronization is for the master controller to periodically send a carrier synchronization signal via a protocol using a downlink optical fiber. When a unit receives this synchronization signal (usually a 1-bit pulse signal), it loads its own carrier to a specific value. For example, in patent number "ZL2019113478796" titled "An SVG Multi-Machine Parallel System Based on CAN Bus and Its Carrier Synchronization Control Method," the master sends a clock counter value at the peak of the wave and controls the slave to load the theoretical value. This method is simple and practical, but has low accuracy and requires the carrier period to be an integer multiple of the communication period. A second method is for the master controller to send its own carrier count in each cycle, and the power unit updates its own carrier counter after receiving the carrier count. This method has a high synchronization rate, but frequent updates will lead to two problems: first, carrier data will occupy the fixed communication bandwidth of downlink communication; second, too frequent updates will cause too many glitches to be generated on the carrier (at the synchronization point), thus "polluting" the carrier. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a method, system, electronic device and medium for parallel carrier synchronization of multiple power units to solve the above-mentioned technical problems.

[0005] In a first aspect, the present invention provides a method for synchronizing multiple power units in parallel carriers, comprising: Frame transmission is performed when the start bit of each frame falls on the same edge of the carrier, including: the master controller sends a synchronization frame to the power unit, receives a response frame of the synchronization frame returned by the power unit, and then sends an acknowledgment frame for the response frame, and the power unit receives the acknowledgment frame. Based on the master control carrier count and power unit carrier count at the transmission and reception times of the synchronization frame and response frame, calculate the carrier count change ΔC1 and the deviation ΔC2 between the master control carrier count and the power unit carrier count during the frame transmission phase, with the master control carrier count as the reference. The power unit recalculates the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame, based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame and the carrier offset ΔC3 generated during the parsing of Ct2.

[0006] Furthermore, the step of calculating the carrier count change ΔC1 and the deviation ΔC2 between the master control carrier count and the power unit carrier count during the frame transmission phase, based on the master control carrier count and the power unit carrier count at the transmission and reception times of the synchronization frame and response frame, includes: If frame transmission occurs on the rising edge of the carrier, it is calculated according to the following formula: (Ct0-ΔC2)+ΔC1=Cr0 (1) (Ct1+ΔC2)+ΔC1=Cr1 (2) If frame transmission occurs on the falling edge of the carrier wave, it is calculated according to the following formula: (Ct0-ΔC2)-ΔC1=Cr0 (3) (Ct1+ΔC2)-ΔC1=Cr1 (4) Wherein, Ct0 is the master control carrier count when the master controller sends the synchronization frame; Cr0 is the power unit carrier count when the power unit receives the synchronization frame; Ct1 is the power unit carrier count when the power unit sends the response frame; and Cr1 is the master control carrier count when the master controller receives the response frame. ΔC1 is the carrier count change based on the master carrier count during the assumed frame transmission time, and the master carrier count is ΔC2 greater than the power unit carrier count. ΔC2 represents the deviation between the master carrier count and the power unit carrier count.

[0007] Furthermore, the power unit recalculates the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame, and the carrier offset ΔC3 generated during the parsing of Ct2, including: If frame transmission occurs on the falling edge of the carrier wave, the master carrier count Ct2 is at the falling edge: The power cell carrier count Cpowercell is calculated using the following formula: Cpowercell = |Ct2 - ΔC1 ​​- ΔC3|; If frame transmission occurs on the rising edge of the carrier, the power cell carrier count Cpowercell is calculated according to the following formula: When Ct2+ΔC1+ΔC3>CMAX, Cpowercell=CMAX-(Ct2+ΔC1+ΔC3-CMAX)=2*CMAX-(Ct2+ΔC1+ΔC3); When Ct2+ΔC1+ΔC3≤CMAX, Cpowercell=Ct2+ΔC1+ΔC3; CMAX represents the peak value of the carrier counter.

[0008] Furthermore, it also includes: the frame transmission where the start bit of each frame falls on the same edge of the carrier, comprising: At time t00, the master controller sends the start bit of the synchronization frame to the power unit. The synchronization frame includes the master controller carrier count Ct0. At time t01, the power unit receives the start bit of the synchronization frame sent by the master controller and the carrier count Ct0 of the master controller at time t00, and at the same time obtains the carrier count Cr0 of the power unit at time t01. The power unit determines whether Ct0 and Cr0 are on the same edge. If not, the power unit sends a fault frame to the master controller to notify the master controller to retransmit the synchronization frame message until Ct0 and Cr0 are on the same edge. After determining that Ct0 and Cr0 are on the same edge, the power unit sends the response frame start bit to the master control synchronization frame at time t02 and obtains the power unit carrier count Ct1 at time t02. At time t03, the master controller receives the start bit of the response frame, which includes the power unit carrier count Ct1, and obtains the master controller carrier count Cr1 at time t03. If the master controller determines that Ct1 and Cr1 are on the same edge, the master controller sends a fault frame to the power unit and notifies the power unit to retransmit the response frame message until Ct1 and Cr1 are on the same edge. After determining that Ct1 and Cr1 are on the same edge, the master controller sends the start bit of the acknowledgment frame at time t04. The acknowledgment frame contains the master control carrier count Cr1 that the power unit did not collect during the time period t03, and the master control carrier count Ct2 at time t04. At time t05, the power unit receives the start bit of the acknowledgment frame and records the power unit carrier count Cr2 at time t05. The carrier count Cr2 is deemed invalid, and the power cell carrier count Cpowercell is recalculated to replace the carrier count Cr2 using the calculation process described in any one of claims 1-3.

[0009] Furthermore, it also includes: The deviation of the power unit carrier count is compensated according to the logic clock speed ratio, wherein the logic clock speed ratio is the ratio of the main control logic clock count of multiple synchronization cycles to the internal logic clock count of the power unit; The deviation of the power unit carrier count is added to the power unit carrier count Cpowercell.

[0010] Furthermore, it also includes: after the power unit carrier count Cpowercell is updated, PLL dynamic phase adjustment technology is used to adjust the logic clock phase of the power unit. After each adjustment, the deviation ΔC2 between the master control carrier count and the power unit carrier count generated by the long-term operation of the asynchronous clock at the same frequency is calculated. After multiple average iterations, a target phase of the power unit logic clock with a smaller ΔC2 can be obtained.

[0011] In a second aspect, the present invention provides a multi-power unit parallel carrier synchronization system, comprising: A frame transmission unit is used to transmit frames so that the start bit of each frame falls on the same edge of the carrier. The unit includes: the master controller sending a synchronization frame to the power unit and receiving a response frame of the synchronization frame returned by the power unit, and then sending an acknowledgment frame for the response frame. The power unit receives the acknowledgment frame. The deviation calculation unit is used to calculate the carrier count change ΔC1 and the deviation ΔC2 between the main control carrier count and the power unit carrier count during the frame transmission phase, based on the main control carrier count and the power unit carrier count at the transmission and reception times of the synchronization frame and response frame. The carrier update unit is used by the power unit to recalculate the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame, based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame and the carrier offset ΔC3 generated during the parsing of Ct2.

[0012] Thirdly, a computer storage medium is provided, wherein instructions are stored therein, which, when executed on a computer, cause the computer to perform the methods described in the above aspects.

[0013] The beneficial effects of this invention are as follows: by transmitting frames between the main controller and the power unit, the carrier count of the power unit is updated, making all power units approximate the carrier value in the main controller, thus achieving high-precision synchronization of the carrier value of the power units; and the carrier synchronization period is decoupled from the communication period, avoiding frequent updates; in addition, by transmitting synchronization information through three data frames, the communication bandwidth is greatly reduced to a certain extent, reducing the generation of carrier spikes; carrier compensation ensures that the carrier does not produce a large offset even after long periods of dissynchronization; and sampling compensation compensates for the error in the alignment of the start bit edge of the sampled data frame, achieving sampling synchronization. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a diagram of the existing multi-power unit communication topology; Figure 2 This is a schematic flowchart of a synchronization method according to an embodiment of the present invention; Figure 3 This is a waveform diagram of a synchronization method according to an embodiment of the present invention; Figure 4 This is a waveform comparison diagram after sampling compensation in a synchronization method according to an embodiment of the present invention. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0017] Figure 1The diagram illustrates a common topology for parallel multi-power units. In this invention, power unit carrier synchronization refers to all power units having the same carrier count at the same time. The main controller and unit carrier counts are generated by a logic clock. To ensure synchronization, the main controller and power units use the same logic clock frequency. This embodiment uses a 10MHz logic clock as an example. Assuming the carrier counter accuracy is 1 nanosecond, and a 100-fold multiplication of the 10MHz logic clock equals 1 nanosecond, then with each 10MHz logic clock cycle, the main controller and power unit carrier counts will increment by 100 (when the carrier is at its rising edge) or decrement by 100 (when the carrier is at its falling edge).

[0018] The core chips of the main control unit and power unit are generally FPGAs, whose parallel computing performance and timing control capabilities play a crucial role. The communication channel between the main control unit and the power unit is divided into downlink frames and uplink frames. Downlink frames are data frames sent by the main control unit to the power unit, and uplink frames are data frames sent by the power unit to the main control unit. The uplink frames have a similar structure to the downlink frames, with each data frame divided into two data areas: a process data area and a parameter data area. The process data area of ​​the downlink frame contains fast data sent by the main control unit to the power unit, such as control commands; the process data area of ​​the uplink frame contains fast data sent by the power unit to the main control unit, such as sampling data. The parameter data area is where the main control unit and the power unit cooperate. The main control unit sends data or commands in this area, and the power unit can respond to the main control unit's data or commands in the parameter data area of ​​the uplink frame, or it can choose not to respond. Through the parameter data area, the main control unit can write certain parameters and read parameters from the power unit. Typically, carrier-synchronized designs use communication based on the parameter data area.

[0019] Based on the above principles, such as Figure 2 As shown, this embodiment of the invention provides a multi-power unit parallel carrier synchronization method. The execution subject of this method can be a multi-power unit parallel carrier synchronization system. The method includes: S1: Frame transmission is performed when the start bit of each frame falls on the same edge of the carrier, including: the master controller sends a synchronization frame to the power unit, receives a response frame of the synchronization frame returned by the power unit, and then sends an acknowledgment frame for the response frame, and the power unit receives the acknowledgment frame. S2: Based on the master control carrier count and power unit carrier count at the transmission and reception times of the synchronization frame and response frame, calculate the carrier count change ΔC1 and the deviation ΔC2 between the master control carrier count and the power unit carrier count during the frame transmission stage, with the master control carrier count as the reference. S3: The power unit recalculates the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame, and the carrier offset ΔC3 generated during the parsing of Ct2.

[0020] Optionally, as an embodiment of the present invention, the frame transmission on the same edge of the carrier includes: At time t00: The master controller sends the start bit of the synchronization frame to the power unit. The synchronization frame includes the master controller carrier count Ct0. At time t01: The power unit receives the start bit of the synchronization frame sent by the master controller and the master controller carrier count Ct0 at time t00, and at the same time obtains the power unit carrier count Cr0 at time t01; ΔT1: The power unit determines whether Ct0 and Cr0 are on the same edge. If not, the power unit sends a fault frame to the master controller to notify the master controller to retransmit the synchronization frame message until Ct0 and Cr0 are on the same edge. At time t02: After determining that Ct0 and Cr0 are on the same edge, the power unit sends out the response frame start bit to the master control synchronization frame and obtains the power unit carrier count Ct1 at time t02; At time t03: The master controller receives the start bit of the response frame, which includes the power unit carrier count Ct1, and obtains the master controller carrier count Cr1 at time t03; ΔT2: If the master controller determines that Ct1 and Cr1 are not on the same edge, the master controller sends a fault frame to the power unit and notifies the power unit to retransmit the response frame message until Ct1 and Cr1 are on the same edge. At time t04: After determining that Ct1 and Cr1 are on the same edge, the master controller sends the start bit of the acknowledgment frame. The acknowledgment frame contains the master control carrier count Cr1 that the power unit did not collect during the time period t03, and the master control carrier count Ct2 at time t04. At time t05: The power unit receives the start bit of the acknowledgment frame and records the power unit carrier count Cr2 at time t05.

[0021] At this point, the power unit has collected Ct0, Cr0, Ct1, Cr1, Ct2, and Cr2. Although the power unit carrier count Cr2 has been obtained, it is determined to be invalid because there is an inevitable deviation from the main control. Next, the power unit carrier count Cpowercell will be recalculated through the S2-S3 calculation process to replace the carrier count Cr2.

[0022] The synchronization process in this embodiment of the invention is as follows: Figure 3 As shown, the triangular wave is the carrier wave generated by the main control. t00~t05 are the key moments of the first synchronization process, t10~t15 are the key moments of the next synchronization process, and so on. t(N-1)(0~5) represents the key moment of the Nth synchronization process. The method for each synchronization process is the same; therefore, this embodiment only describes the first synchronization process.

[0023] t01 - t00 represents the time difference between the start bit sent by the master controller and the start bit received by the power unit in the synchronization frame. This time difference is very small and is represented by ΔT. However, when the logic clock and carrier accuracy are very high, and the optical fiber between the master controller and the power unit is long, this time difference becomes significant and cannot be ignored. After t00~t01, the power unit collects two carrier counts, Ct0 and Cr0.

[0024] Similarly, the time difference between t03 and t02 is the time difference between the power unit sending the start bit and the master controller receiving the start bit. Since the fiber optic circuits of the master controller and the power unit are generally symmetrical, and the downlink and uplink fiber optic paths are approximately equal, the time for the data frame to travel from the master controller to the unit and from the unit to the master controller are approximately equal, and are both considered to be ΔT. After t02~t03, the power unit can collect the Ct1 key carrier count, but Cr1 cannot be collected because its value is calculated internally by the master controller. Therefore, Cr1 needs to be sent to the power unit by the master controller during the synchronization process.

[0025] The ΔT1 process is used by the power unit to determine the directions of Ct0 and Cr0. If the power unit determines that the directions of Ct0 and Cr0 are different (the probability is very low), the power unit sends a fault frame to the master controller to notify the master controller to retransmit the synchronization frame message until the directions are consistent. The time consumption of this process is defined as ΔT1.

[0026] Similarly, the ΔT2 process is used by the master controller to determine the directions of Ct1 and Cr1. If the master controller determines that the directions of Ct1 and Cr1 are different (the probability is very low), the master controller sends a fault frame to the power unit to notify the power unit to retransmit the response frame message until the directions are consistent. The time consumption of this process is defined as ΔT2.

[0027] A synchronization process transmits multiple data frames, but only three data frames (synchronization frame, response frame, and acknowledgment frame) have carrier synchronization information. Compared to the traditional method where each data frame sends carrier synchronization, this greatly reduces the communication bandwidth.

[0028] Optionally, as an embodiment of the present invention, the step of calculating the carrier count change ΔC1 and the deviation ΔC2 between the master control carrier count and the power unit carrier count during the frame transmission stage, based on the master control carrier count and the power unit carrier count at the transmission and reception times of the synchronization frame and the response frame, includes: If frame transmission occurs on the rising edge of the carrier, it is calculated according to the following formula: (Ct0-ΔC2)+ΔC1=Cr0 (1) (Ct1+ΔC2)+ΔC1=Cr1 (2) If frame transmission occurs on the falling edge of the carrier wave, it is calculated according to the following formula: (Ct0-ΔC2)-ΔC1=Cr0 (3) (Ct1+ΔC2)-ΔC1=Cr1 (4) Wherein, Ct0, Cr0, Ct1, and Cr1 are known quantities for the power unit; Ct0 is the master control carrier count when the master controller sends the synchronization frame; Cr0 is the power unit carrier count when the power unit receives the synchronization frame; Ct1 is the power unit carrier count when the power unit sends the response frame; and Cr1 is the master control carrier count when the master controller receives the response frame. ΔC1 is the carrier count change based on the master carrier count during the assumed frame transmission time, and the master carrier count is ΔC2 greater than the power unit carrier count. ΔC2 represents the deviation between the master carrier count and the power unit carrier count.

[0029] Therefore, in the above formula, (Ct0 - ΔC2) represents the carrier count of the power unit at t00. Adding ΔC1 represents the power unit carrier count offset after the data frame has passed through time ΔT (t00~t01), and its value is exactly equal to the power unit carrier count Cr0 at time t01. Similarly, (Ct1+ΔC2) represents the main control carrier count at time t02. Adding ΔC1 represents the main control carrier count after the data frame has shifted by time ΔT (t02~t03), and its value is exactly equal to the main control carrier count Cr1 at time t03. Since the ΔT time is very short, the carrier jitter caused by clock jitter in the main control and power units during the ΔT time is negligible.

[0030] Furthermore, if the synchronization processes are not on the same edge, for example, Cr0 is the rising edge and Cr1 is the falling edge, then the following conditions are met: (Ct0 - ΔC2) + ΔC1 = Cr0; (5) (Ct1 + ΔC2) - ΔC1 ​​= Cr1; (6) Alternatively, if Cr0 is a falling edge and Cr1 is a rising edge, then the following conditions are met: (Ct0 - ΔC2) - ΔC1 ​​= Cr0; (7) (Ct1 + ΔC2) + ΔC1 = Cr1; (8) It can be seen that the addition of pairs (5) and (6), and the addition of pairs (7) and (8), are approximate identities and are meaningless. Therefore, a synchronous process must be carried out on the same edge. Figure 3 This is for illustrative purposes only. In reality, the communication processes in the intervals t00~t01, t02~t03, and t04~t05 should occur on the same edge of the carrier wave, or on the same edge of different periods.

[0031] Optionally, as an embodiment of the present invention, the power unit recalculates the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame, and the carrier offset ΔC3 generated during the parsing of Ct2, including: If frame transmission occurs on the falling edge of the carrier wave, the master carrier count Ct2 is at the falling edge: The power cell carrier count Cpowercell is calculated using the following formula: Cpowercell = |Ct2 - ΔC1 ​​- ΔC3|; If frame transmission occurs on the rising edge of the carrier, the power cell carrier count Cpowercell is calculated according to the following formula: When Ct2+ΔC1+ΔC3>CMAX, Cpowercell=CMAX-(Ct2+ΔC1+ΔC3-CMAX)=2*CMAX-(Ct2+ΔC1+ΔC3); When Ct2+ΔC1+ΔC3≤CMAX, Cpowercell=Ct2+ΔC1+ΔC3; CMAX represents the peak value of the carrier counter.

[0032] At this point, after the power unit updates the carrier count Cpowercell, the power unit's carrier count will be very close to that of the master controller, thus completing the carrier synchronization update.

[0033] Optionally, as an embodiment of the present invention, the main control and power unit clocks are asynchronous clocks. Essentially, since the main control and power units operate at the same frequency, their generated carriers should be completely identical. However, the asynchronous nature and instability of the clocks cause a certain clock deviation when the carriers are out of sync for extended periods. Therefore, the carrier compensation method provided in this embodiment overcomes the jitter characteristics of asynchronous clocks operating at the same frequency. The specific method is as follows: The deviation in the power unit carrier count is compensated according to the logic clock speed ratio, where the logic clock speed ratio is the ratio of the main control logic clock count to the internal logic clock count of the power unit over multiple synchronization cycles; the deviation in the power unit carrier count is added to the power unit carrier count Cpowercell.

[0034] The principle of this compensation method is explained below. The lengths of ΔT1 and ΔT2 within a single synchronization process controlled by the master are arbitrary, but the time of the two synchronization processes controlled by the master is periodic, such as... Figure 3 In process T1, assume Figure 3There are N synchronization processes in the process, and the total duration of the synchronization process is N*T1. Based on the master control logic clock, it is assumed that the master control logic clock has passed through K1 master control logic clocks (when designing the logic clock relationship between the master control and the power unit, the power unit clearly understands the synchronization law of the master control, so K1 is a static parameter for the power unit), and the power unit calculates K2 unit logic clocks within the time t01~t(N-1)(1).

[0035] Let z = K1 / K2, where z represents the clock speed ratio of the main control unit. The larger N is, the more stable the speed ratio becomes. Note that the speed ratio should not be calculated using moving average or first-order filtering methods, as the asynchronous clock fluctuations may cause the speed ratio to fluctuate. Calculating it once every N cycles is more reliable.

[0036] Taking a logic clock of 10MHz and a carrier precision of 1 nanosecond as an example, assuming the speed ratio z is 1.01, meaning the master control clock is 1.01 times faster than the power unit clock, the carrier counter inside the power unit should be "accelerated." That is, for every logic clock generated by the power unit, its carrier value should increase by 1.01 * 100 = 101. In this way, after carrier compensation, the carrier counter inside the power unit will not deviate significantly from the master control clock between two synchronization processes. Even if the time interval T1 between the two synchronization processes is long, there will be no significant step jitter at the synchronization moment, which further reduces the difference between the master control clock and the unit carrier.

[0037] Optionally, as an embodiment of the present invention, since there is an edge alignment problem in the start bit of the sampled data frame, this problem is one of the biggest sources of error. Therefore, this embodiment of the present invention provides a sampling compensation method for optimization. The sampling compensation method specifically includes: after the power unit carrier count Cpowercell is updated, using PLL dynamic phase adjustment technology to adjust the logic clock phase of the power unit, and calculating the deviation ΔC2 between the master control carrier count and the power unit carrier count caused by the long-term operation of the asynchronous clock at the same frequency after each adjustment. After multiple averaging iterations, a target phase of the power unit logic clock with a smaller ΔC2 can be obtained.

[0038] The edge alignment problem at the start of the sampled data frame is one of the biggest sources of error. The sampling compensation method provided in this embodiment mainly adopts PLL dynamic phase adjustment technology. After each synchronization process, the logic clock phase of the unit is dynamically adjusted (generally the minimum is VCO / 8). After each adjustment, ΔC2 is compared (for example, it can be obtained by subtracting equation (2) from equation (1) above). After a long period of operation, it can be found which phase has a smaller ΔC2, and the target phase is selected through multiple average iterations. Note that a smaller ΔC2 indicates that the difference between the carrier values ​​of the main control unit in the two synchronization processes is small, indicating that the sampling synchronization of this phase is better.

[0039] Figure 4 The waveform diagram is after sampling compensation due to the instability of the main control unit clock. L1 is the main control carrier. In Example 1, L2 is the case where the unit clock is faster than the main control logic clock (speed ratio is less than 1). In Example 2, L4 is the case where the unit clock is slower than the main control logic clock (speed ratio is greater than 1). L3 in Examples 1 and 2 is the compensated waveform.

[0040] In a second aspect, the present invention provides a multi-power unit parallel carrier synchronization system, comprising: A frame transmission unit is used to transmit frames on the same edge of a carrier, including: the master controller sending a synchronization frame to the power unit, receiving a response frame of the synchronization frame returned by the power unit, and then sending an acknowledgment frame for the response frame, and the power unit receiving the acknowledgment frame. The deviation calculation unit is used to calculate the carrier count change ΔC1 and the deviation ΔC2 between the main control carrier count and the power unit carrier count during the frame transmission phase, based on the main control carrier count and the power unit carrier count at the transmission and reception times of the synchronization frame and response frame. The carrier update unit is used by the power unit to recalculate the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame, based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame and the carrier offset ΔC3 generated during the parsing of Ct2.

[0041] The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, which, when executed, may include some or all of the steps provided in the embodiments of the present invention. The storage medium may be a magnetic disk, an optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0042] Those skilled in the art will clearly understand that the techniques in the embodiments of the present invention can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of the present invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium such as a USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, or other media capable of storing program code. It includes several instructions to cause a computer terminal (which may be a personal computer, server, or a second terminal, network terminal, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0043] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0044] In the embodiments provided by this invention, it should be understood that the disclosed systems, methods, and approaches can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or units may be electrical, mechanical, or other forms.

[0045] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0046] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0047] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention. Such modifications or substitutions should all fall within the scope of the invention, or any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.

Claims

1. A method for synchronizing multiple power units in parallel carrier circuits, characterized in that, include: Step 1: Frame transmission is performed with the start bit of each frame falling on the same edge of the carrier. This includes: the master controller sending a synchronization frame to the power unit, receiving a response frame from the power unit in response to the synchronization frame, and then sending an acknowledgment frame for the response frame. The power unit receives the acknowledgment frame. Specifically: At time t00, the master controller sends the start bit of the synchronization frame to the power unit. The synchronization frame includes the master controller carrier count Ct0. At time t01, the power unit receives the start bit of the synchronization frame sent by the master controller and the carrier count Ct0 of the master controller at time t00, and at the same time obtains the carrier count Cr0 of the power unit at time t01. The power unit determines whether Ct0 and Cr0 are on the same edge. If not, the power unit sends a fault frame to the master controller to notify the master controller to retransmit the synchronization frame message until Ct0 and Cr0 are on the same edge. After determining that Ct0 and Cr0 are on the same edge, the power unit sends the response frame start bit to the master control synchronization frame at time t02 and obtains the power unit carrier count Ct1 at time t02. At time t03, the master controller receives the start bit of the response frame, which includes the power unit carrier count Ct1, and obtains the master controller carrier count Cr1 at time t03. If the master controller determines that Ct1 and Cr1 are not on the same edge, the master controller sends a fault frame to the power unit and notifies the power unit to retransmit the response frame message until Ct1 and Cr1 are on the same edge. After determining that Ct1 and Cr1 are on the same edge, the master controller sends the start bit of the acknowledgment frame at time t04. The acknowledgment frame contains the master control carrier count Cr1 that the power unit did not collect during the time period t03, and the master control carrier count Ct2 at time t04. At time t05, the power unit receives the start bit of the acknowledgment frame and records the power unit carrier count Cr2 at time t05. The carrier count Cr2 is deemed invalid, and the power cell carrier count Cpowercell is recalculated to replace the carrier count Cr2. Step 2: Based on the master control carrier count and power unit carrier count at the transmission and reception times of the synchronization frame and response frame, calculate the carrier count change ΔC1 and the deviation ΔC2 between the master control carrier count and the power unit carrier count during the frame transmission phase, with the master control carrier count as the reference. Step 3: The power unit recalculates the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame, based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame, and the carrier offset ΔC3 generated during the parsing of Ct2.

2. The multi-power unit parallel carrier synchronization method according to claim 1, characterized in that, The calculation of the carrier count change ΔC1 and the deviation ΔC2 between the main control carrier count and the power unit carrier count during the frame transmission phase, based on the main control carrier count and the power unit carrier count at the transmission and reception times of the synchronization frame and response frame, includes: If frame transmission occurs on the rising edge of the carrier, it is calculated according to the following formula: (Ct0-ΔC2)+ΔC1=Cr0 (1) (Ct1+ΔC2)+ΔC1=Cr1 (2) If frame transmission occurs on the falling edge of the carrier wave, it is calculated according to the following formula: (Ct0-ΔC2)-ΔC1=Cr0 (3) (Ct1+ΔC2)-ΔC1=Cr1 (4) Wherein, Ct0 is the master control carrier count when the master controller sends the synchronization frame; Cr0 is the power unit carrier count when the power unit receives the synchronization frame; Ct1 is the power unit carrier count when the power unit sends the response frame; and Cr1 is the master control carrier count when the master controller receives the response frame. ΔC1 is the carrier count change based on the master carrier count during the assumed frame transmission time, and the master carrier count is ΔC2 greater than the power unit carrier count. ΔC2 represents the deviation between the master carrier count and the power unit carrier count.

3. The multi-power unit parallel carrier synchronization method according to claim 2, characterized in that, The power unit recalculates the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame, based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame, and the carrier offset ΔC3 generated during the parsing of Ct2. This recalculation includes: If frame transmission occurs on the falling edge of the carrier wave, the master carrier count Ct2 is at the falling edge: The power cell carrier count Cpowercell is calculated using the following formula: Cpowercell = |Ct2 - ΔC1 ​​- ΔC3|; If frame transmission occurs on the rising edge of the carrier, the power cell carrier count Cpowercell is calculated according to the following formula: When Ct2+ΔC1+ΔC3>CMAX, Cpowercell=CMAX-(Ct2+ΔC1+ΔC3-CMAX)=2*CMAX-(Ct2+ΔC1+ΔC3); When Ct2+ΔC1+ΔC3≤CMAX, Cpowercell=Ct2+ΔC1+ΔC3; CMAX represents the peak value of the carrier counter.

4. The method for parallel carrier synchronization of multiple power units according to claim 1, characterized in that, Also includes: The deviation of the power unit carrier count is compensated according to the logic clock speed ratio, wherein the logic clock speed ratio is the ratio of the main control logic clock count of multiple synchronization cycles to the internal logic clock count of the power unit; The deviation of the power unit carrier count is added to the power unit carrier count Cpowercell.

5. The method for parallel carrier synchronization of multiple power units according to claim 1, characterized in that, Also includes: After the power unit carrier count Cpowercell is updated, PLL dynamic phase adjustment technology is used to adjust the logic clock phase of the power unit. After each adjustment, the deviation ΔC2 between the master control carrier count and the power unit carrier count caused by the long-term operation of the asynchronous clock at the same frequency is calculated. After multiple average iterations, a target phase of the power unit logic clock with a smaller ΔC2 can be obtained.

6. A multi-power unit parallel carrier synchronization system for implementing the method of claim 1, characterized in that, include: A frame transmission unit is used to transmit frames so that the start bit of each frame falls on the same edge of the carrier. The unit includes: the master controller sending a synchronization frame to the power unit and receiving a response frame of the synchronization frame returned by the power unit, and then sending an acknowledgment frame for the response frame. The power unit receives the acknowledgment frame. The deviation calculation unit is used to calculate the carrier count change ΔC1 and the deviation ΔC2 between the main control carrier count and the power unit carrier count during the frame transmission phase, based on the main control carrier count and the power unit carrier count at the transmission and reception times of the synchronization frame and response frame. The carrier update unit is used by the power unit to recalculate the power unit carrier count Cpowercell at the time the power unit receives the acknowledgment frame, based on the master control carrier count Ct2 at the time the master control sends the acknowledgment frame and the carrier offset ΔC3 generated during the parsing of Ct2.

7. A computer-readable storage medium storing a computer program, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-5.

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