Image sensor, camera assembly, and electronic device

Abstract

This application discloses an image sensor, a camera assembly, and an electronic device, belonging to the field of image sensors. The image sensor includes: a pixel array, a gain mode selection logic module, and a dual-conversion gain control module; the pixel array includes M rows of pixel modules and N columns of pixel modules, each pixel module being provided with a signal selection unit. The signal selection units of the same row of pixel modules are connected to the dual-conversion gain control module via a first signal line, and the signal selection units of the same column of pixel modules are connected to the gain mode selection logic module via a second signal line; wherein, the signal selection unit is used to select a target signal from the first conversion gain mode selection signal transmitted by the dual-conversion gain control module and the second conversion gain mode selection signal transmitted by the gain mode selection logic module, and transmit the target signal to the pixel module corresponding to the signal selection unit.

Description

Technical Field

[0001] This application belongs to the field of image sensor technology, specifically relating to an image sensor, camera assembly, and electronic device. Background Technology

[0002] CMOS (Complementary Metal-Oxide Semiconductor) image sensors are a typical type of solid-state imaging sensor. In CMOS image sensors, dynamic range is generally adjusted holistically by changing the exposure time and pixel signal gain of all pixels. This mainly includes High Dynamic Range (HDR) and Wide Dynamic Range (WDR). For example, in Dual Conversion Gain (DCGHDR) mode, all pixels undergo long / short exposures together, and the output signals are amplified with different gains. The gain can be divided into two modes: High Conversion Gain (HCG) mode and Low Conversion Gain (LCG) mode. Conventional DCG-HDR image sensors use a Row DCG Control to generate a DCG mode selection signal, thus placing the pixels in the corresponding conversion gain mode.

[0003] To address the issue of some pixels being locally overexposed or underexposed in images generated using conventional DCG-HDR image sensors, a proposed solution is an adaptive DCG HDR image sensor. This sensor buffers and drives the DCG mode selection signal corresponding to each pixel to control the conversion gain (CG) mode (Pixel-Wise or Per-Pixel) on a pixel-by-pixel basis, thereby achieving pixel-level CG modulation.

[0004] However, due to issues with the image processing link in practical applications, and certain special scenarios (such as polar night), it is still necessary to use the conventional DCG-HDR method. Adaptive DCG-HDR image sensors and conventional DCG-HDR image sensors have significant differences in circuit structure. Therefore, using existing methods (such as rolling shutter) to achieve functional compatibility between the two will cause unnecessary wire conduction and increase the power consumption of signal transmission. Summary of the Invention

[0005] The purpose of this application is to provide an image sensor, camera component, and electronic device that can solve the problem that adaptive DCG-HDR image sensors in related technologies are difficult to be compatible with conventional DCG-HDR modes.

[0006] In a first aspect, embodiments of this application provide an image sensor, including: a pixel array, a gain mode selection logic module, and a dual-conversion gain control module;

[0007] The pixel array includes M rows of pixel modules and N columns of pixel modules. Each pixel module is provided with a signal selection unit. The signal selection unit of the same row of pixel modules is connected to the dual conversion gain control module through a first signal line, and the signal selection unit of the same column of pixel modules is connected to the gain mode selection logic module through a second signal line. M and N are positive integers.

[0008] The signal selection unit is used to select a target signal from the first conversion gain mode selection signal transmitted by the dual conversion gain control module and the second conversion gain mode selection signal transmitted by the gain mode selection logic module, and transmit the target signal to the pixel module corresponding to the signal selection unit.

[0009] Secondly, embodiments of this application provide a camera assembly, including the image sensor described in the first aspect above.

[0010] Thirdly, embodiments of this application provide an electronic device including the camera component described in the second aspect above.

[0011] In this embodiment, by setting a signal selection unit in each pixel module, the signal selection unit can select a target signal from the first conversion gain mode selection signal transmitted by the dual conversion gain control module and the second conversion gain mode selection signal transmitted by the gain mode selection logic module, and transmit the target signal to the pixel module corresponding to the signal selection unit. This enables the adaptive DCG-HDR image sensor to be compatible with the conventional DCG-HDR mode, meeting the imaging requirements of the image processing chain and special shooting scenarios such as extreme night. Furthermore, this embodiment can achieve switching between the adaptive DCG-HDR mode and the conventional DCG-HDR mode without changing the pixel array architecture of the adaptive DCG-HDR image sensor, improving the flexibility of the control architecture of the adaptive DCG-HDR image sensor. Attached Figure Description

[0012] Figures 1a-1c These are schematic diagrams of several high dynamic range implementation methods;

[0013] Figures 2a-2b This is a circuit diagram of the pixel array in a conventional DCG-HDR image sensor;

[0014] Figure 3 This is a control architecture diagram of a CMOS image sensor;

[0015] Figure 4 This is a pixel structure block diagram of an adaptive DCGHDR image sensor;

[0016] Figure 5 This is a control architecture diagram of an adaptive DCGHDR image sensor;

[0017] Figure 6 It is a display diagram showing the time readout line by line using a rolling shutter.

[0018] Figure 7 This is one of the structural schematic diagrams of the image sensor provided in the embodiments of this application;

[0019] Figure 8 This is a second schematic diagram of the structure of the image sensor provided in the embodiments of this application;

[0020] Figure 9 This is the third schematic diagram of the structure of the image sensor provided in the embodiments of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0022] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0023] The image sensor provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0024] Figures 1a-1cThese are schematic diagrams illustrating several high dynamic range (HDR) implementation methods. As shown in the figure, in CMOS image sensors, whether it's temporal multi-frame HDR (Frame Based HDR), staggered HDR (Staggered HDR), or dual-gain HDR (DCG HDR), all pixels use the same exposure time. The modulation effect of HDR is changed by adjusting the exposure time and the output signal gain. For example, in DCG-HDR mode, all pixels undergo long / short exposures together, and the pixel signals are amplified and readout with high or low gain.

[0025] DCG-HDR is an improvement on 4T-APS (4-Transistor Active Pixel Sensor) pixels. Whether it is a traditional RGGB pixel array or a composite pixel array (the one shown in the figure is a 4-in-1 pixel array), it contains components in the pixel module to implement the DCG function, specifically including DCG transistors and capacitor C.

[0026] like Figures 2a-2b As shown, the photodiodes (PDs) in the optical module of the pixel array perform photosensitive and photoelectric conversion in each frame. The generated charge e- is buffered in the floating diffusion (FD) capacitor after being switched by the TX transistor (usually an NMOS (N-type MOSFET) transistor). During the readout phase, the charge e- in the FD is amplified by the source follower (SF), which is a common-drain amplifier, and converted into a corresponding voltage. After being switched by the SEL transistor, the pixel signal PIX_OUT is output to the outside of the pixel. The RST transistor is used to reset the FD to the voltage VDD, and DCG is used to change the size of the FD. In HCG mode, the FD needs to be as small as possible, while in LCG mode, the FD needs to be as large as possible.

[0027] Therefore, based on the above circuit structure, a DCG transistor switch and a capacitor C are added. The DCG transistor switch is used for mode switching between HCG and LCG, and the capacitor C is used to expand the capacitance of the FD capacitor. When the pixel array needs to be in HCG mode, the DCG transistor switch is open, and FD is used to receive the charge e- transferred from PD; when the pixel array needs to be in LCG mode, the DCG transistor closes, expanding the connection between FD and C (note: the RST transistor switch must remain open to prevent reset). Therefore, the charge e- transferred from PD is FD+C. In summary, the implementation of the DCG function essentially involves changing the size of the FD capacitor according to the required gain mode.

[0028] When implementing the DCG-HDR method described above, the control architecture of the CMOS image sensor (CIS) generally adopts the following approach: Figure 3 The layout shown illustrates that each pixel in the pixel array receives reset, charge transfer, and readout select signals from the outputs of the row logic controllers (Logic and Drivers). Additionally, for the DCG-HDR function, it receives the DCG_SEL (DCG mode selection) signal from the output of the row DCG control module. When DCG_SEL is a binary "1" or high, the pixel is in LCG mode; if DCG_SEL is a binary "0" or low, the pixel is in HCG mode. The DCG_SEL signal is routed in row parallel.

[0029] The proposed adaptive DCGHDR image sensor has the following pixel structure block diagram: Figure 4 As shown, the pixel architecture is based on 4T-APS and includes a photosensitive element / module, a pixel reset / readback circuit module, and circuit elements for implementing DCG functionality. It also includes a DCG mode buffer module to buffer the pixel's DCG mode selection signal. The signals controlling this pixel are primarily the pixel reset signal (PIX_RST), the pixel readout selection signal (PIX_SEL), and related power supplies (VDD voltage and VSS ground). Furthermore, the DCG mode selection signal is DCG_SEL, which can be either a digital or analog signal. Within one frame, the pixel receives the DCG mode selection signal delivered externally and buffers it in the internal DCG mode buffer module circuit. During this frame, the pixel will be affected by the DCG mode selection signal buffered in the DCG mode buffer module circuit, operating in LCG or HCG mode and outputting the corresponding pixel signal PIX_OUT. If there are special requirements, the DCG mode selection signal can bypass / pass through the DCG mode buffer module and directly act on the DCG circuit module within the pixel reset / readback circuit module. With this pixel structure, the pixels on the CIS can achieve pixel DCG programming function.

[0030] Furthermore, such as Figure 5As shown, the adaptive DCG HDR image sensor adds a gain mode selection logic module (shown in the diagram as the column-parallel pixel CG selection logic module) and an in-pixel buffer row decoder and driver module to the traditional CIS architecture. Both new modules use a row / column parallel line layout for signal transmission / control of each pixel. This solves the problem of some pixels being locally overexposed or underexposed in the generated image. However, considering the image processing chain issues in practical applications, and for certain special scenarios (such as polar night), users still prefer to choose the conventional DCG-HDR method.

[0031] Currently, most CMOS image sensors operate using a rolling shutter mechanism. For example... Figure 6 As shown, the working period for each row of pixels in each frame is divided into a reset period, an exposure period, and a readout period. The row driver module controls the reset and readout related signals for each row of pixels, and there is a time difference between rows. When implementing conventional DCG-HDR, two pixel readout processes, HCG and LCG, are forced during the readout period. Since the row-parallel ADC cannot simultaneously read and process the pixel output signals under HCG and LCG, each row of pixels needs to be read twice during the readout period. That is, in the conventional CIS control architecture, the DCG mode selection signal (DCG_SEL) only needs to control the DCG mode selection of one row of pixels at a time, and there is a time difference between the DCG_SEL signals of the rows.

[0032] Compared to Figure 3 The control architecture of the CMOS image sensor shown is as follows: Figure 5 In the control architecture of the adaptive DCGHDR image sensor shown, the layout of the DCG_SEL signals has changed from row parallel to column parallel. If using... Figure 5 The CIS control architecture shown would require the DCG_SEL signal to control the DCG mode selection of all pixels each time. For example, in implementing conventional DCG-HDR based on a rolling shutter, all pixels in the first column (e.g., Row 1) would be read in HCG and LCG modes first during the readout period. Figure 3The CIS control architecture shown only requires the DCG_SEL signal to control all pixels in the first column to simultaneously enter HCG and LCG modes; if using... Figure 5 The CIS control architecture shown requires all columns to output DCG_SEL signals to control all pixels in the first column to simultaneously enter HCG and LCG modes. Since each row of pixels shares a single DCG_SEL signal line, the DCG_SEL signal is transmitted to pixels in other columns while controlling the pixels in the first column (although the pixels in other columns do not receive the DCG_SEL control signal at this time). This control method leads to unnecessary conduction and increased power consumption during signal transmission when implementing conventional DCG-HDR technology. Figure 5 The CIS control architecture shown cannot simultaneously implement both conventional DCG-HDR and adaptive DCG-HDR methods.

[0033] This application provides an image sensor to address the problem in related technologies where adaptive DCG-HDR image sensors are difficult to be compatible with conventional DCG-HDR modes, such as... Figure 7 As shown, the image sensor includes: a pixel array 710, a gain mode selection logic module 720, and a dual-conversion gain control module 730;

[0034] The pixel array 710 includes M rows of pixel modules and N columns of pixel modules. Each pixel module is provided with a signal selection unit. The signal selection unit of the same row of pixel modules is connected to the dual conversion gain control module 730 through a first signal line, and the signal selection unit of the same column of pixel modules is connected to the gain mode selection logic module 720 through a second signal line. M and N are positive integers.

[0035] The signal selection unit is used to select a target signal from the first conversion gain mode selection signal transmitted by the dual conversion gain control module and the second conversion gain mode selection signal transmitted by the gain mode selection logic module, and transmit the target signal to the pixel module corresponding to the signal selection unit.

[0036] In practical implementation, the Column-Parallel PixelCG Selection Logic module adaptively controls the dual-gain high dynamic range of each pixel module by providing the Column-Parallel DCG_SEL2 signal. Simultaneously, the Row DCG Control module performs conventional DCG-HDR control by providing the DCG_SEL1 signal. The Row DCG Control module can be a standalone module or a sub-module of the RowLogic and Drivers module.

[0037] The pixel output signal PIX_OUT is transmitted to the parallel ADC and CDS modules in a row-parallel manner for signal processing. When the parallel DCG_SEL2 signal is generated, the parallel pixel CG selection logic module can be linked as shown in the figure and receive the PIX_OUT signal as feedback to calculate the corresponding DCG_SEL2 signal. Alternatively, the PIX_OUT signal can be ignored.

[0038] Each pixel module contains a DCG_SEL signal selection module (marked as module S in the diagram). The inputs to this module are DCG_SEL1 and DCG_SEL2 signals, corresponding to the first conversion gain mode selection signal transmitted by the dual conversion gain DCG control module and the second conversion gain mode selection signal transmitted by the pixel CG selection logic module, respectively. The output of this module is the DCG_SEL signal, which is fed into the pixel module to enable the pixel to operate in either HCG or LCG mode.

[0039] In one possible implementation, the signal selection unit includes a first signal input terminal, a second signal input terminal, and a signal output terminal;

[0040] The signal selection unit is used to obtain a first conversion gain mode selection signal transmitted by the dual conversion gain control module 730 through the first signal input terminal, obtain a second conversion gain mode selection signal transmitted by the gain mode logic module 720 through the second signal input terminal, and select a target signal from them according to the preset signal selection logic and transmit it to the pixel module corresponding to the signal selection unit through the signal output terminal.

[0041] In a specific implementation, the signal selection unit can be a signal selector. When the first conversion gain mode selection signal and the second conversion gain mode selection signal are input to the signal selector, a target signal is selected from the two input signals as the output according to the preset signal selection logic, and the selected output signal is transmitted to the pixel module corresponding to the signal selection unit. The signal selection unit can also be a signal selection circuit, such as a transistor, comparator, etc.

[0042] Considering the size of the pixel module, in one possible implementation, the signal selection unit includes a first transistor;

[0043] The first port of the first transistor is connected to the dual-conversion gain control module 730 through the first signal line, the second port of the first transistor is connected to the gain mode selection logic module 720 through the second signal line, and the third port of the first transistor is connected to the pixel module.

[0044] The first transistor is configured to transmit the first conversion gain mode selection signal to the pixel module when the second conversion gain mode selection signal is at a first predetermined level; or...

[0045] When the first conversion gain mode selection signal is at the first predetermined level, the second conversion gain mode selection signal is transmitted to the pixel module.

[0046] In specific implementation, such as Figure 8 As shown, the DCG_SEL1 signal wire is connected to the source of an N-type MOSFET switching transistor Ms, and the DCG_SEL2 signal wire is connected to the gate of Ms. The drain of the Ms transistor outputs the DCG_SEL signal to the pixel module. The selection logic for the DCG_SEL1 or DCG_SEL2 signal is as follows: if DCG_SEL1 is needed as the DCG_SEL signal input to the pixel module, then the DCG_SEL2 signal needs to be pulled high to a high level voltage or a binary digital signal "1"; if DCG_SEL2 is needed as the DCG_SEL signal input to the pixel module, then the DCG_SEL1 signal needs to be pulled high to a high level voltage or a binary digital signal "1".

[0047] Subsequently, the DCG_SEL signal selects between DCG_SEL1 and DCG_SEL2 and then inputs it into the pixel module. As shown in the circuit structure of the pixel module, the DCG_SEL signal directly controls the MLCG transistor switch. If the DCG_SEL signal is a high-level voltage or a binary digital signal "1", the MLCG transistor switch is closed, the CFD capacitor is connected in parallel with the CLCG capacitor, and the pixel is in LCG mode; if the DCG_SEL signal is a low-level voltage or a binary digital signal "0", the MLCG transistor switch is open, the CFD capacitor is isolated from the CLCG capacitor, and the pixel is in HCG mode.

[0048] The above method enables switching between adaptive DCG-HDR mode and conventional DCG-HDR mode without altering the pixel array architecture of the adaptive DCG-HDR image sensor, thus improving the flexibility of the adaptive DCG-HDR image sensor's control architecture. Furthermore, the DCG_SEL signal selection module uses a single-transistor switch, which is simple and easy to implement, without significantly increasing the size of the pixel module. Additionally, the DCG_SEL signal selection module does not require a separate selection signal input; it uses the signal transmitted within the CIS pixel array, resulting in good stability.

[0049] In another possible implementation, the selection logic of the DCG_SEL signal selection module (S module) is controlled by the user, that is, the signal selection unit also includes a first control terminal and a second control terminal;

[0050] The signal selection unit is used to select a signal from the first conversion gain mode selection signal and the second conversion gain mode selection signal and transmit it to the corresponding pixel module according to the first control signal input by the first control terminal and the second control signal input by the second control terminal.

[0051] In a specific implementation, the signal selection unit can be a signal selector. When the first conversion gain mode selection signal and the second conversion gain mode selection signal are input to the signal selector, a signal is selected from the two input signals as the output through the logical timing of the first control signal and the second control signal, and the selected output signal is transmitted to the corresponding pixel module. For example, when the first control signal is "1" and the second control signal is "0", the first conversion gain mode selection signal is transmitted to the pixel module. The signal selection unit can also be a signal selection circuit, such as a signal selection circuit composed of multiple transistors.

[0052] In one possible implementation, the signal selection unit is used to transmit the second conversion gain mode selection signal to the pixel module when the first control signal is at a first predetermined level and the second control signal is at a second predetermined level.

[0053] Alternatively, the signal selection unit is used to transmit the first conversion gain mode selection signal to the pixel module when the first control signal is at a second predetermined level and the second control signal is at a first predetermined level.

[0054] The first predetermined level can be a high-level voltage or a binary digital signal "1"; the second predetermined level can be a low level or a binary digital signal "0".

[0055] In one possible implementation, the first control signal and the second control signal are input to the signal selection unit via the first control terminal and the second control terminal, respectively; or...

[0056] The first control signal is input to the signal selection unit through the first control terminal, and after being converted into a second control signal by a preset logic circuit, it is input to the signal selection unit through the second control terminal.

[0057] In practical implementation, the user-selected control signal can be a separate independent signal (imported into the S-module for DCG_SEL1 and DCG_SEL2 selection), or either DCG_SEL1 or DCG_SEL2 can be used as the selection control signal. When using a single independent signal, this independent control signal can be generated by the user-controlled column logic controller and output to the S-module of each pixel, or the user can generate the control signal and output it to the S-module of each pixel through dedicated circuitry inside / outside the CIS chip.

[0058] Considering the size of the pixel module, in one possible implementation, the signal selection unit includes a second transistor and a third transistor;

[0059] The fourth port of the second transistor is connected to the gain mode selection logic module through the first signal line. The first control signal is used to control the on / off state of the second transistor. When the second transistor is on, the first conversion gain mode selection signal is transmitted to the pixel module.

[0060] The fifth port of the third transistor is connected to the dual conversion gain control module through the second signal line. The second control signal is used to control the on / off state of the third transistor. When the third transistor is on, the second conversion gain mode selection signal is transmitted to the pixel module.

[0061] In specific implementation, such as Figure 9 As shown, the DCG_SEL signal selection module (S module) uses two N-type MOSFET transistor switches to select between the DCG_SEL1 and DCG_SEL2 signals respectively. Switching transistor MS1 is used to input the DCG_SEL2 signal, and switching transistor MS2 is used to input the DCG_SEL1 signal. Two control signals S1 and S2 are used to control the switching of transistors MS1 and MS2 respectively.

[0062] If DCG_SEL1 is needed as the DCG_SEL signal input to the pixel module, the control pulls the S2 signal high to a high level voltage or binary digital signal "1" and pulls the S1 signal low to a low level voltage or binary digital signal "0". At this time, transistor MS2 is in the on state and MS1 is in the off state, and the DCG_SEL1 signal will be introduced into the pixel module as the DCG_SEL signal. If DCG_SEL2 is needed as the DCG_SEL signal input to the pixel module, the control pulls the S1 signal high to a high level voltage or binary digital signal "1" and pulls the S2 signal low to a low level voltage or binary digital signal "0". At this time, transistor MS1 is in the on state and MS2 is in the off state, and the DCG_SEL2 signal will be introduced into the pixel module as the DCG_SEL signal.

[0063] Furthermore, the DCG_SEL signal, under the independent control of the S1 signal and S12 signal, selects between DCG_SEL1 and DCG_SEL2 before being input into the pixel module. Moreover, due to the use of an independent control switch, the circuit modules related to another DCG-HDR technology can be completely shut down when implementing a certain DCG-HDR technology. For example, when implementing the conventional DCG-HDR method, the DCG_SEL2 signal does not need to be generated; therefore, the DCG_SEL2 signal generation module (here, the row-parallel pixel CG selection logic) can be completely shut down to save power.

[0064] The above method enables switching between adaptive DCG-HDR and conventional DCG-HDR modes without altering the pixel array architecture of the adaptive DCG-HDR image sensor, thus improving the flexibility of the adaptive DCG-HDR image sensor's control architecture. Furthermore, the DCG_SEL signal selection module employs an NMOS transistor switch, which is simple and feasible in structure, without significantly increasing the size of the pixel module. Simultaneously, due to the independent control signals S1 and S2, when one DCG-HDR mode is implemented, the circuit modules related to the other DCG-HDR mode can be completely shut down, thereby saving energy and reducing power consumption.

[0065] This application also provides a camera assembly including the image sensor described above. By setting a signal selection unit in each pixel module, the signal selection unit can select a signal from the first conversion gain mode selection signal transmitted by the dual conversion gain control module and the second conversion gain mode selection signal transmitted by the gain mode selection logic module, and transmit the signal to the corresponding pixel module. This enables the adaptive DCG-HDR image sensor to be compatible with the conventional DCG-HDR mode, thereby avoiding the influence of the image processing link and being suitable for imaging needs in special shooting scenarios such as extreme night, thus improving user satisfaction.

[0066] This application also provides an electronic device, including the camera component described above. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultramobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application does not specifically limit the scope of the electronic device.

[0067] The electronic device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0068] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0069] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. An image sensor, characterized by, include: Pixel array (710), gain mode selection logic module (720) and dual conversion gain control module (730); The pixel array (710) includes M rows of pixel modules and N columns of pixel modules. Each pixel module is provided with a signal selection unit. The signal selection unit of the same row of pixel modules is connected to the dual conversion gain control module (730) through a first signal line. The signal selection unit of the same column of pixel modules is connected to the gain mode selection logic module (720) through a second signal line. M and N are positive integers. The signal selection unit is used to select a target signal from the first conversion gain mode selection signal transmitted by the dual conversion gain control module (730) and the second conversion gain mode selection signal transmitted by the gain mode selection logic module (720), and transmit the target signal to the pixel module corresponding to the signal selection unit.

2. The image sensor of claim 1, wherein, The signal selection unit includes a first signal input terminal, a second signal input terminal, and a signal output terminal; The signal selection unit is used to acquire the first conversion gain mode selection signal transmitted by the dual conversion gain control module (730) through the first signal input terminal, acquire the second conversion gain mode selection signal transmitted by the gain mode selection logic module (720) through the second signal input terminal, and select a target signal from them according to the preset signal selection logic and transmit it to the pixel module corresponding to the signal selection unit through the signal output terminal.

3. The image sensor of claim 2, wherein, The signal selection unit includes a first transistor; The first port of the first transistor is connected to the dual-conversion gain control module (730) through the first signal line, the second port of the first transistor is connected to the gain mode selection logic module (720) through the second signal line, and the third port of the first transistor is connected to the pixel module. The first transistor is used to transmit the first conversion gain mode selection signal to the pixel module when the second conversion gain mode selection signal is at a first predetermined level; or, When the first conversion gain mode selection signal is at the first predetermined level, the second conversion gain mode selection signal is transmitted to the pixel module.

4. The image sensor of claim 2, wherein, The signal selection unit further includes a first control terminal and a second control terminal; The signal selection unit is used to select a target signal from the first conversion gain mode selection signal and the second conversion gain mode selection signal according to the first control signal input by the first control terminal and the second control signal input by the second control terminal, and transmit it to the pixel module corresponding to the signal selection unit.

5. The image sensor according to claim 4, characterized in that, The signal selection unit is used to transmit the second conversion gain mode selection signal to the pixel module when the first control signal is at a first predetermined level and the second control signal is at a second predetermined level.

6. The image sensor according to claim 5, characterized in that, The signal selection unit is used to transmit the first conversion gain mode selection signal to the pixel module when the first control signal is at a second predetermined level and the second control signal is at a first predetermined level.

7. The image sensor according to claim 4, characterized in that, The first control signal and the second control signal are respectively input to the signal selection unit through the first control terminal and the second control terminal; or, The first control signal is input to the signal selection unit through the first control terminal, and after being converted into a second control signal by a preset logic circuit, it is input to the signal selection unit through the second control terminal.

8. The image sensor according to any one of claims 4 to 7, characterized in that, The signal selection unit includes: a second transistor and a third transistor; The fourth port of the second transistor is connected to the gain mode selection logic module (720) through the first signal line. The first control signal is used to control the on / off state of the second transistor. When the second transistor is on, the first conversion gain mode selection signal is transmitted to the pixel module. The fifth port of the third transistor is connected to the dual conversion gain control module (730) through the second signal line. The second control signal is used to control the on / off state of the third transistor. When the third transistor is on, the second conversion gain mode selection signal is transmitted to the pixel module.

9. A camera assembly, characterized in that, Including the image sensor as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the camera component as described in claim 9.

Images