Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a substrate; a capacitor structure on a top surface of the substrate, comprising a plurality of capacitors arranged in an array along a first direction and a second direction, the first direction and the second direction are both directions parallel to the top surface of the substrate, and the first direction intersects the second direction; a transistor structure above the capacitor structure, comprising a plurality of active pillars and a plurality of word lines, the active pillars are electrically connected with the capacitors, the word lines extend along the second direction and continuously cover the active pillars arranged at intervals along the second direction; a bit line structure above the transistor structure, comprising a plurality of bit lines, the bit lines extend along the first direction and are electrically connected with the active pillars arranged at intervals along the first direction. The present disclosure reduces the process difficulty and helps to improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] Semiconductor structures such as DRAM with TOC (Transistor on Capacitor) structures are difficult to integrate with external circuits due to their inherent structural limitations, and leakage current is prone to occur between the capacitor and the substrate. In addition, the manufacturing process of semiconductor structures such as DRAM is relatively complex, resulting in high manufacturing costs.

[0004] Therefore, improving the performance of semiconductor structures and reducing the difficulty of semiconductor manufacturing processes are urgent technical problems that need to be solved. Summary of the Invention

[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to improve the performance of semiconductor structures and reduce the difficulty of semiconductor manufacturing processes.

[0006] According to some embodiments, this disclosure provides a semiconductor structure, including:

[0007] Substrate;

[0008] A capacitor structure, located on the top surface of the substrate, includes a plurality of capacitors arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction.

[0009] A transistor structure, located above the capacitor structure, includes multiple active pillars and multiple word lines. The active pillars are electrically connected to the capacitor, and the word lines extend along the second direction and continuously cover the active pillars spaced apart along the second direction.

[0010] The bit line structure, located above the transistor structure, includes multiple bit lines that extend along the first direction and are electrically connected to the active pillars that are spaced apart along the first direction.

[0011] In some embodiments, it also includes:

[0012] A substrate isolation layer is located between the substrate and the capacitor structure.

[0013] In some embodiments, the capacitor includes:

[0014] The lower electrode includes a conductive post and a conductive layer covering the surface of the conductive post, wherein the top surface of the conductive post is in contact with the active post for electrical connection.

[0015] A dielectric layer covering the surface of the conductive layer;

[0016] The upper electrode covers the surface of the dielectric layer.

[0017] In some embodiments, the substrate isolation layer includes:

[0018] The first sub-substrate isolation layer is continuously distributed below the plurality of conductive pillars;

[0019] The second sub-substrate isolation layer covers the surface of the first sub-substrate isolation layer.

[0020] In some embodiments, the dielectric layer is made of one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer and the upper electrode are made of one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

[0021] In some embodiments, the conductive pillar is made of a silicide material including a first doped ion.

[0022] In some embodiments, the plurality of word lines are arranged at intervals along the first direction; the transistor structure further includes:

[0023] A word line isolation layer is located between adjacent word lines.

[0024] In some embodiments, each active pillar includes a channel region and a drain region and a source region distributed on opposite sides of the channel region along a direction perpendicular to the top surface of the substrate;

[0025] Along both the first and second directions, the width of the source region is greater than the width of the channel region, and the width of the drain region is greater than the width of the channel region.

[0026] In some embodiments, the transistor structure further includes:

[0027] A protective layer is located between the word line isolation layer and the active post, and covers the sidewall of the source region. Along the first direction, the edge of the protective layer is flush with the edge of the word line.

[0028] In some embodiments, the transistor structure further includes a source electrode located on the top surface of the active pillar; the bit line structure further includes:

[0029] Bit line plug, the bottom surface of which is in contact with the source electrode, and the top surface of which is electrically connected to the bit line.

[0030] According to other embodiments, this disclosure also provides a method for forming a semiconductor structure, comprising the following steps:

[0031] Provide initial substrate;

[0032] A substrate and a capacitor structure located on the top surface of the substrate are formed in the initial substrate. The capacitor structure includes a plurality of capacitors arranged in an array along a first direction and a second direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction and the second direction intersect.

[0033] A transistor structure is formed in the initial substrate above the capacitor structure. The transistor structure includes a plurality of active pillars and a plurality of word lines. The active pillars are electrically connected to the capacitor. The word lines extend along the second direction and continuously cover the active pillars that are spaced apart along the second direction.

[0034] A bit line structure is formed above the transistor structure. The bit line structure includes multiple bit lines that extend along the first direction and are electrically connected to the active pillars that are spaced apart along the first direction.

[0035] In some embodiments, the specific steps of forming a substrate and a capacitor structure located on the top surface of the substrate in the initial substrate include:

[0036] The initial substrate is etched to form a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etch holes located between adjacent semiconductor pillars, and a plurality of grooves that communicate with each of the plurality of etch holes and are located below the etch holes.

[0037] A substrate isolation layer is formed to connect adjacent grooves and fill the grooves, and the initial substrate remaining below the substrate isolation layer serves as the substrate;

[0038] A capacitor is formed within the etched hole.

[0039] In some embodiments, the specific steps of forming a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etching holes located between adjacent semiconductor pillars, and a plurality of grooves communicating with each of the plurality of etching holes and located below the etching holes include:

[0040] The initial substrate is etched to form a plurality of first etch trenches, each of the first etch trenches extending along the first direction, and the plurality of first etch trenches are arranged at intervals along the second direction;

[0041] The initial substrate is etched to form a plurality of second etch trenches, each of the second etch trenches extending along the second direction, and the plurality of second etch trenches are spaced apart along the first direction;

[0042] The initial substrate at the bottom of the second etching trench is etched to form a groove with a width greater than that of the second etching trench in a first direction;

[0043] The first etching trench and the second etching trench are connected to form a plurality of etching holes and semiconductor pillars located between adjacent etching holes.

[0044] In some embodiments, the specific steps for forming the groove with a width greater than that of the second etching groove include:

[0045] The initial substrate at the bottom of the second etching trench is etched using Bosch etching technology to form the groove.

[0046] In some embodiments, the specific steps of forming the substrate and the capacitor structure located on the top surface of the substrate in the initial substrate further include:

[0047] A sacrificial layer is formed to fill the etched holes and the grooves;

[0048] The sacrificial layer is etched back from the top surface of the initial substrate to expose the upper part of the semiconductor pillar;

[0049] A support layer is formed on the top surface of the sacrificial layer to cover the exposed semiconductor pillars.

[0050] In some embodiments, after forming a support layer covering the exposed semiconductor pillar on the top surface of the sacrificial layer, the following steps are further included:

[0051] Remove the sacrificial layer;

[0052] Oxidize the semiconductor pillars between adjacent grooves to form a first sub-substrate isolation layer;

[0053] An insulating material is filled into the groove to form a second sub-substrate isolation layer, and the first sub-substrate isolation layer and the second sub-substrate isolation layer together serve as the substrate isolation layer.

[0054] In some embodiments, the etched hole located between the substrate isolation layer and the support layer serves as a capacitor hole, and the initial substrate material is silicon; the specific steps for forming a capacitor within the etched hole include:

[0055] A first doped ion is injected into the semiconductor pillar between adjacent capacitor holes to form an initial conductive pillar;

[0056] Deposit metallic material onto the initial conductive pillar to form a conductive pillar comprising a silicide;

[0057] A conductive layer covering the sidewall of the conductive pillar, a dielectric layer covering the sidewall of the conductive layer, and an upper electrode covering the surface of the dielectric layer are formed sequentially.

[0058] In some embodiments, the specific steps for forming a conductive layer covering the sidewall of the conductive pillar include:

[0059] The conductive layer, which covers only the sidewalls of the conductive pillar, is formed directly using a selective atomic layer deposition process.

[0060] In some embodiments, the dielectric layer is made of one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer and the upper electrode are made of one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

[0061] In some embodiments, the specific steps of forming a transistor structure located above the capacitor structure in the initial substrate include:

[0062] Remove the support layer to expose the upper part of the etched hole and the upper part of the semiconductor pillar. Use the exposed semiconductor pillar as an active pillar and define a channel region, a drain region located below the channel region and in contact with the conductive pillar, and a source region located above the channel region in the active pillar.

[0063] Reduce the width of the channel region along the first direction and the second direction;

[0064] The word lines are formed to extend along the second direction and continuously cover the plurality of channel areas spaced apart along the second direction.

[0065] In some embodiments, the specific steps of reducing the width of the channel region along the first direction and the second direction include:

[0066] A filling layer is formed to fill the etched holes between adjacent active pillars;

[0067] The filling layer of the etched portion is then exposed to reveal the source region;

[0068] A protective layer is formed covering the sidewalls of the source region;

[0069] The filling layer of the etched portion is re-etched to expose the channel region, and the remaining filling layer on the sidewall of the drain region serves as an initial isolation layer.

[0070] The exposed sidewalls of the channel region are modified to form a modified layer;

[0071] Remove the modified layer and reduce the width of the channel region along the first and second directions.

[0072] In some embodiments, the modification treatment is a thermal oxidation treatment, and the modified layer is an oxide layer.

[0073] In some embodiments, after forming the word lines that extend along the second direction and continuously cover a plurality of channel regions spaced apart along the second direction, the method further includes:

[0074] A second doped ion is implanted into the source region, the channel region, and the drain region, wherein the second doped ion is of the same ion type as the first doped ion.

[0075] In some embodiments, after implanting a second doped ion into the source region, the channel region, and the drain region, the following steps are further included:

[0076] A metallic material is deposited on the surface of the source region to form a source electrode comprising a silicide.

[0077] In some embodiments, the specific steps of forming a bit line structure over the transistor structure include:

[0078] Multiple bit line plugs are formed, each located on the top surface of one of the multiple source electrodes;

[0079] Multiple bit lines are formed above the bit line plugs, and the multiple bit lines are spaced apart along the second direction. Each bit line extends along the first direction and is electrically connected to the multiple bit line plugs spaced apart along the first direction.

[0080] This disclosure provides semiconductor structures and methods for forming the same, in which a transistor structure is disposed above a capacitor structure and a bit line structure is disposed above the transistor structure, forming a semiconductor structure with a TOC structure. This eliminates the need for deep-hole etching to form the bit line structure below the transistor structure, thereby reducing the manufacturing difficulty of the bit lines and lowering the manufacturing cost of the semiconductor structure. Furthermore, since the bit line structure is located above the transistor structure, various materials (such as metals) can be used to manufacture the bit lines, which helps reduce bit line resistance, improves the performance of the semiconductor structure, and enables better compatibility with subsequent peripheral circuit processes. Attached Figure Description

[0081] Appendix Figure 1 This is a schematic diagram of the semiconductor structure in a specific embodiment of this disclosure;

[0082] Appendix Figure 2 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;

[0083] Appendix Figures 3-15 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to the specific embodiments of this disclosure. Detailed Implementation

[0084] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0085] This specific embodiment provides a semiconductor structure, with appended... Figure 1 This is a schematic diagram of a semiconductor structure according to a specific embodiment of this disclosure. The semiconductor structure described in this embodiment may be, but is not limited to, DRAM. For example... Figure 1 As shown, the semiconductor structure provided in this specific embodiment includes:

[0086] Substrate 10;

[0087] A capacitor structure, located on the top surface of the substrate 10, includes a plurality of capacitors arranged in an array along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 10, and the first direction D1 intersects the second direction D2.

[0088] A transistor structure, located above the capacitor structure, includes multiple active pillars 13 and multiple word lines 15. The active pillars 13 are electrically connected to the capacitor, and the word lines 15 extend along the second direction D2 and continuously cover the active pillars 13 that are spaced apart along the second direction D2.

[0089] The bit line structure, located above the transistor structure, includes multiple bit lines 18, which extend along the first direction D1 and are electrically connected to the active pillars 13 arranged at intervals along the first direction D1.

[0090] Specifically, the substrate 10 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 10 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 10 is used to support the device structure thereon. The top surface of the substrate 10 refers to the surface on the substrate 10 on which the capacitor structure is formed.

[0091] The capacitor structure includes a plurality of capacitors arranged in a two-dimensional array along the first direction D1 and the second direction D2. Each capacitor extends along a third direction D3, which is perpendicular to the top surface of the substrate 10. The transistor structure is located above the capacitor structure and includes a plurality of active pillars 13 arranged in a two-dimensional array along the first direction D1 and the second direction D2. Each active pillar 13 includes a channel region and drain and source regions distributed on opposite sides of the channel region along the third direction D3. The capacitors are electrically connected to the drain regions. The transistor structure also includes a plurality of word lines 15 and a word line isolation layer 19 located between two adjacent word lines 15. The word lines 15 extend along the second direction D2 and continuously cover the active pillars 13 arranged at intervals along the second direction D2, forming a channel-encircling structure for the word lines 15. The bit line structure includes multiple bit lines 18, which are located above the transistor structure. This allows the bit lines 18 to be formed using a metallic material such as tungsten, thereby reducing the resistance of the bit lines and simplifying the bit line manufacturing process. Furthermore, placing the bit lines 18 above the transistor structure makes them compatible with peripheral circuit technologies such as CORE (processor core), SA (sensor amplifier), and I / O (input / output).

[0092] In some embodiments, the capacitor includes:

[0093] The lower electrode includes a conductive post 121 and a conductive layer 122 covering the surface of the conductive post 121. The top surface of the conductive post 121 is in contact with the active post 13 for electrical connection.

[0094] A dielectric layer 123 covers the surface of the conductive layer 122;

[0095] The upper electrode 124 covers the surface of the dielectric layer 123.

[0096] Specifically, the lower electrode in the capacitor includes a conductive post 121 extending along the third direction D3, and a conductive layer 122 covering the sidewall of the conductive post 121. The dielectric layer 123 covers the sidewall of the conductive layer 122, the surface of the substrate isolation layer 11, and the bottom surface of the word line isolation layer 19. The upper electrode 124 covers the surface of the dielectric layer 123.

[0097] In some embodiments, the dielectric layer 123 is made of any one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer 122 and the upper electrode 124 are made of any one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

[0098] Specifically, the dielectric layer 123 can be made of STO (strontium titanate) material with a high dielectric constant (HK), and the conductive layer 122 and the upper electrode 124 can be formed using ruthenium or ruthenium oxide, thereby reducing the height of the capacitor along the third direction D3, and thus reducing the etching depth when etching the capacitor holes to form the capacitor, further reducing the manufacturing difficulty. In other examples, the dielectric layer 123 can also be formed using any one or more of alumina, zirconium oxide, and hafnium oxide, and correspondingly, the conductive layer 122 and the upper electrode 124 can be formed using TiN, thereby reducing the manufacturing cost of the semiconductor layer structure.

[0099] In some embodiments, the conductive post 121 is made of a silicide material including a first doped ion to enhance the conductivity of the conductive post 121. In one embodiment, the drain region includes a second doped ion of the same type as the first doped ion to further reduce the contact resistance between the conductive post 121 and the drain region.

[0100] In some embodiments, the semiconductor structure further includes:

[0101] The substrate isolation layer 11 is located between the substrate 10 and the capacitor structure.

[0102] Specifically, the material of the substrate isolation layer 11 can be, but is not limited to, insulating materials such as oxides (e.g., silicon dioxide). By forming the substrate isolation layer 11 between the substrate 10 and the capacitor structure, the leakage path from the bottom of the capacitor to the substrate 10 is isolated, thereby reducing leakage problems between the capacitor and the substrate 10.

[0103] In some embodiments, the substrate isolation layer 11 includes:

[0104] The first sub-substrate isolation layer is continuously distributed below the plurality of conductive pillars 121;

[0105] The second sub-substrate isolation layer covers the surface of the first sub-substrate isolation layer.

[0106] Specifically, the substrate isolation layer 11 includes a first sub-substrate isolation layer continuously distributed below the plurality of conductive pillars 121, and a second sub-substrate isolation layer covering the surface of the first sub-substrate isolation layer. This allows the substrate isolation layer to be formed simultaneously with the capacitor via, ensuring that the substrate isolation layer is formed directly below the capacitor. This ensures that the substrate isolation layer is fully aligned with the bottom of the capacitor, simplifying the semiconductor structure manufacturing process, reducing the process difficulty of the semiconductor structure, and further improving the electrical isolation effect between the capacitor and the substrate.

[0107] In other examples, the substrate isolation layer 11 may also be a single-layer structure, for example, the substrate isolation layer 11 may be a single oxide layer located between the substrate 10 and the capacitor structure.

[0108] In some embodiments, each of the active pillars 13 includes a channel region, and a drain region and a source region distributed on opposite sides of the channel region along a direction perpendicular to the top surface of the substrate 10.

[0109] Along the first direction D1 and the second direction D2, the width of the source region is greater than the width of the channel region, and the width of the drain region is greater than the width of the channel region.

[0110] Specifically, along the third direction D3, the drain region is located below the channel region, and the source region is located above the channel region. The drain region is electrically connected to the lower electrode of the capacitor. Along the first direction D1 and the second direction D2, the widths of both the source and drain regions are greater than the width of the channel region, thereby providing more space for the formation of the word line 15. This not only helps simplify the manufacturing process of the semiconductor structure but also facilitates further miniaturization of the semiconductor structure to meet the application needs of different fields.

[0111] In some embodiments, the plurality of word lines 15 are arranged at intervals along the first direction D1; the transistor structure further includes:

[0112] Word line isolation layer 19 is located between adjacent word lines 15.

[0113] In some embodiments, the transistor structure further includes:

[0114] The protective layer 16 is located between the word line isolation layer 19 and the active post 13 and covers the sidewall of the source region. Along the first direction D1, the edge of the protective layer 16 is flush with the edge of the word line 15.

[0115] Specifically, the material of the protective layer 16 can be, but is not limited to, insulating materials such as nitrides (e.g., silicon nitride). The protective layer 16 can not only be used to electrically isolate two adjacent source regions, but also serve as a mask layer when forming the word line 15, thereby reducing the number of masks and further reducing the manufacturing cost of the semiconductor structure.

[0116] In some embodiments, the transistor structure further includes a source electrode 20 located on the top surface of the active pillar 13; the bit line structure further includes:

[0117] Bit line plug 17, the bottom surface of which is in contact with the source electrode 20, and the top surface of which is electrically connected to the bit line 18.

[0118] Specifically, one end of the bit line plug 17 is electrically connected to the source electrode 20, and the other end is electrically connected to the bit line 18. The bit line 18 extends along the first direction D1, and multiple bit lines 18 are arranged at intervals along the second direction D2. Each bit line 18 is electrically connected to multiple source electrodes 20 arranged at intervals along the first direction D1 through the bit line plug 17. The material of the bit line plug 17 can be the same as the material of the bit line 18, for example, both being tungsten or molybdenum.

[0119] This specific embodiment also provides a method for forming a semiconductor structure, attached... Figure 2 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figures 3-15 This is a schematic diagram of the main process structure during the formation of the semiconductor structure according to the specific embodiments of this disclosure. A schematic diagram of the semiconductor structure formed according to this specific embodiment can be found in [reference needed]. Figure 1 .like Figures 1-15 As shown, the method for forming the semiconductor structure includes the following steps:

[0120] Step S21, provide an initial substrate 30, such as Figure 3 As shown.

[0121] Specifically, the initial substrate 30 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate containing p-type doped ions as an example for illustration. In other examples, the initial substrate 30 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.

[0122] Step S22: A substrate 10 and a capacitor structure located on the top surface of the substrate 10 are formed in the initial substrate 30. The capacitor structure includes a plurality of capacitors arranged in an array along a first direction D1 and a second direction D2. Both the first direction D1 and the second direction D2 are parallel to the top surface of the substrate 10, and the first direction D1 and the second direction D2 intersect. Figure 10 and Figure 15 As shown.

[0123] In some embodiments, the specific steps of forming the substrate 10 and the capacitor structure located on the top surface of the substrate 10 in the initial substrate 30 include:

[0124] The initial substrate 30 is etched to form a plurality of semiconductor pillars 34 arranged in an array along the first direction D1 and the second direction D2, etch holes 41 located between adjacent semiconductor pillars 34, and a plurality of grooves 35 communicating with each of the plurality of etch holes 41 and located below the etch holes 41, such as... Figure 7 As shown;

[0125] A substrate isolation layer 11 is formed to connect adjacent grooves 35 and fill the grooves 35. The initial substrate 30 remaining below the substrate isolation layer 11 serves as substrate 10. Figure 9 As shown;

[0126] A capacitor is formed within the etched hole 41, such as Figure 10 As shown.

[0127] In some embodiments, the specific steps of forming a plurality of semiconductor pillars 34 arranged in an array along the first direction D1 and the second direction D2, etching holes 41 located between adjacent semiconductor pillars 34, and a plurality of grooves 35 communicating with each of the plurality of etching holes 41 and located below the etching holes 41 include:

[0128] The initial substrate 30 is etched to form a plurality of first etch trenches 31, each of the first etch trenches 31 extending along the first direction D1, and the plurality of first etch trenches 31 are arranged at intervals along the second direction D2, such as... Figure 3 As shown;

[0129] The initial substrate 30 is etched to form a plurality of second etching trenches 33, each of the second etching trenches 33 extending along the second direction D2, and the plurality of second etching trenches 33 are arranged at intervals along the first direction D1;

[0130] The initial substrate 30 at the bottom of the second etching trench 33 is etched to form a groove 35 in the first direction D1 with a width greater than that of the second etching trench 33, such as... Figure 4 As shown;

[0131] The first etching trench 31 and the second etching trench 33 are connected to form a plurality of etching holes 41 and semiconductor pillars 34 located between adjacent etching holes 41.

[0132] In some embodiments, the specific steps for forming the groove 35 with a width greater than that of the second etching groove 33 include:

[0133] The initial substrate 30 at the bottom of the second etching trench 33 is etched using Bosch etching technology to form the groove 35.

[0134] Specifically, a photolithography process is used to etch the initial substrate 30 along the third direction D3 to form a plurality of first etch trenches 31 that do not penetrate the initial substrate 30. Each first etch trench 31 extends along the first direction D1, and the plurality of first etch trenches 31 are spaced apart along the second direction D2. The depth of the first etch trenches 31 along the third direction D3 is 500nm to 1200nm. Next, the first etch trenches 31 are filled with a material such as an oxide (e.g., silicon dioxide) to form a first dielectric layer 32, such as... Figure 4 As shown. The first dielectric layer 32 is used to support the initial substrate 30, preventing the initial substrate 30 from tilting or collapsing during the formation of the second etched trench 33. After forming the first dielectric layer 32, the initial substrate 30 can be etched again along the third direction D3 using photolithography to form multiple second etched trenches 33 that do not penetrate the initial substrate 30. Each second etched trench 33 extends along the second direction D2, and the multiple second etched trenches 33 are spaced apart along the first direction D1. The depth of the second etched trench 33 along the third direction D3 can be less than that of the first etched trench 31, so as to facilitate the subsequent formation of the groove 35 below the second etched trench 33. After forming the second etched trench 33, the initial substrate 30 at the bottom of the second etched trench 33 is etched using Bosch etching technology to form the groove 35, which communicates with the second etched trench 33 and has an inner diameter larger than that of the second etched trench 33, as shown. Figure 4 As shown. Since the inner diameter of the groove 35 is larger than the inner diameter of the second etching groove 33, the width of the semiconductor pillar 34 between adjacent second etching grooves 33 is greater than the width of the semiconductor pillar 34 between adjacent grooves 35 along the first direction D1.

[0135] This specific embodiment uses a Bosch etching process to form the groove 25 after forming the second etched groove 33, thereby simplifying the semiconductor structure formation process. In other embodiments, those skilled in the art can also select other etching processes as needed to form the second etched groove 33 and the groove 35 communicating with the second etched groove 33.

[0136] In some embodiments, the specific steps of forming the substrate 10 and the capacitor structure located on the top surface of the substrate 10 in the initial substrate 30 further include:

[0137] A sacrificial layer 37 is formed to fill the etched holes 41 and the grooves 35;

[0138] The sacrificial layer 37 is etched back from the top surface of the initial substrate 30, exposing the upper part of the semiconductor pillar 34, as shown. Figure 5 As shown;

[0139] A support layer 38 is formed on the top surface of the sacrificial layer 37 to cover the exposed semiconductor pillar 34, such as... Figure 6 As shown.

[0140] Specifically, after forming the groove 35, an oxide (e.g., silicon dioxide) or similar material is deposited in the second etch trench 33 and the groove 35 to form a second dielectric layer filling the second etch trench 33 and the groove 35. The first dielectric layer 32 and the second dielectric layer together constitute the sacrificial layer 37. Then, the sacrificial layer 37 is etched back, exposing the upper part of the semiconductor pillar 34, such as... Figure 5 As shown. The height of the exposed semiconductor pillar 34 along the third direction D3 can be 50nm to 200nm. Next, a support material is deposited on the top surface of the sacrificial layer 37 to form a support layer 38 covering the exposed semiconductor pillar 34. After planarizing the support layer 38, a first mask layer 39 is formed on the top surface of the support layer 38, as shown. Figure 6 As shown. The supporting material can be, but is not limited to, nitride materials (e.g., silicon nitride). The material of the first mask layer 39 can be, but is not limited to, hard mask materials such as polysilicon. The supporting layer 38 protects the upper part of the semiconductor pillar 34 from damage during subsequent capacitor formation processes; furthermore, the supporting layer 38 also supports the semiconductor pillar 34 to prevent it from tipping over after the sacrificial layer 37 is removed.

[0141] In some embodiments, after forming a support layer 38 covering the exposed semiconductor pillar 34 on the top surface of the sacrificial layer 37, the following steps are further included:

[0142] Remove the sacrificial layer 37, as follows Figure 7 As shown;

[0143] Oxidize the semiconductor pillars 34 between adjacent grooves 35 to form a first sub-substrate isolation layer 36;

[0144] An insulating material is filled into the groove 35 to form a second sub-substrate isolation layer 42. The first sub-substrate isolation layer 36 and the second sub-substrate isolation layer 42 together serve as the substrate isolation layer 11. Figure 9 As stated above.

[0145] Specifically, the first mask layer 39 is patterned using photolithography to form multiple first openings that penetrate the first mask layer 39 and expose the support layer 38. A mask used to form the first etching groove 31 and the second etching groove 33 can be used to pattern the first mask layer 39, aligning the positions of the multiple first openings with the multiple etching holes. The support layer 38 is etched downwards along the first openings, forming a second opening 40 in the support layer 38 that exposes the sacrificial layer 37. After removing the first mask layer 39, the sacrificial layer 37 is etched away along the second opening 40, resulting in... Figure 7 The structure shown.

[0146] After removing the sacrificial layer 37, the semiconductor pillars 34 located below the support layer 38 can be oxidized in situ, for example, by using in-situ water vapor generation. Since the inner diameter of the groove 35 is larger than the inner diameter of the second etch groove 33, the width of the semiconductor pillars 34 between adjacent second etch grooves 33 is greater than the width of the semiconductor pillars 34 between adjacent grooves 35 along the first direction D1. Therefore, by controlling oxidation parameters (e.g., oxidation time, oxidant dosage, etc.), the semiconductor pillars 34 between adjacent grooves 35 can be completely oxidized, and the surfaces of the semiconductor pillars 34 between adjacent etch holes 41 can be oxidized, thereby forming a first sub-substrate isolation layer 36 covering the sidewalls of the etch holes 41 and located between adjacent grooves 35 and covering the bottom surface of the grooves 35. Then, the second sub-substrate isolation layer 42 is deposited along the second opening 40, forming... Figure 8 The structure is shown. Next, a reverse etching process is performed to remove the first sub-substrate isolation layer 36 and the second sub-substrate isolation layer 42 located within the etched hole 41. The remaining first sub-substrate isolation layer 36 and the second sub-substrate isolation layer 42 together serve as the substrate isolation layer 11, as shown. Figure 9 As shown.

[0147] In some embodiments, the etched hole 41 located between the substrate isolation layer 11 and the support layer 38 serves as a capacitor hole, and the initial substrate 30 is made of silicon; the specific steps for forming a capacitor within the etched hole 41 include:

[0148] A first doped ion is implanted into the semiconductor pillar 34 between adjacent capacitor holes to form an initial conductive pillar;

[0149] Depositing metallic material onto the initial conductive pillars forms conductive pillars 121, the material of which includes silicide, such as... Figure 9 As shown;

[0150] A conductive layer 122 covering the sidewall of the conductive pillar 121, a dielectric layer 123 covering the sidewall of the conductive layer 122, and an upper electrode 124 covering the surface of the dielectric layer 123 are sequentially formed, as follows: Figure 10 As shown.

[0151] Specifically, after etching back to remove the first sub-substrate isolation layer 36 and the second sub-substrate isolation layer 42 located within the etched hole 41, the first doped ions (e.g., N-type ions) can be implanted into the semiconductor pillar 34 between adjacent capacitor holes using plasma implantation or vapor diffusion to form initial conductive pillars, thereby enhancing the conductivity of the initial conductive pillars. Then, an atomic layer deposition process is used to deposit a metal material such as nickel on the surface of the initial conductive pillars, followed by heat treatment to form the conductive pillar 121, which is made of metal silicide, to further enhance the conductivity of the conductive pillar 121. Then, a conductive layer 122 covering the sidewalls of the conductive pillar 121, a dielectric layer 123 covering the sidewalls of the conductive layer 122, and an upper electrode 124 covering the surface of the dielectric layer 123 are sequentially formed to form a capacitor including the conductive pillar 121, the conductive layer 122, the dielectric layer 123, and the upper electrode 124.

[0152] To reduce etching steps and further simplify the manufacturing process of the semiconductor structure, in some embodiments, the specific steps for forming the conductive layer 122 covering the sidewalls of the conductive pillar 121 include:

[0153] The conductive layer 122, which covers only the sidewalls of the conductive pillar 121, is formed directly using a selective atomic layer deposition process.

[0154] In some embodiments, the dielectric layer 123 is made of any one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer 122 and the upper electrode are made of any one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

[0155] Specifically, the dielectric layer 123 can be made of STO (strontium titanate) material with a high dielectric constant (HK), and the conductive layer 122 and the upper electrode 124 can be formed using ruthenium or ruthenium oxide, thereby reducing the height of the capacitor along the third direction D3, and thus reducing the etching depth when etching the capacitor holes used to form the capacitor, thereby further reducing the manufacturing difficulty. In other examples, the dielectric layer 123 can also be formed using any one or more of alumina, zirconium oxide, and hafnium oxide, and correspondingly, the conductive layer 122 and the upper electrode 124 can be formed using TiN, etc., to reduce the manufacturing cost of the semiconductor layer structure.

[0156] Step S23: A transistor structure is formed in the initial substrate 30 above the capacitor structure. The transistor structure includes a plurality of active pillars 13 and a plurality of word lines 15. The active pillars 13 are electrically connected to the capacitor, and the word lines 15 extend along the second direction D2 and continuously cover the active pillars 13 spaced apart along the second direction D2. Figure 14 As shown.

[0157] In some embodiments, the specific steps of forming a transistor structure above the capacitor structure in the initial substrate 30 include:

[0158] The support layer 38 is removed, exposing the upper part of the etched hole 41 and the upper part of the semiconductor pillar 34. The exposed semiconductor pillar 34 serves as the active pillar 13, and a channel region, a drain region located below the channel region and in contact with the conductive pillar 121, and a source region located above the channel region are defined in the active pillar 13. Figure 11 As shown;

[0159] Reduce the width of the channel region 451 along the first direction D1 and the second direction D2, such as Figure 13 As shown;

[0160] The word lines 15 are formed by extending along the second direction D2 and continuously covering the plurality of channel regions spaced apart along the second direction D2, such as... Figure 14 As shown.

[0161] In some embodiments, the specific steps for reducing the width of the channel region along the first direction D1 and the second direction D2 include:

[0162] A filling layer 46 is formed to fill the etched holes 41 between adjacent active pillars 13, such as... Figure 12 As shown;

[0163] The filling layer 46 of the etched portion exposes the source region;

[0164] A protective layer 16 is formed covering the sidewalls of the source region, such as Figure 12 As shown;

[0165] The filling layer 46 is etched back to expose the channel region 451, and the remaining filling layer 46 on the sidewall of the drain region serves as a first initial isolation layer.

[0166] The exposed sidewalls of the channel region 451 are modified to form a modified layer;

[0167] Remove the modified layer and reduce the width of the channel region 451 along the first direction D1 and the second direction D2.

[0168] Specifically, after forming the protective layer 16, the filling layer 46 is etched back to expose the channel region 451 in the active pillar 13. During the etch-back process, to prevent the filling layer 46 from being penetrated, a one-step etching process or a two-step etching process can be used, and appropriate etching parameters (such as temperature, pressure, etc.) can be selected to leave a certain thickness of the first initial isolation layer. Since the sidewalls of the source region in the active pillar 13 are covered by the protective layer 16 and the sidewalls of the drain region are covered by the initial isolation layer, the modification treatment of the channel region 451 will not damage the source region and the drain region. In this specific embodiment, the sidewalls of the channel region 451 are modified to achieve a high etching selectivity (e.g., an etching selectivity greater than 3) between the sidewalls of the channel region 451 and the interior of the channel region 451 surrounded by the sidewalls. This allows for the selective etching removal of the modified sidewalls of the channel region 451, thereby reducing the width of the channel region 451 and increasing the gap width between adjacent channel regions 451, thus reserving more space for the subsequent formation of the word line 15.

[0169] Since the thermal oxidation process is relatively simple, in some embodiments, the modification treatment is thermal oxidation, and the modified layer is an oxide layer.

[0170] After narrowing the width of the channel region 451 along the first direction D1 and the second direction D2, the sidewalls of the channel region are oxidized to form a gate dielectric layer 14. Then, a word line 15 extending only along the second direction D2 is directly formed using a selective atomic layer deposition process. Next, a second initial isolation layer is deposited between two adjacent active pillars 13 to form a word line isolation layer 19 including the first initial isolation layer and the second initial isolation layer.

[0171] In other examples, the word line 15 can also be formed by etching the word line material using an etch-back process after depositing the word line material using an atomic layer deposition process, thereby forming the word line 15 that extends only along the second direction D2.

[0172] In some embodiments, after forming the word lines 15 that extend along the second direction D2 and continuously cover a plurality of channel regions spaced apart along the second direction D2, the method further includes:

[0173] A second doped ion is implanted into the source region, the channel region, and the drain region, wherein the second doped ion is of the same ion type as the first doped ion.

[0174] In some embodiments, after implanting a second doped ion into the source region, the channel region, and the drain region, the following steps are further included:

[0175] Depositing metallic material on the surface of the source region forms a source electrode 20 comprising a silicide, such as... Figure 14 As shown.

[0176] Step S24: A bit line structure is formed above the transistor structure. The bit line structure includes multiple bit lines 18, which extend along the first direction D1 and are electrically connected to the active pillars 13 arranged at intervals along the first direction D1. Figure 15 As shown.

[0177] In some embodiments, the specific steps of forming a bit line structure over the transistor structure include:

[0178] Multiple bit line plugs 17 are formed on the top surfaces of the multiple source electrodes 20 respectively;

[0179] Multiple bit lines 18 are formed above the bit line plugs 17, and the multiple bit lines 18 are arranged at intervals along the second direction D2. Each bit line 18 extends along the first direction D1 and is electrically connected to the multiple bit line plugs 17 arranged at intervals along the first direction D1.

[0180] The semiconductor structure and its formation method provided in some embodiments of this specific implementation place the transistor structure on top of the capacitor structure and the bit line structure on top of the transistor structure to form a semiconductor structure with a TOC structure. This eliminates the need for deep-hole etching to form the bit line structure below the transistor structure, thereby reducing the manufacturing difficulty of the bit line and lowering the manufacturing cost of the semiconductor structure. Furthermore, since the bit line structure is located above the transistor structure, various materials (such as metals) can be used to manufacture the bit line, which helps reduce bit line resistance, improves the performance of the semiconductor structure, and enables better compatibility with subsequent peripheral circuit processes.

[0181] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A capacitor structure, located on the top surface of the substrate, includes a plurality of capacitors arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects the second direction. A transistor structure, located above the capacitor structure, includes multiple active pillars and multiple word lines. The active pillars are electrically connected to the capacitor, and the word lines extend along the second direction and continuously cover the active pillars spaced apart along the second direction. The bit line structure is located above the transistor structure and includes multiple bit lines. The bit lines extend along the first direction and are electrically connected to the active pillars that are spaced apart along the first direction. Each of the active pillars includes a channel region and a drain region and a source region distributed on opposite sides of the channel region along a direction perpendicular to the top surface of the substrate. Along both the first and second directions, the width of the source region is greater than the width of the channel region, and the width of the drain region is greater than the width of the channel region.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A substrate isolation layer is located between the substrate and the capacitor structure.

3. The semiconductor structure according to claim 2, characterized in that, The capacitor includes: The lower electrode includes a conductive post and a conductive layer covering the surface of the conductive post, wherein the top surface of the conductive post is in contact with the active post for electrical connection. A dielectric layer covering the surface of the conductive layer; The upper electrode covers the surface of the dielectric layer.

4. The semiconductor structure according to claim 3, characterized in that, The substrate isolation layer includes: The first sub-substrate isolation layer is continuously distributed below the plurality of conductive pillars; The second sub-substrate isolation layer covers the surface of the first sub-substrate isolation layer.

5. The semiconductor structure according to claim 3, characterized in that, The dielectric layer is made of one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer and the upper electrode are made of one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

6. The semiconductor structure according to claim 3, characterized in that, The conductive pillar is made of a silicide material containing a first doped ion.

7. The semiconductor structure according to claim 3, characterized in that, The plurality of word lines are arranged at intervals along the first direction; the transistor structure further includes: A word line isolation layer is located between adjacent word lines.

8. The semiconductor structure according to claim 1, characterized in that, The transistor structure also includes: A protective layer is located between the word line isolation layer and the active post, and covers the sidewall of the source region. Along the first direction, the edge of the protective layer is flush with the edge of the word line.

9. The semiconductor structure according to claim 1, characterized in that, The transistor structure further includes a source electrode located on the top surface of the active pillar; the bit line structure further includes: Bit line plug, the bottom surface of which is in contact with the source electrode, and the top surface of which is electrically connected to the bit line.

10. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide initial substrate; A substrate and a capacitor structure located on the top surface of the substrate are formed in the initial substrate. The capacitor structure includes a plurality of capacitors arranged in an array along a first direction and a second direction. The first direction and the second direction are both parallel to the top surface of the substrate, and the first direction and the second direction intersect. A transistor structure is formed in the initial substrate above the capacitor structure. The transistor structure includes a plurality of active pillars and a plurality of word lines. The active pillars are electrically connected to the capacitor. The word lines extend along the second direction and continuously cover the active pillars that are spaced apart along the second direction. A bit line structure is formed above the transistor structure. The bit line structure includes multiple bit lines, which extend along the first direction and are electrically connected to the active pillars that are spaced apart along the first direction. Each of the active pillars includes a channel region and a drain region and a source region distributed on opposite sides of the channel region along a direction perpendicular to the top surface of the substrate. Along both the first and second directions, the width of the source region is greater than the width of the channel region, and the width of the drain region is greater than the width of the channel region.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The specific steps for forming the substrate and the capacitor structure located on the top surface of the substrate in the initial substrate include: The initial substrate is etched to form a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etch holes located between adjacent semiconductor pillars, and a plurality of grooves that communicate with each of the plurality of etch holes and are located below the etch holes. A substrate isolation layer is formed to connect adjacent grooves and fill the grooves, and the initial substrate remaining below the substrate isolation layer serves as the substrate; A capacitor is formed within the etched hole.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The specific steps for forming a plurality of semiconductor pillars arranged in an array along the first direction and the second direction, etched holes located between adjacent semiconductor pillars, and a plurality of grooves communicating with each of the plurality of etched holes and located below the etched holes include: The initial substrate is etched to form a plurality of first etch trenches, each of the first etch trenches extending along the first direction, and the plurality of first etch trenches are spaced apart along the second direction; The initial substrate is etched to form a plurality of second etch trenches, each of the second etch trenches extending along the second direction, and the plurality of second etch trenches are spaced apart along the first direction; The initial substrate at the bottom of the second etching trench is etched to form a groove with a width greater than that of the second etching trench in a first direction; The first etching trench and the second etching trench are connected to form a plurality of etching holes and semiconductor pillars located between adjacent etching holes.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The specific steps for forming the groove with a width greater than that of the second etching groove include: The initial substrate at the bottom of the second etching trench is etched using Bosch etching technology to form the groove.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, The specific steps of forming the substrate and the capacitor structure located on the top surface of the substrate in the initial substrate further include: A sacrificial layer is formed to fill the etched holes and the grooves; The sacrificial layer is etched back from the top surface of the initial substrate to expose the upper part of the semiconductor pillar; A support layer is formed on the top surface of the sacrificial layer to cover the exposed semiconductor pillars.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, After forming a support layer covering the exposed semiconductor pillar on the top surface of the sacrificial layer, the following steps are further included: Remove the sacrificial layer; Oxidize the semiconductor pillars between adjacent grooves to form a first sub-substrate isolation layer; An insulating material is filled into the groove to form a second sub-substrate isolation layer, and the first sub-substrate isolation layer and the second sub-substrate isolation layer together serve as the substrate isolation layer.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, The etched hole located between the substrate isolation layer and the support layer serves as a capacitor hole, and the initial substrate material is silicon. The specific steps for forming a capacitor within the etched hole include: A first doped ion is injected into the semiconductor pillar between adjacent capacitor holes to form an initial conductive pillar; Deposit metallic material onto the initial conductive pillar to form a conductive pillar comprising a silicide; A conductive layer covering the sidewall of the conductive pillar, a dielectric layer covering the sidewall of the conductive layer, and an upper electrode covering the surface of the dielectric layer are formed sequentially.

17. The method for forming a semiconductor structure according to claim 16, characterized in that, The specific steps for forming a conductive layer covering the sidewalls of the conductive pillar include: The conductive layer, which covers only the sidewalls of the conductive pillar, is formed directly using a selective atomic layer deposition process.

18. The method for forming a semiconductor structure according to claim 16, characterized in that, The dielectric layer is made of one or more of strontium titanate, aluminum oxide, zirconium oxide, and hafnium oxide, and the conductive layer and the upper electrode are made of one or more of titanium, ruthenium, ruthenium oxide, and titanium nitride.

19. The method for forming a semiconductor structure according to claim 16, characterized in that, The specific steps for forming a transistor structure located above the capacitor structure in the initial substrate include: Remove the support layer to expose the upper part of the etched hole and the upper part of the semiconductor pillar. Use the exposed semiconductor pillar as an active pillar and define a channel region, a drain region located below the channel region and in contact with the conductive pillar, and a source region located above the channel region in the active pillar. Reduce the width of the channel region along the first direction and the second direction; The word lines are formed to extend along the second direction and continuously cover the plurality of channel areas spaced apart along the second direction.

20. The method for forming a semiconductor structure according to claim 19, characterized in that, The specific steps for reducing the width of the channel region along the first direction and the second direction include: A filling layer is formed to fill the etched holes between adjacent active pillars; The filling layer of the etched portion is then exposed to reveal the source region; A protective layer is formed covering the sidewalls of the source region; The filling layer of the etched portion is re-etched to expose the channel region, and the remaining filling layer on the sidewall of the drain region serves as an initial isolation layer. The exposed sidewalls of the channel region are modified to form a modified layer; Remove the modified layer and reduce the width of the channel region along the first and second directions.

21. The method for forming a semiconductor structure according to claim 20, characterized in that, The modification treatment is a thermal oxidation treatment, and the modified layer is an oxide layer.

22. The method for forming a semiconductor structure according to claim 19, characterized in that, After forming the word lines that extend along the second direction and continuously cover the plurality of channel regions spaced apart along the second direction, the method further includes: A second doped ion is implanted into the source region, the channel region, and the drain region, wherein the second doped ion is of the same ion type as the first doped ion.

23. The method for forming a semiconductor structure according to claim 22, characterized in that, After implanting a second doped ion into the source region, the channel region, and the drain region, the following steps are further included: A metallic material is deposited on the surface of the source region to form a source electrode comprising a silicide.

24. The method for forming a semiconductor structure according to claim 23, characterized in that, The specific steps for forming a bit line structure above the transistor structure include: Multiple bit line plugs are formed, each located on the top surface of one of the multiple source electrodes; Multiple bit lines are formed above the bit line plugs, and the multiple bit lines are spaced apart along the second direction. Each bit line extends along the first direction and is electrically connected to the multiple bit line plugs spaced apart along the first direction.

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