Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and its manufacturing method in the field of semiconductor technology. The semiconductor structure includes: bit lines, a transistor structure, and a capacitor structure arranged sequentially along a first direction. The capacitor structure extends along the first direction, and both the transistor structure and the capacitor structure include a semiconductor layer extending along the first direction. The semiconductor layer includes a capacitor region directly opposite the capacitor structure. The capacitor structure includes at least: a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer sequentially surrounding a sidewall extending along the first direction of the capacitor region. At least a portion of the lower electrode layer surrounds both the sidewall extending along the first direction of the capacitor region and the bottom and sidewall extending along the first direction of the upper electrode layer. The capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer. This disclosure provides an advantage in increasing the capacitance of the capacitor structure while simultaneously increasing the integration density of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] However, with the increasing demand for capacitor structures with large capacitance, it is difficult to control the size of the capacitor structure, making it difficult to achieve a balance between the layout space occupied by the capacitor structure in the dynamic memory and the capacitance of the capacitor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to increase the capacitance of the capacitor structure while increasing the integration density of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: bit lines, a transistor structure, and a capacitor structure arranged sequentially along a first direction, wherein the capacitor structure extends along the first direction, and both the transistor structure and the capacitor structure include a semiconductor layer extending along the first direction; wherein the semiconductor layer includes a capacitor region opposite to the capacitor structure, and the capacitor structure includes at least: a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer sequentially surrounding a sidewall of the capacitor region extending along the first direction, wherein at least a portion of the lower electrode layer surrounds the sidewall of the capacitor region extending along the first direction, as well as the bottom of the upper electrode layer and the sidewall extending along the first direction, and the capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer.

[0006] In some embodiments, the lower electrode layer itself forms a first annular groove, and the direction from the bottom of the first annular groove to the groove opening is the first direction; the capacitor dielectric layer covers the bottom and sidewalls of the first annular groove, and the capacitor dielectric layer itself forms a second annular groove, and the direction from the bottom of the second annular groove to the groove opening is the first direction; the upper electrode layer fills the second annular groove.

[0007] In some embodiments, on a cross section perpendicular to the first direction, the cross-sectional shape of the first annular groove and the cross-sectional shape of the second annular groove include a circular or square shape.

[0008] In some embodiments, along the first direction, the capacitor region has an end face away from the transistor structure, the capacitor dielectric layer covers the end face, and the upper electrode layer covers the side of the capacitor dielectric layer away from the end face.

[0009] In some embodiments, the upper electrode layer includes a diffusion barrier layer and an electrical connection layer stacked sequentially, the diffusion barrier layer covering the surface of the capacitor dielectric layer away from the lower electrode layer, and the electrical connection layer covering the surface of the diffusion barrier layer away from the capacitor dielectric layer.

[0010] In some embodiments, the transistor structure includes a plurality of sub-transistor structures spaced apart along a third direction, the capacitor structure includes a plurality of sub-capacitor structures spaced apart along the third direction, the semiconductor layer includes a plurality of sub-semiconductor layers spaced apart along the third direction, and the sub-transistor structures correspond one-to-one with the sub-capacitor structures; along the first direction, the sub-semiconductor layer includes a first region and a sub-capacitor region, the end face of the first region away from the sub-capacitor region is in contact with the bit line; the sub-transistor structure includes the first region and a gate structure, the gate structure surrounding a sidewall of a portion of the first region extending along the first direction; the sub-capacitor structure includes the sub-capacitor region and a lower electrode layer, a portion of a capacitor dielectric layer and a portion of an upper electrode layer stacked sequentially, the lower electrode layer surrounding the sidewall of the sub-capacitor region extending along the first direction, and the lower electrode layer and the sub-capacitor region correspond one-to-one.

[0011] In some embodiments, the length of the lower electrode layer in the first direction is less than or equal to the length of the sub-capacitor region in the first direction.

[0012] In some embodiments, multiple sub-capacitor structures arranged at intervals along the third direction in the same capacitor structure share the capacitor dielectric layer.

[0013] In some embodiments, multiple sub-capacitor structures arranged at intervals along the third direction in the same capacitor structure share the upper electrode layer.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, including: forming bit lines, a transistor structure, and a capacitor structure arranged sequentially along a first direction, wherein the capacitor structure extends along the first direction, and both the transistor structure and the capacitor structure include a semiconductor layer extending along the first direction; wherein the semiconductor layer includes a capacitor region opposite to the capacitor structure, and the capacitor structure includes at least: a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer sequentially surrounding a sidewall of the capacitor region extending along the first direction, wherein at least a portion of the lower electrode layer surrounds the sidewall of the capacitor region extending along the first direction, as well as the bottom of the upper electrode layer and the sidewall extending along the first direction, and the capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer.

[0015] In some embodiments, the step of forming the bit lines and the transistor structures includes: forming a plurality of spaced bit lines and a plurality of spaced transistor structures along a second direction, wherein the bit lines correspond one-to-one with the transistor structures, and each of the plurality of transistor structures includes a partial gate structure, wherein the gate structure extends along the second direction, and the first direction and the second direction intersect.

[0016] In some embodiments, the step of forming the bit line and the transistor structure further includes: forming a plurality of spaced sub-transistor structures and a plurality of spaced sub-semiconductor layers along a third direction, wherein at least a portion of the sub-transistor structures arranged along the third direction constitute the transistor structure, and at least a portion of the sub-semiconductor layers arranged along the third direction constitute the semiconductor layers.

[0017] In some embodiments, along the first direction, the sub-semiconductor layer includes a first region and a sub-capacitor region, the first region being directly opposite the sub-transistor structure; the step of forming the sub-capacitor structure includes: forming a first dielectric layer, the first dielectric layer being located between adjacent sub-capacitor regions, and having a third annular groove between the first dielectric layer and the sub-capacitor regions, the direction from the bottom of the third annular groove to the groove opening being the first direction, the third annular groove corresponding to each sub-capacitor region; forming a lower electrode layer, the lower electrode layer covering the bottom and sidewalls of the third annular groove, and the lower electrode layer itself forming a first annular groove, the direction from the bottom of the first annular groove to the groove opening being the first direction, and the lower electrode layer corresponding to each sub-capacitor region; forming a capacitor dielectric layer, the capacitor dielectric layer at least covering the bottom and sidewalls of the first annular groove, and the capacitor dielectric layer itself forming a second annular groove, the direction from the bottom of the second annular groove to the groove opening being the first direction; forming an upper electrode layer, the upper electrode layer at least filling the second annular groove; wherein, the sub-capacitor region, the lower electrode layer, a portion of the capacitor dielectric layer, and a portion of the upper electrode layer constitute the sub-capacitor structure.

[0018] In some embodiments, the cross-sectional shape of the third annular groove along a cross-section perpendicular to the first direction includes a circular or square shape.

[0019] In some embodiments, the step of forming the lower electrode layer includes: forming an initial lower electrode layer, the initial lower electrode layer conformally covering the surface of the first dielectric layer and the sub-capacitor region exposed by the third annular groove; etching the initial lower electrode layer to remove the initial lower electrode layer located on the end face of the sub-capacitor region away from the first region, leaving the remaining initial lower electrode layer as the lower electrode layer.

[0020] In some embodiments, the step of forming the first dielectric layer and the third annular groove includes: forming a second dielectric layer located on a sidewall of the sub-capacitor region extending along the first direction, and having a gap between adjacent second dielectric layers; forming a first dielectric layer located in the gap, and exposing a portion of the second dielectric layer; and removing the second dielectric layer using the first dielectric layer as a mask to form the third annular groove.

[0021] In some embodiments, the step of forming the first dielectric layer further includes: forming an initial first dielectric layer, the initial first dielectric layer filling the gap and covering the end face of the second dielectric layer away from the first region; etching the initial first dielectric layer to at least expose the end face of the second dielectric layer away from the first region, with the remaining initial first dielectric layer serving as the first dielectric layer.

[0022] The technical solutions provided in this disclosure have at least the following advantages:

[0023] In the capacitor structure, at least part of the lower electrode layer surrounds the sidewalls of the capacitor region extending in the first direction, and also surrounds the bottom and sidewalls of the upper electrode layer extending in the first direction. Furthermore, the lower electrode layer, the capacitor dielectric layer, and the upper electrode layer sequentially surround the sidewalls of the capacitor region extending in the first direction. It is understood that the upper electrode layer surrounds the sidewalls of the capacitor region extending in the first direction, meaning that the capacitor region has upper electrode layers on both sides in the direction perpendicular to the first direction. Based on this, the lower electrode layer surrounds the sidewalls and bottom of the upper electrode layer, resulting in the upper electrode layer having lower electrode layers on both sides perpendicular to the first direction. That is, each side of the capacitor region in the direction perpendicular to the first direction has two lower electrode layers extending in the first direction, and these two lower electrode layers are in contact with each other. This is beneficial for increasing the facing area between the upper and lower electrode layers while reducing the layout length of the lower electrode layer in the first direction, thereby increasing the capacitance of the capacitor structure.

[0024] It is understood that the placement space of the capacitor structure in the semiconductor structure mainly depends on the length of the lower electrode layer in the first direction. Under the condition of the same capacitance, reducing the length of the lower electrode layer in the first direction is beneficial to reducing the placement length of the capacitor structure in the first direction, thereby enabling the integration of more capacitor structures in a unit area of ​​the semiconductor structure, thus improving the integration density of the semiconductor structure. Therefore, the semiconductor structure provided by the embodiments of this disclosure is beneficial to improving the capacitance of the capacitor structure while increasing the integration density of the semiconductor structure. Attached Figure Description

[0025] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a partial three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figure 2 for Figure 1 The diagram shows a partial cross-sectional view of the semiconductor structure along the first cross-sectional direction AA1.

[0028] Figure 3 for Figure 1 The semiconductor structure shown is a partial cross-sectional schematic diagram along the second section direction BB1;

[0029] Figure 4 for Figure 1 The diagram shows a partial cross-sectional view of the semiconductor structure along the third section direction CC1.

[0030] Figure 5 for Figure 3 A partial cross-sectional view of the lower electrode layer and semiconductor layer, the lower electrode layer, the capacitor dielectric layer and semiconductor layer in the semiconductor structure;

[0031] Figures 6 to 14 This is a partial cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0032] As can be seen from the background technology, while improving the capacitance of capacitor structures, the integration density of semiconductor structures needs to be improved.

[0033] This disclosure provides a semiconductor structure and its manufacturing method. In the semiconductor structure, a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer sequentially surround a sidewall extending along a first direction of a capacitor region. At least a portion of the lower electrode layer surrounds both the sidewall extending along the first direction of the capacitor region and the bottom and sidewall extending along the first direction of the upper electrode layer. It is understood that the upper electrode layer surrounds the sidewall extending along the first direction of the capacitor region, meaning that the capacitor region has upper electrode layers on both sides in a direction perpendicular to the first direction. Furthermore, the lower electrode layer surrounds the sidewall and bottom of the upper electrode layer, resulting in lower electrode layers on both sides perpendicular to the first direction of the upper electrode layer. This means that either side of the capacitor region in a direction perpendicular to the first direction has two lower electrode layers extending along the first direction, and these two lower electrode layers are in contact with each other. This facilitates reducing the layout length of the lower electrode layer in the first direction while increasing the facing area between the upper and lower electrode layers, thereby increasing the capacitance of the capacitor structure. It is understood that the placement space of the capacitor structure in the semiconductor structure mainly depends on the length of the lower electrode layer in the first direction. Under the condition of the same capacitance, reducing the length of the lower electrode layer in the first direction is beneficial to reducing the placement length of the capacitor structure in the first direction, thereby enabling the integration of more capacitor structures in a unit area of ​​the semiconductor structure, thus improving the integration density of the semiconductor structure. Therefore, the semiconductor structure provided by the embodiments of this disclosure is beneficial to improving the capacitance of the capacitor structure while increasing the integration density of the semiconductor structure.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] This disclosure provides a method for manufacturing a semiconductor structure according to an embodiment. The method for manufacturing a semiconductor structure according to an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 This is a partial three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 for Figure 1 The diagram shows a partial cross-sectional view of the semiconductor structure along the first cross-sectional direction AA1.

[0036] Figure 3 for Figure 1 The semiconductor structure shown is a partial cross-sectional schematic diagram along the second section direction BB1; Figure 4 for Figure 1 The diagram shows a partial cross-sectional view of the semiconductor structure along the third section direction CC1. Figure 5 for Figure 3 A partial cross-sectional view of the lower electrode layer and semiconductor layer, the lower electrode layer, the capacitor dielectric layer, and the semiconductor layer in the semiconductor structure.

[0037] refer to Figures 1 to 4 The semiconductor structure includes: bit lines 100, transistor structure 101, and capacitor structure 102 arranged sequentially along a first direction X. The capacitor structure 102 extends along the first direction X, and both the transistor structure 101 and the capacitor structure 102 include a portion of a semiconductor layer 103, which extends along the first direction X. The semiconductor layer 103 includes a capacitor region 113 opposite to the capacitor structure 102. The capacitor structure 102 includes at least: a lower electrode layer 112, a capacitor dielectric layer 122, and an upper electrode layer 132 that sequentially surround the sidewalls of the capacitor region 113 extending along the first direction X. At least a portion of the lower electrode layer 112 surrounds the sidewalls of the capacitor region 113 extending along the first direction X, as well as the bottom of the upper electrode layer 132 and the sidewalls extending along the first direction X. The capacitor dielectric layer 122 is located between the upper electrode layer 132 and the lower electrode layer 112.

[0038] It is understood that the upper electrode layer 132 surrounds the sidewall of the capacitor region 113 extending along the first direction X, that is, the capacitor region 113 has an upper electrode layer 132 on both sides in the direction perpendicular to the first direction X. On this basis, the lower electrode layer 112 surrounds the sidewall and bottom of the upper electrode layer 132, so that the upper electrode layer 132 has a lower electrode layer 112 on both sides in the direction perpendicular to the first direction X. That is, there are two lower electrode layers 112 extending along the first direction X on either side of the capacitor region 113 in the direction perpendicular to the first direction X, and the two lower electrode layers 112 are in contact with each other. In this way, it is beneficial to increase the facing area between the upper electrode layer 132 and the lower electrode layer 112 while reducing the layout length of the lower electrode layer 112 in the first direction X, thereby increasing the capacitance of the capacitor structure 102.

[0039] In one example, refer to Figure 2 and Figure 3 Along any direction perpendicular to the first direction X, the capacitor structure 102 surrounding the sidewall of the capacitor region 113 extending along the first direction X may sequentially include: a lower electrode layer 112 extending along the first direction X, a capacitor dielectric layer 122 extending along the first direction X, an upper electrode layer 132, another portion of the capacitor dielectric layer 122 extending along the first direction X, and another portion of the lower electrode layer 112 extending along the first direction X.

[0040] It is understood that the upper electrode layer 132 has an inner side facing the capacitor region 113 and an outer side away from the capacitor region 113. Both the inner and outer sides are covered with a capacitor dielectric layer 122. Along the first direction X, the upper electrode layer 132 has a first end face close to the transistor structure 101. This first end face is also covered with a capacitor dielectric layer 122. The capacitor dielectric layer 122 located on this first end face connects the capacitor dielectric layers 122 located on the inner and outer sides together. The capacitor dielectric layer 122 and the capacitor region A lower electrode layer 112 is spaced apart from the upper electrode layer 132 in the capacitor dielectric layer 122. The lower electrode layer 112 is also located on the side of the capacitor dielectric layer 122 away from the upper electrode layer 132 and along the first direction X. The capacitor dielectric layer 122 has a second end face close to the transistor structure 101. The lower electrode layer 112 is also covered on the second end face. The lower electrode layer 112 located on the second end face is connected to the capacitor region 113 and the lower electrode layer 112 located on the side of the capacitor dielectric layer 122 away from the upper electrode layer 132. In this way, the inner side, outer side and the first end face of the upper electrode layer 132 are all directly opposite the lower electrode layer 112. That is, multiple sides of the upper electrode layer 132 are directly opposite the lower electrode layer 112, which helps to increase the facing area between the upper electrode layer 132 and the lower electrode layer 112, thereby increasing the capacitance of the capacitor structure 102.

[0041] Furthermore, the layout space of the capacitor structure 102 in the semiconductor structure mainly depends on the length of the lower electrode layer 112 in the first direction X. Compared with the prior art, under the same capacitance condition, the length of the lower electrode layer 112 in the first direction X of the improved capacitor structure 102 in one embodiment of this disclosure is reduced, which is beneficial to reducing the layout length of the capacitor structure 102 in the first direction X, thereby facilitating the integration of more capacitor structures 102 in a semiconductor structure per unit area, so as to improve the integration density of the semiconductor structure.

[0042] Therefore, the semiconductor structure provided in one embodiment of this disclosure is advantageous in increasing the capacitance of the capacitor structure 102 while increasing the integration density of the semiconductor structure.

[0043] Furthermore, the bit line 100, transistor structure 101, and capacitor structure 102 are all arranged along the first direction X, and both transistor structure 101 and capacitor structure 102 include a semiconductor layer 103. It can be understood that the transistor structure 101 and capacitor structure 102 share the semiconductor layer 103, and the semiconductor layer 103 in transistor structure 101 is electrically connected to the semiconductor layer 103 in capacitor structure 102, thereby achieving electrical connection between transistor structure 101 and capacitor structure 102. This facilitates the construction of a new layout among the bit line 100, transistor structure 101, and capacitor structure 102.

[0044] The following combination Figures 2 to 5 The capacitor structure 102 is described in detail.

[0045] In some embodiments, in conjunction with reference Figures 2 to 5 The lower electrode layer 112 forms a first annular groove 114, with the bottom of the first annular groove 114 pointing towards the groove opening in the first direction X. The capacitor dielectric layer 122 covers the bottom and sidewalls of the first annular groove 114, and the capacitor dielectric layer 122 forms a second annular groove 124, with the bottom of the second annular groove 124 pointing towards the groove opening in the first direction X. The upper electrode layer 132 fills the second annular groove 124. This arrangement allows multiple sides of the upper electrode layer 132 to face the lower electrode layer 112, increasing the facing area between the upper electrode layer 132 and the lower electrode layer 112, thereby increasing the capacitance of the capacitor structure 102.

[0046] In some embodiments, in conjunction with reference Figures 2 to 5In a cross-section perpendicular to the first direction X, the cross-sectional shape of the first annular groove 114 and the second annular groove 124 can be square. In other embodiments, the cross-sectional shapes of the first annular groove 114 and the second annular groove 124 can also be annular. In practical applications, there are no restrictions on the cross-sectional shapes of the first annular groove 114 and the second annular groove 124, as long as they are annular grooves to increase the facing area between the upper electrode layer 132 and the lower electrode layer 112.

[0047] In some embodiments, along the first direction X, reference Figure 2 The capacitor region 113 has an end face away from the transistor structure 101, the capacitor dielectric layer 122 also has a shell covering the end face, and the upper electrode layer 132 can also cover the side of the capacitor dielectric layer 122 away from the end face.

[0048] In some embodiments, the upper electrode layer 132 includes a diffusion barrier layer (not shown) and an electrical connection layer (not shown) stacked sequentially. The diffusion barrier layer covers the surface of the capacitor dielectric layer 122 away from the lower electrode layer 112, and the electrical connection layer covers the surface of the diffusion barrier layer away from the capacitor dielectric layer 122. The diffusion barrier layer helps to prevent the diffusion of conductive material in the electrical connection layer into the capacitor dielectric layer 122, thereby ensuring good insulation performance of the capacitor dielectric layer 122 and good conductivity performance of the electrical connection layer.

[0049] In one example, the diffusion barrier layer can be made of titanium nitride, the electrical connection layer and the lower electrode layer 112 can be made of at least one of conductive materials such as titanium nitride, polycrystalline silicon, tungsten or copper, and the capacitor dielectric layer 122 can be made of dielectric materials with high dielectric constants such as strontium titanate, hafnium oxide, chromium oxide or zirconium oxide.

[0050] In some embodiments, a plurality of bit lines 100, a plurality of transistor structures 101, and a plurality of capacitor structures 102 are arranged along the second direction Y, and the bit lines 100 correspond one-to-one with the transistor structures 101, the transistor structures 101 correspond one-to-one with the capacitor structures 102, and the plurality of transistor structures 101 each include a partial gate structure 111, the gate structure 111 extends along the second direction Y, and the first direction X and the second direction Y intersect.

[0051] It is understandable that the gate structure 111 is used to control the transistor structure 101. Since multiple transistor structures 101 include a portion of the gate structure 111, one gate structure 111 can control multiple transistor structures 101 arranged along the second direction Y. This is beneficial to increase the integration density of transistor structures 101, bit lines 100 and capacitor structures 102 in the semiconductor structure while reducing the control complexity of multiple devices in the semiconductor structure.

[0052] It should be noted that, Figures 1 to 4 Taking the semiconductor structure including four bit lines 100 arranged along the second direction Y as an example, in practical applications, there is no limit to the number of bit lines 100 included in the semiconductor structure, as long as the number of bit lines 100 is equal to the number of transistor structures 101.

[0053] In some embodiments, reference Figures 1 to 4 The transistor structure 101 may include a plurality of sub-transistor structures 121 spaced apart along the third direction Z, the capacitor structure 102 includes a plurality of sub-capacitor structures 142 spaced apart along the third direction Z, and the semiconductor layer 103 includes a plurality of sub-semiconductor layers 123 spaced apart along the third direction Z. The sub-transistor structures 121 and the sub-capacitor structures 142 correspond one-to-one, and both the sub-transistor structure 121 and the corresponding sub-capacitor structure 142 include a sub-semiconductor layer 123. Furthermore, the bit line 100 extends along the third direction Z and is electrically connected to the plurality of sub-transistor structures 121 in the same transistor structure 101.

[0054] In this configuration, the first direction X, the second direction Y, and the third direction Z intersect each other pairwise. In one example, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other pairwise.

[0055] It is understood that multiple sub-transistor structures 121 and multiple sub-capacitor structures 142 can be arranged along the third direction Z. A sub-transistor structure 121 can be independently used as a transistor unit, and a sub-capacitor structure 142 can be independently used as a capacitor unit. A transistor unit and a capacitor unit can constitute a memory cell. In this way, it is beneficial to increase the layout density of memory cells in the semiconductor structure by stacking sub-transistor structures 121 and sub-capacitor structures 142 along the third direction Z, thereby increasing the integration density of the semiconductor structure.

[0056] It should be noted that, Figures 2 to 4 Taking the example of a transistor structure 101 with four sub-transistor structures 121 stacked along the third direction Z, in practical applications, there is no limit to the number of sub-transistor structures 121 stacked along the third direction Z in a transistor structure 101. It can be designed according to actual needs, as long as the number of sub-transistor structures 121, sub-capacitor structures 142 and sub-semiconductor layers 123 are consistent.

[0057] In one example, the number of sub-transistor structures 121 stacked along the third direction Z in a transistor structure 101 can be one, then the sub-transistor structure 121 is the transistor structure 101; the number of sub-capacitor structures 142 stacked along the third direction Z in a capacitor structure 102 is one, then the sub-capacitor structure 142 is the capacitor structure 102; and the number of sub-semiconductor layers 123 stacked along the third direction Z in a semiconductor layer 103 is one, then the sub-semiconductor layer 123 is the semiconductor layer 103.

[0058] It should be noted that, Figures 2 to 4 In the topmost sub-capacitor structure 142 along the Z-direction, the lower electrode layer 112, capacitor dielectric layer 122, and upper electrode layer 132 on the top surface of the sub-semiconductor layer 123 can be a single layer. That is, the upper electrode layer 132 on the top surface can be uncovered by the capacitor dielectric layer 122 and the lower electrode layer 112, facilitating subsequent conductive layers to transmit electrical signals to the upper electrode layer 132 or to transmit electrical signals from the upper electrode layer 132 to other electrical devices through the exposed upper electrode layer 132. In practical applications, along the Z-direction, the topmost sub-capacitor structure 142 can also have the lower electrode layer 112, capacitor dielectric layer 122, upper electrode layer 132, capacitor dielectric layer 122, and lower electrode layer 112 stacked sequentially on the top surface of the sub-semiconductor layer 123. Subsequent conductive layers can then transmit electrical signals to the upper electrode layer 132 or to other electrical devices through other exposed areas of the upper electrode layer 132.

[0059] In some embodiments, reference Figures 2 to 4 Along the first direction X, the bit line 100 may include a first side 110 and a second side 120, which are electrically connected to different transistor structures 101. Thus, two transistor structures 101 share a bit line 100, which is beneficial for further increasing the integration density of transistor structures 101, bit lines 100, and capacitor structures 102 in the semiconductor structure, while further reducing the control complexity of multiple devices in the semiconductor structure.

[0060] It should be noted that, Figure 2 Only the transistor structure 101 electrically connected to the second side 120 is shown. In actual applications, the first side 110 can also be electrically connected to another transistor structure 101.

[0061] In some embodiments, continue to refer to Figures 2 to 4Along the first direction X, the sub-semiconductor layer 123 may include a first region 133 and a sub-capacitor region 143, with the end face of the first region 133 away from the sub-capacitor region 143 in contact with the bit line 100; the sub-transistor structure 121 may include a first region 133 and a gate structure 111, with the gate structure 111 surrounding a portion of the sidewall of the first region 133 extending along the first direction X; the sub-capacitor structure 142 includes a sub-capacitor region 143 and a lower electrode layer 112, a portion of the capacitor dielectric layer 122, and a portion of the upper electrode layer 132 stacked sequentially, with the lower electrode layer 112 surrounding the sidewall of the sub-capacitor region 143 extending along the first direction X, and the lower electrode layer 112 and the sub-capacitor region 143 corresponding one-to-one.

[0062] It is understood that capacitor region 113 includes multiple sub-capacitor regions 143 arranged at intervals along the third direction Z.

[0063] In some embodiments, reference Figure 2 and Figure 4 The first region 133 of the transistor structure 101 includes, along the first direction X, a second region contacting the bit line 100, a channel region opposite the gate structure 111, and a third region contacting and connected to the capacitor region 113. The second region can be either the source or drain of the transistor structure 101, and the third region can be either the source or drain. The third region is contacted and connected to the capacitor region 113 to achieve electrical connection between the transistor structure 101 and the capacitor structure 102. Specifically, the third region is contacted and connected to the sub-capacitor region 143 to achieve electrical connection between the sub-transistor structure 121 and the sub-capacitor structure 142.

[0064] It should be noted that the plane perpendicular to the third direction Z is the reference plane. The fact that the gate structure 111 is directly opposite the channel region means that the orthographic projection of the gate structure 111 on the reference plane coincides with the orthographic projection of the channel region on the reference plane.

[0065] In some embodiments, continue to refer to Figure 2 and Figure 4 The gate structure 111 may include a gate dielectric layer 131 and a gate conductive layer 141. The gate dielectric layer 131 surrounds a sidewall extending along a first direction X around the channel region. The gate conductive layer 141 surrounds a sidewall extending along the first direction X away from the channel region and also around the gate dielectric layer 131. The gate conductive layer 141 extends along a second direction Y, such that one gate conductive layer 141 is in contact with the gate dielectric layer 131 in a plurality of sub-transistor structures 121 spaced apart along the second direction Y. It is understood that the material of the gate conductive layer 141 may be at least one of conductive materials such as titanium nitride, tungsten, or silver, and the material of the gate dielectric layer 131 may be at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0066] In some embodiments, the semiconductor structure may further include: a dielectric layer 105, the dielectric layer 105 including a plurality of regions, a portion of the dielectric layer 105 being located between the bit line 100 and the transistor structure 101 to achieve electrical isolation between the bit line 100 and the transistor structure 101; a portion of the dielectric layer 105 being located between the transistor structure 101 and the capacitor structure 102 to achieve electrical isolation between the transistor structure 101 and the capacitor structure 102; a portion of the dielectric layer 105 being located between adjacent sub-transistor structures 121 along the second direction Y and / or along the third direction Z to achieve electrical isolation between adjacent sub-transistor structures 121; and a portion of the dielectric layer 105 being located between adjacent sub-capacitor structures 142 along the second direction Y and / or along the third direction Z to achieve electrical isolation between adjacent sub-capacitor structures 142.

[0067] It should be noted that this disclosure does not limit whether the dielectric layer 105 is a single-layer structure or a multilayer structure. In practical applications, it can be set according to actual needs. In some embodiments, the material of the dielectric layer 105 may include at least one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0068] In some embodiments, reference Figure 2 and Figure 4 The length of the lower electrode layer 112 in the first direction X is less than the length of the sub-capacitor region 143 in the first direction X. In practical applications, the length of the lower electrode layer 112 in the first direction X can also be equal to the length of the sub-capacitor region 143 in the first direction X.

[0069] In some embodiments, reference Figure 2 In the same capacitor structure 102, multiple sub-capacitor structures 142 arranged at intervals along the third direction Z share a common capacitor dielectric layer 122. This simplifies the fabrication process of the capacitor dielectric layer 122.

[0070] In some embodiments, continue to refer to Figure 2 In the same capacitor structure 102, multiple sub-capacitor structures 140 arranged at intervals along the third direction Z share the upper electrode layer 132. This simplifies the fabrication process of the upper electrode layer 132.

[0071] The following describes in detail the specific details of the lower electrode layer 112, the capacitor dielectric layer 122, and the upper electrode layer 132 through three specific embodiments.

[0072] In one example, multiple sub-capacitor structures 142 arranged at intervals along the third direction Z in the same capacitor structure 102 can share only the capacitor dielectric layer 122. The upper electrode layers 132 in different sub-capacitor structures 142 are not in contact with each other, that is, different sub-capacitor structures 142 have different upper electrode layers 132. Specifically, the dielectric layer 105 located between adjacent sub-capacitor structures 142 has a third end face away from the transistor structure 101. The upper electrode layer 132 is not located on the third end face, and the capacitor dielectric layer 122 is located on the end face of the sub-capacitor region 143 away from the first region 133 and on the end face of the dielectric layer 105 away from the transistor structure 101, so as to realize that multiple sub-capacitor structures 142 arranged at intervals along the third direction Z in the same capacitor structure 102 share the capacitor dielectric layer 122 but do not share the upper electrode layer 132.

[0073] In another example, multiple sub-capacitor structures 142 arranged at intervals along the third direction Z in the same capacitor structure 102 can share only the upper electrode layer 132. The capacitor dielectric layers 122 in different sub-capacitor structures 142 do not contact each other, that is, different sub-capacitor structures 142 have different capacitor dielectric layers 122. Specifically, the length of the lower electrode layer 112 in the first direction X is less than the length of the sub-capacitor region 143 in the first direction X, and the length of the lower electrode layer 112 in the first direction X is less than the length of the dielectric layer 105 located between adjacent sub-capacitor structures 142 in the first direction X. The capacitor dielectric layer 122 only covers the sidewalls of the remaining sub-capacitor regions 143 extending along the first direction X and only covers the sidewalls of the remaining dielectric layer 105 extending along the first direction X. It is not located on the end face of the sub-capacitor region 143 away from the first region 133 and not located on the end face of the dielectric layer 105 away from the transistor structure 101. The upper electrode layer 132 covers the end face of the sub-capacitor region 143 away from the first region 133 and the end face of the dielectric layer 105 away from the transistor structure 101, so as to realize that multiple sub-capacitor structures 142 arranged at intervals along the third direction Z in the same capacitor structure 102 share the upper electrode layer 132, but do not share the capacitor dielectric layer 122.

[0074] In yet another example, along the first direction X, refer to Figure 2 The capacitor dielectric layer 122 is located on the end face of the sub-capacitor region 143 away from the first region 133 and the end face of the dielectric layer 105 away from the transistor structure 101. The upper electrode layer 132 covers all surfaces exposed by the capacitor dielectric layer 122, so that multiple sub-capacitor structures 142 arranged at intervals along the third direction Z in the same capacitor structure 102 share the upper electrode layer 132 and the capacitor dielectric layer 122.

[0075] It should be noted that, in practical applications, multiple sub-capacitor structures 142 arranged at intervals along the third direction Z in the same capacitor structure 102 can also share the upper electrode layer 132.

[0076] In summary, the upper electrode layer 132 surrounds the sidewall of the capacitor region 113 extending along the first direction X, meaning that the capacitor region 113 has an upper electrode layer 132 on both sides in the direction perpendicular to the first direction X. Furthermore, the lower electrode layer 112 surrounds the sidewall and bottom of the upper electrode layer 132, resulting in a lower electrode layer 112 on both sides of the upper electrode layer 132 in the direction perpendicular to the first direction X. This means that either side of the capacitor region 113 in the direction perpendicular to the first direction X has two lower electrode layers 112 extending along the first direction X, and these two lower electrode layers 112 are in contact with each other. This arrangement helps to reduce the layout length of the lower electrode layer 112 in the first direction X to increase the integration density of the semiconductor structure while increasing the facing area between the upper electrode layer 132 and the lower electrode layer 112, thereby increasing the capacitance of the capacitor structure 102.

[0077] Another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, used to prepare the semiconductor structure provided in the foregoing embodiments. The following will be combined with... Figures 1 to 14 A method for manufacturing a semiconductor structure according to another embodiment of this disclosure will be described in detail. Figures 6 to 14 This is a partial cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be described again here.

[0078] It should be noted that, Figure 2 for Figure 1 The diagram shows a partial cross-sectional view of the semiconductor structure along the first cross-sectional direction AA1. Figure 3 for Figure 1 The semiconductor structure shown is a partial cross-sectional schematic diagram along the second section direction BB1; Figure 4 for Figure 1 The semiconductor structure shown is a partial cross-sectional view along the third cross-section direction CC1. Subsequently, depending on the description needs, one, two, or three of the following will be provided: a cross-sectional view along the first cross-section direction AA1, a cross-sectional view along the second cross-section direction BB1, or a partial cross-sectional view along the third cross-section direction CC1.

[0079] refer to Figures 6 to 14The method for manufacturing a semiconductor structure includes: forming bit lines 100, a transistor structure 101, and a capacitor structure 102 arranged sequentially along a first direction X. The capacitor structure 102 extends along the first direction X, and both the transistor structure 101 and the capacitor structure 102 include a semiconductor layer 103, which extends along the first direction X. The semiconductor layer 103 includes a capacitor region 113 opposite to the capacitor structure 102. The capacitor structure 102 includes at least a lower electrode layer 112, a capacitor dielectric layer 122, and an upper electrode layer 132 that sequentially surround the sidewalls of the capacitor region 113 extending along the first direction X. At least a portion of the lower electrode layer 112 surrounds the bottom of the upper electrode layer 132 and the sidewalls extending along the first direction X while also surrounding the sidewalls of the capacitor region 113 extending along the first direction X. The capacitor dielectric layer 122 is located between the upper electrode layer 132 and the lower electrode layer 112.

[0080] In some embodiments, reference Figure 6 and Figure 7 The steps of forming bit lines 100 and transistor structures 101 may include: forming a plurality of spaced bit lines 100 and a plurality of spaced transistor structures 101 along the second direction Y, wherein the bit lines 100 and transistor structures 101 correspond one-to-one, and the plurality of transistor structures 101 each include a partial gate structure 111, the gate structure 111 extending along the second direction Y, and the first direction X and the second direction Y intersecting.

[0081] In some embodiments, continue to refer to Figure 6 and Figure 7 The steps of forming bit line 100 and transistor structure 101 may further include: forming a plurality of spaced sub-transistor structures 121 and a plurality of spaced sub-semiconductor layers 123 along the third direction Z, wherein at least a portion of the sub-transistor structures 121 arranged along the third direction Z constitutes transistor structure 101, and at least a portion of the sub-semiconductor layers 123 arranged along the third direction Z constitutes semiconductor layer 103.

[0082] This facilitates the formation of sub-transistor structures 121 and sub-semiconductor layers 123 spaced along the second direction X and / or the third direction Y, further facilitating the subsequent formation of sub-capacitor structures spaced along the second direction X and / or the third direction Y, thereby increasing the integration density of transistor structures 101, bit lines 100, and sub-capacitor structures in the semiconductor structure.

[0083] It should be noted that, in another embodiment of this disclosure, there are no limitations on the specific methods and order of forming the bit line 100, the sub-transistor structure 121, and the sub-semiconductor layer 123. Furthermore, for details regarding the bit line 100, the sub-transistor structure 121, and the sub-semiconductor layer 123, please refer to the foregoing embodiments; further details will not be repeated here.

[0084] In some embodiments, continue to refer to Figure 6 and Figure 7 In the step of forming transistor structure 101, the method may further include forming a third dielectric layer 145, wherein the third dielectric layer 145 is located between adjacent sub-transistor structures 121 along the second direction Y and / or along the third direction Z.

[0085] In some embodiments, reference Figures 6 to 14 Along the first direction X, the sub-semiconductor layer 123 may include a first region 133 and a sub-capacitor region 143, with the first region 133 directly opposite the sub-transistor structure 121; forming the sub-capacitor structure 142 may include the following steps:

[0086] refer to Figures 6 to 11 A first dielectric layer 115 is formed, which is located between adjacent sub-capacitor regions 143. A third annular groove 134 is formed between the first dielectric layer 115 and the sub-capacitor region 143. The bottom of the third annular groove 134 points to the groove opening in the first direction X. The third annular groove 134 corresponds one-to-one with the sub-capacitor region 143. The third annular groove 134 is used to subsequently form a lower electrode layer 112, a capacitor dielectric layer 122, and an upper electrode layer 132 that sequentially surround the sidewalls of the sub-capacitor region 143 extending along the first direction X. It can be understood that, since in the capacitor structure 102 to be formed, at least part of the lower electrode layer 112 surrounds the sidewalls of the capacitor region 113 extending along the first direction X, and also surrounds the bottom of the upper electrode layer 132 and the sidewalls extending along the first direction X, and the capacitor dielectric layer 122 is located between the upper electrode layer 132 and the lower electrode layer 112, then, in the direction perpendicular to the first direction X, the distance between the sidewall of the third annular groove 134 and the sub-capacitor region 143 is greater than or equal to twice the thickness of the subsequently designed lower electrode layer 112, twice the thickness of the capacitor dielectric layer 122, and the sum of the thickness of the upper electrode layer 132.

[0087] In practical applications, the distance between the sidewall of the third annular groove 134 and the sub-capacitor region 143 can be designed based on the thickness of the lower electrode layer 112, the capacitor dielectric layer 122 and the upper electrode layer 132 in the direction perpendicular to the first direction X.

[0088] In some embodiments, reference Figure 11 Along a cross-section perpendicular to the first direction X, the cross-sectional shape of the third annular groove 134 can be square. In other embodiments, the cross-sectional shape of the third annular groove 134 can also be circular. In practical applications, the cross-sectional shape of the third annular groove 134 is not limited, as long as it satisfies the relationship between the distance between the sidewall of the third annular groove 134 and the sub-capacitor region 143 and the thicknesses of the lower electrode layer 112, the capacitor dielectric layer 122, and the upper electrode layer 132.

[0089] In some embodiments, the step of forming the first dielectric layer 115 and the third annular groove 134 may include: referring to Figure 6 and Figure 7 A second dielectric layer 125 is formed, which is located on the sidewall of the sub-capacitor region 143 extending along the first direction X, and there is a spacing 104 between adjacent second dielectric layers 125; Reference Figures 8 to 9 A first dielectric layer 115 is formed, located in the spacer 104, and the first dielectric layer 115 exposes a portion of the second dielectric layer 125; Reference Figures 9 to 11 The second dielectric layer 125 is removed using the first dielectric layer 115 as a mask to form the third annular groove 134.

[0090] Under the same etching conditions, the choice of etching material between the first dielectric layer 115 and the second dielectric layer 125 is relatively large. In one example, the material of the first dielectric layer 115 can be silicon nitride, and the material of the second dielectric layer 125 can be silicon oxide.

[0091] It should be noted that, Figures 8 to 11 In the example, along the third direction Z, the first dielectric layer 115 does not cover the top surface of the second dielectric layer 125 located at the top layer, so that there is no gap 104 on the top surface of the sub-capacitor region 143 located at the top layer. In actual applications, the first dielectric layer 115 can also cover the top surface of the second dielectric layer 125 located at the top layer, so that there is also a gap 104 between the top surface of the sub-capacitor region 143 located at the top layer and the first dielectric layer 115. Subsequently, a portion of a lower electrode layer 112 extending along the first direction X, a portion of a capacitor dielectric layer 122 extending along the first direction X, an upper electrode layer 132, another portion of a capacitor dielectric layer 122 extending along the first direction X, and another portion of a lower electrode layer 112 extending along the first direction X can be formed in the sub-capacitor region 143 along the third direction Z.

[0092] It should be noted that, Figure 9 Taking the first dielectric layer 115 filling most of the area of ​​the spacing 104 as an example, in practical applications, the first dielectric layer 115 can also fill the spacing 104 and expose the second dielectric layer 125. That is, the end face of the first dielectric layer 115 away from the sub-transistor structure 121 is flush with the end face of the second dielectric layer 125 away from the sub-transistor structure 121, so as to expose the end face of the second dielectric layer 125 away from the sub-transistor structure 121.

[0093] In some embodiments, the step of forming the first dielectric layer 115 may further include: referring to... Figure 7 and Figure 8An initial first dielectric layer 135 is formed, which fills the gap 104 and covers the end face of the second dielectric layer 125 away from the first region 133; in conjunction with reference Figure 8 and Figure 9 The initial first dielectric layer 135 is etched to expose at least the end face of the second dielectric layer 125 away from the first region 133, and the remaining initial first dielectric layer 135 serves as the first dielectric layer 115.

[0094] Understandably, because the distance between the bottom surface and the opening of the spacer 104 is relatively large, i.e., the length of the spacer 104 in the first direction X is relatively large, the depth-to-width ratio of the spacer 104 is also relatively large. When forming the first dielectric layer 115 that needs to fill most of the area of ​​the spacer 104, due to the large depth-to-width ratio of the spacer 104, the material used to form the first dielectric layer 115 is likely to cover the end face of the second dielectric layer 125 away from the first region 133 and the end face of the second dielectric layer 125 away from the first region 133. Therefore, forming the initial first dielectric layer 135 that fills the spacer 104 first, and then etching the initial first dielectric layer 135, is beneficial to forming the first dielectric layer 115 that meets the requirements, which is beneficial to the subsequent formation of the third annular groove 134 based on the first dielectric layer 115 and the second dielectric layer 125.

[0095] refer to Figures 12 to 14 A lower electrode layer 112 is formed, which covers the bottom and sidewalls of the third annular groove 134. The lower electrode layer 112 itself forms a first annular groove 114. The bottom of the first annular groove 114 points to the groove opening in the first direction X. The lower electrode layer 112 corresponds one-to-one with the sub-capacitor region 143.

[0096] It should be noted that, Figures 8 to 14 In the example, along the third direction Z, the first dielectric layer 115 does not cover the top surface of the second dielectric layer 125 located at the top layer, so that there is no gap 104 on the top surface of the sub-capacitor region 143 located at the top layer. In actual applications, the first dielectric layer 115 can also cover the top surface of the second dielectric layer 125 located at the top layer, so that there is also a gap 104 between the top surface of the sub-capacitor region 143 located at the top layer and the first dielectric layer 115. Subsequently, a portion of a lower electrode layer 112 extending along the first direction X, a portion of a capacitor dielectric layer 122 extending along the first direction X, an upper electrode layer 132, another portion of a capacitor dielectric layer 122 extending along the first direction X, and another portion of a lower electrode layer 112 extending along the first direction X can be formed in the sub-capacitor region 143 along the third direction Z.

[0097] In some embodiments, the step of forming the lower electrode layer 112 may include: referencing Figure 12An initial lower electrode layer 152 is formed, which conformally covers the surface of the first dielectric layer 115 and the sub-capacitor region 143 exposed by the third annular groove 134; in conjunction with reference Figure 12 and Figure 13 The initial lower electrode layer 152 is etched to remove the initial lower electrode layer 152 located on the end face of the sub-capacitor region 143 away from the first region 133, and the remaining initial lower electrode layer 152 serves as the lower electrode layer 112.

[0098] It is understandable that, due to the large distance between the bottom surface and the opening of the third annular groove 134, i.e., the large length of the third annular groove 134 in the first direction X, the depth-to-width ratio of the third annular groove 134 is large. When it is necessary to form a lower electrode layer 112 covering the bottom and sidewalls of the third annular groove 134, due to the large depth-to-width ratio of the third annular groove 134, the material used to form the lower electrode layer 112 can easily cover the end face of the first dielectric layer 115 away from the first region 133 and the end face of the sub-capacitor region 143 away from the first region 133. Therefore, it is beneficial to first form an initial lower electrode layer 152 that conformally covers the exposed surfaces of the first dielectric layer 115 and the sub-capacitor region 143 of the third annular groove 134, and then etch the initial lower electrode layer 152. This facilitates the formation of a lower electrode layer 112 that meets the requirements, thereby facilitating the subsequent formation of the capacitor dielectric layer 122 and the upper electrode layer 132 based on the lower electrode layer 112.

[0099] refer to Figures 2 to 5 A capacitor dielectric layer 122 is formed, which at least covers the bottom and sidewalls of the first annular groove 114, and the capacitor dielectric layer 122 itself forms a second annular groove 124, the bottom of the second annular groove 124 pointing to the groove opening in the first direction X.

[0100] Continue to refer to Figures 2 to 5 An upper electrode layer 132 is formed, which at least fills the second annular groove 124. The sub-capacitor region 143, the lower electrode layer 112, part of the capacitor dielectric layer 122, and part of the upper electrode layer 132 constitute the sub-capacitor structure 142.

[0101] It should be noted that the specific descriptions of the lower electrode layer 112, the capacitor dielectric layer 122, and the upper electrode layer 132 are provided in the foregoing embodiments and will not be repeated here. Furthermore, the first dielectric layer 115 and the third dielectric layer 145 together constitute the dielectric layer 105.

[0102] In summary, in the semiconductor structure formed by the improved manufacturing method according to another embodiment of this disclosure, the upper electrode layer 132 surrounds the sidewall of the capacitor region 113 extending along the first direction X, that is, the upper electrode layer 132 is provided on both sides of the capacitor region 113 in the direction perpendicular to the first direction X. On this basis, the lower electrode layer 112 surrounds the sidewall and bottom of the upper electrode layer 132, so that the upper electrode layer 132 has a lower electrode layer 112 on both sides in the direction perpendicular to the first direction X. That is, there are two lower electrode layers 112 extending along the first direction X on either side of the capacitor region 113 in the direction perpendicular to the first direction X, and the two lower electrode layers 112 are in contact with each other. In this way, it is beneficial to increase the facing area between the upper electrode layer 132 and the lower electrode layer 112 while reducing the layout length of the lower electrode layer 112 in the first direction X to improve the integration density of the semiconductor structure, thereby increasing the capacitance of the capacitor structure 102.

[0103] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A bit line, a transistor structure, and a capacitor structure are arranged sequentially along a first direction. The capacitor structure extends along the first direction, and both the transistor structure and the capacitor structure include a semiconductor layer that extends along the first direction. The semiconductor layer includes a capacitor region directly opposite the capacitor structure. The capacitor structure includes at least a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer that sequentially surround the sidewalls of the capacitor region extending in the first direction. At least a portion of the lower electrode layer surrounds the bottom of the upper electrode layer and the sidewalls extending in the first direction while also surrounding the sidewalls of the capacitor region extending in the first direction. The capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer. The steps of forming the bit line and the transistor structure further include: Along a third direction, a plurality of spaced sub-transistor structures and a plurality of spaced sub-semiconductor layers are formed, wherein at least a portion of the sub-transistor structures arranged along the third direction constitute the transistor structure, and at least a portion of the sub-semiconductor layers arranged along the third direction constitute the semiconductor layer. Along the first direction, the sub-semiconductor layer includes a first region and a sub-capacitor region, the first region being directly opposite the sub-transistor structure; wherein, the sub-capacitor region, the lower electrode layer, a portion of the capacitor dielectric layer, and a portion of the upper electrode layer constitute the sub-capacitor structure; wherein the step of forming the sub-capacitor structure includes: A first dielectric layer is formed, which is located between adjacent sub-capacitor regions, and a third annular groove is formed between the first dielectric layer and the sub-capacitor regions. The direction from the bottom of the third annular groove to the groove opening is the first direction, and the third annular groove corresponds one-to-one with the sub-capacitor regions. A lower electrode layer is formed, which covers the bottom and sidewalls of the third annular groove, and the lower electrode layer itself forms a first annular groove. The direction from the bottom of the first annular groove to the groove opening is the first direction, and the lower electrode layer corresponds one-to-one with the sub-capacitor region. A capacitor dielectric layer is formed, which at least covers the bottom and sidewalls of the first annular groove, and the capacitor dielectric layer itself forms a second annular groove, wherein the direction from the bottom of the second annular groove to the groove opening is the first direction; An upper electrode layer is formed, wherein the upper electrode layer at least fills the second annular groove.

2. The manufacturing method as described in claim 1, characterized in that, The steps of forming the bit line and the transistor structure include: Along the second direction, a plurality of spaced bit lines and a plurality of spaced transistor structures are formed, and the bit lines correspond one-to-one with the transistor structures. Each of the plurality of transistor structures includes a partial gate structure, and the gate structure extends along the second direction. The first direction and the second direction intersect.

3. The manufacturing method as described in claim 1, characterized in that, Along a cross-section perpendicular to the first direction, the cross-sectional shape of the third annular groove includes a circular or square shape.

4. The manufacturing method as described in claim 1, characterized in that, The steps for forming the lower electrode layer include: An initial lower electrode layer is formed, which conformally covers the surface of the first dielectric layer and the sub-capacitor region exposed by the third annular groove; The initial lower electrode layer is etched to remove the initial lower electrode layer located on the end face of the sub-capacitor region away from the first region, and the remaining initial lower electrode layer serves as the lower electrode layer.

5. The manufacturing method as described in claim 1, characterized in that, The steps of forming the first dielectric layer and the third annular groove include: A second dielectric layer is formed, the second dielectric layer being located on the sidewall of the sub-capacitor region extending along the first direction, and there is a gap between adjacent second dielectric layers; A first dielectric layer is formed, the first dielectric layer is located in the interval, and the first dielectric layer exposes a portion of the second dielectric layer; The second dielectric layer is removed using the first dielectric layer as a mask to form the third annular groove.

6. The manufacturing method as described in claim 5, characterized in that, The step of forming the first dielectric layer further includes: An initial first dielectric layer is formed, the initial first dielectric layer fills the gap, and the initial first dielectric layer covers the end face of the second dielectric layer away from the first region; The initial first dielectric layer is etched to expose at least the end face of the second dielectric layer away from the first region, and the remaining initial first dielectric layer serves as the first dielectric layer.

7. A semiconductor structure formed using the manufacturing method of any one of claims 1-6, characterized in that, include: The bit lines, transistor structure and capacitor structure are arranged sequentially along a first direction, the capacitor structure extends along the first direction, and both the transistor structure and the capacitor structure include a semiconductor layer that extends along the first direction. The semiconductor layer includes a capacitor region opposite to the capacitor structure. The capacitor structure includes at least a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer that sequentially surround the sidewalls of the capacitor region extending in the first direction. At least a portion of the lower electrode layer surrounds the bottom of the upper electrode layer and the sidewalls extending in the first direction while also surrounding the sidewalls of the capacitor region extending in the first direction. The capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer.

8. The semiconductor structure as described in claim 7, characterized in that, The lower electrode layer itself forms a first annular groove, and the direction from the bottom of the first annular groove to the groove opening is the first direction; the capacitor dielectric layer covers the bottom and sidewalls of the first annular groove, and the capacitor dielectric layer itself forms a second annular groove, and the direction from the bottom of the second annular groove to the groove opening is the first direction; the upper electrode layer fills the second annular groove.

9. The semiconductor structure as described in claim 8, characterized in that, On a cross-section perpendicular to the first direction, the cross-sectional shape of the first annular groove and the cross-sectional shape of the second annular groove include circular or square.

10. The semiconductor structure as described in claim 7 or 8, characterized in that, Along the first direction, the capacitor region has an end face away from the transistor structure, the capacitor dielectric layer covers the end face, and the upper electrode layer covers the side of the capacitor dielectric layer away from the end face.

11. The semiconductor structure as described in claim 7 or 8, characterized in that, The upper electrode layer includes a diffusion barrier layer and an electrical connection layer stacked sequentially. The diffusion barrier layer covers the surface of the capacitor dielectric layer away from the lower electrode layer, and the electrical connection layer covers the surface of the diffusion barrier layer away from the capacitor dielectric layer.

12. The semiconductor structure as claimed in claim 7, characterized in that, The transistor structure includes a plurality of sub-transistor structures spaced apart along a third direction; the capacitor structure includes a plurality of sub-capacitor structures spaced apart along the third direction; the semiconductor layer includes a plurality of sub-semiconductor layers spaced apart along the third direction upward; and the sub-transistor structures correspond one-to-one with the sub-capacitor structures. Along the first direction, the sub-semiconductor layer includes a first region and a sub-capacitor region, the end face of the first region away from the sub-capacitor region being in contact with the bit line; the sub-transistor structure includes the first region and a gate structure, the gate structure surrounding a sidewall of a portion of the first region extending along the first direction; the sub-capacitor structure includes the sub-capacitor region and a lower electrode layer, a portion of a capacitor dielectric layer, and a portion of an upper electrode layer stacked sequentially, the lower electrode layer surrounding the sidewall of the sub-capacitor region extending along the first direction, the lower electrode layer and the sub-capacitor region corresponding one-to-one.

13. The semiconductor structure as described in claim 11, characterized in that, The length of the lower electrode layer in the first direction is less than or equal to the length of the sub-capacitor region in the first direction.

14. The semiconductor structure as claimed in claim 11, characterized in that, Multiple sub-capacitor structures arranged at intervals along the third direction in the same capacitor structure share the capacitor dielectric layer.

15. The semiconductor structure as described in claim 12 or 13, characterized in that, Multiple sub-capacitor structures arranged at intervals along the third direction in the same capacitor structure share the upper electrode layer.

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