A semiconductor device and a method of forming the same

Abstract

The embodiment of the present disclosure provides a forming method of a semiconductor device, which comprises the following steps: providing a substrate; performing a first etching to form a U-shaped groove in the substrate; forming a U-shaped channel stack structure in the U-shaped groove; performing a second etching on the U-shaped channel stack structure to form a plurality of U-shaped channel blocks arranged at intervals along a first direction, the U-shaped channel blocks extending along a second direction; each of the U-shaped channel blocks comprises a plurality of U-shaped channel layers stacked along a third direction; the first direction, the second direction and the third direction are perpendicular to each other in pairs, and the third direction is a thickness direction of the substrate; forming a word line extending along the first direction and electrically connected with the plurality of U-shaped channel blocks; and forming a capacitor and a bit line contact structure at two ends of each of the U-shaped channel layers, respectively.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a common semiconductor device widely used in various consumer electronics products, such as computers, mobile phones, and digital cameras. As these products increasingly demand higher storage capacity, improving the storage density and integration of DRAM has become a pressing issue. Summary of the Invention

[0003] In view of this, the main objective of this disclosure is to provide a semiconductor device and a method for forming the same.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] This disclosure provides a method for forming a semiconductor device, the method comprising:

[0006] Provide a base;

[0007] Perform the first etching to form a U-shaped trench in the substrate;

[0008] A U-shaped channel stacking structure is formed in the U-shaped groove;

[0009] A second etching is performed on the U-shaped channel stack structure to form a plurality of U-shaped channel blocks spaced apart along a first direction, the U-shaped channel blocks extending along a second direction; each U-shaped channel block includes multiple layers of U-shaped channel stacked along a third direction; the first direction, the second direction and the third direction are mutually perpendicular to each other, the third direction being the thickness direction of the substrate;

[0010] Form word lines that extend along the first direction and are electrically connected to the plurality of said U-shaped channel blocks;

[0011] A capacitor and a bit line contact structure are formed at both ends of each of the U-shaped channel layers.

[0012] In the above scheme, each of the U-shaped channel layers includes a first segment, a second segment, and a third segment connected in sequence; wherein the second segment extends along the second direction, and the first segment and the third segment extend along the third direction.

[0013] In the above scheme, the second segment of the multi-layer U-shaped channel layer is stacked along the third direction, and the first segment and the third segment of the multi-layer U-shaped channel layer are stacked along the second direction.

[0014] In the above scheme, forming a capacitor and a bit line contact structure at both ends of each of the U-shaped channel layers includes:

[0015] Capacitor and bit line contact structures are formed on the first and third segments of each of the U-shaped channel layers, respectively.

[0016] In the above scheme, the word line is electrically connected to each of the U-shaped channel layers of the U-shaped channel block.

[0017] In the above scheme, the word line that extends along the first direction and is electrically connected to the plurality of U-shaped channel blocks includes:

[0018] A gate dielectric layer is formed covering the plurality of U-shaped channel blocks;

[0019] A gate layer is formed that covers the gate dielectric layer;

[0020] A third etching is performed on the gate layer to form word lines that extend along the first direction and are electrically connected to the plurality of U-shaped channel blocks.

[0021] In the above scheme, forming a capacitor and a bit line contact structure at both ends of each of the U-shaped channel layers includes:

[0022] A first stacked structure is formed to cover the plurality of U-shaped channel blocks, the first stacked structure comprising a first isolation layer and a first support layer alternately stacked along the third direction;

[0023] The first stacked structure is etched to form a first through-hole, which exposes the first segment.

[0024] A lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially formed within the first through-hole to form a capacitor, which extends along the third direction.

[0025] In the above scheme, forming a capacitor and a bit line contact structure at both ends of each of the U-shaped channel layers further includes:

[0026] A second structure is formed to cover the first stacked structure, the second structure including a second isolation layer and a second support layer;

[0027] The second structure and the first stacked structure are etched to form a second through-hole, which exposes the third segment.

[0028] A first conductive layer and a second conductive layer are sequentially formed within the second through-hole to form a bit line contact structure.

[0029] In the above scheme, the second structure and the first stacked structure are etched to form a third through hole, which exposes the word line;

[0030] A first conductive layer and a second conductive layer are sequentially formed within the third through hole to form a word line contact structure.

[0031] The method in the above scheme further includes:

[0032] The second structure is etched to form a fourth through hole, the fourth through hole exposing the end of the capacitor away from the substrate;

[0033] A first conductive layer and a second conductive layer are sequentially formed within the fourth through hole to form a capacitive contact structure.

[0034] In the above scheme, the bit line contact structure, the word line contact structure, and the capacitor contact structure all extend along the third direction.

[0035] This disclosure also provides a semiconductor device, including:

[0036] Base;

[0037] A plurality of U-shaped channel blocks are spaced apart along a first direction in the substrate, and the U-shaped channel blocks extend along a second direction; each U-shaped channel block includes multiple layers of U-shaped channel stacked along a third direction; the first direction, the second direction and the third direction are perpendicular to each other, and the third direction is the thickness direction of the substrate;

[0038] Word lines extending along the first direction and electrically connected to the plurality of said U-shaped channel blocks;

[0039] Capacitors and bit line contact structures are located at both ends of each of the U-shaped channel layers.

[0040] In the above scheme, the semiconductor device further includes:

[0041] A word line contact structure that extends along the third direction and is electrically connected to the word line;

[0042] A capacitor contact structure that extends along the third direction and is electrically connected to the capacitor.

[0043] In the above scheme, each of the U-shaped channel layers includes a first segment, a second segment, and a third segment connected in sequence; wherein the second segment extends along the second direction, and the first segment and the third segment extend along the third direction.

[0044] In the above scheme, the second segment of the multi-layer U-shaped channel layer is stacked along the third direction, and the first segment and the third segment of the multi-layer U-shaped channel layer are stacked along the second direction.

[0045] In the above scheme, the word line is electrically connected to each of the U-shaped channel layers of the U-shaped channel block.

[0046] In the above scheme, the bit line contact structure, the word line contact structure, and the capacitor contact structure have different lengths in the third direction.

[0047] In a method for forming a semiconductor device according to embodiments of this disclosure, multiple U-shaped channel blocks are formed in a substrate. Each U-shaped channel block includes multiple U-shaped channel layers stacked along a third direction. This structure can increase the density of channel layers in the semiconductor device under the same process size conditions. In subsequent processes, each channel layer serves as a channel for a memory cell. Word lines electrically connected to the multiple U-shaped channel blocks are then formed, allowing the word lines to simultaneously control multiple memory cells, thus improving the word lines' control capability over the channels as gates. Furthermore, the U-shaped channel layers effectively extend the channel length, reducing quantum tunneling effects within the channel and avoiding leakage current caused by short channel effects. Therefore, the performance of the semiconductor device is effectively improved, enabling higher integration density of memory cells. Attached Figure Description

[0048] Figure 1 A schematic diagram illustrating the implementation flow of a method for forming a semiconductor device according to an embodiment of this disclosure;

[0049] Figure 2 A schematic diagram of the structure of the substrate provided in the embodiments of this disclosure;

[0050] Figure 3 A schematic diagram of the structure of another substrate provided in an embodiment of this disclosure;

[0051] Figures 4A to 4D A schematic diagram of the process for forming a U-shaped trench according to an embodiment of this disclosure;

[0052] Figures 5A to 5C This is a schematic diagram of the process for forming a U-shaped stacked structure provided in an embodiment of the present disclosure;

[0053] Figures 6A to 6H A schematic diagram of the process for forming a U-shaped channel block provided in an embodiment of this disclosure;

[0054] Figure 6I for Figure 6H The cross-sectional view shown is along the tangent AA' direction;

[0055] Figures 7A to 7E This is a schematic diagram of the process for forming word lines provided in an embodiment of the present disclosure;

[0056] Figures 8A to 8H This is a schematic diagram of the process for forming the first through hole provided in an embodiment of the present disclosure;

[0057] Figure 8I for Figure 8H The cross-sectional view shown is along the tangent AA' direction;

[0058] Figures 8J to 8M A schematic diagram of the process for forming a capacitor provided in an embodiment of this disclosure;

[0059] Figures 8N to 8Q A schematic diagram of the process for forming the second through hole, the third through hole, and the fourth through hole provided in an embodiment of this disclosure;

[0060] Figure 8R for Figure 8Q The cross-sectional view shown is along the tangent AA' direction;

[0061] Figures 8S to 8U This is a schematic diagram of the process for forming the bit line contact structure, word line contact structure and capacitor contact structure according to embodiments of this disclosure;

[0062] Figure 8V for Figure 8U The cross-sectional view shown is along the tangent AA' direction;

[0063] Figure 8W for Figure 8U The diagram shows a cross-sectional view along the tangent BB' direction. Detailed Implementation

[0064] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0065] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0066] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0068] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0069] As mentioned in the background section, how to further improve the storage density and integration of DRAM has become an urgent technical problem to be solved.

[0070] Therefore, the following technical solutions are proposed according to the embodiments of this disclosure.

[0071] This disclosure provides a method for forming a semiconductor device. Figure 1 This is a schematic diagram illustrating the implementation flow of a method for forming a semiconductor device according to an embodiment of this disclosure. The method mainly includes the following steps:

[0072] Step S101: Provide a substrate;

[0073] Step S102: Perform the first etching to form a U-shaped trench in the substrate;

[0074] Step S103: Form a U-shaped channel stacking structure in the U-shaped trench;

[0075] Step S104: Perform a second etching on the U-shaped channel stack structure to form a plurality of U-shaped channel blocks spaced apart along a first direction, the U-shaped channel blocks extending along a second direction; each U-shaped channel block includes multiple U-shaped channel layers stacked along a third direction; the first direction, the second direction and the third direction are mutually perpendicular, the third direction being the thickness direction of the substrate;

[0076] Step S105: Form word lines that extend along the first direction and are electrically connected to the plurality of U-shaped channel blocks;

[0077] Step S106: A capacitor and a bit line contact structure are formed at both ends of each of the U-shaped channel layers.

[0078] In this embodiment of the disclosure, reference is made to Figure 2 The substrate 210 includes a substrate, which may be a single-element semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0079] In another specific embodiment, refer to Figure 3 The substrate 310 includes a substrate 312 and a dielectric layer 311 located on the substrate 312. The dielectric layer 311 may be made of one or more of tetraethyl orthosilicate (TEOS), silicon oxide, and phosphorus-doped silicon dioxide (PSG), and may be formed using a chemical vapor deposition (CVD) process. The substrate 310 serves as a process platform for subsequent process fabrication.

[0080] Figures 4A to 8W This is a schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. The following will be combined with... Figure 1 , Figures 4A to 8W The method for manufacturing a semiconductor device provided in the embodiments of this disclosure will be further described in detail.

[0081] Reference Figures 4A to 4D The first etching is performed to form a U-shaped trench in the substrate. For example... Figure 4A A first mask layer 410 is formed on the substrate 310. The material of the first mask layer 410 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The first mask layer 410 can be a single layer or a multilayer stacked structure.

[0082] In some embodiments, the first mask layer 410 includes a silicon nitride layer. In one specific embodiment, the silicon nitride layer can be formed by plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0083] In some embodiments, refer to Figure 4B The process of forming the first opening 411 on the first mask layer 410 includes: firstly forming a photoresist layer (not shown in the figure) on the mask layer; then exposing and developing the photoresist layer to form a patterned photoresist layer with photolithographic openings; and finally, using the patterned photoresist layer as a mask, etching the first mask layer 410 to form the first opening 411 on the first mask layer 410. Here, the positions of the photolithographic openings and the first opening 411 are one-to-one. In one specific embodiment, the etching of the first mask layer 410 can be performed using an anisotropic plasma etching process.

[0084] Reference Figure 4C and Figure 4D The dielectric layer 311 is etched along the first opening 411 to form a U-shaped trench 412 in the dielectric layer 311, and then the first mask layer 410 is removed. The process of forming the U-shaped trench 412 can be performed using either a wet etching process or a dry etching process. In some embodiments, the etching of the dielectric layer 311 can stop at the substrate, i.e., the substrate serves as an etching stop layer.

[0085] Reference Figures 5A to 5C In a U-shaped trench 412, a channel layer 510 and an insulating layer 511 are alternately deposited to form a channel stack structure 520. A conformal deposition process (such as ALD deposition) is used, and the resulting channel stack structure 520 is also U-shaped. The channel layer 510 can be made of polycrystalline silicon, which can be deposited by CVD and then recrystallized by high-temperature annealing to form polycrystalline silicon. This method can improve the carrier conduction performance of the polycrystalline silicon channel layer. In other examples, the channel layer 510 can also be made of germanium silicon. The insulating layer 511 can be made of materials such as silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. It should be noted that when the substrate is used as an etch stop layer to form the U-shaped trench 412 in the dielectric layer 311, the insulating layer 511 can be deposited first in the U-shaped trench 412, followed by the channel layer 510, and so on, to form the U-shaped channel stack structure 520.

[0086] Generally, the more stacked layers a U-shaped channel stack structure has, the greater the storage density of the resulting semiconductor device. In practical applications, the number of channel layers and insulating layers in the U-shaped channel stack structure can be selected as needed, for example, between 2 and 10 layers.

[0087] Next, refer to Figures 6A to 6H A second etching is performed on the U-shaped channel stack structure 520 to form a plurality of U-shaped channel blocks 540 spaced apart along the first direction. For example... Figure 6A and Figure 6B As shown, a second mask layer 610 is formed on the U-shaped channel stack structure 520, and a plurality of second openings 611 are formed on the second mask layer 610, the plurality of second openings 611 being spaced apart along a first direction.

[0088] Reference Figures 6C to 6D As shown, the U-shaped channel stack structure 520 is etched along multiple second openings 611 until the surface of the dielectric layer 311 is exposed, and then the second mask layer 610 is removed. After the above etching operation, the U-shaped channel stack structure 520 is divided into multiple sub-U-shaped channel stack structures 530 arranged at intervals along a first direction, and the sub-U-shaped channel stack structures 530 extend along a second direction. Each sub-U-shaped channel stack structure 530 includes multiple U-shaped channel layers stacked along a third direction. Here, the X direction is the first direction, the Y direction is the second direction, and the Z direction is the third direction.

[0089] Reference Figures 6E to 6G Further etching is performed on the sub-U-shaped channel stack structure to form U-shaped channel blocks. For example... Figure 6E and 6F As shown, a third mask layer 612 is formed to cover the sub-U-shaped channel stack structure 530, and a third opening is formed on the third mask layer 612 to expose the two opposite ends of the sub-U-shaped channel stack structure 530 in the second direction.

[0090] Reference Figure 6G and Figure 6H The exposed ends of the U-shaped channel stack 530 are etched along the third opening of the third mask layer 612 until the ends of the U-shaped channel stack 530 are flush with the dielectric layer 311, so that the channel layer 541 and the insulating layer 542 are exposed on the end surfaces of the U-shaped channel block 540. The third mask layer 612 is removed, forming a plurality of U-shaped channel blocks 540 spaced apart along the first direction, and the U-shaped channel blocks 540 extend along the second direction.

[0091] Figure 6I for Figure 6H The schematic cross-sectional view shown is along the tangent AA' direction, as follows: Figure 6IAs shown, each U-shaped channel block 540 includes alternately stacked U-shaped channel layers 541 and insulating layers 542 along a third direction. In one specific embodiment, each U-shaped channel layer 541 includes a first segment 541-1, a second segment 541-2, and a third segment 541-3 connected in sequence; wherein the second segment 541-2 extends along the second direction, and the first segment 541-1 and the third segment 541-3 extend along the third direction. It should be noted that... Figure 6I The first section 541-1, the second section 541-2, and the third section 541-3 are explained using the uppermost U-shaped channel layer 541 of the U-shaped channel block 540 as an example.

[0092] In this embodiment, Figure 6I The dashed lines shown are only used to distinguish the first segment 541-1, the second segment 541-2, and the third segment 541-3 of the U-shaped channel layer 541. It should be emphasized that these dashed lines do not exist in actual semiconductor devices.

[0093] In this embodiment of the disclosure, the second segment 541-2 of the multi-layer U-shaped channel layer is stacked along the third direction, and the first segment 541-1 and the third segment 541-3 of the multi-layer U-shaped channel layer are stacked along the second direction.

[0094] In this embodiment, the U-shaped channel layer structure can increase the density of channel layers in semiconductor devices under the same process size conditions. In addition, the U-shaped channel layer effectively extends the length of the channel, which can reduce the quantum tunneling effect in the channel and avoid leakage caused by the short channel effect.

[0095] Reference Figures 7A to 7E This forms word lines that extend along the first direction and are electrically connected to the plurality of said U-shaped channel blocks. Specifically, as... Figure 7A As shown, a gate dielectric layer 710 is formed covering multiple U-shaped channel blocks. The material of the gate dielectric layer 710 can be an oxide layer or other dielectric materials with high dielectric constant.

[0096] like Figure 7B As shown, a gate layer 711 is formed covering the gate dielectric layer 710. In some embodiments, the material of the gate layer 711 may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other conductive materials. In a preferred embodiment, the material of the gate layer 711 is tungsten.

[0097] In the embodiments disclosed herein, such as Figures 7C to 7EAs shown, a fourth mask layer 712 is formed on the gate layer 711. A third etching is performed on the gate layer 711 through the fourth mask layer 712 until the surface of the gate dielectric layer 710 is exposed. Then, the fourth mask layer 712 is removed to form word lines 713 extending along the first direction and electrically connected to the plurality of U-shaped channel blocks. Specifically, the third etching can be dry etching, such as plasma etching.

[0098] In this embodiment, the word line 713 is electrically connected to each U-shaped channel layer 541 of the U-shaped channel block 540, so that the word line 713 can simultaneously control multiple U-shaped channel layers 541 of the multiple U-shaped channel blocks 540. In other words, the above method can improve the control capability of the word line as a gate over the channel.

[0099] Next, refer to Figures 8A to 8T Capacitor and bit line contact structures are formed on the first and third segments of each of the U-shaped channel layers, respectively.

[0100] Specifically, such as Figure 8A and 8B As shown, a first isolation layer 810 covering multiple U-shaped channel blocks is formed. The first isolation layer 810 is planarized by a chemical mechanical polishing (CMP) process, exposing the gate dielectric layer 710 at both ends of the U-shaped channel blocks, so that the first isolation layer 810 is flush with the gate dielectric layer 710 at both ends of the U-shaped channel blocks.

[0101] In the embodiments disclosed herein, such as Figures 8C to 8F As shown, a first isolation layer 810 and a first support layer 811 are alternately deposited on a third side to form a first stacked structure 800 covering the plurality of U-shaped channel blocks. The first stacked structure 800 includes alternately stacked first isolation layers 810 and first support layers 811. In a specific example, the material of the first isolation layer 810 may be silicon oxide or TEOS, and the material of the first support layer 811 may be a nitride such as silicon nitride or silicon oxynitride.

[0102] In one specific embodiment, the steps of forming the first stacked structure 800 include: firstly forming a first isolation layer 810 using a CVD process, then forming a first support layer 811 on the surface of the first isolation layer 810 using a CVD process, and subsequently depositing the first isolation layer 810 and the first support layer 811 alternately in sequence. In practical applications, the number of layers of the first isolation layer 810 and the first support layer 811 can be set as needed. In addition, the thickness of the first isolation layer 810 along a third direction is greater than the thickness of the first support layer 811 along a third direction.

[0103] In the embodiments disclosed herein, such as Figure 8G and8H As shown, a fifth mask layer 812 is formed on the first stacked structure 800. The fifth mask layer 812 has a plurality of fourth openings 813. The first stacked structure 800 is etched along the fourth openings 813 to remove the fifth mask layer 812 and form a first via 814. Figure 8I for Figure 8H The schematic cross-sectional view shown is along the tangent AA' direction, as follows: Figure 8I As shown, the first through hole 814 exposes as follows Figure 6I The first segment 541-1 of the multi-channel layer 541 shown.

[0104] In the embodiments disclosed herein, such as Figures 8J to 8M As shown, a lower electrode layer 815 is formed on the inner wall of the first through-hole 814. The lower electrode layer 815 also covers the top surface of the uppermost first support layer 810 in the first stacked structure 800. A capacitor dielectric layer 816 is formed on the surface of the lower electrode layer 815, and an upper electrode layer 817 is formed on the surface of the capacitor dielectric layer 816. The lower electrode layer 815, capacitor dielectric layer 816, and upper electrode layer 817 located on the first support layer 810 are removed using a CMP process to form a capacitor 818, which extends along the third direction.

[0105] Capacitor 818 is located in the first stacked structure 800, wherein the first support layer 811 is used to support capacitor 818, giving capacitor 818 greater robustness to avoid problems such as collapse or tilting. The first isolation layer 810 is used to isolate adjacent capacitors 818 and reduce parasitic capacitance between adjacent capacitors 818. Therefore, the material of the first isolation layer 810 has a low dielectric constant, such as silicon oxide or TEOS.

[0106] In some embodiments, the materials of the lower electrode layer 815 and the upper electrode layer 817 are selected from one or more of titanium, titanium nitride, or tungsten, wherein the material of the upper electrode layer may be the same as or different from the material of the lower electrode layer. In a preferred embodiment, both the material of the lower electrode layer 815 and the material of the upper electrode layer 817 are tungsten.

[0107] In some embodiments, the material of the capacitor dielectric layer 816 is selected from one or more of alumina, silicon nitride, silicon oxide, tantalum oxide, hafnium oxide, and zirconium oxide, or other dielectric materials with high dielectric constants to improve the performance of the capacitor 818. The capacitor dielectric layer 816 can be formed using methods such as CVD, ALD, or metal-organic chemical vapor deposition (MOCVD). In a preferred embodiment, the material of the capacitor dielectric layer 816 is silicon oxide.

[0108] In the embodiments disclosed herein, such as Figure 8N and Figure 8O As shown, a second isolation layer 819 and a second support layer 820 are alternately deposited on a third-party side to form a second structure 830 covering the first stacked structure 810. The second structure 830 includes alternately stacked second isolation layers 819 and second support layers 820. In a specific example, the material of the second isolation layer 819 may be silicon oxide or TEOS, and the material of the second support layer 820 may be a nitride such as silicon nitride or silicon oxynitride.

[0109] In one specific embodiment, the step of forming the second structure 830 includes: first forming a second isolation layer 819 using a CVD process, and then forming a second support layer 820 on the surface of the second isolation layer 819 using a CVD process. It should be noted that the thickness of the second isolation layer 819 along a third direction is greater than the thickness of the second support layer 820 along a third direction.

[0110] In the embodiments disclosed herein, such as Figure 8P As shown, a sixth mask layer 821 is formed covering the second structure 830. The sixth mask layer 821 has a plurality of fifth openings 822, combined with... Figure 6I The position of the fifth opening 822 corresponds to the first segment 541-1, the third segment 541-3, and the letter line 713 of each channel layer of the U-shaped channel block 540.

[0111] In the embodiments disclosed herein, such as Figure 8Q As shown, the second structure 830 and the first stacked structure 800 are etched along the fifth opening 822 to form the second through hole 823. Figure 8R for Figure 8Q The schematic cross-sectional view shown is along the tangent AA' direction, as follows: Figure 8R As shown, the second through-hole 823 exposes the third section 541-3 of the U-shaped channel layer.

[0112] In some embodiments, such as Figure 8Q As shown, etching along the fifth opening 822 can also form a third through hole 824, which exposes the word line 713.

[0113] In other embodiments, such as Figure 8Q and Figure 8R As shown, a fourth through hole 825 is formed in the second structure 830 along the fifth opening 822, and the fourth through hole 825 exposes the end of the capacitor 818 away from the substrate.

[0114] In the embodiments disclosed herein, such as Figures 8S to 8UAs shown, a first conductive layer 826 and a second conductive layer 827 are sequentially formed in the second through hole 823, the third through hole 824 and the fourth through hole 825 to form a bit line contact structure 828, a word line contact structure 829 and a capacitor contact structure 831, respectively.

[0115] Specifically, the material of the first conductive layer 826 includes, but is not limited to, titanium nitride or tantalum nitride.

[0116] After the first conductive layer 826 is formed, a second conductive layer 827 is filled into the second, third, and fourth vias using a deposition process. The material of the second conductive layer 827 includes, but is not limited to, W, Co, Cu, Al, or other conductive materials. In a preferred embodiment, the material of the second conductive layer 827 is W.

[0117] Figure 8V for Figure 8U The schematic cross-sectional view shown is along the tangent AA' direction, as follows: Figure 8V As shown, bit line contact structure 828, word line contact structure 829 (not shown in the figure) and capacitor contact structure 831 all extend along a third direction.

[0118] Figure 8W for Figure 8U The schematic cross-sectional view shown is along the tangent BB' direction, as follows: Figures 8U to 8W As shown, in one specific embodiment, after forming the bit line contact structure 828, a bit line 833 is formed on the side of the bit line contact structure 828 away from the substrate 310, that is, the bit line 833 is electrically connected to the third segment 541-3 of the U-shaped channel layer through the bit line contact structure 828. In one example, the step of forming the bit line 833 includes: forming a seventh mask layer covering the second structure 830, and the seventh mask layer having a plurality of sixth openings, the plurality of sixth openings respectively corresponding to the plurality of bit line contact structures 828; forming contact plugs 832 on the top surface of the plurality of bit line contact structures 828 through the plurality of sixth openings; and forming the bit line 833 above the contact plugs 832. Specifically, the material of the contact plugs 832 is selected from W, Co, Cu, Al or other conductive materials.

[0119] In one specific implementation, such as Figure 8W As shown, bit line 833 extends along a first direction, in which three contact plugs 832 are connected to the same bit line 833. It should be noted that the number of U-shaped channel blocks and the number of U-shaped channel layers included in each U-shaped channel block shown in the figure are merely illustrative examples and are not intended to limit the number of U-shaped channel blocks or the number of U-shaped channel layers included in each U-shaped channel block in the semiconductor device of this application.

[0120] Thus, capacitor 818 and bit line 833 are formed on the first segment 541-1 and the third segment 541-3 of the U-shaped channel layer in the U-shaped channel block, respectively, wherein the first segment includes a drain region and the third segment includes a source region. Word line 713, as the gate, together with the source and drain regions, constitutes a metal-oxide-semiconductor field-effect transistor (MOSFET) of the memory cell. Furthermore, the source region is connected to bit line 833, and the drain region is electrically connected to capacitor 818, which can form a semiconductor device, such as DRAM, or other types of memory.

[0121] Since the word line is electrically connected to each U-channel layer of the U-channel block, the voltage signal on the word line can simultaneously control the opening or closing of multiple memory cells, thereby improving the word line's ability to control the channel as a gate. This allows for the selection of specific memory cells to be charged and discharged via the bit line, i.e., reading data information stored in the capacitor via the bit line, or writing data information into the capacitor via the bit line for storage.

[0122] This disclosure also provides a semiconductor device, see embodiments thereof. Figure 8U and Figure 8V As shown, the semiconductor device includes: a substrate 310; a plurality of U-shaped channel blocks 540 spaced apart along a first direction on the substrate 310, the U-shaped channel blocks 540 extending along a second direction; each of the U-shaped channel blocks 540 includes multiple U-shaped channel layers stacked along a third direction; the first direction, the second direction and the third direction are mutually perpendicular to each other, the third direction being the thickness direction of the substrate; word lines 713 extending along the first direction and electrically connected to the plurality of U-shaped channel blocks 540; and capacitors 818 and bit line contact structures 828 located at both ends of each U-shaped channel layer.

[0123] In this embodiment, the substrate includes a substrate, which may be a single-element semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In one specific embodiment, refer to... Figure 8U As shown, the substrate 310 includes a substrate 312 and a dielectric layer 311 located on the substrate 312. The material of the dielectric layer 311 may include one or more of tetraethyl orthosilicate (TEOS), silicon oxide, and phosphorus-doped silicon dioxide (PSG), and the dielectric layer 311 may be formed using a CVD process.

[0124] In one specific implementation, such as Figure 8V As shown, capacitor 818 includes a lower electrode layer 815, a dielectric layer 816, and an upper electrode layer 817 arranged radially from the outside to the inside. Specifically, the materials of the lower electrode layer 815 and the upper electrode layer 817 are selected from one or more of titanium, titanium nitride, or tungsten, wherein the material of the upper electrode layer may be the same as or different from the material of the lower electrode layer. In a preferred embodiment, both the lower electrode layer 815 and the upper electrode layer 817 are made of tungsten.

[0125] In some embodiments, the material of the capacitor dielectric layer 816 is selected from one or more of alumina, silicon nitride, silicon oxide, tantalum oxide, hafnium oxide, and zirconium oxide, or other dielectric materials with high dielectric constants to improve the performance of the capacitor 818. The capacitor dielectric layer 816 can be formed using methods such as CVD, ALD, or MOCVD. In a preferred embodiment, the material of the capacitor dielectric layer 816 is silicon oxide.

[0126] In the embodiments disclosed herein, such as Figure 8U and Figure 8V As shown, the semiconductor device further includes: a word line contact structure 829 extending along the third direction and electrically connected to the word line 713; and a capacitor contact structure 831 extending along the third direction and electrically connected to the capacitor 818.

[0127] In one specific implementation, see [reference] Figure 8U and Figure 8V It is known that the bit line contact structure 828, word line contact structure 829, and capacitor contact structure 831 have different lengths in the third direction. Each of the bit line contact structure 828, word line contact structure 829, and capacitor contact structure 831 includes a first conductive layer 826 and a second conductive layer 827, wherein the first conductive layer 826 and the second conductive layer 827 are arranged radially from the outside to the inside. Specifically, the material of the first conductive layer 826 includes, but is not limited to, titanium nitride or tantalum nitride. The material of the second conductive layer 827 includes, but is not limited to, W, Co, Cu, Al, or other conductive materials. In a preferred embodiment, the material of the second conductive layer 827 is W.

[0128] In the embodiments disclosed herein, see Figures 8U to 8W It is understood that the semiconductor device further includes a bit line 833 on the side of the bit line contact structure 828 away from the substrate 310, the bit line 833 being connected to the bit line contact structure 828 via contact plugs 832. In one example, the bit line 833 extends along a first direction, in which three contact plugs 832 are connected to the same bit line 833. Specifically, the material of the contact plugs 832 is selected from W, Co, Cu, Al, or other conductive materials.

[0129] In this embodiment of the disclosure, reference is made to Figure 6H and Figure 6I As shown, the U-shaped channel layer 541 includes a first segment 541-1, a second segment 541-2, and a third segment 541-3 connected in sequence; wherein the second segment 541-2 extends along the second direction, and the first segment 541-1 and the third segment 541-3 extend along the third direction. The material of the channel layer 541 may be polycrystalline silicon; in other examples, the material of the channel layer 510 may also include germanium silicon.

[0130] In this embodiment, the second segment 541-2 of the multilayer U-shaped channel layer 541 is stacked along the third direction, and the first segment 541-1 and the third segment 541-3 of the multilayer U-shaped channel layer 541 are stacked along the second direction. The U-shaped channel layer structure can increase the density of channel layers in semiconductor devices under the same process size conditions. In addition, the U-shaped channel layer effectively extends the channel length, which can reduce the quantum tunneling effect in the channel and avoid leakage current caused by short-channel effect.

[0131] In the embodiments disclosed herein, see Figure 7E As can be seen, word line 713 is electrically connected to each U-channel layer of the U-channel block. Therefore, the voltage signal on the word line can simultaneously control the opening or closing of multiple memory cells. In turn, the bit line can be used to select specific memory cells for charging and discharging. That is, the bit line can be used to read data information stored in the capacitor or write data information into the capacitor for storage.

[0132] In a method for forming a semiconductor device according to embodiments of this disclosure, multiple U-shaped channel blocks are formed in a substrate. Each U-shaped channel block includes multiple U-shaped channel layers stacked along a third direction. This structure can increase the density of channel layers in the semiconductor device under the same process size conditions. In subsequent processes, each channel layer serves as a channel for a memory cell. Word lines electrically connected to the multiple U-shaped channel blocks are then formed, allowing the word lines to simultaneously control multiple memory cells, thus improving the word lines' control capability over the channels as gates. Furthermore, the U-shaped channel layers effectively extend the channel length, reducing quantum tunneling effects within the channel and avoiding leakage current caused by short-channel effects. Therefore, the performance of the semiconductor device is effectively improved, enabling higher integration density of memory cells.

[0133] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0134] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: Provide a base; Perform the first etching to form a U-shaped trench in the substrate; A U-shaped channel stacking structure is formed in the U-shaped groove; A second etching is performed on the U-shaped channel stack structure to form a plurality of U-shaped channel blocks spaced apart along a first direction, the U-shaped channel blocks extending along a second direction; each U-shaped channel block includes multiple layers of U-shaped channel stacked along a third direction; the first direction, the second direction and the third direction are mutually perpendicular to each other, the third direction being the thickness direction of the substrate; Form word lines that extend along the first direction and are electrically connected to the plurality of said U-shaped channel blocks; A capacitor and a bit line contact structure are formed at both ends of each of the U-shaped channel layers.

2. The method according to claim 1, characterized in that, Each of the U-shaped channel layers includes a first segment, a second segment, and a third segment connected in sequence; wherein the second segment extends along the second direction, and the first segment and the third segment extend along the third direction.

3. The method according to claim 2, characterized in that, The second segment of the multi-layer U-shaped channel layer is stacked along the third direction, and the first segment and the third segment of the multi-layer U-shaped channel layer are stacked along the second direction.

4. The method according to claim 3, characterized in that, The step of forming a capacitor and a bit line contact structure at both ends of each of the U-shaped channel layers includes: Capacitor and bit line contact structures are formed on the first and third segments of each of the U-shaped channel layers, respectively.

5. The method according to claim 1, characterized in that, The word line is electrically connected to each of the U-shaped channel layers of the U-shaped channel block.

6. The method according to claim 3, characterized in that, The word line formed extending along the first direction and electrically connected to the plurality of U-shaped channel blocks includes: A gate dielectric layer is formed covering multiple U-shaped channel blocks; A gate layer is formed that covers the gate dielectric layer; A third etching is performed on the gate layer to form word lines that extend along the first direction and are electrically connected to the plurality of U-shaped channel blocks.

7. The method according to claim 4, characterized in that, The step of forming a capacitor and a bit line contact structure at both ends of each of the U-shaped channel layers includes: A first stacked structure is formed covering multiple U-shaped channel blocks, the first stacked structure including a first isolation layer and a first support layer alternately stacked along the third direction; The first stacked structure is etched to form a first through-hole, which exposes the first segment. A lower electrode layer, a capacitor dielectric layer, and an upper electrode layer are sequentially formed within the first through-hole to form a capacitor, which extends along the third direction.

8. The method according to claim 7, characterized in that, The method of forming a capacitor and a bit line contact structure at both ends of each of the U-shaped channel layers further includes: A second structure is formed to cover the first stacked structure, the second structure including a second isolation layer and a second support layer; The second structure and the first stacked structure are etched to form a second through-hole, which exposes the third segment. A first conductive layer and a second conductive layer are sequentially formed within the second through-hole to form a bit line contact structure.

9. The method according to claim 8, characterized in that, The method further includes: The second structure and the first stacked structure are etched to form a third via, which exposes the word lines; A first conductive layer and a second conductive layer are sequentially formed within the third through hole to form a word line contact structure.

10. The method according to claim 9, characterized in that, The method further includes: The second structure is etched to form a fourth through hole, the fourth through hole exposing the end of the capacitor away from the substrate; A first conductive layer and a second conductive layer are sequentially formed within the fourth through hole to form a capacitive contact structure.

11. The method according to claim 10, characterized in that, The bit line contact structure, the word line contact structure, and the capacitor contact structure all extend along the third direction.

12. A semiconductor device, characterized in that, include: Base; A plurality of U-shaped channel blocks are spaced apart along a first direction in the substrate, and the U-shaped channel blocks extend along a second direction; each U-shaped channel block includes multiple layers of U-shaped channel stacked along a third direction; the first direction, the second direction and the third direction are perpendicular to each other, and the third direction is the thickness direction of the substrate; Word lines extending along the first direction and electrically connected to the plurality of said U-shaped channel blocks; Capacitors and bit line contact structures are located at both ends of each of the U-shaped channel layers.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: A word line contact structure that extends along the third direction and is electrically connected to the word line; A capacitor contact structure that extends along the third direction and is electrically connected to the capacitor.

14. The semiconductor device according to claim 12, characterized in that, Each of the U-shaped channel layers includes a first segment, a second segment, and a third segment connected in sequence; wherein the second segment extends along the second direction, and the first segment and the third segment extend along the third direction.

15. The semiconductor device according to claim 14, characterized in that, The second segment of the multi-layer U-shaped channel layer is stacked along the third direction, and the first segment and the third segment of the multi-layer U-shaped channel layer are stacked along the second direction.

16. The semiconductor device according to claim 12, characterized in that, The word line is electrically connected to each of the U-shaped channel layers of the U-shaped channel block.

17. The semiconductor device according to claim 13, characterized in that, The bit line contact structure, the word line contact structure, and the capacitor contact structure have different lengths in the third direction.

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