Scanning circuit, display device, and method of operating the scanning circuit

Abstract

A scanning circuit is provided. The scanning circuit includes multiple scanning units at multiple stages. Each scanning unit includes an output sub-circuit. The output sub-circuit includes a first switching transistor and a second switching transistor. The source of the first switching transistor is coupled to a third terminal configured to receive a first clock signal. The drain of the first switching transistor is coupled to a first output terminal configured to output a first control signal. The source of the second switching transistor is coupled to a fourth terminal configured to receive a third clock signal. The drain of the second switching transistor is coupled to a second output terminal configured to output a second control signal. The gates of the first and second switching transistors are coupled to a first node.

Description

Technical Field

[0001] This invention relates to display technology, and more specifically, to scanning circuits, display devices, and methods of operating scanning circuits. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In one aspect, this disclosure provides a scanning circuit including a plurality of scanning units at multiple levels; wherein each scanning unit includes at least one of an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, or an output sub-circuit; each scanning unit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal; wherein the output sub-circuit includes a first output terminal, a second output terminal, a first switching transistor, and a second switching transistor; the source of the first switching transistor is coupled to a third terminal configured to receive the first clock signal; the drain of the first switching transistor is coupled to the first output terminal configured to output a first control signal; the source of the second switching transistor is coupled to a fourth terminal configured to receive the third clock signal; the drain of the second switching transistor is coupled to a second output terminal configured to output a second control signal; and the gates of the first switching transistor and the second switching transistor are coupled to a first node.

[0004] Optionally, the output sub-circuit further includes a tenth transistor and a thirteenth transistor; the source of the tenth transistor and the source of the thirteenth transistor are coupled to a fifth terminal configured to receive the first reference signal; the drain of the tenth transistor is coupled to the first output terminal; the drain of the thirteenth transistor is coupled to the second output terminal; and the gates of the tenth transistor and the thirteenth transistor are coupled to a second node.

[0005] Optionally, the output sub-circuit further includes an eleventh transistor coupled between the tenth transistor and the first switching transistor; the gate of the eleventh transistor is coupled to the first node; and at least one of the source and drain of the eleventh transistor is coupled to the first output terminal.

[0006] Optionally, both the source and the drain of the eleventh transistor are coupled to the first output terminal.

[0007] Optionally, each scanning unit further includes a second capacitor; the first capacitor electrode of the second capacitor is coupled to the source of the tenth transistor; and the second capacitor electrode of the second capacitor is coupled to the second node.

[0008] Optionally, each scanning unit further includes a third capacitor; the first capacitor electrode of the third capacitor is coupled to the first node; and the second capacitor electrode of the third capacitor is coupled to a second terminal configured to receive a second reference signal.

[0009] Optionally, the input sub-circuit includes an input transistor, a first transistor, an input terminal, and a first terminal; the gate of the input transistor and the source of the first transistor are coupled to the first terminal configured to receive the second clock signal; the gate of the first transistor and the drain of the input transistor are coupled to a third node; the source of the input transistor is coupled to the input terminal configured to receive a start signal or an output signal from a previous scan unit of the previous stage; and the drain of the first transistor is coupled to a second node.

[0010] Optionally, the first processing sub-circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor; the sources of the third transistor and the fourth transistor are coupled to the drain of the fifth transistor; the drains of the third transistor and the fourth transistor are coupled to a third node; the gate of the third transistor is coupled to a third terminal configured to receive the first clock signal; and the gate of the fourth transistor is coupled to a fourth terminal configured to receive the third clock signal.

[0011] Optionally, the gate of the fifth transistor and the drain of the second transistor are coupled to the second node; the source of the fifth transistor is coupled to the fifth terminal configured to receive the first reference signal; and the source of the second transistor is coupled to the second terminal configured to receive the second reference signal.

[0012] Optionally, the second processing sub-circuit includes a seventh transistor and an eighth transistor; the gate of the seventh transistor is coupled to a fourth node; the source of the seventh transistor and the gate of the eighth transistor are coupled to a sixth terminal configured to receive the fourth clock signal; the drain of the seventh transistor and the source of the eighth transistor are coupled to a fifth node; and the drain of the eighth transistor is coupled to the first node.

[0013] Optionally, the second processing sub-circuit further includes a sixth transistor and a first capacitor; the gate of the sixth transistor is coupled to a second terminal configured to receive the second reference signal; the source of the sixth transistor is coupled to a third node; the drain of the sixth transistor and the first capacitor electrode of the first capacitor are coupled to the fourth node; and the second capacitor electrode of the first capacitor is coupled to the fifth node.

[0014] Optionally, each scanning unit further includes a third processing sub-circuit; wherein the third processing sub-circuit includes a ninth transistor having a gate coupled to the second node, a source coupled to a sixth terminal configured to receive the fourth clock signal, and a drain coupled to the first node.

[0015] In another aspect, this disclosure provides a display device including a light-emitting substrate and a scanning circuit described herein or manufactured by the methods described herein, the scanning circuit being configured to provide control signals to the light-emitting substrate.

[0016] Optionally, the display device includes a plurality of sub-pixels; wherein each of the plurality of sub-pixels includes: a first light-emitting element; a first pixel driving circuit configured to control the first light-emitting element to emit light; a second light-emitting element; and a second pixel driving circuit configured to control the second light-emitting element to emit light; wherein the first pixel driving circuit is configured to receive a first control signal output from a first output terminal; and the second pixel driving circuit is configured to receive a second control signal output from a second output terminal.

[0017] Optionally, the first light-emitting element and the second light-emitting element are configured to emit light of the same color.

[0018] Optionally, the display device further includes a color filter substrate; wherein the color filter substrate includes: a color conversion layer including a plurality of color conversion blocks; and a color filter including a plurality of color filter blocks.

[0019] In another aspect, this disclosure provides a method for operating a display device, the display device including a light-emitting substrate and a scanning circuit configured to provide control signals to the light-emitting substrate, the method comprising: providing at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal to each of a plurality of scanning units of the scanning circuit; outputting an effective voltage of the first clock signal as a first control signal to the light-emitting substrate; and outputting an effective voltage of the third clock signal as a second control signal to the light-emitting substrate.

[0020] Optionally, outputting the first control signal and outputting the second control signal includes: providing the first clock signal to the source of the first switching transistor; providing the third clock signal to the source of the second switching transistor; and coupling the gates of the first switching transistor and the second switching transistor to the first node.

[0021] Optionally, the first control signal and the second control signal are out of phase with respect to each other; and the light-emitting substrate includes a plurality of sub-pixels, each of the plurality of sub-pixels including at least one main light-emitting element driven by a main pixel driving circuit and at least one auxiliary light-emitting element driven by an auxiliary pixel driving circuit; wherein the method further includes: providing the first control signal to the main pixel driving circuit; providing the second control signal to the auxiliary pixel driving circuit; providing a first data signal to the main pixel driving circuit; and providing a second data signal to the auxiliary pixel driving circuit; wherein the first data signal and the second data signal are provided using a single data line connecting the source integrated circuit and the light-emitting substrate.

[0022] Optionally, the method further includes: adjusting the third clock signal to have a constant invalid voltage level; and outputting the invalid voltage of the third clock signal to the light-emitting substrate.

[0023] Optionally, the light-emitting substrate includes a plurality of sub-pixels, each of the plurality of sub-pixels including at least one main light-emitting element driven by a main pixel driving circuit and at least one auxiliary light-emitting element driven by an auxiliary pixel driving circuit; wherein, the method further includes: providing the first control signal to the main pixel driving circuit; and providing the invalid voltage of the third clock signal to the auxiliary pixel driving circuit.

[0024] Optionally, the first control signal and the second control signal are in phase with respect to each other.

[0025] Optionally, the method includes: providing a control signal to a high-resolution sub-region of the light-emitting substrate; and providing a control signal to a low-resolution sub-region of the light-emitting substrate; wherein providing the control signal to the high-resolution sub-region of the light-emitting substrate includes: using the effective voltage of the first clock signal as the first control signal and outputting it to a first adjacent row sub-pixel in the high-resolution sub-region; and using the effective voltage of the third clock signal as the second control signal and outputting it to a second adjacent row sub-pixel in the high-resolution sub-region; wherein providing the control signal to the low-resolution sub-region of the light-emitting substrate includes: using the effective voltage of the first clock signal as the first control signal and outputting it to a third adjacent row sub-pixel in the low-resolution sub-region; adjusting the third clock signal to have a constant invalid voltage level; and outputting the invalid voltage of the third clock signal to a fourth adjacent row sub-pixel in the low-resolution sub-region. Attached Figure Description

[0026] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0027] Figure 1 This is a schematic diagram illustrating a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0028] Figure 2 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0029] Figure 3 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure.

[0030] Figure 4 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure.

[0031] Figure 5 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure.

[0032] Figure 6 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0033] Figure 7 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure.

[0034] Figure 8 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure.

[0035] Figure 9This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure.

[0036] Figure 10 This is a schematic diagram illustrating a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0037] Figure 11 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0038] Figure 12 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0039] Figure 13 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0040] Figure 14 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure.

[0041] Figure 15 This is a schematic diagram illustrating the structure of a light-emitting substrate according to some embodiments of the present disclosure.

[0042] Figure 16 This is a circuit diagram of a light-emitting substrate according to some embodiments of the present disclosure.

[0043] Figure 17 This is a cross-sectional view of a light-emitting substrate according to some embodiments of the present disclosure.

[0044] Figure 18 This is a cross-sectional view of a light-emitting substrate according to some embodiments of the present disclosure.

[0045] Figure 19A This is a schematic diagram of a light-emitting substrate for image display in a first mode according to some embodiments of the present disclosure.

[0046] Figure 19B This is a schematic diagram of a light-emitting substrate for image display in a second mode according to some embodiments of the present disclosure.

[0047] Figure 20 This is a cross-sectional view of a light-emitting substrate according to some embodiments of the present disclosure.

[0048] Figure 21 This is a circuit diagram illustrating the structure of the main pixel driving circuit, the auxiliary pixel driving circuit, the main light-emitting element, and the auxiliary light-emitting element according to some embodiments of the present disclosure.

[0049] Figure 22AThis is a circuit diagram illustrating the structure of the main pixel driving circuit, the auxiliary pixel driving circuit, the main light-emitting element, and the auxiliary light-emitting element according to some embodiments of the present disclosure.

[0050] Figure 22B This is a timing diagram of operating the light-emitting substrate according to some embodiments of this disclosure.

[0051] Figure 23 This is a circuit diagram illustrating the structure of the main pixel driving circuit, the auxiliary pixel driving circuit, the main light-emitting element, and the auxiliary light-emitting element according to some embodiments of the present disclosure.

[0052] Figure 24 This is a circuit diagram illustrating the structure of the main pixel driving circuit, the auxiliary pixel driving circuit, the main light-emitting element, and the auxiliary light-emitting element according to some embodiments of the present disclosure.

[0053] Figure 25 This is a circuit diagram illustrating the structure of a main pixel driving circuit, an auxiliary pixel driving circuit, a second auxiliary pixel driving circuit, a main light-emitting element, an auxiliary light-emitting element, and a second auxiliary light-emitting element according to some embodiments of the present disclosure.

[0054] Figure 26 This is a cross-sectional view of a light-emitting substrate according to some embodiments of the present disclosure.

[0055] Figure 27 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0056] Figure 28A This is a plan view of the color filter and light-emitting element according to some embodiments of the present disclosure.

[0057] Figure 28B This is a plan view of the color filter and light-emitting element according to some embodiments of the present disclosure.

[0058] Figure 28C This is a plan view of the color filter and light-emitting element according to some embodiments of the present disclosure. Detailed Implementation

[0059] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0060] Therefore, this disclosure particularly provides a scanning circuit, a light-emitting substrate, a display device, and a method for operating the scanning circuit, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes a plurality of scanning units, each at multiple levels. Optionally, each of the plurality of scanning units includes at least one of an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, or an output sub-circuit. Optionally, each scanning unit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal. Optionally, the output sub-circuit includes a first output terminal, a second output terminal, a twelfth transistor (e.g., a first switching transistor), and a fourteenth transistor (i.e., a second switching transistor). Optionally, the source of the twelfth transistor is coupled to a third terminal configured to receive the first clock signal. Optionally, the drain of the twelfth transistor is coupled to the first output terminal configured to output a first control signal. Optionally, the source of the fourteenth transistor is coupled to a fourth terminal configured to receive the third clock signal. Optionally, the drain of the fourteenth transistor is coupled to the second output terminal configured to output a second control signal. Optionally, the gates of the twelfth and fourteenth transistors are coupled to the first node.

[0061] Figure 1 This is a schematic diagram illustrating a scanning unit in a scanning circuit according to some embodiments of the present disclosure. (See reference) Figure 1 In some embodiments, each scanning unit includes an input sub-circuit Isc, a first processing sub-circuit Psc1, a second processing sub-circuit Psc2, a third processing sub-circuit Psc3, and an output sub-circuit Osc. The input sub-circuit Isc is configured to receive a start signal STV or an output signal G_(n-1) from the previous scanning unit in the preceding stage. Optionally, the input sub-circuit Isc is also configured to receive a second clock signal CLK2. The input sub-circuit is connected to the first processing sub-circuit Psc1 and the second processing sub-circuit Psc2.

[0062] In some embodiments, the first processing sub-circuit Psc1 is configured to receive at least one of a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, a first reference signal VREF1, or a second reference signal VREF2. Optionally, the first processing sub-circuit Psc1 is configured to receive the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the first reference signal VREF1, and the second reference signal VREF2. Optionally, the first processing sub-circuit Psc1 is connected to the input sub-circuit Isc, the second processing sub-circuit Psc2, and the output sub-circuit Osc. Optionally, the first processing sub-circuit Psc1 serves as a first noise reduction sub-circuit.

[0063] In some embodiments, the second processing sub-circuit Psc2 is configured to receive at least one of a fourth clock signal CLK4 or a second reference signal VREF2. Optionally, the second processing sub-circuit Psc2 is configured to receive the fourth clock signal CLK4 and the second reference signal VREF2. Optionally, the second processing sub-circuit Psc2 is connected to the input sub-circuit Isc, the first processing sub-circuit Psc1, the third processing sub-circuit Psc3, and the output sub-circuit Osc. Optionally, the second processing sub-circuit Psc2 serves as a delayed write sub-circuit.

[0064] In some embodiments, the third processing sub-circuit Psc3 is configured to receive a fourth clock signal CLK4. Optionally, the third processing sub-circuit Psc3 is connected to the second processing sub-circuit Psc2 and the output sub-circuit Osc. Optionally, the third processing sub-circuit Psc3 serves as a second noise reduction sub-circuit.

[0065] In some embodiments, the output sub-circuit Osc is configured to output a first control signal G1(n) and a second control signal G2(n). In one example, the first control signal G1(n) and the second control signal G2(n) are output sequentially in time. In another example, the first control signal G1(n) and the second control signal G2(n) are output simultaneously.

[0066] In some embodiments, the output sub-circuit OSc is configured to receive at least one of a first clock signal CLK1, a third clock signal CLK3, or a first reference signal VREF1. Optionally, the output sub-circuit OSc is connected to a first processing sub-circuit Psc1, a second processing sub-circuit Psc2, or a third processing sub-circuit Psc3.

[0067] Figure 2 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 2A scanning unit is shown, where the transistor is a p-type transistor. Various implementations of the scanning circuit can be practiced. In one example, the transistor in the scanning circuit can be a p-type transistor, such as... Figure 2 As shown. In another example, the transistors in the scan circuit can be n-type transistors. In yet another example, the transistors in the scan circuit can include one or more p-type transistors and one or more n-type transistors.

[0068] See Figure 2 In some embodiments, the input sub-circuit is configured to write the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage into the first capacitor C1, and to write the second clock signal CLK2 into the second capacitor C2 to maintain a low voltage level at the gate of the tenth transistor M10. In some embodiments, the second processing sub-circuit Psc2 is configured to write the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage into the gate of the twelfth transistor M12 (i.e., the first switching transistor) and / or the fourteenth transistor M14 (i.e., the second switching transistor) to achieve signal delay. In some embodiments, the output sub-circuit Osc is configured to output a first control signal G1(n) when the twelfth transistor M12 is turned on, and is configured to output a second control signal G2(n) when the fourteenth transistor M14 is turned on. In some embodiments, the first processing sub-circuit Psc1 is configured to set the voltage level at the fourth node N4 to a cutoff voltage level (e.g., a high voltage level when the transistors in each scan unit are p-type transistors). In some embodiments, the third processing sub-circuit Psc3 is configured to set the voltage level at the fifth node N5 to a cutoff voltage level (e.g., a high voltage level when the transistors in each scan unit are p-type transistors) when the voltage level at the gate of the tenth transistor M10 is a turn-on voltage level (e.g., a low voltage level when the transistors in each scan unit are p-type transistors). This sets the voltage levels at the gates of the tenth transistor M10 and the twelfth transistor M12 to be opposite to each other, preventing the output voltage signal from becoming floating. For example, if the voltage levels at the gates of both the tenth transistor M10 and the twelfth transistor M12 are high voltage levels, the output voltage signal may become floating and susceptible to noise interference.

[0069] In some embodiments, the input sub-circuit Isc includes a first transistor M1 and an input transistor M0. The first transistor M1 is coupled between a first terminal TM1 and a second node N2. The input transistor M0 is coupled between an input terminal TMi and a third node N3. The third node N3 is coupled to a first processing sub-circuit Psc1 and a second processing sub-circuit Psc2.

[0070] The gate of the first transistor M1 is coupled to the drain of the input transistor M0. The source of the first transistor M1 is coupled to the first terminal TM1 and configured to receive the second clock signal CLK2. The drain of the first transistor M1 is coupled to the second node N2.

[0071] The gate of input transistor M0 is coupled to the first terminal TM1 and configured to receive a second clock signal CLK2 from the first terminal TM1. The source of input transistor M0 is coupled to the input terminal TMi and configured to receive a start signal STV or an output signal G_(n-1) from the previous scan unit of the previous stage. The drain of input transistor M0 is coupled to the third node N3. When the second clock signal CLK2 is provided to the first terminal TM1, input transistor M0 is turned on to electrically couple the input terminal TMi to the third node N3; the first transistor M1 is turned on to electrically couple the first terminal TM1 to the second node N2.

[0072] In some embodiments, the first processing sub-circuit Psc1 includes a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The second transistor M2 is coupled between the second node N2 and the second terminal TM2 and is configured to receive a second reference signal VREF2 from the second terminal TM2. The third transistor M3 is coupled between node N3 and the fifth transistor M5. The fourth transistor M4 is coupled between node N3 and the fifth transistor M5. The fifth transistor M5 is coupled between the fifth terminal TM5 and either the third transistor M3 or the fourth transistor M4 and is configured to receive a first reference signal VREF1 from the fifth terminal TM5.

[0073] The gate of the second transistor M2 is coupled to the first terminal TM1 and configured to receive the second clock signal CLK2 from the first terminal TM1. The source of the second transistor M2 is coupled to the second terminal TM2 and configured to receive the second reference signal VREF2 from the second terminal TM2. The drain of the second transistor M2 is coupled to the second node N2.

[0074] The gate of the third transistor M3 is coupled to the third terminal TM3 and is configured to receive the first clock signal CLK1 from the third terminal TM3. The source of the third transistor M3 is coupled to the drain of the fifth transistor M5. The drain of the third transistor M3 is coupled to the third node N3.

[0075] The gate of the fourth transistor M4 is coupled to the fourth terminal TM4 and is configured to receive the third clock signal CLK3 from the fourth terminal TM4. The source of the fourth transistor M4 is coupled to the drain of the fifth transistor M5. The drain of the fourth transistor M4 is coupled to the third node N3.

[0076] The gate of the fifth transistor M5 is coupled to the second node N2. The source of the fifth transistor M5 is coupled to the fifth terminal TM5 and configured to receive the first reference signal VREF1 from the fifth terminal TM5. The drain of the fifth transistor M5 is coupled to the sources of the third transistor M3 and the fourth transistor M4.

[0077] In some embodiments, the second processing sub-circuit Psc2 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a first capacitor C1. The sixth transistor M6 is coupled between the third node N3 and the fourth node N4. The seventh transistor M7 is coupled between the sixth terminal TM6 and the fifth node N5 and is configured to receive a fourth clock signal CLK4 from the sixth terminal TM6. The eighth transistor M8 is coupled between the first node N1 and the fifth node N5. The first node N1 is coupled to the third processing sub-circuit Psc3 and the output sub-circuit Osc. The first capacitor C1 is coupled between the fourth node N4 and the fifth node N5.

[0078] The gate of the sixth transistor M6 is coupled to the second terminal TM2 and is configured to receive the second reference signal VREF2 from the second terminal TM2. The source of the sixth transistor M6 is coupled to the third node N3. The drain of the sixth transistor M6 is coupled to the fourth node N4. When the input transistor M0 is turned on by the second clock signal CLK2, the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage will reach the fourth node N4 through the input transistor M0, the third node N3, and the sixth transistor M6.

[0079] The gate of the seventh transistor M7 is coupled to the fourth node N4. The source of the seventh transistor M7 is coupled to the sixth terminal TM6 and is configured to receive the fourth clock signal CLK4 from the sixth terminal TM6. The drain of the seventh transistor M7 is connected to the fifth node N5. When the start signal STV or the output signal G_(n-1) from the previous scan unit of the preceding stage is transmitted to the fourth node N4, the seventh transistor M7 is turned on, thereby allowing the fourth clock signal CLK4 to be transmitted to the fifth node N5.

[0080] The gate of the eighth transistor M8 is coupled to the sixth terminal TM6 and is configured to receive the fourth clock signal CLK4 from the sixth terminal TM6. The source of the eighth transistor M8 is coupled to the fifth node N5. The drain of the eighth transistor M8 is coupled to the first node N1. When the eighth transistor M8 is turned on by the fourth clock signal CLK4, the first node N1 is electrically connected to the fifth node N5.

[0081] The first capacitor electrode of the first capacitor C1 is coupled to the fifth node N5. The second capacitor electrode of the first capacitor C1 is coupled to the fourth node N4.

[0082] In some embodiments, the third processing sub-circuit Psc3 includes a ninth transistor M9. The ninth transistor M9 is coupled between the sixth terminal TM6 and the first node N1.

[0083] The gate of the ninth transistor M9 is coupled to the second node N2. The source of the ninth transistor M9 is coupled to the sixth terminal TM6 and is configured to receive the fourth clock signal CLK4 from the sixth terminal TM6. The drain of the ninth transistor M9 is coupled to the first node N1.

[0084] In some embodiments, the output sub-circuit OSc includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14. The tenth transistor M10 is coupled between the fifth terminal TM5 and the first output terminal TMo1, and is configured to receive a first reference signal VREF1 from the fifth terminal TM5. The eleventh transistor M11 is coupled between the tenth transistor M10 and the twelfth transistor M12. The twelfth transistor M12 is coupled between the third terminal TM3 and the first output terminal TMo1, and is configured to receive a first clock signal CLK1 from the third terminal TM3. The thirteenth transistor M13 is coupled between the fifth terminal TM5 and the second output terminal TMo2, and is configured to receive the first reference signal VREF1 from the fifth terminal TM5. The fourteenth transistor M14 is coupled between the fourth terminal TM4 and the second output terminal TMo2, and is configured to receive a third clock signal CLK3 from the fourth terminal TM4.

[0085] The gate of the tenth transistor M10 is coupled to the second node N2. The source of the tenth transistor M10 is coupled to the fifth terminal TM5 and is configured to receive the first reference signal VREF1 from the fifth terminal TM5. The drain of the tenth transistor M10 is coupled to the first output terminal TMo1 and the source of the eleventh transistor M11.

[0086] The gate of the eleventh transistor M11 is coupled to the first node N1. The source and drain of the eleventh transistor M11 are connected to the first output terminal TMo1.

[0087] The gate of the twelfth transistor M12 is coupled to the first node N1. The source of the twelfth transistor M12 is coupled to the third terminal TM3 and is configured to receive the first clock signal CLK1 from the third terminal TM3. The drain of the twelfth transistor M12 is coupled to the first output terminal TMo1 and the drain of the eleventh transistor M11.

[0088] In some embodiments, the gates of the eleventh transistor M11 and the twelfth transistor M12 are connected to each other, and the source and drain of the eleventh transistor M11 are connected to each other. During the operation of each scan unit, the twelfth transistor M12 remains in the off state for a relatively long time, resulting in a relatively large gate-source voltage Vgs. By providing such an eleventh transistor M11 in each scan unit, the gate-source voltage Vgs of the twelfth transistor M12 can be reduced, especially when both the eleventh transistor M11 and the twelfth transistor M12 are off.

[0089] The gate of the thirteenth transistor M13 is coupled to the second node N2. The source of the thirteenth transistor M13 is coupled to the fifth terminal TM5 and is configured to receive the first reference signal VREF1 from the fifth terminal TM5. The drain of the thirteenth transistor M13 is coupled to the second output terminal TMo2.

[0090] The gate of the fourteenth transistor M14 is coupled to the first node N1. The source of the fourteenth transistor M14 is coupled to the fourth terminal TM4 and is configured to receive the third clock signal CLK3 from the fourth terminal TM4. The drain of the fourteenth transistor M14 is coupled to the second output terminal TMo2.

[0091] Figure 3 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of this disclosure. (See reference...) Figure 3 Each scanning unit in the image frame can operate in at least one of sixteen stages t1 to t16. In some embodiments, the operation of each scanning unit includes stages t1 to t8. Optionally, the operation of each scanning unit also includes stages t9 to t16.

[0092] Reference Figure 1 , Figure 2 and Figure 3 In the first stage t1, the effective voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal TMi; the effective voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. As used herein, the effective voltage refers to a low voltage in the case of a p-type transistor and a high voltage in the case of an n-type transistor; while the invalid voltage refers to a high voltage in the case of a p-type transistor and a low voltage in the case of an n-type transistor.

[0093] In the first stage t1, input transistor M0 is turned on by the effective voltage of the second clock signal CLK2, and the sixth transistor M6 is turned on by the second reference signal VREF2. When input transistor M0 and the sixth transistor M6 are turned on, the fourth node N4 is charged to an effective voltage level (e.g., a low voltage level in the case of a p-type transistor) by the effective voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The first transistor M1 is turned on by the effective voltage charged at the fourth node N4, causing the effective voltage of the second clock signal CLK2 to charge the second node N2. The fifth node N5 and the first node N1 remain at an ineffective voltage level (e.g., a high voltage level in the case of a p-type transistor).

[0094] The tenth transistor M10 and the thirteenth transistor M13 are turned on by the effective voltage charged at the second node N2, causing the first reference signal VREF1 to be sent to the first output terminal TMo1 and the second output terminal TMo2. The first reference signal VREF1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). Therefore, the first output signal G1(n) and the second output signal G2(n) are invalid control signals.

[0095] In the second stage t2, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the first terminal TM1 switches from an active voltage level to an invalid voltage level.

[0096] In the second phase t2, the voltage level at the fourth node N4 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor), and the first transistor M1 remains on, thereby allowing the invalid voltage of the second clock signal CLK2 to pass through the first transistor M1 to charge the second node N2. The voltage level at the second node N2 switches from an effective voltage level to an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor).

[0097] In the second stage t2, the tenth transistor M10 and the thirteenth transistor M13 are turned off by the invalid voltage at the second node N2. The eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M14 are turned off by the invalid voltage at the first node N1. Therefore, the first output signal G1(n) and the second output signal G2(n) remain invalid control signals.

[0098] In the third stage t3, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the valid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the sixth terminal TM6 switches from an invalid voltage level to an valid voltage level.

[0099] In the third stage t3, the voltage level at node N4 remains at an active voltage level, while the voltage level at node N2 remains at an inactive voltage level. The active voltage of the fourth clock signal CLK4 turns on the eighth transistor M8. The active voltage at node N4 turns on the seventh transistor M7. The active voltage of the fourth clock signal CLK4 passes through the seventh transistor M7 to reach node N5, and then through the eighth transistor M8 to reach node N1. Therefore, the voltage levels at nodes N5 and N1 switch from inactive to active voltage levels.

[0100] In the third stage t3, the twelfth transistor M12 is turned on by the effective voltage at the first node N1, causing the invalid voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is turned on by the effective voltage at the first node N1, causing the invalid voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) and the second output signal G2(n) remain invalid control signals.

[0101] In the fourth stage t4, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the sixth terminal TM6 switches from an active voltage level to an invalid voltage level.

[0102] In the fourth stage t4, the voltage level at node N4 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor), and the first transistor M1 remains on, allowing the invalid voltage of the second clock signal CLK2 to pass through the first transistor M1 to charge node N2. The voltage level at node N2 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor). The voltage level at node N1 remains at an effective voltage level. The effective voltage at node N4 turns on the seventh transistor M7, allowing the invalid voltage of the fourth clock signal CLK4 to charge node N5. The voltage level at node N5 switches from an effective voltage level to an invalid voltage level.

[0103] In the fourth stage t4, the twelfth transistor M12 is kept on by the effective voltage at the first node N1, allowing the invalid voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is kept on by the effective voltage at the first node N1, thereby allowing the invalid voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) and the second output signal G2(n) remain invalid control signals.

[0104] In the fifth stage t5, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the valid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the fourth terminal TM4 switches from an invalid voltage level to a valid voltage level.

[0105] In the fifth stage t5, the voltage level at node N4 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor), and the first transistor M1 remains on, allowing the invalid voltage of the second clock signal CLK2 to pass through the first transistor M1 to charge node N2. The voltage level at node N2 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor). The voltage level at node N1 remains at an effective voltage level. The effective voltage at node N4 turns on the seventh transistor M7, allowing the invalid voltage of the fourth clock signal CLK4 to charge node N5. The voltage level at node N5 remains at an invalid voltage level.

[0106] In the fifth stage t5, the twelfth transistor M12 is kept on by the effective voltage at the first node N1, allowing the invalid voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is kept on by the effective voltage at the first node N1, thereby allowing the effective voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) is output as an effective control signal.

[0107] In the sixth stage t6, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the fourth terminal TM4 switches from an active voltage level to an invalid voltage level.

[0108] In stage t6, the voltage level at node N4 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor), and the first transistor M1 remains on, allowing the invalid voltage of the second clock signal CLK2 to pass through the first transistor M1 to charge node N2. The voltage level at node N2 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor). The voltage level at node N1 remains at an effective voltage level. The effective voltage at node N4 turns on the seventh transistor M7, allowing the invalid voltage of the fourth clock signal CLK4 to charge node N5. The voltage level at node N5 remains at an invalid voltage level.

[0109] In stage t6, the twelfth transistor M12 is kept on by the effective voltage at the first node N1, allowing the invalid voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is kept on by the effective voltage at the first node N1, thus allowing the invalid voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) is also output as an invalid control signal.

[0110] In the seventh stage t7, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the valid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the third terminal TM3 switches from an invalid voltage level to a valid voltage level.

[0111] In stage t7, the voltage level at node N4 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor), and the first transistor M1 remains on, allowing the invalid voltage of the second clock signal CLK2 to pass through the first transistor M1 to charge node N2. The voltage level at node N2 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor). The voltage level at node N1 remains at an effective voltage level. The effective voltage at node N4 turns on the seventh transistor M7, allowing the invalid voltage of the fourth clock signal CLK4 to charge node N5. The voltage level at node N5 remains at an invalid voltage level.

[0112] In stage t7, the twelfth transistor M12 is kept on by the effective voltage at the first node N1, allowing the effective voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is kept on by the effective voltage at the first node N1, thus allowing the invalid voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. Therefore, the second output signal G2(n) remains an invalid control signal. The first output signal G1(n) is output as an valid control signal.

[0113] In stage 8 t8, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3. The voltage level at the third terminal TM3 switches from an active voltage level to an invalid voltage level.

[0114] In stage t8, the voltage level at node N4 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor), and the first transistor M1 remains on, allowing the invalid voltage of the second clock signal CLK2 to pass through the first transistor M1 to charge node N2. The voltage level at node N2 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor). The voltage level at node N1 remains at an effective voltage level. The effective voltage at node N4 turns on the seventh transistor M7, allowing the invalid voltage of the fourth clock signal CLK4 to charge node N5. The voltage level at node N5 remains at an invalid voltage level.

[0115] In stage t8, the twelfth transistor M12 is kept on by the effective voltage at the first node N1, allowing the invalid voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is kept on by the effective voltage at the first node N1, thus allowing the invalid voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. Therefore, the second output signal G2(n) remains an invalid control signal. The first output signal G1(n) is also output as an invalid control signal.

[0116] In the ninth stage t9, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal TMi; the valid voltage of the second clock signal CLK2 is provided to the first terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third terminal TM3.

[0117] In the ninth stage t9, input transistor M0 is turned on by the effective voltage of the second clock signal CLK2, and the sixth transistor M6 is turned on by the second reference signal VREF2. When input transistor M0 and the sixth transistor M6 are turned on, the fourth node N4 is charged to an ineffective voltage level (e.g., a high voltage level in the case of a p-type transistor) by the ineffective signal of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage. The first transistor M1 is turned off by the ineffective voltage charged at the fourth node N4. The second transistor M2 is turned on by the effective voltage of the second clock signal CLK2 to allow the second reference signal VREF2 (e.g., the effective voltage) to pass through the second transistor M2. The second node N2 is charged to an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The ninth transistor M9 is turned on by the effective voltage at the second node N2, thereby allowing the ineffective voltage of the fourth clock signal CLK4 to pass through the ninth transistor M9 and reach the first node N1. The first node N1 switches from an effective voltage level to an ineffective voltage level (e.g., a high voltage level in the case of a p-type transistor). When the seventh transistor M7 is turned off by the invalid voltage at the fourth node N4 and the eighth transistor M8 is turned off by the invalid voltage of the fourth clock signal CLK4, the fifth node N5 remains at the invalid voltage level.

[0118] The tenth transistor M10 and the thirteenth transistor M13 are turned on by the effective voltage charged at the second node N2, causing the first reference signal VREF1 to be sent to the first output terminal TMo1 and the second output terminal TMo2. The first reference signal VREF1 is an invalid voltage signal (e.g., a high voltage signal in the case of a p-type transistor). Therefore, the first output signal G1(n) and the second output signal G2(n) are invalid control signals.

[0119] In the tenth stage t10, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level at the first input terminal TM1 switches from an active voltage level to an invalid voltage level.

[0120] In stage 10 t10, the voltage level at node 4 N4 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), and the first transistor M1 remains off. The voltage level at node 2 N2 remains at an active voltage level. The voltage level at node 1 N1 remains at an invalid voltage level. The voltage level at node 5 N5 remains at an invalid voltage level.

[0121] In stage t10, the eleventh transistor M11, the twelfth transistor M12, and the fourteenth transistor M14 are turned off by the invalid voltage at the first node N1. The tenth transistor M10 and the thirteenth transistor M13 are turned on by the effective voltage at the second node N2, so that the first reference signal VREF1 passes through the tenth transistor M10 and the thirteenth transistor M13 to reach the first output terminal TMo1 and the second output terminal TMo2. The voltage level of the first reference signal VREF1 is an invalid voltage level (e.g., a high voltage level in the case of p-type transistors). Therefore, the first output signal G1(n) and the second output signal G2(n) remain invalid control signals.

[0122] In stage eleven (t11), the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; the valid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level at the sixth input terminal TM6 switches from an invalid voltage level to an valid voltage level.

[0123] In stage eleven (t11), the voltage level at node four (N4) remains at an invalid voltage level, while the voltage level at node two (N2) remains at an active voltage level. The active voltage at node two (N2) turns on transistor nine (M9). The active voltage of the fourth clock signal (CLK4) passes through transistor nine (M9) and reaches node one (N1). The active voltage of the fourth clock signal (CLK4) turns on transistor eight (M8). The active voltage at node one (N1) passes through transistor eight (M8) and reaches node five (N5). Therefore, the voltage levels at nodes five (N5) and one (N1) switch from invalid to active voltage levels.

[0124] In stage eleven (t11), the twelfth transistor M12 is turned on by the effective voltage at the first node N1, allowing the invalid voltage of the first clock signal CLK1 to pass through the twelfth transistor M12 and reach the first output terminal TMo1. The fourteenth transistor M14 is turned on by the effective voltage at the first node N1, allowing the invalid voltage of the third clock signal CLK3 to pass through the fourteenth transistor M14 and reach the second output terminal TMo2. The tenth transistor M10 is turned on by the effective voltage at the second node N2, allowing the invalid voltage of the first reference signal VREF1 to pass through the tenth transistor M10 and reach the first output terminal TMo1. The thirteenth transistor M13 is turned on by the effective voltage at the second node N2, allowing the invalid voltage of the first reference signal VREF1 to pass through the thirteenth transistor M13 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) and the second output signal G2(n) remain invalid control signals.

[0125] In the twelfth stage t12, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level at the sixth input terminal TM6 switches from an active voltage level to an invalid voltage level.

[0126] In stage t12, the voltage level at node N4 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), and the first transistor M1 remains off. The voltage level at node N2 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The voltage level at node N5 remains at an effective voltage level. The effective voltage at node N2 turns on the ninth transistor M9, thereby allowing the invalid voltage of the fourth clock signal CLK4 to charge node N1. The voltage level at node N1 switches from an effective voltage level to an invalid voltage level.

[0127] In stage t12, the tenth transistor M10 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the tenth transistor M10 and reach the first output terminal TMo1. The thirteenth transistor M13 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the thirteenth transistor M13 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) remains an invalid control signal.

[0128] In stage thirteen (t13), the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; the valid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level at the fourth input terminal TM4 switches from an invalid voltage level to a valid voltage level.

[0129] In stage thirteen (t13), the voltage level at node four (N4) remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), and the first transistor (M1) remains off. The voltage level at node two (N2) remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The voltage level at node one (N1) remains at an invalid voltage level. The voltage level at node five (N5) remains at an effective voltage level.

[0130] In the thirteenth stage t13, the tenth transistor M10 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the tenth transistor M10 and reach the first output terminal TMo1. The thirteenth transistor M13 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the thirteenth transistor M13 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) remains an invalid control signal.

[0131] In the fourteenth stage t14, the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level at the fourth input terminal TM4 switches from an active voltage level to an invalid voltage level.

[0132] In stage fourteen, t14, the voltage level at node four, N4, remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), and the first transistor, M1, remains off. The voltage level at node two, N2, remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The voltage level at node one, N1, remains at an invalid voltage level. The voltage level at node five, N5, remains at an effective voltage level.

[0133] In stage fourteen (t14), the tenth transistor M10 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the tenth transistor M10 and reach the first output terminal TMo1. The thirteenth transistor M13 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the thirteenth transistor M13 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) remains an invalid control signal.

[0134] In stage 15 t15, an invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; an invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; an invalid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; an invalid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and an valid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level at the third input terminal TM3 switches from an invalid voltage level to a valid voltage level.

[0135] In stage 15 t15, the voltage level at node 4 N4 remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), and the first transistor M1 remains off. The voltage level at node 2 N2 remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The voltage level at node 1 N1 remains at an invalid voltage level. The voltage level at node 5 N5 remains at an effective voltage level.

[0136] In the fifteenth stage t15, the tenth transistor M10 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the tenth transistor M10 and reach the first output terminal TMo1. The thirteenth transistor M13 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the thirteenth transistor M13 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) remains an invalid control signal.

[0137] In stage sixteen (t16), the invalid voltage of the start signal STV or the output signal G_(n-1) from the previous scan unit of the previous stage is provided to the input terminal; the invalid voltage of the second clock signal CLK2 is provided to the first input terminal TM1; the invalid voltage of the fourth clock signal CLK4 is provided to the sixth input terminal TM6; the invalid voltage of the third clock signal CLK3 is provided to the fourth input terminal TM4; and the invalid voltage of the first clock signal CLK1 is provided to the third input terminal TM3. The voltage level of the third input terminal TM3 switches from an active voltage level to an invalid voltage level.

[0138] In stage sixteen (t16), the voltage level at node four (N4) remains at an invalid voltage level (e.g., a high voltage level in the case of a p-type transistor), and the first transistor (M1) remains off. The voltage level at node two (N2) remains at an effective voltage level (e.g., a low voltage level in the case of a p-type transistor). The voltage level at node one (N1) remains at an invalid voltage level. The voltage level at node five (N5) remains at an effective voltage level.

[0139] In stage sixteen (t16), the tenth transistor M10 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the tenth transistor M10 and reach the first output terminal TMo1. The thirteenth transistor M13 is turned on by the effective voltage at the second node N2, thereby allowing the invalid voltage of the first reference signal VREF1 to pass through the thirteenth transistor M13 and reach the second output terminal TMo2. Therefore, the first output signal G1(n) remains an invalid control signal. The second output signal G2(n) remains an invalid control signal.

[0140] Figure 4 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure. Figure 4 The operation of each scanning unit described herein is otherwise similar to Figure 3 The operation of each scanning unit described herein is the same, except that the third clock signal CLK3 remains an invalid voltage throughout t1 to t16, and the second control signal G2(n) output from the second output terminal TMo2 is an invalid voltage throughout t1 to t16.

[0141] Figure 5 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure. Figure 5 The operation of each scanning unit described herein is otherwise similar to Figure 3The operation of each scanning unit described herein is the same, except that the third clock signal CLK3 and the first clock signal CLK1 are in phase. The first control signal G1(n) output from the first output terminal TMo1 and the second control signal G2(n) output from the second output terminal TMo2 are also in phase.

[0142] Figure 6 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 6 The various scanning units described herein are otherwise similar to Figure 2 The scanning units described in the text are the same, except that... Figure 6 The transistors in each scanning unit described are all n-type transistors, while Figure 2 The transistors in each scanning unit described herein are all p-type transistors. Figure 6 The operation of each scanning unit described herein is otherwise similar to Figure 2 The operation of each scanning unit described in the text is the same, except that the operation... Figure 6 The effective voltage of each scanning unit depicted is high voltage, while the operation... Figure 2 The effective voltage of each scanning unit depicted is low voltage.

[0143] Figure 7 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure. Figure 7 Some embodiments according to this disclosure are shown. Figure 6 The operation of the scanning unit shown. Figure 7 Timing diagrams and operations of each scanning unit shown Figure 3 The timing diagrams of the various scan units shown are identical in all other respects, except for those used for operation. Figure 7 The effective voltage of each scanning unit shown is a high voltage, while the voltage used for operation is... Figure 3 The effective voltage of each scanning unit shown is a low voltage.

[0144] Figure 8 This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure. Figure 8 Some embodiments according to this disclosure are shown. Figure 6 The operation of the scanning unit shown. Figure 8 Timing diagrams and operations of each scanning unit shown Figure 4 The timing diagrams of the various scan units shown are identical in all other respects, except for those used for operation. Figure 8 The effective voltage of each scanning unit shown is a high voltage, while the operation... Figure 4 The effective voltage of each scanning unit shown is a low voltage.

[0145] Figure 9This is a timing diagram of the scanning unit in the scanning circuit operating according to some embodiments of the present disclosure. Figure 9 Some embodiments according to this disclosure are shown. Figure 6 The operation of the scanning unit shown. Figure 9 Timing diagrams and operations of each scanning unit shown Figure 5 The timing diagrams for each scan unit shown are identical, except for those used for operation. Figure 9 The effective voltage of each scanning unit shown is a high voltage, while the voltage used for operation is... Figure 5 The effective voltage of each scanning unit shown is a low voltage.

[0146] In some embodiments, the third processing sub-circuit Psc3 is optional; for example, each scanning unit may not include the third processing sub-circuit Psc3. Figure 10 This is a schematic diagram illustrating a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 11 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of this disclosure. (See reference...) Figure 10 and Figure 11 In some embodiments, each scanning unit includes an input sub-circuit Isc, a first processing sub-circuit Psc1, a second processing sub-circuit Psc2, and an output sub-circuit Osc. Figure 10 The various scanning units described herein are otherwise similar to Figure 1 The scanning units described in the text are the same, except that... Figure 10 The scanning units described herein do not include the third processing sub-circuit. Figure 11 The various scanning units described herein are otherwise similar to Figure 2 The scanning units described in the text are the same, except that... Figure 11 The scanning units described herein do not include the third processing sub-circuit.

[0147] Figure 12 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 12 The various scanning units described herein are otherwise similar to Figure 2 The scanning units described in the text are the same, except that... Figure 12 The output sub-circuit Osc in each scanning unit described herein has the same characteristics as... Figure 2 The output sub-circuits Osc in each scanning unit described in the text have different structures, specifically, Figure 12 The output sub-circuit Osc in each scanning unit described herein does not include the eleventh transistor M11.

[0148] Figure 13 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 13 The various scanning units described herein are otherwise similar to Figure 2 The descriptions of the various scanning units are the same, except that in Figure 13 In each described scan cell, the source and drain of the eleventh transistor M11 are not shorted. Figure 13 In each of the described scanning units, the first output terminal TMo1 is directly connected to the drain of the eleventh transistor M11, rather than directly to the source of the eleventh transistor M11.

[0149] Figure 14 This is a circuit diagram of a scanning unit in a scanning circuit according to some embodiments of the present disclosure. Figure 14 The various scanning units described herein are otherwise similar to Figure 2 The scanning units described in the text are the same, except that in Figure 14 In the various scanning units described, the source and drain of the eleventh transistor M11 are not shorted. Figure 14 In each scanning unit described herein, the first output terminal TMo1 is directly connected to the source of the eleventh transistor M11, rather than directly connected to the drain of the eleventh transistor M11.

[0150] In some embodiments, reference Figures 1 to 14 Each of the multiple scanning units includes at least one of an input sub-circuit Isc, a first processing sub-circuit Psc1, a second processing sub-circuit Psc2, or an output sub-circuit Osc. Each scanning unit is configured to receive at least one of a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, a fourth clock signal CLK4, a first reference signal VREF1, or a second reference signal VREF2. Optionally, the output sub-circuit Osc includes a first output terminal TMo1, a second output terminal TMo2, a twelfth transistor M12, and a fourteenth transistor M14. Optionally, the source of the twelfth transistor M12 is coupled to a third terminal TM3 configured to receive the first clock signal CLK1. Optionally, the drain of the twelfth transistor M12 is coupled to a first output terminal TMo1 configured to output a first control signal G1(n). Optionally, the source of the fourteenth transistor M14 is coupled to a fourth terminal TM4 configured to receive the third clock signal CLK3. Optionally, the drain of the fourteenth transistor M14 is coupled to a second output terminal TMo2 configured to output a second control signal G2(n). Optionally, the gates of the twelfth transistor M12 and the fourteenth transistor M14 are coupled to (e.g., directly connected to) the first node N1. In one example, the gates of the twelfth transistor M12 and the fourteenth transistor M14 are directly connected to the first node N1.

[0151] In some embodiments, the output sub-circuit OSc further includes a tenth transistor M10 and a thirteenth transistor M13. Optionally, the sources of the tenth transistor M10 and the thirteenth transistor M13 are coupled to a fifth terminal configured to receive a first reference signal VREF1. Optionally, the drain of the tenth transistor M10 is coupled to a first output terminal TMo1. Optionally, the drain of the thirteenth transistor M13 is coupled to a second output terminal TMo2. Optionally, the gates of the tenth transistor M10 and the thirteenth transistor M13 are coupled to (e.g., directly connected to) a second node N2. In one example, the gates of the tenth transistor M10 and the thirteenth transistor M13 are directly connected to the second node N2.

[0152] In some embodiments, the output sub-circuit OSc further includes an eleventh transistor M11 coupled between the tenth transistor M10 and the twelfth transistor M12. Optionally, the gate of the eleventh transistor M11 is coupled to the first node N1. Optionally, at least one of the source and drain of the eleventh transistor M11 is coupled to the first output terminal TMo1. Optionally, both the source and drain of the eleventh transistor M11 are coupled to the first output terminal TMo1.

[0153] In some embodiments, each scanning unit further includes a second capacitor C2. Optionally, the first capacitor electrode of the second capacitor C2 is coupled to the source of the tenth transistor M10. Optionally, the second capacitor electrode of the second capacitor C2 is coupled to the second node N2.

[0154] In some embodiments, each scanning unit further includes a third capacitor C3. Optionally, the first capacitor electrode of the third capacitor C3 is coupled to the first node N1. Optionally, the second capacitor electrode of the third capacitor C3 is coupled to the second terminal TM2 configured to receive the second reference signal VREF2.

[0155] In some embodiments, the input sub-circuit Isc includes an input transistor M0, a first transistor M1, an input terminal Tmi, and a first terminal TM1. Optionally, the gate of the input transistor M0 and the source of the first transistor M1 are coupled to the first terminal TM1, which is configured to receive a second clock signal CLK2. Optionally, the gate of the first transistor M1 and the drain of the input transistor M0 are coupled to a third node N3. Optionally, the source of the input transistor M0 is coupled to an input terminal TMi, which is configured to receive a start signal STV or an output signal G_(n-1) from the previous scan unit of the previous stage. Optionally, the drain of the first transistor M1 is coupled to a second node N2.

[0156] In some embodiments, the first processing sub-circuit Psc1 includes at least one of a second transistor M2, a third transistor M3, a fourth transistor M4, or a fifth transistor M5. Optionally, the sources of the third transistor M3 and the fourth transistor M4 are coupled to the drain of the fifth transistor M5. Optionally, the drains of the third transistor M3 and the fourth transistor M4 are coupled to a third node N3. Optionally, the gate of the third transistor M3 is coupled to a third terminal TM3 configured to receive a first clock signal CLK1. Optionally, the gate of the fourth transistor M4 is coupled to a fourth terminal TM4 configured to receive a third clock signal CLK3.

[0157] In some embodiments, the gate of the fifth transistor M5 and the drain of the second transistor M2 are coupled to the second node N2. Optionally, the source of the fifth transistor M5 is coupled to a fifth terminal TM5 configured to receive a first reference signal VREF1. Optionally, the source of the second transistor M2 is coupled to a second terminal TM2 configured to receive a second reference signal VREF2.

[0158] In some embodiments, the second processing sub-circuit Psc2 includes a seventh transistor M7 and an eighth transistor M8. Optionally, the gate of the seventh transistor M7 is coupled to a fourth node N4. Optionally, the source of the seventh transistor M7 and the gate of the eighth transistor M8 are coupled to a sixth terminal TM6 configured to receive a fourth clock signal CLK4. Optionally, the drain of the seventh transistor M7 and the source of the eighth transistor M8 are coupled to a fifth node N5. Optionally, the drain of the eighth transistor M8 is coupled to a first node N1.

[0159] In some embodiments, the second processing sub-circuit Psc2 further includes a sixth transistor M6 and a first capacitor C1. Optionally, the gate of the sixth transistor M6 is coupled to a second terminal TM2 configured to receive the second reference signal VREF2. Optionally, the source of the sixth transistor M6 is coupled to a third node N3. Optionally, the drain of the sixth transistor M6 and the first capacitor electrode of the first capacitor C1 are coupled to a fourth node N4. Optionally, the second capacitor electrode of the first capacitor C1 is coupled to a fifth node N5.

[0160] In some embodiments, each scanning unit further includes a third processing sub-circuit Psc3. Optionally, the third processing sub-circuit Psc3 includes a ninth transistor M9, which has a gate coupled to the second node N2, a source coupled to the sixth terminal TM6 configured to receive the fourth clock signal CLK6, and a drain coupled to the first node N1.

[0161] In another aspect, this disclosure provides a light-emitting substrate driven by a scanning circuit. Figure 15 This is a schematic diagram illustrating the structure of a light-emitting substrate according to some embodiments of the present disclosure. (Refer to...) Figure 15 In some embodiments, the light-emitting substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the light-emitting substrate in a display panel that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas of two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the light-emitting substrate in a display panel that provides various circuits and wiring to transmit signals to the display substrate area. To increase the transparency of the array device, non-transparent or opaque components of the display device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area instead of the display area.

[0162] Figure 16 This is a circuit diagram of a light-emitting substrate according to some embodiments of this disclosure. (Refer to...) Figure 16 The light-emitting substrate includes a sub-pixel array. Each sub-pixel includes an electronic component, such as a light-emitting element. In some embodiments, the light-emitting substrate further includes multiple light-emitting elements driven by multiple pixel driving circuits. In one example, the light-emitting elements are driven by corresponding pixel driving circuits. The light-emitting substrate includes multiple gate lines GL, multiple data lines DL, and multiple power supply voltage lines Vdd. The emission of light from each sub-pixel Sp is driven by a corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to a corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through a corresponding one of the multiple power supply voltage lines Vdds; a low-voltage signal (constant voltage power supply line) is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., the VDD signal) and the low-voltage signal (e.g., the VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0163] In some embodiments, the light-emitting substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. Optionally, each pixel of the light-emitting substrate includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The plurality of sub-pixels in the light-emitting substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3-S4, wherein S1 represents a first sub-pixel, S2 represents a second sub-pixel, S3 represents a third sub-pixel, and S4 represents a fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents a first sub-pixel of a first color, C2 represents a second sub-pixel of a second color, C3 represents a third sub-pixel of a third color, and C4 represents a fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the first sub-pixel of the first color, C2 represents the second sub-pixel of the second color, C3 represents the third sub-pixel of the third color, and C2' represents the fourth sub-pixel of the second color. In yet another example, the C1-C2-C3-C2' format is the RGBG format, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, each third sub-pixel is a blue sub-pixel, and each fourth sub-pixel is a green sub-pixel.

[0164] Various suitable pixel driving circuits can be used in this light-emitting substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. Various suitable light-emitting elements can be used in this light-emitting substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0165] Figure 17 This is a cross-sectional view of a light-emitting substrate according to some embodiments of this disclosure. (Refer to...) Figure 17 In some embodiments, the display panel includes a plurality of sub-pixels. In some embodiments, each sub-pixel Sp among the plurality of sub-pixels includes n1 main light-emitting elements and n2 auxiliary light-emitting elements, where n1≥1 and n2≥1. Optionally, n1 is an integer. Optionally, n2 is an integer.

[0166] In this light-emitting substrate, the term "sub-pixel" refers to a pixel element, which may include multiple pixel driving circuits and multiple light-emitting elements. However, the multiple light-emitting elements in a sub-pixel emit light to achieve the desired grayscale of the pixel element. For example, a pixel may include three sub-pixels: a red sub-pixel, a green sub-pixel, and a blue sub-pixel. To display an image, the red sub-pixel emits light to achieve a first grayscale, the green sub-pixel emits light to achieve a second grayscale, and the blue sub-pixel emits light to achieve a third grayscale. The light emitted from the multiple light-emitting elements in the red sub-pixel together achieves the first grayscale. The light emitted from the multiple light-emitting elements in the green sub-pixel together achieves the second grayscale. The light emitted from the multiple light-emitting elements in the blue sub-pixel together achieves the third grayscale. Therefore, the multiple pixel driving circuits are controlled by at least one identical control signal. For example, a signal from a light-emitting control signal line can be transmitted in phase to the multiple pixel driving circuits as a light-emitting control signal for each of the multiple pixel driving circuits. In another example, a signal from a gate line can be transmitted in phase to the multiple pixel driving circuits as a gate scan signal for each of the multiple pixel driving circuits. In another example, only one data signal is transmitted to multiple pixel driving circuits; for example, the data signal is transmitted to only one or two of the multiple pixel driving circuits.

[0167] Refer again Figure 17 The light-emitting substrate further includes a pixel driving layer (DVL), which includes n1 main pixel driving circuits and n2 auxiliary pixel driving circuits, where n1 ≥ 1 and n2 ≥ 1. Optionally, n1 is an integer. Optionally, n2 is an integer. Each of the n1 main pixel driving circuits is configured to drive each of the n1 main light-emitting elements to emit light. Each of the n2 auxiliary pixel driving circuits is configured to drive each of the n2 auxiliary light-emitting elements to emit light.

[0168] Figure 18 This is a cross-sectional view of a light-emitting substrate according to some embodiments of this disclosure. (Refer to...) Figure 18 The pixel on the light-emitting substrate comprises three sub-pixels Sp1, Sp2, and Sp3. Each sub-pixel includes a single light-emitting element and a single pixel driving circuit in the pixel driving layer (DVL). Figure 4 The diagram shows three light-emitting elements, LE1, LE2, and LE3. The inventors of this disclosure discovered that crosstalk occurs between adjacent sub-pixels. For example, light emitted from the first light-emitting element LE1 may enter the second sub-pixel Sp2. To reduce crosstalk, the light-emitting substrate includes a black matrix BM in the inter-sub-pixel region between adjacent sub-pixels. However, the inventors of this disclosure found that the black matrix BM typically absorbs light, reducing the light utilization efficiency in the light-emitting substrate. When all light-emitting elements are blue light-emitting elements, the crosstalk problem is particularly pronounced due to the wider angle of light emitted from the blue light-emitting elements.

[0169] The inventors of this disclosure have discovered that the display method and complex structure of the light-emitting substrate according to the present invention can effectively prevent crosstalk between sub-pixels while maintaining excellent light utilization efficiency. The display method includes multiple display modes, wherein different numbers of light-emitting elements in the same sub-pixel are configured to emit light. In some embodiments, for displaying a first frame image, the method includes controlling the light emission of each sub-pixel to be limited to m auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m ≤ n2. For displaying a second frame image, the light emission of each sub-pixel is controlled to be limited to m' auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m' ≤ n2, and m ≠ m'.

[0170] In one example, to display the first frame image in the first mode, the emission of each sub-pixel is restricted to n1 main light-emitting elements, where m = 0. To display the second frame image in the second mode, the emission of each sub-pixel is restricted to n1 main light-emitting elements and n2 auxiliary light-emitting elements, where m' = n2.

[0171] The inventors of this disclosure have discovered that the display method and complex structure of the light-emitting substrate according to this disclosure can effectively prevent crosstalk between sub-pixels while maintaining excellent light utilization efficiency. This display method includes multiple display modes, wherein different numbers of light-emitting elements in the same sub-pixel are configured to emit light. In some embodiments, for displaying a first frame image, the method includes controlling the light emission of each sub-pixel to be limited to m auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m ≤ n2. For displaying a second frame image, the light emission of each sub-pixel is controlled to be limited to m' auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m' ≤ n2, and m ≠ m'.

[0172] In one example, to display the first frame image in the first mode, the emission of each sub-pixel is restricted to n1 main light-emitting elements, where m = 0. To display the second frame image in the second mode, the emission of each sub-pixel is restricted to n1 main light-emitting elements and n2 auxiliary light-emitting elements, where m' = n2.

[0173] Figure 19A This is a schematic diagram of a light-emitting substrate for image display in a first mode, according to some embodiments of the present disclosure. Figure 19A In the example shown, n1 = 1, n2 = 3. (Refer to...) Figure 19A In the first mode, only n1 main light-emitting elements are configured to emit light, while n2 auxiliary light-emitting elements are configured not to emit light. Figure 19BThis is a schematic diagram of a light-emitting substrate for image display in a second mode, according to some embodiments of this disclosure. (Refer to...) Figure 19B In the second mode, n1 main light-emitting elements and n2 auxiliary light-emitting elements are both configured to emit light.

[0174] This display method can be used in different scenarios depending on the display mode. In one example, the first mode is used when at least a portion of the display panel, including each sub-pixel, is configured to display a monochrome image. (See reference...) Figure 5 The n1 main light-emitting elements are adjacent to the black matrix BM, which prevents crosstalk between the corresponding sub-pixel and the adjacent first sub-pixel on the first side (left side) of the corresponding sub-pixel. Because the n2 auxiliary light-emitting elements do not emit light, and the n1 main light-emitting elements are spaced apart from the adjacent second sub-pixel on the second side (right side), crosstalk between the corresponding sub-pixel and the adjacent second sub-pixel on the second side of the corresponding sub-pixel is also prevented.

[0175] Similarly, the first mode can be used when the first frame of each sub-pixel has high contrast compared to a frame of its neighboring sub-pixels. In one example, the first mode is used when the grayscale of a frame of its neighboring sub-pixels is lower than the grayscale of the first frame of each sub-pixel.

[0176] In another example, when at least a portion of the display panel, including the individual sub-pixels, is configured to display a color image, a second mode is used, for which light utilization efficiency becomes more important. For example, to achieve a brightness of 80 nits in each sub-pixel, n1 main light-emitting elements can be configured to contribute 65 nits, while n2 auxiliary light-emitting elements contribute 15 nits, which can significantly improve the light utilization efficiency in the light-emitting substrate.

[0177] The display mode is not limited to the first mode and the second mode. A total of n2 modes can be implemented in this display method. In some embodiments, a third mode is used. In order to display a third frame image in the third mode, the method includes controlling the emission of each sub-pixel to be limited to m” auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, 1 < m” < n2, and m < m” < m'.

[0178] In one example, n1 = 1 and n2 = 1. Figure 20 This is a cross-sectional view of a light-emitting substrate according to some embodiments of this disclosure. (Refer to...) Figure 20 In some embodiments, the n1 main light-emitting elements are composed of a single main light-emitting element, the n2 auxiliary light-emitting elements are composed of a single auxiliary light-emitting element, the n1 main pixel driving circuits in the pixel driving layer DVL are composed of a single main pixel driving circuit, and the n2 auxiliary pixel driving circuits are composed of a single auxiliary pixel driving circuit.

[0179] Various suitable implementations can be used to implement this display method. In some embodiments, each of the n2 modes can be implemented by controlling n1 main pixel driving circuits and n2 auxiliary pixel driving circuits. In some embodiments, the method includes driving a corresponding main light-emitting element among the n1 main light-emitting elements to emit light through each main pixel driving circuit; and driving a corresponding auxiliary light-emitting element among the n2 auxiliary light-emitting elements to emit light through a corresponding auxiliary pixel driving circuit coupled to each main pixel driving circuit.

[0180] Figure 21 This is a circuit diagram illustrating the structure of a main pixel driving circuit, an auxiliary pixel driving circuit, a main light-emitting element, and an auxiliary light-emitting element according to some embodiments of the present disclosure. Various suitable pixel driving circuits can be used in this light-emitting substrate. Examples of suitable driving circuits for the various main pixel driving circuits and the various auxiliary pixel driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In one example, the various auxiliary pixel driving circuits have a simpler circuit structure compared to the various main pixel driving circuits. In another example, the total number of transistors in the various main pixel driving circuits is greater than the total number of transistors in the various auxiliary pixel driving circuits.

[0181] Reference Figure 21In one example, each main pixel driving circuit rmp is a 3T1C driving circuit. In some embodiments, each main pixel driving circuit rmp includes a first storage capacitor Cst, which includes a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first driving transistor Td, which has a gate coupled to the first capacitor electrode Ce1 of the first storage capacitor Cst and a source coupled to a power supply voltage signal line Vdd; a first transistor T1, which has a gate coupled to a corresponding gate line Gate(n) and configured to receive a first control signal from the corresponding gate line Gate(n), a source coupled to a corresponding first data line DL1 and configured to receive a first data signal from the corresponding first data line DL1, and a drain coupled to the first capacitor electrode Ce1 of the first storage capacitor Cst; a second transistor T2, which has a gate coupled to a detection control gate line Gate_d, a source coupled to the second capacitor electrode Ce2 of the first storage capacitor Cst and the drain of the driving transistor Td, and a drain coupled to a voltage detection unit configured to detect a threshold voltage of the driving transistor Td. In some embodiments, each auxiliary pixel driving circuit rap includes a second storage capacitor Cst', which includes a first capacitor electrode Ce1' and a second capacitor electrode Ce2'; a second driving transistor Td', which has a gate coupled to the first capacitor electrode Ce1' of the second storage capacitor Cst' and a source coupled to the power supply voltage signal line Vdd; and a third transistor T3, which has a gate coupled to the corresponding gate line Gate(n) and configured to receive a first control signal from the corresponding gate line Gate(n), a source coupled to the corresponding second data line DL2 and configured to receive a second data signal from the corresponding second data line DL2, and a drain coupled to the first capacitor electrode Ce1' of the second storage capacitor Cst'.

[0182] exist Figure 21 In the illustrated light-emitting substrate, each main pixel driving circuit (rmp) and each auxiliary pixel driving circuit (rap) is configured to independently provide corresponding data signals from two different data lines, namely, the first data line DL1 and the second data line DL2. To accommodate the auxiliary light-emitting elements and auxiliary pixel driving circuits, the total number of data lines required in the light-emitting substrate increases. Therefore, more source integrated circuits are needed, making the manufacture of the light-emitting substrate more complex.

[0183] Figure 22A This is a circuit diagram illustrating the structure of a main pixel driving circuit, an auxiliary pixel driving circuit, a main light-emitting element, and an auxiliary light-emitting element according to some embodiments of the present disclosure. (Refer to...) Figure 22AIn one example, each main pixel driving circuit rmp is a 6T1C driving circuit. In some embodiments, each main pixel driving circuit rmp includes a first storage capacitor Cst, which includes a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first driving transistor Td, which has a gate coupled to the first capacitor electrode Ce1 and a source coupled to the power supply voltage signal line Vdd; a first transistor T1, which has a gate coupled to the reset control signal line rst(n), a source coupled to the drain of the first driving transistor Td, and a drain coupled to the gate of the first driving transistor Td and the first capacitor electrode Ce1; a second transistor T2, which has a gate coupled to the gate line GL(n), a source coupled to the corresponding first data line DL1, and a drain coupled to the second capacitor electrode Ce2; The three transistors T3 have a gate coupled to the light-emitting control signal line em(n), a source coupled to the constant voltage power supply line Vss, and a drain coupled to the second capacitor electrode Ce2 and the drain of the second transistor T2; the fourth transistor T4 has a gate coupled to the reset control signal line rst(n), a source coupled to the constant voltage power supply line Vss, and a drain coupled to the anode of the corresponding main light-emitting element LE among the n1 main light-emitting elements; and the first light-emitting control transistor Te has a gate coupled to the light-emitting control signal line em(n), a source coupled to the drain of the first driving transistor Td and the source of the first transistor T1, and a drain coupled to the anode of the corresponding main light-emitting element LE and the drain of the fourth transistor T4.

[0184] Reference Figure 22A In one example, each auxiliary pixel driving circuit rap is a 4T1C driving circuit. In some embodiments, each auxiliary pixel driving circuit rap includes a second driving transistor Td' having a source coupled to a power supply voltage signal line Vdd; a second light-emitting control transistor Te' having a gate coupled to a light-emitting control signal line em(n), a source coupled to the drain of the second driving transistor Td', and a drain coupled to the anode of a corresponding auxiliary light-emitting element LE' among n2 auxiliary light-emitting elements; and a switching transistor Ts having a first driving transistor Td coupled to a corresponding main pixel driving circuit rmp and a first storage transistor Ts coupled to the corresponding main pixel driving circuit rmp. The storage capacitor Cst has a source of a first capacitor electrode Ce1 and a drain of a second driving transistor Td' coupled to the gate of the corresponding auxiliary pixel driving circuit rap; a control transistor Tc has a gate coupled to the gate line GL(n), a source coupled to the corresponding second data line DL2, and a drain coupled to the gate of the switching transistor Ts; and a second storage capacitor Cst' has a first capacitor electrode Ce1' coupled to the gate of the switching transistor Ts and the drain of the control transistor Tc, and a second capacitor electrode Ce2' coupled to the constant voltage supply line Vss.

[0185] exist Figure 22A In the illustrated light-emitting substrate, each main pixel driving circuit (rmp) and each auxiliary pixel driving circuit (rap) is configured to independently provide corresponding data signals from two different data lines, namely, the first data line DL1 and the second data line DL2. To accommodate the auxiliary light-emitting elements and auxiliary pixel driving circuits, the total number of data lines required in the light-emitting substrate increases. Therefore, more source integrated circuits are needed, making the manufacture of the light-emitting substrate more complex.

[0186] The inventors of this disclosure have discovered that the scanning circuit described herein can be used to drive a light-emitting substrate having a main light-emitting element and an auxiliary light-emitting element to emit light without increasing the total number of data lines in the light-emitting substrate.

[0187] Figure 22B This is a timing diagram of operating the light-emitting substrate according to some embodiments of this disclosure. (Refer to...) Figure 22B In some embodiments, the image display phase for each sub-pixel includes a first sub-phase t1 and a second sub-phase t2. In the first sub-phase T1, the reset control signal line rst(n) is configured to provide a low voltage signal to the gates of the first transistor T1 and the fourth transistor T4 in each main pixel driving circuit, thereby turning on the first transistor T1 and the fourth transistor T4. The light emission control signal line em(n) is configured to provide a low voltage signal to the gates of the third transistor T3 and the first light emission control transistor Te in each main pixel driving circuit, thereby turning on the third transistor T3 and the first light emission control transistor Te. The light emission control signal line em(n) is configured to provide the same low voltage signal to the gate of the second light emission control transistor Te' in each auxiliary pixel driving circuit, thereby turning on the second light emission control transistor Te' in each auxiliary pixel driving circuit rap. In the first sub-phase t1, the switching transistor Ts in each auxiliary pixel driving circuit rap is turned off. The voltage levels at nodes N1 and N2 are reset to the low voltage level of the constant voltage power supply line Vss.

[0188] In the second sub-stage t2, the reset control signal line rst(n) is configured to provide a low voltage signal to the gates of the first transistor T1 and the fourth transistor T4 in each main pixel driving circuit, thereby turning on the first transistor T1 and the fourth transistor T4. The light emission control signal line em(n) is configured to provide a high voltage signal to the gates of the third transistor T3 and the first light emission control transistor Te in each main pixel driving circuit rmp, thereby turning off the third transistor T3 and the first light emission control transistor Te. The light emission control signal line em(n) is configured to provide the same high voltage signal to the gate of the second light emission control transistor Te' in each auxiliary pixel driving circuit, thereby turning off the second light emission control transistor Te' in each auxiliary pixel driving circuit rap. The gate line GL(n) is configured to provide a low voltage signal to the gate of the second transistor T2 in each main pixel driving circuit rmp, thereby turning on the second transistor T2 in each main pixel driving circuit rmp. The gate line GL(n) is configured to provide the same low voltage signal to the gate of the control transistor Tc in each auxiliary pixel driving circuit rap, thereby turning on the control transistor Tc in each auxiliary pixel driving circuit rap. In the second sub-stage t2, the third transistor T3 in the main pixel driving circuit rmp is turned off. The first transistor T1 and the second transistor T2 in each main pixel driving circuit rmp are turned on. The first light-emitting control transistor Te in each main pixel driving circuit rmp is turned off. Node N1 charges the gate of the first driving transistor Td until the voltage level at the gate of the first driving transistor Td reaches the level of the power supply voltage signal line Vdd plus the threshold voltage of the first driving transistor Td. Node N2 is charged to the level of the data line DL(n). The control transistor Tc in each auxiliary pixel driving circuit rap is turned on, and node N3 is charged to the level of the control signal line CSL. The control signal line CSL is configured to provide a high voltage signal (VGH) or a low voltage signal (VGL).

[0189] In the third sub-stage t3, the light emission control signal line em(n) is configured to provide a low voltage signal to the gates of the third transistor T3 and the first light emission control transistor Te in each main pixel driving circuit rmp, thereby turning on the third transistor T3 and the first light emission control transistor Te. The light emission control signal line em(n) is configured to provide the same low voltage signal to the gates of the second light emission control transistor Te' in each auxiliary pixel driving circuit, thereby turning on the second light emission control transistor Te' in each auxiliary pixel driving circuit rap. The gate line GL(n) is configured to provide a high voltage signal to the gate of the second transistor T2 in each main pixel driving circuit rmp, thereby turning off the second transistor T2 in each main pixel driving circuit rmp. The gate line GL(n) is configured to provide the same high voltage signal to the gates of the control transistor Tc in each auxiliary pixel driving circuit rap, thereby turning off the control transistor Tc in each auxiliary pixel driving circuit rap. The reset control signal line rst(n) is configured to provide a high voltage signal to the gates of the first transistor T1 and the fourth transistor T4 in each main pixel driving circuit, thereby turning off the first transistor T1 and the fourth transistor T4. The voltage level at node N2 changes from the level of data line DL(n) to the level of constant voltage supply line Vss. The voltage level at node N1 changes from Vdd + Vth (the level of power supply voltage signal line Vdd plus the threshold voltage of the first driving transistor Td) to Vdd + Vth + Vss - DL(n) (the level of power supply voltage signal line Vdd plus the threshold voltage of the first driving transistor Td plus the level of constant voltage supply line Vss minus the level of data line DL(n)).

[0190] If the control signal line CSL is configured to provide a high voltage signal (VGH) in the second sub-stage t2, then the switching transistor Ts is turned off in the third sub-stage t3, and the individual auxiliary light-emitting elements LE' do not emit light in the third sub-stage t3.

[0191] If the control signal line CSL is configured to provide a low voltage signal (VGL) in the second sub-stage t2, then the switching transistor Ts is turned on in the third sub-stage t3. The gates of the second driving transistors Td' in each auxiliary pixel driving circuit rap are charged to the same voltage level at node N1, for example, Vdd + Vth + Vss - DL(n), that is, the level of the power supply voltage signal line Vdd plus the threshold voltage of the first driving transistor Td plus the level of the constant voltage power supply line Vss minus the level of the data line DL(n). Because the second light-emitting control transistors Te' in each auxiliary pixel driving circuit rap are turned on in the third sub-stage t3, each auxiliary light-emitting element LE' emits light in the third sub-stage t3.

[0192] In some embodiments, each main pixel driving circuit rmp includes a compensation sub-circuit CSC. Optionally, the compensation sub-circuit CSC includes a first transistor T1 having a gate coupled to a reset control signal line rst(n), a source coupled to the drain of a first driving transistor Td, and a drain of a first capacitor electrode Ce1 coupled to the gate of the first driving transistor Td and the storage capacitor Cst; a second transistor T2 having a gate coupled to a gate line GL(n), a source coupled to a data line DL(n), and a drain of a second capacitor electrode Ce2 coupled to the storage capacitor Cst; a third transistor T3 having a gate coupled to a light emission control signal line em(n), a source coupled to a constant voltage power supply line Vss, and a drain of a second capacitor electrode Ce2 coupled to the storage capacitor Cst and the drain of the second transistor T2; and a fourth transistor T4 having a gate coupled to a reset control signal line rst(n), a source coupled to a constant voltage power supply line Vss, and a drain coupled to the anode of a corresponding main light emission element LE among the n1 main light emission elements.

[0193] In some embodiments, the corresponding auxiliary pixel driving circuit rap and the corresponding main pixel driving circuit rmp share a compensation sub-circuit CSC. In some embodiments, the threshold voltage levels of the first driving transistor Td and the second driving transistor Td' are substantially the same. Optionally, the ratio of the channel width to the channel length of the active layer in the first driving transistor Td is substantially the same as the ratio of the channel width to the channel length of the active layer in the second driving transistor Td'. In one example, the first driving transistor Td and the second driving transistor Td' are fabricated in a light-emitting substrate such that they are close to each other to ensure that their threshold voltage levels are substantially the same. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8%, 6%, 4%, 2%, 1%, 0.5%, 0.1%, 0.05%, and 0.01% of the base value.

[0194] In some embodiments, each auxiliary pixel driving circuit rap includes a selection sub-circuit SSC. Optionally, the selection sub-circuit SSC includes a switching transistor Ts having a source of a first capacitor electrode Ce1 coupled to a first driving transistor Td and a first storage capacitor Cst of the corresponding main pixel driving circuit rmp, and a drain coupled to the gate of a second driving transistor Td' of the corresponding auxiliary pixel driving circuit rap; and a control transistor Tc having a gate coupled to a gate line GL(n), a source coupled to a control signal line CSL, and a drain coupled to the gate of the switching transistor Ts.

[0195] Reference Figure 22AThe gates of the second driving transistor Td' in each auxiliary pixel driving circuit rap and the first driving transistor Td in each main pixel driving circuit rmp are jointly coupled to node N1. As described above, when the control signal line CSL is configured to provide an on-state voltage in the second sub-stage t2, the gates of the second driving transistor Td' in each auxiliary pixel driving circuit rap are charged to the same voltage level at node N1, and each auxiliary light-emitting element LE' emits light in the third sub-stage t3. Therefore, in some embodiments, the display method includes providing the same voltage signal to the gates of the second driving transistor Td' in each auxiliary pixel driving circuit and the gates of the first driving transistor Td in each main pixel driving circuit, thereby driving each auxiliary light-emitting element and each main light-emitting element to emit light.

[0196] In some embodiments, the display method includes providing a control signal to each auxiliary pixel driving circuit to control the transmission of a common voltage signal to the gate of a second driving transistor Td' in each auxiliary pixel driving circuit. Optionally, when the control signal is an on signal, the common voltage signal is transmitted to the gate of the second driving transistor in each auxiliary pixel driving circuit, thereby turning on the second driving transistor. Each auxiliary light-emitting element LE' emits light. Optionally, where the control signal is an off signal, the gate of the second driving transistor in each auxiliary pixel driving circuit is configured not to receive the common voltage signal, and the second driving transistor is turned off. Each auxiliary light-emitting element LE' does not emit light.

[0197] Reference Figure 22A The data signals for each sub-pixel are provided only to the respective main pixel driving circuits rmp, and not to the respective auxiliary pixel driving circuits rap. Specifically, the data signals for each sub-pixel are provided to the source of the second transistor T2 in each main pixel driving circuit rmp. In some embodiments, the display method includes providing data signals to the respective main pixel driving circuits rmp configured to drive each main light-emitting element LE to emit light, but not to the respective auxiliary pixel driving circuits rap configured to drive each auxiliary light-emitting element LE' to emit light.

[0198] In some embodiments, the display method includes providing the same light-emitting control signal to the light-emitting control transistors in each main pixel driving circuit and each auxiliary pixel driving circuit. For example... Figure 22A As shown, the same light emission control signal is provided in phase to the first light emission control transistor Te in each main pixel driving circuit rmp and the second light emission control transistor Te' in each auxiliary pixel driving circuit rap.

[0199] In some embodiments, the display method includes providing the same gate scan signal in phase to a data writing transistor (e.g., a second transistor T2) in each main pixel driving circuit rmp and a control transistor Tc in each auxiliary pixel driving circuit rap.

[0200] Figure 23 This is a circuit diagram illustrating the structure of a main pixel driving circuit, an auxiliary pixel driving circuit, a main light-emitting element, and an auxiliary light-emitting element according to some embodiments of the present disclosure. (Refer to...) Figure 23 In one example, each main pixel driving circuit rmp is a 3T1C driving circuit. In some embodiments, each main pixel driving circuit rmp includes a first storage capacitor Cst, which includes a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first driving transistor Td, which has a gate coupled to the first capacitor electrode Ce1 of the first storage capacitor Cst and a source coupled to a power supply voltage signal line Vdd; a first transistor T1, which has a gate coupled to a corresponding first gate line Gate1(n) and configured to receive a first control signal from the corresponding first gate line Gate1(n), a source coupled to a corresponding data line DL and configured to receive a first data signal Data1 from the corresponding data line DL, and a drain coupled to the first capacitor electrode Ce1 of the first storage capacitor Cst; a second transistor T2, which has a gate coupled to a detection control gate line Gate_d, a source coupled to the second capacitor electrode Ce2 of the first storage capacitor Cst and the drain of the driving transistor Td, and a drain coupled to a voltage detection unit configured to detect a threshold voltage of the driving transistor Td. In some embodiments, each auxiliary pixel driving circuit rap includes a second storage capacitor Cst', which includes a first capacitor electrode Ce1' and a second capacitor electrode Ce2'; a second driving transistor Td', which has a gate coupled to the first capacitor electrode Ce1' of the second storage capacitor Cst' and a source coupled to the power supply voltage signal line Vdd; and a third transistor T3, which has a gate coupled to the corresponding second gate line Gate2(n) and configured to receive a second control signal from the corresponding second gate line Gate2(n), a source coupled to the corresponding data line DL and configured to receive a second data signal Data2 from the corresponding data line DL, and a drain coupled to the first capacitor electrode Ce1' of the second storage capacitor Cst'.

[0201] exist Figure 23In the illustrated light-emitting substrate, each main pixel driving circuit (rmp) and each auxiliary pixel driving circuit (rap) are configured to provide corresponding data signals (first data signal Data1 and second data signal Data2) from the same data line. This same data line is configured to transmit the first data signal Data1 and the second data signal Data2 in a time-division manner. The total number of data lines in the light-emitting substrate remains the same as the total number of data lines in a light-emitting substrate without auxiliary light-emitting elements.

[0202] By controlling the timing of the first control signal and the second control signal transmitted by the corresponding first gate line Gate1(n) and the corresponding second gate line Gate2(n), respectively, the first data signal Data1 and the second data signal Data2 transmitted by the same data line can be written into the corresponding main pixel driving circuit rmp and the corresponding auxiliary pixel driving circuit rap, respectively.

[0203] Figure 24 This is a circuit diagram illustrating the structure of a main pixel driving circuit, an auxiliary pixel driving circuit, a main light-emitting element, and an auxiliary light-emitting element according to some embodiments of the present disclosure. (Refer to...) Figure 24 In one example, each main pixel driving circuit rmp is a 6T1C driving circuit. In some embodiments, each main pixel driving circuit rmp includes a first storage capacitor Cst, which includes a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first driving transistor Td, which has a gate coupled to the first capacitor electrode Ce1 and a source coupled to the power supply voltage signal line Vdd; a first transistor T1, which has a gate coupled to the reset control signal line rst(n), a source coupled to the drain of the first driving transistor Td, and a drain coupled to the gate of the first driving transistor Td and the first capacitor electrode Ce1; and a second transistor T2, which has a gate coupled to the corresponding first gate line Gate1(n), a source coupled to the corresponding data line DL, and a drain coupled to the second capacitor electrode Ce2. The third transistor T3 has a gate coupled to the light-emitting control signal line em(n), a source coupled to the constant voltage power supply line Vss, and a drain coupled to the second capacitor electrode Ce2 and the drain of the second transistor T2; the fourth transistor T4 has a gate coupled to the reset control signal line rst(n), a source coupled to the constant voltage power supply line Vss, and a drain coupled to the anode of the corresponding main light-emitting element LE among the n1 main light-emitting elements; and the first light-emitting control transistor Te has a gate coupled to the light-emitting control signal line em(n), a source coupled to the drain of the first driving transistor Td and the source of the first transistor T1, and a drain coupled to the anode of the corresponding main light-emitting element LE and the drain of the fourth transistor T4.

[0204] Reference Figure 24In one example, each auxiliary pixel driving circuit rap is a 4T1C driving circuit. In some embodiments, each auxiliary pixel driving circuit rap includes a second driving transistor Td' having a source coupled to a power supply voltage signal line Vdd; a second light-emitting control transistor Te' having a gate coupled to a light-emitting control signal line em(n), a source coupled to the drain of the second driving transistor Td', and a drain coupled to the anode of a corresponding auxiliary light-emitting element LE' among n2 auxiliary light-emitting elements; and a switching transistor Ts having a first driving transistor Td coupled to a corresponding main pixel driving circuit rmp and a first storage capacitor of the corresponding main pixel driving circuit rmp. The source of the first capacitor electrode Ce1 of Cst, and the drain of the second driving transistor Td' coupled to the gate of the corresponding auxiliary pixel driving circuit rap; the control transistor Tc, which has a gate coupled to the corresponding second gate line Gate2(n), a source coupled to the corresponding second data line DL2, and a drain coupled to the gate of the switching transistor Ts; the second storage capacitor Cst', which has a first capacitor electrode Ce1' coupled to the gate of the switching transistor Ts and the drain of the control transistor Tc, and a second capacitor electrode Ce2' coupled to the constant voltage power supply line Vss.

[0205] exist Figure 24 In the illustrated light-emitting substrate, each main pixel driving circuit (rmp) and each auxiliary pixel driving circuit (rap) are configured to provide corresponding data signals (first data signal Data1 and second data signal Data2) from the same data line. This same data line is configured to transmit the first data signal Data1 and the second data signal Data2 in a time-division manner. The total number of data lines in the light-emitting substrate remains the same as the total number of data lines in a light-emitting substrate without auxiliary light-emitting elements.

[0206] By controlling the timing of the first control signal and the second control signal transmitted by the corresponding first gate line Gate1(n) and the corresponding second gate line Gate2(n), respectively, the first data signal Data1 and the second data signal Data2 transmitted by the same data line can be written into the corresponding main pixel driving circuit rmp and the corresponding auxiliary pixel driving circuit rap, respectively.

[0207] See Figure 23 , Figure 24 , Figures 1 to 14 The first control signal transmitted by the corresponding first gate line Gate1(n) can be from... Figures 1 to 14 The first control signal G1(n) output by the scanning unit depicted in the figure, and the second control signal transmitted by the corresponding second gate line Gate2(n) can be from... Figures 1 to 14 The second control signal G2(n) output by the scanning unit is depicted in the figure.

[0208] In some embodiments, the scanning unit is configured to transmit a first control signal G1(n) and a second control signal G2(n) to each main pixel driving circuit and each auxiliary pixel driving circuit in a row of sub-pixels. Optionally, the first control signal G1(n) and the second control signal G2(n) are different from each other. (See reference...) Figure 3 and Figure 7 At different stages (e.g., at stage 5 t5 and stage 7 t7 respectively), a first control signal G1(n) and a second control signal G2(n) are provided. Data is written to transistors (e.g., Figure 23 T1 and T3 in the middle, or Figure 24 T2 and Tc in the data are turned on at different times to utilize the same data line (e.g., Figure 23 and Figure 24 The data line DL in the middle provides the first data signal Data1 and the second data signal Data2 to the corresponding main pixel driving circuit rmp and the corresponding auxiliary pixel driving circuit rap.

[0209] In some embodiments, the scanning unit is configured to transmit a first control signal G1(n) to the corresponding first gate line Gate1(n), but not to transmit a second control signal G2(n) to the corresponding second gate line Gate2(n). (Refer to...) Figure 4 and Figure 8 In stage 7 t7, the first control signal G1(n) is provided, but the second control signal is not provided. See also Figure 23 and Figure 24 The data is written to the transistor in the corresponding main pixel driving circuit rmp (e.g., Figure 23 T1 in, or Figure 24 T2 in the first control signal G1(n) is turned on, but the data writing transistor in the corresponding auxiliary pixel driving circuit rap (e.g., Figure 23 T3 in, or Figure 24 Tc) remains off. The first data signal Data1 is written to the corresponding main pixel driving circuit rmp; however, no data signal is written to the corresponding auxiliary pixel driving circuit rap. As a result, only the main light-emitting elements LE emit light, while the auxiliary light-emitting elements LE' do not emit light.

[0210] In some embodiments, the scanning unit is configured to transmit a first control signal G1(n) and a second control signal G2(n) to the corresponding main pixel driving circuit and the corresponding auxiliary pixel driving circuit in a row of sub-pixels. Optionally, the first control signal G1(n) and the second control signal G2(n) are different from each other. (See reference...) Figure 5 and Figure 9 In the same stage (e.g., in the seventh stage t7), a first control signal G1(n) and a second control signal G2(n) are provided. See reference... Figure 21 and Figure 22A The data write transistors in the corresponding main pixel driving circuit (rmp) and the corresponding auxiliary pixel driving circuit (rap) are coupled to different data lines, for example, the corresponding first data line DL1 and the corresponding second data line DL2. The data write transistors (e.g., Figure 21 T1 and T3 in the middle, or Figure 22A T2 and Tc in the data are turned on at the same time to use two different data lines (e.g., Figure 21 and Figure 22A The corresponding first data line DL1 and the corresponding second data line DL2 simultaneously provide the first data signal Data1 and the second data signal Data2 to the corresponding main pixel driving circuit rmp and the corresponding auxiliary pixel driving circuit rap.

[0211] In some embodiments, the scanning circuit and the light-emitting substrate are implemented in a display panel having multiple display sub-regions, which have at least two different resolutions. The scanning circuit described herein can be used to drive the multiple display sub-regions to emit light. Optionally, in the display sub-region with higher resolution, a first control signal G1(n) and a second control signal G2(n) are provided to two rows of sub-pixels in the high-resolution display sub-region. Optionally, in the display sub-region with lower resolution, the first control signal G1(n) is provided to one row of the two rows of sub-pixels in the low-resolution display sub-region. The other row of sub-pixels in the low-resolution display sub-region is not provided with the second control signal G2(n). In one example, Figure 3 , Figure 5 , Figure 7 or Figure 9 The operating method shown can be used to display sub-regions at high resolution, while Figure 4 or Figure 8 The operation method shown can be used to display sub-regions at low resolution.

[0212] Figure 25 This is a circuit diagram illustrating the structure of a main pixel driving circuit, an auxiliary pixel driving circuit, a second auxiliary pixel driving circuit, a main light-emitting element, an auxiliary light-emitting element, and a second auxiliary light-emitting element according to some embodiments of the present disclosure. Figure 25 In the example shown, n1 = 1 and n2 = 2. The structures of each main pixel driving circuit rmp and each auxiliary pixel driving circuit rap are similar to... Figure 22A The same as shown. The second auxiliary pixel driving circuit rap' is configured to drive the second auxiliary light-emitting element LE" to emit light.

[0213] Reference Figure 25In one example, the second auxiliary pixel driving circuit rap' is a 4T1C driving circuit. In some embodiments, the second auxiliary pixel driving circuit rap' includes a third driving transistor Td'' having a source coupled to the power supply voltage signal line Vdd; a third light-emitting control transistor Te'' having a gate coupled to the light-emitting control signal line em(n), a source coupled to the drain of the third driving transistor Td'', and a drain coupled to the anode of the second auxiliary light-emitting element LE'' among the n2 auxiliary light-emitting elements; and a switching transistor Ts' having a first driving transistor Td coupled to each main pixel driving circuit rmp and a first storage transistor of each main pixel driving circuit rmp. The first capacitor electrode Ce1 of the container Cst has a source and a drain of the third driving transistor Td” coupled to the gate of the second auxiliary pixel driving circuit rap’; the control transistor Tc’ has a gate coupled to the gate line GL(n), a source coupled to the second control signal line CSL’, and a drain coupled to the gate of the switching transistor Ts’; the third storage capacitor Cst” has a first capacitor electrode Ce1” coupled to the gate of the switching transistor Ts’ and the drain of the control transistor Tc’, and a second capacitor electrode Ce2 coupled to the constant voltage power supply line Vss.

[0214] In some embodiments, the total number of control signal lines configured to transmit signals to each sub-pixel is n². The illumination of the n² auxiliary light-emitting elements can be controlled independently relative to each individual auxiliary light-emitting element. This depends on the individual control signals (CSL1,...,CSL) transmitted to the individual auxiliary pixel driving circuits. i ,...,CSL n2 (1 ≤ i ≤ n²), each of the n² auxiliary light-emitting elements can be turned on or off independently. When CSL i When the provided i-th control signal is a turn-on signal, the same voltage signal (Vdd+Vth+Vss-DL(n)) is transmitted to the gate of the driving transistor in the i-th auxiliary pixel driving circuit, thereby turning on the driving transistor in the i-th auxiliary pixel driving circuit. When CSL i When the provided i-th control signal is a cutoff signal, the gate of the driving transistor in the i-th auxiliary pixel driving circuit is configured not to receive the same voltage signal, and the driving transistor in the i-th auxiliary pixel driving circuit is cut off.

[0215] In some embodiments, the gates of the second driving transistors in the n2 auxiliary pixel driving circuits and the gates of the first driving transistors in the n1 main pixel driving circuits are jointly coupled to node N1. The display method includes providing the same voltage signal (Vdd+Vth+Vss-DL(n)) to the gates of the second driving transistors in the n2 auxiliary pixel driving circuits and the gates of the first driving transistors in the n1 main pixel driving circuits.

[0216] In some embodiments, data signals for each sub-pixel are provided only to each main pixel driving circuit rmp, and not to the n2 auxiliary pixel driving circuits. Specifically, data signals for each sub-pixel are provided to the source of the second transistor T2 in each main pixel driving circuit rmp. In some embodiments, the display method includes providing data signals to each main pixel driving circuit rmp configured to drive each main light-emitting element LE to emit light, and not providing data signals to the n2 auxiliary pixel driving circuits configured to drive the n2 auxiliary light-emitting elements to emit light.

[0217] In some embodiments, the same light emission control signal is provided to the first light emission control transistor in each main pixel driving circuit and the second light emission control transistor in each of the n2 auxiliary pixel driving circuits.

[0218] In some embodiments, the same gate scan signal is provided to the data write transistors in each main pixel driving circuit and the control transistors in n2 auxiliary pixel driving circuits.

[0219] The n1 main light-emitting elements and n2 auxiliary light-emitting elements can have various suitable areas. In one example, the n1 main light-emitting elements and n2 auxiliary light-emitting elements have the same uniform area. In another example, the area of ​​each of the n1 main light-emitting elements is larger than the area of ​​each of the n2 auxiliary light-emitting elements. In yet another example, the area of ​​each of the n1 main light-emitting elements is smaller than the area of ​​each of the n2 auxiliary light-emitting elements.

[0220] Therefore, in some embodiments, the display method includes providing a display panel comprising a plurality of sub-pixels, each sub-pixel comprising n1 main light-emitting regions and n2 auxiliary light-emitting regions, where n1≥1 and n2≥1. Optionally, for displaying a first frame image, the light emission of each sub-pixel is controlled to be limited to m auxiliary light-emitting regions among the n1 main light-emitting regions and n2 auxiliary light-emitting regions, where 0≤m≤n2. Optionally, for displaying a second frame image, the light emission of each sub-pixel is controlled to be limited to m' auxiliary light-emitting regions among the n1 main light-emitting regions and n2 auxiliary light-emitting regions, where 0≤m'≤n2 and m≠m'.

[0221] In some embodiments, in order to display the first frame image in the first mode, the emission of each sub-pixel is restricted to n1 main emission regions, where m = 0. Optionally, in order to display the second frame image in the second mode, the emission of each sub-pixel is restricted to n1 main emission regions and n2 auxiliary emission regions, where m' = n2.

[0222] In some embodiments, in a first mode, at least a portion of the display panel including the respective sub-pixels is configured to display a monochrome image, or the first frame image has high contrast compared to a frame image among adjacent sub-pixels. Optionally, in a second mode, at least a portion of the display panel including the respective sub-pixels is configured to display a color image.

[0223] In some embodiments, the display method further includes: in order to display a third frame image in a third mode, controlling the emission of each sub-pixel to be limited to m” auxiliary light-emitting regions among n1 main light-emitting regions and n2 auxiliary light-emitting regions, where 1 < m” < n2 and m < m” < m'.

[0224] In another aspect, this disclosure also provides a method for operating a display device, the display device including a light-emitting substrate and a scanning circuit configured to provide control signals to the light-emitting substrate. In some embodiments, the method includes providing at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal to each of a plurality of scanning units of the scanning circuit; outputting the effective voltage of the first clock signal as a first control signal to the light-emitting substrate; and outputting the effective voltage of the third clock signal as a second control signal to the light-emitting substrate.

[0225] In some embodiments, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are independent of each other. For example, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are generated independently and transmitted to the scanning circuit independently through separate signal lines. Optionally, at least two of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are different signals. Optionally, all four of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are different signals.

[0226] In some embodiments, the first control signal and the second control signal are independent of each other; for example, the first control signal and the second control signal are generated independently and transmitted to the scanning circuit independently through separate signal lines. Optionally, the first control signal and the second control signal are different signals.

[0227] In some embodiments, outputting the first control signal and the second control signal includes providing a first clock signal to the source of the twelfth transistor; providing a third clock signal to the source of the fourteenth transistor; and coupling the gates of the twelfth transistor and the fourth transistor to the first node.

[0228] In some embodiments, the first control signal and the second control signal are out of phase with respect to each other. Optionally, the light-emitting substrate includes a plurality of sub-pixels. Each sub-pixel in the plurality of sub-pixels includes at least one main light-emitting element driven by a main pixel driving circuit and at least one auxiliary light-emitting element driven by an auxiliary pixel driving circuit. Optionally, the method further includes providing a first control signal to the main pixel driving circuit; providing a second control signal to the auxiliary pixel driving circuit; providing a first data signal to the main pixel driving circuit; and providing a second data signal to the auxiliary pixel driving circuit. Optionally, a single data line connecting the source integrated circuit and the light-emitting substrate is used to provide the first data signal and the second data signal. In one example, at least a portion of the data line that simultaneously transmits the first data signal and the second data signal is a data line that extends at least partially in the display area. In another example, a single data line connecting the source integrated circuit and the light-emitting substrate is used to provide n1 first data signals for n1 main pixel driving circuits and n2 second data signals for n2 auxiliary pixel driving circuits. In another example, at least a portion of the data lines that simultaneously transmit n1 first data signals for n1 main pixel driving circuits and n2 second data signals for n2 auxiliary pixel driving circuits are data lines that extend at least partially in the display area.

[0229] In some embodiments, the method further includes adjusting a third clock signal to have a constant invalid voltage level; and outputting the invalid voltage of the third clock signal to the light-emitting substrate.

[0230] In some embodiments, the light-emitting substrate includes a plurality of sub-pixels. Each sub-pixel includes at least one main light-emitting element driven by a main pixel driving circuit and at least one auxiliary light-emitting element driven by an auxiliary pixel driving circuit. Optionally, the method further includes providing a first control signal to the main pixel driving circuit and providing an invalid voltage of a third clock signal to the auxiliary pixel driving circuit.

[0231] In some embodiments, the first control signal and the second control signal are in phase with respect to each other.

[0232] In some embodiments, the method includes providing a control signal to a high-resolution sub-region of the light-emitting substrate; and providing a control signal to a low-resolution sub-region of the light-emitting substrate.

[0233] In some embodiments, providing control signals to a high-resolution sub-region of the light-emitting substrate includes outputting an effective voltage of a first clock signal as a first control signal to a first adjacent row sub-pixel in the high-resolution sub-region; and outputting an effective voltage of a third clock signal as a second control signal to a second adjacent row sub-pixel in the high-resolution sub-region. Optionally, the first control signal output to the first adjacent row sub-pixel in the high-resolution sub-region and the second control signal output to the second adjacent row sub-pixel in the high-resolution sub-region are out of phase with each other. Optionally, the first control signal output to the first adjacent row sub-pixel in the high-resolution sub-region and the second control signal output to the second adjacent row sub-pixel in the high-resolution sub-region are in phase with each other.

[0234] In some embodiments, providing a control signal to a low-resolution sub-region of the light-emitting substrate includes outputting an effective voltage of a first clock signal as a first control signal to a third adjacent row sub-pixel in the low-resolution sub-region; adjusting a third clock signal to have a constant invalid voltage level; and outputting the invalid voltage of the third clock signal to a fourth adjacent row sub-pixel in the low-resolution sub-region.

[0235] In another aspect, this disclosure provides a light-emitting substrate having a plurality of sub-pixels. In some embodiments, each sub-pixel of the plurality of sub-pixels includes n1 main light-emitting elements; n1 main pixel driving circuits configured to drive the n1 main light-emitting elements to emit light; n2 auxiliary light-emitting elements; and n2 auxiliary pixel driving circuits configured to drive the n2 auxiliary light-emitting elements to emit light. Optionally, n1 ≥ 1 and n2 ≥ 1. Optionally, n1 = 1 and n2 = 1. Optionally, each main pixel driving circuit in the n1 main pixel driving circuits includes a first storage capacitor, a first driving transistor, a first light-emitting control transistor, and a compensation sub-circuit. Optionally, each auxiliary pixel driving circuit in the n2 auxiliary pixel driving circuits includes a second storage capacitor, a second driving transistor, a second light-emitting control transistor, and a selection sub-circuit. Optionally, the threshold voltage levels of the first driving transistor and the second driving transistor are substantially the same.

[0236] Reference Figure 22A In some embodiments, the gates of the second driving transistors Td' in each of the n2 auxiliary pixel driving circuits rap and the gates of the first driving transistors Td in each of the n1 main pixel driving circuits rmp are coupled to the same node (N1 node). Optionally, the gates of the first driving transistors in the n1 main pixel driving circuits and the gates of the second driving transistors in the n2 auxiliary pixel driving circuits are jointly coupled to the same node. In some embodiments, each main pixel driving circuit includes a first storage capacitor Cst, which includes a first capacitor electrode Ce1 coupled to the same node.

[0237] In some embodiments, the gate of the first driving transistor Td and the first capacitor electrode Ce1 of the first storage capacitor Cst are connected to the first node N1. Optionally, the gate of the second driving transistor Td' and the first capacitor electrode Ce1' of the second storage capacitor Cst' are connected to the first node N1 through a switching transistor Ts.

[0238] In some embodiments, each auxiliary pixel driving circuit rap includes a switching transistor Ts coupled to the gate of the second driving transistor Td' of each auxiliary pixel driving circuit rap and coupled to the same node (node ​​N1). Optionally, the switching transistor Ts is configured to control the gate of the second driving transistor Td' of each auxiliary pixel driving circuit rap to be electrically connected or disconnected from the same node.

[0239] In some embodiments, each auxiliary pixel driving circuit rap includes a control transistor Tc coupled to a switching transistor Ts of each auxiliary pixel driving circuit rap. The source of the control transistor Tc of each auxiliary pixel driving circuit rap is coupled to a control signal line CSL. The drain of the control transistor Tc of each auxiliary pixel driving circuit rap is coupled to the gate of the switching transistor Ts of each auxiliary pixel driving circuit rap. The gate of the control transistor Tc of each auxiliary pixel driving circuit rap is coupled to a gate line GL(n). The gate of the control transistor Tc of each auxiliary pixel driving circuit rap is provided with the same gate scan signal provided to the data write transistor (e.g., T2) in each main pixel driving circuit rmp.

[0240] In some embodiments, the control signal line CSL is configured to provide a control signal. When the control signal is an ON signal, the switching transistor Ts is ON, allowing the gates of the second driving transistors Td' in each auxiliary pixel driving circuit rap and the gates of the first driving transistors Td in each main pixel driving circuit rmp to receive the same voltage signal at the same node. When the control signal is an OFF signal, the switching transistor Ts is OFF, disconnecting the gates of the second driving transistors Td' in each auxiliary pixel driving circuit rap from the same node.

[0241] In some embodiments, the light-emitting substrate includes n² control signal lines configured to independently send control signals to n² auxiliary pixel driving circuits. The n² control signal lines (CSL1,...,CSL...) i ,...,CSL n2 Each of the following (1≤i≤n2) can independently send a separate control signal to a separate auxiliary pixel driving circuit. This depends on the individual control signals (CSL1,...,CSL2) transmitted to the individual auxiliary pixel driving circuit. i,...,CSL n2 (1 ≤ i ≤ n²), each of the n² auxiliary light-emitting elements can be independently turned on or off. The illumination of the n² auxiliary light-emitting elements can be independently controlled relative to each individual auxiliary light-emitting element. When CSL i When the provided i-th control signal is a turn-on signal, the same voltage signal (Vdd+Vth+Vss-DL(n)) is transmitted to the gate of the driving transistor in the i-th auxiliary pixel driving circuit, thereby turning on the driving transistor in the i-th auxiliary pixel driving circuit. When CSL i When the provided i-th control signal is a cutoff signal, the gate of the driving transistor in the i-th auxiliary pixel driving circuit is configured not to receive the same voltage signal, and the driving transistor in the i-th auxiliary pixel driving circuit is cut off.

[0242] In some embodiments, each auxiliary pixel driving circuit rap further includes a second storage capacitor Cst', which includes a first capacitor electrode Ce1' and a second capacitor electrode Ce2'. The first capacitor electrode Ce1' of the second storage capacitor Cst' is coupled to the gate of the switching transistor Ts and the drain of the control transistor Tc; the second capacitor electrode Ce2' of the second storage capacitor Cst' is coupled to the constant voltage power supply line Vss.

[0243] In some embodiments, each main pixel driving circuit rmp includes a compensation sub-circuit CSC. Optionally, the compensation sub-circuit CSC includes a first transistor T1 having a gate coupled to a reset control signal line rst(n), a source coupled to the drain of a first driving transistor Td, and a drain of a first capacitor electrode Ce1 coupled to the gate of the first driving transistor Td and the storage capacitor Cst; a second transistor T2 having a gate coupled to a gate line GL(n), a source coupled to a data line DL(n), and a drain of a second capacitor electrode Ce2 coupled to the storage capacitor Cst; a third transistor T3 having a gate coupled to a light emission control signal line em(n), a source coupled to a constant voltage power supply line Vss, and a drain of a second capacitor electrode Ce2 coupled to the storage capacitor Cst and the drain of the second transistor T2; and a fourth transistor T4 having a gate coupled to a reset control signal line rst(n), a source coupled to a constant voltage power supply line Vss, and a drain coupled to the anode of each of the n1 main light emission elements LE.

[0244] In some embodiments, the auxiliary pixel driving circuits rap and the main pixel driving circuits rmp share a compensation sub-circuit CSC. In some embodiments, the threshold voltage levels of the first driving transistor Td and the second driving transistor Td' are substantially the same. Optionally, the ratio of the channel width to the channel length of the active layer in the first driving transistor Td is substantially the same as the ratio of the channel width to the channel length of the active layer in the second driving transistor Td'. In one example, the first driving transistor Td and the second driving transistor Td' are fabricated in a light-emitting substrate such that they are close to each other to ensure that their threshold voltage levels are substantially the same.

[0245] In some embodiments, each auxiliary pixel driving circuit rap includes a selection sub-circuit SSC. Optionally, the selection sub-circuit SSC includes a switching transistor Ts having a source of a first capacitor electrode Ce1 coupled to a first driving transistor Td and a first storage capacitor Cst of each main pixel driving circuit rmp, and a drain coupled to the gate of a second driving transistor Td' coupled to the gate of each auxiliary pixel driving circuit rap; and a control transistor Tc having a gate coupled to a gate line GL(n), a source coupled to a control signal line CSL, and a drain coupled to the gate of the switching transistor Ts.

[0246] In some embodiments, n1 main light-emitting elements and n2 auxiliary light-emitting elements are configured to emit light of the same color. Optionally, the light of the same color has a wavelength in the range of 435 nm to 480 nm, such as 435 nm to 440 nm, 440 nm to 445 nm, 445 nm to 450 nm, 450 nm to 455 nm, 455 nm to 460 nm, 460 nm to 465 nm, 465 nm to 470 nm, 470 nm to 475 nm, or 475 nm to 480 nm. In one example, the light of the same color has a wavelength in the range of 450 nm to 460 nm.

[0247] In some embodiments, each of the n1 main light-emitting elements has a first light-emitting region; and each of the n2 auxiliary light-emitting elements has a second light-emitting region. Optionally, the first light-emitting region is larger than the second light-emitting region.

[0248] In some embodiments, n1 main light-emitting elements have a first combined light-emitting region; and n2 auxiliary light-emitting elements have a second combined light-emitting region. Optionally, the first combined light-emitting region is larger than the second combined light-emitting region.

[0249] In another aspect, the present invention provides a display panel. In some embodiments, the display panel includes a light-emitting substrate manufactured as described herein or by the methods described herein, and a color filter. (See also...) Figure 17, Figure 18 and Figure 20 In some embodiments, the display panel further includes a color filter, which comprises a plurality of color filter blocks (CFBs). The orthographic projection of each of the plurality of color filter blocks (CFBs) on the substrate BS at least partially overlaps with the orthographic projections of n1 main light-emitting elements on the substrate BS, and at least partially overlaps with the orthographic projections of n2 auxiliary light-emitting elements on the substrate BS.

[0250] Reference Figure 17 , Figure 18 and Figure 20 In some embodiments, the display panel further includes a first encapsulation layer EN1 encapsulating multiple light-emitting elements and a second encapsulation layer EN2 encapsulating multiple color filter blocks CFB.

[0251] Reference Figure 17 , Figure 18 and Figure 20 In some embodiments, the display panel also includes a cathode CD extending throughout a plurality of subpixels.

[0252] In some embodiments, one or more auxiliary light-emitting elements may be shared by two adjacent color filters in a plurality of color filters (CFBs). Figure 26 This is a cross-sectional view of a light-emitting substrate according to some embodiments of this disclosure. (Refer to...) Figure 26 The light-emitting substrate also includes a common light-emitting element SLE shared between an individual sub-pixel Sp and an adjacent sub-pixel Asp, and a common pixel driving circuit. The common pixel driving circuit is configured to drive the common light-emitting element SLE to emit light. The orthographic projection of the common light-emitting element SLE on the substrate BS at least partially overlaps with the orthographic projection of an individual color filter block RCB among the plurality of color filter blocks CFB on the substrate BS, and at least partially overlaps with the orthographic projection of an adjacent color filter block ACB among the plurality of color filter blocks CFB on the substrate BS. The individual color filter block RCB and the adjacent color filter block ACB are adjacent to each other. The individual color filter block RCB corresponds to an individual sub-pixel Sp, and the adjacent color filter block ACB corresponds to an adjacent sub-pixel Asp.

[0253] In one example, a common pixel driving circuit is coupled to each main pixel driving circuit in a separate sub-pixel Sp, and the gate of the driving transistor in the common pixel driving circuit is coupled to the gate of the first driving transistor in the main pixel driving circuit of the separate sub-pixel Sp.

[0254] In another example, a shared pixel driving circuit is coupled to a main pixel driving circuit in an adjacent sub-pixel Asp, and the gate of the driving transistor in the shared pixel driving circuit is coupled to the gate of the first driving transistor in the main pixel driving circuit in the adjacent sub-pixel Asp.

[0255] Figure 27This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 27 In some embodiments, the color filter includes a plurality of color filter blocks CFB, each located in a plurality of light-transmitting regions TA. n1 main light-emitting elements have a first light-emitting region LA1. n2 auxiliary light-emitting elements have a second light-emitting region LA2. In some embodiments, each light-transmitting region in the plurality of light-transmitting regions TA at least partially overlaps with the first light-emitting region of the n1 main light-emitting elements and at least partially overlaps with the second light-emitting region of the n2 auxiliary light-emitting elements.

[0256] In some embodiments, the display panel further includes a color conversion layer (CCL). Optionally, the color conversion layer CCL includes a plurality of color conversion blocks CCP1 for a first color, a plurality of color conversion blocks CCP2 for a second color, and a plurality of light-transmitting blocks, and optionally includes a plurality of light-transmitting blocks TP. In one example, the first color is red and the second color is green. The plurality of light-transmitting blocks TP do not convert light into different wavelengths. In another example, the plurality of light-transmitting blocks TP correspond to blue sub-pixels.

[0257] In some embodiments, the display panel includes a first capping layer CAP1 on a light-emitting substrate; a color conversion layer CCL located on the side of the first capping layer CAP1 away from the light-emitting substrate; and a second capping layer CAP2 located on the side of the color conversion layer CCL away from the first capping layer CAP1. Optionally, a color filter is located on the side of the second capping layer CAP2 away from the color conversion layer CCL. The first capping layer CAP1 and the second capping layer CAP2 may be made of inorganic insulating materials, such as silicon dioxide, silicon nitride, and silicon oxynitride.

[0258] Figure 28A This is a plan view of the color filter and light-emitting element according to some embodiments of this disclosure. (Refer to...) Figure 28A Each color filter in a CFB is located in a corresponding light-transmitting region of multiple light-transmitting regions (e.g., Figure 27 In some embodiments, a corresponding light-transmitting region among the plurality of light-transmitting regions at least partially overlaps with the light-emitting regions of the n1 main light-emitting elements and at least partially overlaps with the light-emitting regions of the n2 auxiliary light-emitting elements. Optionally, a corresponding light-transmitting region among the plurality of light-transmitting regions completely covers the light-emitting regions of the n1 main light-emitting elements and at least partially overlaps with the light-emitting regions of the n2 auxiliary light-emitting elements.

[0259] In some embodiments, the orthographic projection of each color filter block in the plurality of color filter blocks (CFBs) onto the substrate at least partially overlaps with the orthographic projections of n1 main light-emitting elements onto the substrate, and at least partially overlaps with the orthographic projections of n2 auxiliary light-emitting elements onto the substrate. Optionally, the orthographic projection of each color filter block in the plurality of color filter blocks (CFBs) onto the substrate completely covers the orthographic projections of n1 main light-emitting elements onto the substrate, and at least partially overlaps with the orthographic projections of n2 auxiliary light-emitting elements onto the substrate.

[0260] In some embodiments, the center C1 of the orthographic projection of the n1 main light-emitting elements on the substrate substantially overlaps with the center C2 of the orthographic projection of each of the plurality of color filter blocks on the substrate. As used herein, the term “substantially overlap” means that two points (e.g., “centers”) are spaced no more than 1000 μm apart, for example, no more than 900 μm, no more than 800 μm, no more than 700 μm, no more than 600 μm, no more than 500 μm, no more than 400 μm, no more than 300 μm, no more than 200 μm, no more than 100 μm, no more than 90 μm, no more than 80 μm, no more than 70 μm, no more than 60 μm, no more than 50 μm, no more than 40 μm, no more than 30 μm, no more than 20 μm, no more than 10 μm, no more than 5 μm, no more than 4 μm, no more than 3 μm, no more than 2 μm, or no more than 1 μm.

[0261] Figure 28B This is a plan view of the color filter and light-emitting element according to some embodiments of this disclosure. (Refer to...) Figure 28B Each of the multiple light-transmitting regions completely covers the light-emitting areas of the n1 main light-emitting elements and completely covers the light-emitting areas of the n2 auxiliary light-emitting elements. Optionally, the orthographic projection of each color filter block (CFB) on the substrate completely covers the orthographic projection of the n1 main light-emitting elements and completely covers the orthographic projection of the n2 auxiliary light-emitting elements on the substrate. Optionally, the center C1 of the orthographic projection of the n1 main light-emitting elements on the substrate substantially overlaps with the center C2 of the orthographic projection of each color filter block on the substrate. Figure 28B In this system, the light-emitting area of ​​each main light-emitting element is larger than the light-emitting area of ​​each auxiliary light-emitting element.

[0262] Figure 28C This is a plan view of the color filter and light-emitting element according to some embodiments of this disclosure. (Refer to...) Figure 28C The light-emitting areas of each main light-emitting element are basically the same as the light-emitting areas of each auxiliary light-emitting element.

[0263] As used in this article, the term "center" refers to, for example, the geometric center (especially for regular shapes), the approximate geometric center, or the equivalent center, such as the centroid or center of mass (especially for irregular shapes).

[0264] In another aspect, the present invention provides a display device including a scanning circuit and a light-emitting substrate manufactured by the methods described herein or by means thereof, the scanning circuit being configured to provide control signals to the light-emitting substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a liquid crystal display (LCD) device.

[0265] In some embodiments, the display device includes one or more processors configured to determine a display mode for each of the plurality of sub-pixels in the display device. In some embodiments, the one or more processors are configured to receive data signals from printed circuitry for displaying an image on the display panel, and the one or more processors are further configured to determine, based on the data signals, whether at least a portion of the display panel including the respective sub-pixels is configured to display a monochrome image. Optionally, when it is determined that at least a portion of the display panel including the respective sub-pixels is configured to display a monochrome image, the one or more processors are configured to send one or more signals to each sub-pixel to control the light emission of each sub-pixel to be limited to m auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m ≤ n2.

[0266] In some embodiments, one or more processors are configured to receive a data signal of a frame image, and the one or more processors are further configured to determine, based on the data signal, whether the first frame image of each sub-pixel has high contrast compared to a frame image of its neighboring sub-pixels. Optionally, when it is determined that the first frame image of each sub-pixel has high contrast compared to the frame image of its neighboring sub-pixels, the one or more processors are configured to send one or more signals to each sub-pixel to control the emission of each sub-pixel to be limited to m auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m ≤ n2.

[0267] In some embodiments, one or more processors are configured to receive a data signal of a frame of image, and the one or more processors are further configured to determine whether at least a portion of the display panel including each sub-pixel is configured to display a color image. Optionally, when it is determined that at least a portion of the display panel including each sub-pixel is configured to display a color image, the one or more processors are configured to send one or more signals to each sub-pixel to control the light emission of each sub-pixel to be limited to m' auxiliary light-emitting elements out of n1 main light-emitting elements and n2 auxiliary light-emitting elements, where 0 ≤ m' ≤ n2, and m ≠ m'.

[0268] In some embodiments, one or more processors are configured to receive a data signal of a frame of image, and the one or more processors are further configured to transmit one or more signals to each sub-pixel to control the light emission of each sub-pixel to be limited to m” auxiliary light-emitting elements among n1 main light-emitting elements and n2 auxiliary light-emitting elements, 1 < m” < n2, and m < m” < m'.

[0269] In another aspect, the present invention provides a method for manufacturing a scanning circuit. In some embodiments, the method includes forming a plurality of scanning units, each at multiple levels. In some embodiments, forming each of the plurality of scanning units includes forming at least one of an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, or an output sub-circuit. Optionally, each scanning unit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal. Optionally, forming the output sub-circuit includes forming a first output terminal, forming a second output terminal, forming a twelfth transistor, and forming a fourteenth transistor. Optionally, forming the output sub-circuit includes coupling the source of the twelfth transistor to a third terminal configured to receive the first clock signal; coupling the drain of the twelfth transistor to the first output terminal configured to output a first control signal; coupling the source of the fourteenth transistor to a fourth terminal configured to receive the third clock signal; coupling the drain of the fourteenth transistor to a second output terminal configured to output a second control signal; and coupling the gates of the twelfth and fourth transistors to a first node.

[0270] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A scanning circuit, comprising multiple scanning units respectively located in multiple stages; in, Each of the plurality of scanning units includes at least one of an input sub-circuit, a first processing sub-circuit, a second processing sub-circuit, or an output sub-circuit; Each scanning unit is configured to receive at least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal; The output sub-circuit includes a first output terminal, a second output terminal, a first switching transistor, and a second switching transistor; the first output terminal and the second output terminal are connected to a pixel driving circuit in the same sub-pixel, and the pixel driving circuit connected to the first output terminal is different from the pixel driving circuit connected to the second output terminal, so as to drive different light-emitting elements in the same sub-pixel to emit light. The source of the first switching transistor is coupled to a third terminal configured to receive the first clock signal; The drain of the first switching transistor is coupled to the first output terminal configured to output a first control signal; The source of the second switching transistor is coupled to a fourth terminal configured to receive the third clock signal; The drain of the second switching transistor is coupled to the second output terminal configured to output a second control signal; and The gates of the first switching transistor and the second switching transistor are coupled to the first node.

2. The scanning circuit according to claim 1, wherein, The output sub-circuit also includes a tenth transistor and a thirteenth transistor; The source of the tenth transistor and the source of the thirteenth transistor are coupled to a fifth terminal configured to receive the first reference signal. The drain of the tenth transistor is coupled to the first output terminal; The drain of the thirteenth transistor is coupled to the second output terminal; as well as The gates of the tenth transistor and the thirteenth transistor are coupled to the second node.

3. The scanning circuit according to claim 2, wherein, The output sub-circuit also includes an eleventh transistor coupled between the tenth transistor and the first switching transistor; The gate of the eleventh transistor is coupled to the first node; as well as At least one of the source and drain of the eleventh transistor is coupled to the first output terminal.

4. The scanning circuit according to claim 3, wherein, The source and drain of the eleventh transistor are both coupled to the first output terminal.

5. The scanning circuit according to claim 2, wherein, Each scanning unit also includes a second capacitor; The first capacitor electrode of the second capacitor is coupled to the source of the tenth transistor; as well as The second capacitor electrode of the second capacitor is coupled to the second node.

6. The scanning circuit according to any one of claims 1 to 5, wherein, Each scanning unit also includes a third capacitor; The first capacitor electrode of the third capacitor is coupled to the first node; as well as The second capacitor electrode of the third capacitor is coupled to the second terminal configured to receive the second reference signal.

7. The scanning circuit according to claim 1, wherein, The input sub-circuit includes an input transistor, a first transistor, an input terminal, and a first terminal; The gate of the input transistor and the source of the first transistor are coupled to the first terminal configured to receive the second clock signal; The gate of the first transistor and the drain of the input transistor are coupled to the third node; The source of the input transistor is coupled to the input terminal configured to receive a start signal or an output signal from the previous scan unit of the previous stage; and The drain of the first transistor is coupled to the second node.

8. The scanning circuit according to claim 1, wherein, The first processing sub-circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The sources of the third transistor and the fourth transistor are coupled to the drain of the fifth transistor; The drains of the third transistor and the fourth transistor are coupled to the third node; The gate of the third transistor is coupled to the third terminal configured to receive the first clock signal; as well as The gate of the fourth transistor is coupled to the fourth terminal configured to receive the third clock signal.

9. The scanning circuit according to claim 8, wherein, The gate of the fifth transistor and the drain of the second transistor are coupled to the second node; The source of the fifth transistor is coupled to a fifth terminal configured to receive the first reference signal; as well as The source of the second transistor is coupled to a second terminal configured to receive the second reference signal.

10. The scanning circuit according to claim 1, wherein, The second processing sub-circuit includes a seventh transistor and an eighth transistor; The gate of the seventh transistor is coupled to the fourth node; The source of the seventh transistor and the gate of the eighth transistor are coupled to a sixth terminal configured to receive the fourth clock signal. The drain of the seventh transistor and the source of the eighth transistor are coupled to the fifth node; as well as The drain of the eighth transistor is coupled to the first node.

11. The scanning circuit according to claim 10, wherein, The second processing sub-circuit also includes a sixth transistor and a first capacitor; The gate of the sixth transistor is coupled to the second terminal configured to receive the second reference signal; The source of the sixth transistor is coupled to the third node; The drain of the sixth transistor and the first capacitor electrode of the first capacitor are coupled to the fourth node; as well as The second capacitor electrode of the first capacitor is coupled to the fifth node.

12. The scanning circuit according to claim 1, wherein, Each scanning unit also includes a third processing sub-circuit; The third processing sub-circuit includes a ninth transistor having a gate coupled to the second node, a source coupled to a sixth terminal configured to receive the fourth clock signal, and a drain coupled to the first node.

13. A display device comprising a light-emitting substrate and a scanning circuit according to any one of claims 1 to 12, the scanning circuit being configured to provide a control signal to the light-emitting substrate.

14. The display device according to claim 13, comprising a plurality of sub-pixels; in, Each of the plurality of sub-pixels includes: First light-emitting element; A first pixel driving circuit is configured to control the first light-emitting element to emit light. Second light-emitting element; and The second pixel driving circuit is configured to control the second light-emitting element to emit light. Wherein, the first pixel driving circuit is configured to receive the first control signal output from the first output terminal; and The second pixel driving circuit is configured to receive the second control signal output from the second output terminal.

15. The display device according to claim 14, wherein, The first light-emitting element and the second light-emitting element are configured to emit light of the same color.

16. The display device according to claim 14, further comprising a color filter substrate; in, The color filter substrate includes: A color conversion layer, comprising multiple color conversion blocks; and Color filter, which consists of multiple color filter blocks.

17. A method of operating a display device, the display device comprising a light-emitting substrate and a scanning circuit configured to provide control signals to the light-emitting substrate, the method comprising: At least one of a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reference signal, or a second reference signal is provided to each of the multiple scanning units of the scanning circuit; The effective voltage of the first clock signal is output as a first control signal to the light-emitting substrate; as well as The effective voltage of the third clock signal is output to the light-emitting substrate as a second control signal. The first control signal and the second control signal are output to the pixel driving circuit in the same sub-pixel of the light-emitting substrate. The pixel driving circuit that receives the first control signal is different from the pixel driving circuit that receives the second control signal, so as to drive different light-emitting elements in the same sub-pixel to emit light.

18. The method according to claim 17, wherein, The output of the first control signal and the output of the second control signal include: The first clock signal is provided to the source of the first switching transistor; The third clock signal is provided to the source of the second switching transistor; and The gates of the first switching transistor and the second switching transistor are coupled to the first node.

19. The method of claim 17, wherein, The first control signal and the second control signal are out of phase with respect to each other; and The light-emitting substrate includes a plurality of sub-pixels, each of the plurality of sub-pixels including at least one main light-emitting element driven by a main pixel driving circuit and at least one auxiliary light-emitting element driven by an auxiliary pixel driving circuit. The method further includes: The first control signal is provided to the main pixel driving circuit; The second control signal is provided to the auxiliary pixel driving circuit; The first data signal is provided to the main pixel driving circuit; and The second data signal is provided to the auxiliary pixel driving circuit; The first data signal and the second data signal are provided using a single data line connecting the source integrated circuit and the light-emitting substrate.

20. The method according to any one of claims 17 to 19, further comprising: The third clock signal is adjusted to have a constant invalid voltage level; as well as The invalid voltage of the third clock signal is output to the light-emitting substrate.

21. The method according to claim 20, wherein, The light-emitting substrate includes a plurality of sub-pixels, each of the plurality of sub-pixels including at least one main light-emitting element driven by a main pixel driving circuit and at least one auxiliary light-emitting element driven by an auxiliary pixel driving circuit. The method further includes: The first control signal is provided to the main pixel driving circuit; and The invalid voltage of the third clock signal is provided to the auxiliary pixel driving circuit.

22. The method according to claim 17, wherein, The first control signal and the second control signal are in phase with each other.

23. The method of claim 17, comprising: The control signal is provided to a high-resolution sub-region of the light-emitting substrate; as well as The control signal is provided to the low-resolution sub-region of the light-emitting substrate; The high-resolution sub-region for providing control signals to the light-emitting substrate includes: The effective voltage of the first clock signal is used as the first control signal and output to the first adjacent row sub-pixel in the high-resolution sub-region; and The effective voltage of the third clock signal is used as the second control signal and output to the second adjacent row sub-pixel in the high-resolution sub-region. The low-resolution sub-region for providing control signals to the light-emitting substrate includes: The effective voltage of the first clock signal is used as the first control signal and output to the third adjacent row sub-pixel in the low-resolution sub-region; Adjust the third clock signal to have a constant invalid voltage level; and The invalid voltage of the third clock signal is output to the fourth adjacent row sub-pixel in the low-resolution sub-region.

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