Display panel and its driving method, display device

Abstract

A pixel circuit and its driving method, a display panel, and a display device are disclosed. The pixel circuit includes a driving sub-circuit (101), a writing sub-circuit (102), a reset sub-circuit (103), a coupling sub-circuit (104), a storage sub-circuit (105), and a light-emitting element. The driving sub-circuit (101) is configured to provide a driving current to the light-emitting element under the control of signals from a first node (N1) and a second node (N2). The writing sub-circuit (102) is configured to transfer data signals from the data terminal under the control of signals from the scan signal terminals (Gate_P, Gate_N). The (Data) signal is written to the second node (N2); the storage sub-circuit (105) is configured to store the voltage of the first node (N1); the coupling sub-circuit (104) is configured to boost the voltage of the first node (N1) through coupling; the reset sub-circuit (103) is configured to reset the anode of the light-emitting element under the control of the scan signal terminal (Gate_P,Gate_N) and reset the control terminal of the drive sub-circuit (101) under the control of the reset control signal terminal (Reset_P,Reset_N).

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display panel and its driving method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. They are widely used in display products such as mobile phones, tablets, and digital cameras. OLED displays are current-driven, requiring current to be output to the OLED through pixel circuits to drive it to emit light. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] An exemplary embodiment of this disclosure provides a display panel, the display panel including a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; The display panel further includes a plurality of pixel circuits and a plurality of first light-emitting elements, located in the first display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits being distributed among the plurality of first pixel circuits; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements; The display panel further includes a plurality of second light-emitting elements located in the second display area; at least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements. Both the first pixel circuit and the second pixel circuit are pixel circuits as described below: The pixel circuit includes a driving sub-circuit, a writing sub-circuit, a reset sub-circuit, a coupling sub-circuit, a storage sub-circuit, and a light-emitting element, wherein: the driving sub-circuit is configured to provide a driving current to the light-emitting element under the control of signals from the first node and the second node; the writing sub-circuit is configured to write a signal from the data signal terminal to the second node under the control of a signal from the scan signal terminal; the storage sub-circuit is configured to store the voltage of the first node; the coupling sub-circuit is configured to boost the voltage of the first node through coupling; and the reset sub-circuit is configured to reset the anode of the light-emitting element under the control of the signal from the scan signal terminal, and reset the control terminal of the driving sub-circuit under the control of a signal from the reset control signal terminal. The storage sub-circuit includes a first capacitor, and the coupling sub-circuit includes a second capacitor; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to a first voltage terminal; one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the anode of the light-emitting element; or, one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the third node; one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the first voltage terminal. The charging voltage at the data signal terminal of the first pixel circuit is The charging voltage at the data signal terminal of the second pixel circuit is ,in, C1 is the voltage at which the first light-emitting element emits light stably, C2 is the capacitance value of the second capacitor, and Cst is the capacitance value of the first capacitor.

[0005] An exemplary embodiment of this disclosure also provides a driving method for a display panel, used to drive the display panel described in any embodiment of this disclosure, the driving method comprising: The reset sub-circuit resets the first node and the fourth node under the control of the reset control signal terminal and the scan signal terminal, wherein the fourth node is the anode of the light-emitting element; Under the control of the signal at the scanning signal terminal, the write sub-circuit writes the signal at the data signal terminal to the second node, wherein the charging voltage of the data signal terminal of the first pixel circuit is... The charging voltage at the data signal terminal of the second pixel circuit is ,in, C1 is the voltage at which the first light-emitting element emits light stably, C2 is the capacitance value of the second capacitor, and Cst is the capacitance value of the first capacitor. The storage sub-circuit stores the voltage of the first node; The coupler circuit increases the voltage of the first node through coupling. The driving sub-circuit provides driving current to the light-emitting element under the control of the signals from the first and second nodes.

[0006] This disclosure also provides a display device, including a display panel and a photosensitive element, wherein the display panel is the display panel described in any embodiment of this disclosure.

[0007] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0008] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0009] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present disclosure; Figure 3 An equivalent circuit diagram of a pixel circuit provided in an embodiment of this disclosure; Figure 4 An equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure; Figure 5 An equivalent circuit diagram of another pixel circuit provided in an embodiment of this disclosure; Figure 6 for Figure 3 The diagram shows a timing diagram of a pixel circuit. Figure 7 for Figure 3 The diagram shows the equivalent capacitive load of the pixel circuit. Figure 8 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure; Figure 9 This is a partial structural schematic diagram of a display panel provided in an embodiment of the present disclosure; Figure 10a Simulated waveforms of the drive current of the pixel circuit in some implementations are shown. Figure 10b Simulation waveform of the driving current of the pixel circuit provided in the embodiments of this disclosure; Figure 11a for Figure 10a Enlarged view of region A in the middle; Figure 11b for Figure 10b Enlarged view of region B in the middle; Figure 12a A simulation comparison diagram of the first node voltage of the pixel circuit in an embodiment of this disclosure and the pixel circuit in some embodiments; Figure 12b This is a simulation comparison diagram of the fourth node voltage of the pixel circuit in an embodiment of the present disclosure and the pixel circuit in some embodiments. Figure 13 This is a simulation comparison diagram of the driving current of the display panel in the first and second display areas according to an embodiment of this disclosure. Detailed Implementation

[0010] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0011] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" always cover the elements or objects listed after the term and their equivalents, without excluding other elements or objects, provided that the element or object preceding the term is included.

[0012] In the embodiments of this disclosure, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0013] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0014] In this specification, "connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0015] OLED displays possess numerous advantages, including self-emissiveness, low driving voltage, high luminous efficiency, short response time, and a wide operating temperature range, making them widely recognized as the display devices with the greatest development potential. OLED pixels require current-driven illumination. In mobile display devices such as smartphones, cameras are typically installed within the display area to meet various photography applications. The camera in the display area needs to capture light that penetrates the display area to reach the lens, thus requiring high transmittance from the display area. To achieve a true full-screen display, an external pixel circuitry with transparent traces is commonly used. The backplane (BP) driving pixels are externally located in the non-under-display camera (FDC) area, and the driving signal is transmitted to the FDC area via transparent traces, driving the anode and OLED devices in the FDC area to emit light.

[0016] However, in the FDC region, the transparent traces are too long and the load is too large. This results in a smaller driving current for the pixel circuit at high frequencies or low grayscale, which cannot quickly charge the anode voltage of the OLED to the predetermined value. As a result, the OLED device is slow to light up, causing the pixels in the FDC region to be generally darker than those in the non-FDC region. At the same time, due to the difference in the light-emitting current of R / G / B pixels, under the same brightness, G pixels are the slowest to light up compared to R / B pixels, which causes the image in the FDC region to be purple. Moreover, the lower the grayscale and the higher the driving frequency, the more severe the purple and dark image becomes.

[0017] This disclosure provides a pixel circuit. Figure 1 and Figure 2 Here are schematic diagrams of the structures of two pixel circuits provided in the embodiments of this disclosure, such as... Figure 1 and Figure 2 As shown, the pixel circuit includes: a driving sub-circuit 101, a writing sub-circuit 102, a reset sub-circuit 103, a coupling sub-circuit 104, a storage sub-circuit 105, and a light-emitting element.

[0018] The driving sub-circuit 101 is connected to the first node N1, the second node N2 and the third node N3 respectively, and is configured to provide driving current to the light-emitting element under the control of the signals of the first node N1 and the second node N2. The write sub-circuit 102 is connected to the scan signal terminal (which can be the first scan signal terminal Gate_P or the second scan signal terminal Gate_N), the data signal terminal Data, and the second node N2, respectively, and is configured to write the signal of the data signal terminal Data to the second node N2 under the control of the signal of the scan signal terminal. The storage sub-circuit 105 is connected to the first voltage terminal VDD and the first node N1 respectively, or to the first node N1 and the third node N3 respectively, and is configured to store the voltage of the first node N1 (i.e. the control terminal of the driving sub-circuit 101); The coupling sub-circuit 104 is connected to the first node N1 and the fourth node N4 respectively, or to the first node N1 and the first voltage terminal VDD respectively, and is configured to increase the voltage of the first node N1 (i.e. the control terminal of the driving sub-circuit 101) through coupling. The reset sub-circuit 103 is connected to the reset control signal terminal (which can be the first reset control signal terminal Reset_P or the second reset control signal terminal Reset_N), the scan signal terminal (which can be the first scan signal terminal Gate_P or the second scan signal terminal Gate_N), the fourth node N4, and the first node N1, respectively. It is configured to reset the fourth node N4 under the control of the signal at the scan signal terminal and reset the first node N1 under the control of the signal at the reset control signal terminal. One end of the light-emitting element is connected to the fourth node N4, and the other end is connected to the second voltage terminal VSS.

[0019] The pixel circuit provided in this embodiment increases the voltage of the first node N1 (i.e., the control terminal of the driving sub-circuit 101) through the coupling effect of the coupling sub-circuit 104. During the initial stage of light emission, the driving current through the light-emitting element is relatively large. As the fourth node N4 charges to a predetermined voltage, the driving current gradually decreases to a normal value. Furthermore, when the load on the fourth node N4 is larger and the charging is slower (i.e., the transparent trace is longer), the driving current remains at a relatively large value for a longer period, increasing the high-speed charging time and achieving self-compensation for the charging of the equivalent capacitive load of the light-emitting element, thereby improving the display uniformity of the display panel.

[0020] In some exemplary implementations, such as Figure 1 and Figure 2 As shown, the pixel circuit also includes a compensation sub-circuit 106, wherein: The compensation sub-circuit 106 is connected to the scan signal terminal (which can be the first scan signal terminal Gate_P or the second scan signal terminal Gate_N), the first node N1 and the third node N3 respectively, and is configured to compensate the threshold voltage of the drive sub-circuit 101 under the control of the signal at the scan signal terminal.

[0021] In some exemplary implementations, such as Figure 1 and Figure 2 As shown, the pixel circuit also includes a first light-emitting control sub-circuit 107 and a second light-emitting control sub-circuit 108, wherein: The first light-emitting control sub-circuit 107 is connected to the first voltage terminal VDD, the light-emitting control signal terminal (which can be the first light-emitting control signal terminal EM_P or the second light-emitting control signal terminal EM_N) and the second node N2 respectively, and is configured to form a path between the first voltage terminal VDD and the second node N2 under the control of the signal of the light-emitting control signal terminal. The second light-emitting control sub-circuit 108 is connected to the light-emitting control signal terminal (which can be the first light-emitting control signal terminal EM_P or the second light-emitting control signal terminal EM_N), the third node N3, and the fourth node N4, respectively, and is configured to form a path between the third node N3 and the fourth node N4 under the control of the signal from the light-emitting control signal terminal.

[0022] In some exemplary embodiments, Figure 3 and Figure 4 This is a schematic diagram of the equivalent circuits of two pixel circuits provided in the embodiments of this disclosure. In the pixel circuits provided in the embodiments of this disclosure, the storage sub-circuit 105 includes: a first capacitor Cst, and the coupling sub-circuit 104 includes: a second capacitor C2, wherein: like Figure 3 As shown, one end of the first capacitor Cst is connected to the first node N1, and the other end of the first capacitor Cst is connected to the first voltage terminal VDD; one end of the second capacitor C2 is connected to the first node N1, and the other end of the second capacitor C2 is connected to the fourth node N4; or, Or, such as Figure 4 As shown, one end of the first capacitor Cst is connected to the first node N1, and the other end of the first capacitor Cst is connected to the third node N3; one end of the second capacitor C2 is connected to the first node N1, and the other end of the second capacitor C2 is connected to the first voltage terminal VDD.

[0023] Figure 3 and Figure 4 Two exemplary structures of the storage sub-circuit 105 and the coupling sub-circuit 104 are shown. It will be readily understood by those skilled in the art that the implementation of the storage sub-circuit 105 and the coupling sub-circuit 104 is not limited to these, as long as their respective functions can be achieved.

[0024] In some exemplary implementations, such as Figure 3 and Figure 4 As shown, in the pixel circuit provided in this embodiment, the compensation sub-circuit 106 includes a second transistor T2, the driving sub-circuit 101 includes a third transistor (i.e., driving transistor) T3, and the writing sub-circuit 102 includes a fourth transistor T4.

[0025] Among them, the control electrode of the second transistor T2 is connected to the scan signal terminal (which can be the first scan signal terminal Gate_P or the second scan signal terminal Gate_N), the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1. The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The control terminal of the fourth transistor T4 is connected to the scan signal terminal (which can be the first scan signal terminal Gate_P or the second scan signal terminal Gate_N), the first terminal of the fourth transistor T4 is connected to the data signal terminal Data, and the second terminal of the fourth transistor T4 is connected to the second node N2.

[0026] Figure 3 and Figure 4 Two exemplary structures of the compensation sub-circuit 106, the driving sub-circuit 101, and the writing sub-circuit 102 are shown. It will be readily understood by those skilled in the art that the implementation of the compensation sub-circuit 106, the driving sub-circuit 101, and the writing sub-circuit 102 is not limited to these, as long as their respective functions can be achieved.

[0027] In one exemplary embodiment, such as Figure 3 and Figure 4 As shown, the first light-emitting control sub-circuit 107 provided in this embodiment includes a fifth transistor T5, and the second light-emitting control sub-circuit 108 includes a sixth transistor T6.

[0028] Among them, the control electrode of the fifth transistor T5 is connected to the light-emitting control signal terminal (which can be the first light-emitting control signal terminal EM_P or the second light-emitting control signal terminal EM_N), the first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the light-emitting control signal terminal (which can be the first light-emitting control signal terminal EM_P or the second light-emitting control signal terminal EM_N), the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0029] Figure 3 and Figure 4 Two exemplary structures of the first light-emitting control sub-circuit 107 and the second light-emitting control sub-circuit 108 are shown. It will be readily understood by those skilled in the art that the implementation of the first light-emitting control sub-circuit 107 and the second light-emitting control sub-circuit 108 is not limited to these, as long as their respective functions can be achieved.

[0030] In one exemplary embodiment, such as Figure 3 and Figure 4 As shown, the reset sub-circuit 103 provided in this embodiment includes a first transistor T1 and a seventh transistor T7.

[0031] The control electrode of the first transistor T1 is connected to the reset control signal terminal (which can be the first reset control signal terminal Reset_P or the second reset control signal terminal Reset_N), the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the first initial signal terminal INIT1. The control terminal of the seventh transistor T7 is connected to the scan signal terminal (which can be the first scan signal terminal Gate_P or the second scan signal terminal Gate_N), the first terminal of the seventh transistor T7 is connected to the second initial signal terminal INIT2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4.

[0032] Figure 3 and Figure 4 Two exemplary structures of the reset sub-circuit 103 are shown. It will be readily understood by those skilled in the art that the implementation of the reset sub-circuit 103 is not limited to these, as long as its function can be achieved.

[0033] In some exemplary embodiments, such as Figure 3 As shown, in the pixel circuit provided in this embodiment, the storage sub-circuit 105 includes a first capacitor Cst, the coupling sub-circuit 104 includes a second capacitor C2, the compensation sub-circuit 106 includes a second transistor T2, the driving sub-circuit 101 includes a third transistor T3, the writing sub-circuit 102 includes a fourth transistor T4, the first light-emitting control sub-circuit 107 includes a fifth transistor T5, the second light-emitting control sub-circuit 108 includes a sixth transistor T6, and the reset sub-circuit 103 includes a first transistor T1 and a seventh transistor T7.

[0034] In this configuration, one end of the first capacitor Cst is connected to the first node N1, and the other end of the first capacitor Cst is connected to the first voltage terminal VDD; one end of the second capacitor C2 is connected to the first node N1, and the other end of the second capacitor C2 is connected to the fourth node N4; the control electrode of the second transistor T2 is connected to the first scan signal terminal Gate_P, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1; the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is connected to the first scan signal terminal Gate_P, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the second node N2; the control electrode of the fifth transistor T5 is connected to the first light emission control signal terminal... The EM_P connection is established. The first terminal of the fifth transistor T5 is connected to the first voltage terminal VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2. The control terminal of the sixth transistor T6 is connected to the first light-emitting control signal terminal EM_P, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the fourth node N4. The control terminal of the first transistor T1 is connected to the first reset control signal terminal Reset_P, the first terminal of the first transistor T1 is connected to the first node N1, and the second terminal of the first transistor T1 is connected to the first initial signal terminal INIT1. The control terminal of the seventh transistor T7 is connected to the first scan signal terminal Gate_P, the first terminal of the seventh transistor T7 is connected to the second initial signal terminal INIT2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. One end of the light-emitting element is connected to the fourth node N4, and the other end of the light-emitting element is connected to the second voltage terminal VSS.

[0035] Figure 3 An exemplary structure of the driving sub-circuit 101, writing sub-circuit 102, compensation sub-circuit 106, storage sub-circuit 105, coupling sub-circuit 104, first light-emitting control sub-circuit 107, second light-emitting control sub-circuit 108, and reset sub-circuit 103 is shown. It will be readily understood by those skilled in the art that the implementation of each of the above sub-circuits is not limited to this, as long as their respective functions can be achieved.

[0036] In some exemplary embodiments, such as Figure 4As shown, in the pixel circuit provided in this embodiment, the storage sub-circuit 105 includes a first capacitor Cst, the coupling sub-circuit 104 includes a second capacitor C2, the compensation sub-circuit 106 includes a second transistor T2, the driving sub-circuit 101 includes a third transistor T3, the writing sub-circuit 102 includes a fourth transistor T4, the first light-emitting control sub-circuit 107 includes a fifth transistor T5, the second light-emitting control sub-circuit 108 includes a sixth transistor T6, and the reset sub-circuit 103 includes a first transistor T1 and a seventh transistor T7.

[0037] In this configuration, one end of the first capacitor Cst is connected to the first node N1, and the other end of the first capacitor Cst is connected to the third node N3; one end of the second capacitor C2 is connected to the first node N1, and the other end of the second capacitor C2 is connected to the first voltage terminal VDD; the control electrode of the second transistor T2 is connected to the second scan signal terminal Gate_N, the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1; the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is connected to the second scan signal terminal Gate_N, the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the second node N2; the control electrode of the fifth transistor T5 is connected to the second light emission control signal terminal... The EM_N connection is established. The first terminal of the fifth transistor T5 is connected to the first voltage terminal VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2. The control terminal of the sixth transistor T6 is connected to the second light-emitting control signal terminal EM_N, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the fourth node N4. The control terminal of the first transistor T1 is connected to the second reset control signal terminal Reset_N, the first terminal of the first transistor T1 is connected to the first node N1, and the second terminal of the first transistor T1 is connected to the first initial signal terminal INIT1. The control terminal of the seventh transistor T7 is connected to the second scan signal terminal Gate_N, the first terminal of the seventh transistor T7 is connected to the second initial signal terminal INIT2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. One end of the light-emitting element is connected to the fourth node N4, and the other end of the light-emitting element is connected to the second voltage terminal VSS.

[0038] Figure 4An exemplary structure of the driving sub-circuit 101, writing sub-circuit 102, compensation sub-circuit 106, storage sub-circuit 105, coupling sub-circuit 104, first light-emitting control sub-circuit 107, second light-emitting control sub-circuit 108, and reset sub-circuit 103 is shown. It will be readily understood by those skilled in the art that the implementation of each of the above sub-circuits is not limited to this, as long as their respective functions can be achieved.

[0039] In some exemplary embodiments, the light-emitting element EL can be an organic light-emitting diode (OLED) or any other type of light-emitting diode. In some examples, the light-emitting element can be a quantum dot light-emitting diode (QLED), a micro-LED, or a mini-LED, etc.

[0040] In some exemplary embodiments, such as Figure 3 As shown, the third transistor T3 is a P-type transistor, the first transistor T1 is a P-type transistor or an N-type transistor, the second transistor T2 is a P-type transistor or an N-type transistor, the fourth transistor T4 is a P-type transistor or an N-type transistor, the fifth transistor T5 is a P-type transistor or an N-type transistor, the sixth transistor T6 is a P-type transistor or an N-type transistor, and the seventh transistor T7 is a P-type transistor or an N-type transistor.

[0041] In some exemplary embodiments, such as Figure 4 As shown, the third transistor T3 is an N-type transistor, the first transistor T1 is a P-type transistor or an N-type transistor, the second transistor T2 is a P-type transistor or an N-type transistor, the fourth transistor T4 is a P-type transistor or an N-type transistor, the fifth transistor T5 is a P-type transistor or an N-type transistor, the sixth transistor T6 is a P-type transistor or an N-type transistor, and the seventh transistor T7 is a P-type transistor or an N-type transistor.

[0042] In some exemplary embodiments, such as Figure 3 As shown, transistors T1 through T7 are all P-type transistors, or, as... Figure 4 As shown, the first transistor T1 to the seventh transistor T7 are all N-type transistors.

[0043] In this embodiment, the first transistor T1 to the seventh transistor T7 can all be N-type thin-film transistors or P-type thin-film transistors. Using the same type of transistor for the first transistor T1 to the seventh transistor T7 can unify the process flow, reduce the number of process steps, and help improve the product yield.

[0044] In some exemplary embodiments, considering the low leakage current of low-temperature polycrystalline silicon thin-film transistors, the first transistor T1 to the seventh transistor T7 can all be low-temperature polycrystalline silicon thin-film transistors. The thin-film transistors can be either bottom-gate or top-gate structures. This disclosure does not limit this, as long as the switching function can be achieved.

[0045] In some exemplary embodiments, the first capacitor Cst and the second capacitor C2 may be a liquid crystal capacitor composed of a pixel electrode and a common electrode, or an equivalent capacitor composed of a liquid crystal capacitor composed of a pixel electrode and a common electrode and a storage capacitor. This disclosure does not limit the specific capacitance.

[0046] In some exemplary embodiments, the first initial signal terminal INIT1 and the second initial signal terminal INIT2 can be a single initial signal terminal or two separate independent initial signal terminals. By separating the first initial signal terminal INIT1 and the second initial signal terminal INIT2 into two independent initial signal terminals, the reset voltage of the light-emitting element and the reset voltage of the first node N1 can be adjusted separately, thereby achieving better display effects and improving problems such as low-frequency flicker.

[0047] In some exemplary embodiments, Figure 5 An equivalent circuit diagram of another pixel circuit provided in this disclosure embodiment is shown below. Figure 5 As shown, the reset sub-circuit 103 provided in this embodiment includes a first transistor T1, a seventh transistor T7, and an eighth transistor T8.

[0048] Among them, the control electrode of the first transistor T1 is connected to the first reset control signal terminal Reset_P', the first electrode of the first transistor T1 is connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is connected to the fifth node; The control terminal of the seventh transistor T7 is connected to the first reset control signal terminal Reset_P', the first terminal of the seventh transistor T7 is connected to the second initial signal terminal INIT2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. The control terminal of the eighth transistor T8 is connected to the second scan signal terminal Gate_N', the first terminal of the eighth transistor T8 is connected to the fifth node N5, and the second terminal of the eighth transistor T8 is connected to the first node N1.

[0049] Figure 5 An exemplary structure of the reset sub-circuit 103 is shown. It will be readily understood by those skilled in the art that the reset sub-circuit 103 is not limited to this, as long as its function can be achieved.

[0050] In this embodiment, the pixel circuit has low leakage current at the control electrode voltage of the driving sub-circuit 101, thus achieving a high brightness retention rate for the light-emitting element.

[0051] In some exemplary embodiments, such as Figure 5 As shown, in the pixel circuit provided in this embodiment, the storage sub-circuit 105 includes a first capacitor Cst, the coupling sub-circuit 104 includes a second capacitor C2, the compensation sub-circuit 106 includes a second transistor T2, the driving sub-circuit 101 includes a third transistor T3, the writing sub-circuit 102 includes a fourth transistor T4, the first light-emitting control sub-circuit 107 includes a fifth transistor T5, the second light-emitting control sub-circuit 108 includes a sixth transistor T6, and the reset sub-circuit 103 includes a first transistor T1, a seventh transistor T7, and an eighth transistor T8.

[0052] In this configuration, one end of the first capacitor Cst is connected to the first node N1, and the other end of the first capacitor Cst is connected to the first voltage terminal VDD; one end of the second capacitor C2 is connected to the first node N1, and the other end of the second capacitor C2 is connected to the fourth node N4; the control electrode of the second transistor T2 is connected to the first scan signal terminal Gate_P', the first electrode of the second transistor T2 is connected to the third node N3, and the second electrode of the second transistor T2 is connected to the first node N1; the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3; the control electrode of the fourth transistor T4 is connected to the first scan signal terminal Gate_P', the first electrode of the fourth transistor T4 is connected to the data signal terminal Data, and the second electrode of the fourth transistor T4 is connected to the second node N2; the control electrode of the fifth transistor T5 is connected to the first light emission control signal terminal EM_P', the first electrode of the fifth transistor T5 is connected to the first voltage terminal VDD, and the fifth transistor T5... The second electrode of transistor 5 is connected to the second node N2; the control electrode of the sixth transistor T6 is connected to the first light-emitting control signal terminal EM_P', the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4; the control electrode of the first transistor T1 is connected to the first reset control signal terminal Reset_P', the first electrode of the first transistor T1 is connected to the first initial signal terminal INIT1, and the second electrode of the first transistor T1 is connected to the fifth node; the control electrode of the seventh transistor T7 is connected to the first reset control signal terminal Reset_P', the first electrode of the seventh transistor T7 is connected to the second initial signal terminal INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4; the control electrode of the eighth transistor T8 is connected to the second scan signal terminal Gate_N', the first electrode of the eighth transistor T8 is connected to the fifth node N5, and the second electrode of the eighth transistor T8 is connected to the first node N1; one end of the light-emitting element is connected to the fourth node N4, and the other end of the light-emitting element is connected to the second voltage terminal VSS.

[0053] Figure 5 An exemplary structure of the driving sub-circuit 101, writing sub-circuit 102, compensation sub-circuit 106, storage sub-circuit 105, coupling sub-circuit 104, first light-emitting control sub-circuit 107, second light-emitting control sub-circuit 108, and reset sub-circuit 103 is shown. It will be readily understood by those skilled in the art that the implementation of each of the above sub-circuits is not limited to this, as long as their respective functions can be achieved.

[0054] In some exemplary embodiments, the first transistor T1 to the seventh transistor T7 can be low-temperature polysilicon (LTPS) thin film transistors (TFTs), and the eighth transistor T8 can be an indium gallium zinc oxide (IGZO) thin film transistor.

[0055] In this embodiment, indium gallium zinc oxide (IGN) thin-film transistors (LTVs) generate less leakage current compared to low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS). Therefore, using an IGNV thin-film transistor as the eighth transistor T8 can significantly reduce leakage current. Furthermore, the first transistor T1 and the second transistor T2 do not need to be IGNV thin-film transistors. Since LTPS thin-film transistors are generally smaller than IGNV thin-film transistors, the pixel circuit in this embodiment occupies less space, which is beneficial for improving the resolution of the display panel.

[0056] The pixel circuit in this embodiment combines the excellent switching characteristics of LTPS-TFT and the low leakage current characteristics of Oxide-TFT, enabling low-frequency driving (1Hz~60Hz) and significantly reducing the power consumption of the display screen.

[0057] The following example uses a pixel circuit provided in this disclosure, where the first transistor T1 to the seventh transistor T7 are all P-type thin-film transistors, as an example. Figure 3 The pixel circuit unit shown and Figure 6 The timing diagram shown provides a detailed description of the operation of a pixel circuit unit within one frame period, and further illustrates the technical solution of the embodiments of this disclosure through the operation of the driving circuit.

[0058] Figure 7 for Figure 3 The diagram shows the equivalent capacitive load corresponding to the pixel circuit, as follows: Figure 7 As shown, for pixels in the under-display camera area, since the pixel circuit is externally located in the non-camera area via transparent traces, the transparent traces are relatively long, resulting in a large equivalent capacitive load Cfdc, which cannot be ignored. The pixel circuit provided in this embodiment includes 7 transistor units (T1~T7), 2 capacitor units (Cst and C2), and 4 power signal terminals (VDD, VSS, INIT1, and INIT2). The first voltage terminal VDD continuously provides a high-level signal, and the second voltage terminal VSS continuously provides a low-level signal. In an exemplary embodiment, the operation of this pixel circuit within one frame period includes: In the first stage, t1, known as the initialization stage, both the first scan signal terminal Gate_P and the first light emission control signal terminal EM_P are high-level signals, while the first reset control signal terminal Reset_P is low-level. The first transistor T1 is turned on, and the signal from the first initial signal terminal INIT1 is provided to the first node N1 to initialize the first capacitor Cst, clearing the original data voltage in the first capacitor. The second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 are turned off; the OLED does not emit light during this stage.

[0059] The second stage, t2, is called the data writing stage or threshold compensation stage. During this stage, the first scan signal terminal (Gate_P) is low, while the first reset control signal terminal (Reset_P) and the first light emission control signal terminal (EM_P) are both high. The data signal terminal (Data) outputs a data voltage. Because the second terminal of the first capacitor (Cst) is low during this stage, the third transistor (T3) is turned on. The low signal at the first scan signal terminal (Gate_P) turns on the second transistor (T2), the fourth transistor (T4), and the seventh transistor (T7). The turn on the second transistor (T2) and the fourth transistor (T4) causes the data signal terminal (Data) to output a data voltage. The data voltage output from the Data signal terminal is supplied to the first node N1 via the second node N2, the conducting third transistor T3, the third node N3, and the conducting second transistor T2, and is then transmitted to the first node N1. The sum of the threshold voltage Vth of the third transistor T3 and the voltage of the first capacitor Cst is used to charge the first capacitor Cst. Therefore, the voltage at the second terminal (first node N1) of the first capacitor Cst is... +Vth, Vth is the data voltage output from the data signal terminal Data, and Vth is the threshold voltage of the third transistor T3. The gate-source voltage difference of the third transistor... = -Vdd= +Vth-Vdd, where Vdd is the power supply voltage output from the first voltage terminal VDD. The seventh transistor T7 turns on, providing the initial voltage of the second initial signal terminal INIT2 to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, and completing the initialization process. = The first reset control signal, Reset_P, is high, causing the first transistor T1 to turn off. The first light emission control signal, EM_P, is also high, causing the fifth transistor T5 and the sixth transistor T6 to turn off, and the OLED does not emit light.

[0060] The third stage, t3, is called the holding stage. During this stage, the signals at the first scan signal terminal Gate_P, the first reset control signal terminal Reset_P, and the first light emission control signal terminal EM_P are all high-level signals. The second transistor T2, the fourth transistor T4, and the seventh transistor T7 are disconnected, and the voltage at the first node N1 is maintained at [value missing]. +Vth remains unchanged, and the voltage at the fourth node N4 remains constant. The same applies; OLEDs do not emit light.

[0061] The fourth stage, t4, is called the light-emitting stage. During this stage, the first light-emitting control signal terminal EM_P is low, while the first scan signal terminal Gate_P and the first reset control signal terminal Reset_P are both high. The low signal at EM_P turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first voltage terminal VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, causing a driving current to flow through the OLED and emitting light.

[0062] The driving current when an OLED first emits light Size: ; in, The driving current flowing through the third transistor T3 is the driving current of the driving transistor (DTFT). W is the width of the channel of the third transistor T3, L is the length of the channel of the third transistor T3, and W / L is the width-to-length ratio of the channel of the third transistor T3 (i.e., the ratio of width to length). For electron mobility, Let K be the capacitance per unit area, and K be a constant. Vth is the voltage difference between the gate electrode and the first electrode of the third transistor T3, and Vth is the threshold voltage of the third transistor T3. The charging voltage output by the data signal terminal (Data) is located in the under-display camera area. = , This refers to the actual data voltage output from the data signal terminal.

[0063] In the fourth stage t4, as the voltage at the fourth node N4 decreases from... Gradually rise to The second capacitor C2 electrically couples to the first node N1, causing the voltage of the first node N1 to rise. Ultimately, the voltage of the first node N1 will be... = +Vth increases to = +Vth + ( - ) c2 / (c2+cst), where, Let C2 be the voltage at which the light-emitting element emits light stably, and C2 be the capacitance value of the second capacitor C2, and Cst be the capacitance value of the first capacitor Cst. The voltage increase of the first node N1 of all pixels is ( - ) c2 / (c2+cst), therefore, for pixels in the normal area (i.e., the non-under-display camera area), the charging voltage of the data signal terminal Data in the second stage t2 is... = -( - ) c2 / (c2+cst), then the final drive current is: .

[0064] As can be seen from the above formula, the current I flowing through the light-emitting element EL is independent of the threshold voltage Vth of the third transistor T3, thus eliminating the influence of the threshold voltage Vth of the third transistor T3 on the current I and ensuring the uniformity of brightness.

[0065] For some implementations of pixel circuit design, the driving current of the driving transistor (DTFT) is... It remains a fixed value. However, the pixel circuit of this embodiment, in the initial stage of light emission... The value is relatively large, as the fourth node N4 charges to the predetermined voltage. The charging speed gradually decreases to the normal value. Furthermore, the higher the load on the fourth node N4 and the slower the charging, the more likely it is to fail. It maintains a larger value for a longer period of time, improving the high-speed charging time and achieving self-compensation for charging the equivalent capacitive load Cfdc capacitor.

[0066] Figure 4 and Figure 5 The timing diagram of the pixel circuit shown can be used as a reference. Figure 6 The settings are configured, but will not be described in detail in this embodiment.

[0067] Based on the above working timing, the pixel circuit eliminates the residual positive charge of the light-emitting element after the last emission, realizes the compensation of the gate voltage of the driving transistor, avoids the influence of the threshold voltage drift of the driving transistor on the EL driving current of the light-emitting element, and improves the uniformity of the displayed image and the display quality of the display panel.

[0068] This disclosure also provides a display panel, the display area of ​​which has a plurality of sub-pixels, and at least one sub-pixel is provided with a pixel circuit as described in any embodiment of this disclosure.

[0069] In some exemplary embodiments, such as Figure 8 As shown, the display panel includes a display area and a border area R3 surrounding the display area. The border area R3 surrounds the display area. The display area includes a first display area R1 and a second display area R2, with the first display area R1 at least partially surrounding the second display area R2. For example, Figure 8 The second display area R2 shown is located at the top center of the display substrate, and one side of the second display area R2 is adjacent to the border area R3. However, this embodiment is not limited to this. For example, the second display area R2 can be located at other positions such as the upper left corner or the upper right corner of the display substrate.

[0070] In some exemplary implementations, such as Figure 8 As shown, the display area can be rectangular, for example, a rounded rectangle. The second display area R2 can be circular. However, this embodiment is not limited to this. For example, the second display area R2 can be rectangular, elliptical, or other shapes.

[0071] In some exemplary embodiments, the first display area R1 can be a non-transparent display area, and the second display area R2 can be a transparent display area. That is, the first display area R1 is opaque, while the second display area R2 is transparent. For example, the orthographic projection of hardware such as a photosensor (e.g., a camera) onto the display substrate can be located within the second display area R2 of the display substrate, meaning the first display area R1 can be a non-under-display camera area, and the second display area R2 can be an under-display camera area. In this example, the display substrate does not require drilling, making a true full-screen display possible while ensuring the practicality of the display substrate.

[0072] In some exemplary embodiments, the display panel may include a plurality of sub-pixels disposed on a substrate. At least one sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit is configured to drive the light-emitting element. For example, the pixel circuit is configured to provide a driving current to drive the light-emitting element to emit light. For example, the light-emitting element may be an organic light-emitting diode (OLED), which emits red, green, blue, or white light under the drive of its corresponding pixel circuit. The color emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and an organic light-emitting layer disposed between the first and second electrodes. The first electrode may be connected to the pixel circuit. However, this embodiment is not limited thereto.

[0073] In some exemplary embodiments, a pixel unit may include three sub-pixels (e.g., a red sub-pixel R, a blue sub-pixel B, and a green sub-pixel G), which may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. For example, a pixel unit may include four sub-pixels (a red sub-pixel R, a blue sub-pixel B, a green sub-pixel G, and a white sub-pixel), which may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, the embodiments disclosed herein are not limited to this.

[0074] In some exemplary embodiments, to improve the light transmittance of the second display area R2, only a light-emitting element can be provided in the second display area R2, while the pixel circuit that drives the light-emitting element of the second display area R2 is provided in the first display area R1. That is, the light transmittance of the second display area R2 is improved by separating the light-emitting element and the pixel circuit. In this example, no pixel circuit is provided in the second display area R2.

[0075] Figure 9 This is a partial structural diagram of a display panel according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 9 As shown, the display panel includes: a plurality of first pixel circuits 10, a plurality of second pixel circuits 20, and a plurality of first light-emitting elements 30 located in a first display area R1, and a plurality of second light-emitting elements 40 located in a second display area R2. The plurality of second pixel circuits 20 may be spaced apart from the plurality of first pixel circuits 10; for example, the plurality of first pixel circuits 20 may be arranged between two adjacent second pixel circuits 20 in a first direction. At least one of the plurality of first pixel circuits 10 may be connected to at least one of the plurality of first light-emitting elements 30, and the orthographic projection of at least one first pixel circuit 10 on the substrate and the orthographic projection of at least one first light-emitting element 30 on the substrate may at least partially overlap. The first pixel circuits 10 may be configured to provide a driving signal to the connected first light-emitting element 30 to drive the first light-emitting element 30 to emit light. At least one of the plurality of second pixel circuits 20 may be connected to at least one of the plurality of second light-emitting elements 40 via a conductive line L. The second pixel circuits 20 may be configured to provide a driving signal to the connected second light-emitting element 40 to drive the second light-emitting element 40 to emit light. Since the second light-emitting element 40 and the second pixel circuit 20 are located in different regions, there is no overlap between the orthographic projection of at least one second pixel circuit 20 on the substrate and the orthographic projection of at least one second light-emitting element 40 on the substrate.

[0076] In some exemplary embodiments, the density of the second light-emitting element 40 in the second display area R2 can be approximately equal to the density of the first light-emitting element 30 in the first display area R1. That is, the resolution of the second display area R2 can be approximately the same as the resolution of the first display area R1. However, this embodiment is not limited to this. For example, the density of the second light-emitting element 40 can be greater than or less than the density of the first light-emitting element 30. That is, the resolution of the second display area R2 can be greater than or less than the resolution of the first display area R1.

[0077] In some exemplary embodiments, the light-emitting area of ​​the second light-emitting element 40 may be smaller than the light-emitting area of ​​the first light-emitting element 30. That is, the light-emitting area of ​​the first light-emitting element 30 is larger than the light-emitting area of ​​the second region light-emitting element 40. The light-emitting area of ​​the light-emitting element may correspond to the area of ​​the opening in the pixel definition layer. In some examples, a light-transmitting area is provided between adjacent second light-emitting elements 40 in the second display area R2. For example, multiple light-transmitting areas are connected to each other, forming a continuous light-transmitting area spaced apart by multiple second light-emitting elements 40. The conductive line L may be made of a transparent conductive material to maximize the light transmittance of the light-transmitting area.

[0078] In some exemplary embodiments, within the first display area R1, the area where the second pixel circuit 20 is disposed can be obtained by reducing the size of the first pixel circuit 10 in the second direction D2. For example, the size of the first pixel circuit 10 in the second direction D2 can be smaller than the size of the first light-emitting element 30 in the second direction D2. The second direction D2 is, for example, a sub-pixel row direction, but is not limited thereto. In other embodiments, the second direction D2 can be a sub-pixel column direction. This exemplary embodiment is described using the second direction D2 as a sub-pixel row direction as an example. For example, the sizes of the first pixel circuit 10 and the second pixel circuit 20 in the second direction D2 can be the same, and the size of each pixel circuit in the second direction D2 can differ from the size of the first light-emitting element 30 in the second direction D2 by approximately 4 micrometers (μm). The size of each pixel circuit in the first direction D1 is approximately the same as the size of the first light-emitting element 30 in the first direction D1. Wherein, the first direction D1 is perpendicular to the second direction D2.

[0079] In some exemplary embodiments, the first pixel circuit 10 and the second pixel circuit 20 can both be pixel circuits as described in any embodiment of this disclosure. For example, the first pixel circuit 10 and the second pixel circuit 20 can both be... Figure 3 , Figure 4 or Figure 5 Any pixel circuit in the circuit.

[0080] In some exemplary embodiments, the charging voltage of the data signal terminal Data of the first pixel circuit 10 is The charging voltage of the data signal terminal Data of the second pixel circuit 20 is ,in, C1 is the voltage when the first light-emitting element 30 emits light stably, C2 is the capacitance value of the second capacitor C2, and Cst is the capacitance value of the first capacitor Cst.

[0081] In some exemplary embodiments, the first pixel circuit 10 may be a pixel circuit from other implementations, and the second pixel circuit 20 may be a pixel circuit as described in any embodiment of this disclosure. For example, the first pixel circuit 10 may be a 3T1C, 7T1C, 8T1C, etc. This disclosure does not limit this. The second pixel circuit 20 may be... Figure 3 , Figure 4 or Figure 5 Any pixel circuit in the circuit.

[0082] Figure 10a The following are simulation waveforms of the drive current of the pixel circuit in some implementation methods. Figure 10b Simulated waveform of the driving current of the pixel circuit provided in the embodiments of this disclosure (wherein, both the first pixel circuit 10 and the second pixel circuit 20 adopt...) Figure 3 (The structure of the pixel circuit shown) Figure 11a for Figure 10a Enlarged view of region A in the middle. Figure 11b for Figure 10b A magnified view of region B in the middle. Figure 10a and Figure 10b Each simulation lasts for one frame. The first pulse phase includes a charging phase, while the pixel circuits in the remaining three pulse phases simply act as switches and do not charge. As can be seen from the figure, compared with the driving current of the pixel circuits in some embodiments, the display panel of this disclosure embodiment charges faster in the second display area (i.e., the under-display camera area) in the first pulse phase due to the driving current (approximately proportional to the display brightness).

[0083] Figure 12a This is a simulation comparison diagram of the first node voltage of the pixel circuit in this embodiment and some other embodiments of the pixel circuit. Figure 12b This is a simulation comparison diagram of the fourth node voltage of the pixel circuit in this embodiment and some other embodiments of the pixel circuit. Figure 13 This is a simulation comparison diagram of the drive current of the display panel in the first and second display areas according to an embodiment of this disclosure. Figure 12a , Figure 12b and Figure 13 As can be seen, in the embodiment of this disclosure, the display panel initially has a large driving current in the second display area, which decreases very slowly and maintains a high current for a long time, resulting in a good current improvement effect.

[0084] This disclosure also provides a display device, including a display panel and a photosensitive element. The display panel includes a first display area and a second display area, the first display area at least partially surrounding the second display area, and the photosensitive element located in the second display area. The display panel further includes a plurality of pixel circuits and a plurality of first light-emitting elements, located in the first display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of second pixel circuits being distributed among the plurality of first pixel circuits; at least one of the plurality of first pixel circuits is connected to at least one of the plurality of first light-emitting elements; The display panel further includes a plurality of second light-emitting elements located in the second display area; at least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements. The second pixel circuit is a pixel circuit as described in any embodiment of this disclosure.

[0085] With the rapid development of the information age, the manufacturing industries of mobile phones, computers, etc., have also developed rapidly. In order to achieve full-screen display, sensors such as cameras, fingerprint recognition, and facial recognition are usually integrated under the screen. Therefore, the concept of an under-screen functional area has emerged, which places sensing functions such as camera and proximity sensing under the screen. The display device of this disclosure sets a photosensitive element in a second display area. The second display area is both light-transmitting and displayable, which facilitates the under-screen integration of the photosensitive element and the design of a full-screen display. It can be applied to under-screen cameras, fingerprint, facial recognition, etc. The display device of this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. In an exemplary embodiment, the display device can be a wearable display device that can be worn on the human body in some way, such as a smartwatch or smart bracelet.

[0086] This disclosure also provides a driving method for a pixel circuit, applied to the pixel circuit provided in any of the foregoing embodiments, the driving method comprising: The reset sub-circuit resets the first node and the fourth node under the control of the reset control signal terminal and the scan signal terminal; Under the control of the signal at the scan signal terminal, the write sub-circuit writes the signal at the data signal terminal to the second node; The storage sub-circuit stores the voltage of the first node; The coupler circuit increases the voltage of the first node through coupling. The driving sub-circuit provides driving current to the light-emitting element under the control of the signals from the first and second nodes.

[0087] In an exemplary embodiment, the driving method includes: During the reset phase, the reset sub-circuit resets the first node under the control of the reset control signal terminal; During the data writing phase, the writing sub-circuit, under the control of the signal at the scanning signal terminal, writes the signal at the data signal terminal to the second node; the compensation sub-circuit, under the control of the signal at the scanning signal terminal, compensates the threshold voltage of the driving sub-circuit to the first node; and the storage sub-circuit stores the voltage at the control terminal of the driving sub-circuit. During the light-emitting stage, the first light-emitting control sub-circuit forms a path between the first voltage terminal and the second node under the control of the light-emitting control signal terminal; the driving sub-circuit provides driving current to the third node under the control of the signals of the first node and the second node; the second light-emitting control sub-circuit forms a path between the third node and the fourth node under the control of the signal of the light-emitting control signal terminal.

[0088] The technical solution provided in this disclosure increases the voltage of the first node (i.e., the control terminal of the driving sub-circuit) through the coupling effect of the coupling sub-circuit. During the initial stage of light emission, the driving current through the light-emitting element is relatively large. As the fourth node charges to a predetermined voltage, the driving current gradually decreases to a normal value. Furthermore, when the load on the fourth node is larger and the charging is slower (i.e., the transparent trace is longer), the driving current remains at a relatively large value for a longer period, thus increasing the high-speed charging time and achieving self-compensation for the equivalent capacitive load of the light-emitting element, thereby improving the display uniformity of the display panel.

[0089] The following points need to be explained: The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0090] Where there is no conflict, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments.

[0091] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display panel, the display panel comprising a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; The display panel further comprises a plurality of pixel circuits and a plurality of first light emitting elements located in the first display area. The plurality of pixel circuits include: A plurality of first pixel circuits and a plurality of second pixel circuits, wherein the plurality of second pixel circuits are distributed among the plurality of first pixel circuits; At least one pixel circuit of the plurality of first pixel circuits is connected to at least one light-emitting element of the plurality of first light-emitting elements; The display panel also includes a plurality of second light-emitting elements located in the second display area; At least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements; Both the first pixel circuit and the second pixel circuit are pixel circuits as described below: The pixel circuit includes a driving sub-circuit, a writing sub-circuit, a reset sub-circuit, a coupling sub-circuit, a storage sub-circuit, and a light-emitting element, wherein: The driving sub-circuit is configured to provide driving current to the light-emitting element under the control of the signals of the first node and the second node; The write sub-circuit is configured to write the signal from the data signal terminal to the second node under the control of the signal from the scan signal terminal; The storage sub-circuit is configured to store the voltage of the first node; The coupling sub-circuit is configured to boost the voltage of the first node through coupling. The reset sub-circuit is configured to reset the fourth node under the control of the signal at the scanning signal terminal, and to reset the first node under the control of the signal at the reset control signal terminal, wherein the fourth node is the anode of the light-emitting element; The storage sub-circuit includes a first capacitor, and the coupling sub-circuit includes a second capacitor; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to a first voltage terminal; one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to the anode terminal of the light-emitting element. The charging voltage of the data signal terminal of the first pixel circuit is The charging voltage of the data signal terminal of the second pixel circuit is wherein is the voltage when the first light emitting element stably emits light, c2 is the capacitance value of the second capacitor, and cst is the capacitance value of the first capacitor.

2. The display panel according to claim 1, wherein the pixel circuit further comprises a compensation sub-circuit, a first light-emitting control sub-circuit, and a second light-emitting control sub-circuit, wherein: The compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit under the control of the signal at the scanning signal terminal; The first light-emitting control sub-circuit is configured to form a path between the first voltage terminal and the second node under the control of the signal at the light-emitting control signal terminal. The second light-emitting control sub-circuit is configured to form a path between the third node and the fourth node under the control of the signal at the light-emitting control signal terminal. One end of the light-emitting element is connected to the fourth node, and the other end of the light-emitting element is connected to the second voltage terminal.

3. The display panel of claim 2, wherein, The scanning signal terminal includes a first scanning signal terminal, the driving sub-circuit includes a third transistor, and the writing sub-circuit includes a fourth transistor; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; The control electrode of the fourth transistor is connected to the first scan signal terminal, the first electrode of the fourth transistor is connected to the data signal terminal, and the second electrode of the fourth transistor is connected to the second node.

4. The display panel of claim 3, wherein, The light emission control signal terminal includes a first light emission control signal terminal, the reset control signal terminal includes a first reset control signal terminal, the compensation sub-circuit includes a second transistor, the first light emission control sub-circuit includes a fifth transistor, the second light emission control sub-circuit includes a sixth transistor, and the reset sub-circuit includes a first transistor and a seventh transistor. The control electrode of the second transistor is connected to the first scan signal terminal, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the first node; The control electrode of the fifth transistor is connected to the first light-emitting control signal terminal, the first electrode of the fifth transistor is connected to the first voltage terminal, and the second electrode of the fifth transistor is connected to the second node; The control electrode of the sixth transistor is connected to the first light-emitting control signal terminal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node; The control electrode of the first transistor is connected to the first reset control signal terminal, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the first initial signal terminal. The control electrode of the seventh transistor is connected to the first scan signal terminal, the first electrode of the seventh transistor is connected to the second initial signal terminal, and the second electrode of the seventh transistor is connected to the fourth node.

5. The display panel of claim 3, wherein: The third transistor is a P-type thin-film transistor, and the fourth transistor is either a P-type thin-film transistor or an N-type thin-film transistor.

6. The display panel of claim 3, wherein, The scanning signal terminal further includes a second scanning signal terminal, the light emission control signal terminal includes a first light emission control signal terminal, the reset control signal terminal includes a first reset control signal terminal, the compensation sub-circuit includes a second transistor, the first light emission control sub-circuit includes a fifth transistor, the second light emission control sub-circuit includes a sixth transistor, and the reset sub-circuit includes a first transistor, a seventh transistor, and an eighth transistor. The control electrode of the second transistor is connected to the first scan signal terminal, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the fifth node; The control electrode of the fifth transistor is connected to the first light-emitting control signal terminal, the first electrode of the fifth transistor is connected to the first voltage terminal, and the second electrode of the fifth transistor is connected to the second node; The control electrode of the sixth transistor is connected to the first light-emitting control signal terminal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node; The control electrode of the first transistor is connected to the first reset control signal terminal, the first electrode of the first transistor is connected to the fifth node, and the second electrode of the first transistor is connected to the first initial signal terminal. The control electrode of the seventh transistor is connected to the first scan signal terminal, the first electrode of the seventh transistor is connected to the second initial signal terminal, and the second electrode of the seventh transistor is connected to the fourth node; The control electrode of the eighth transistor is connected to the second scan signal terminal, the first electrode of the eighth transistor is connected to the fifth node, and the second electrode of the eighth transistor is connected to the first node.

7. The display panel of claim 6, wherein: The first to the seventh transistors are all P-type thin-film transistors, and the eighth transistor is an N-type thin-film transistor.

8. A display panel, the display panel comprising a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; The display panel further comprises a plurality of pixel circuits and a plurality of first light emitting elements located in the first display area. The plurality of pixel circuits include: A plurality of first pixel circuits and a plurality of second pixel circuits, wherein the plurality of second pixel circuits are distributed among the plurality of first pixel circuits; At least one pixel circuit of the plurality of first pixel circuits is connected to at least one light-emitting element of the plurality of first light-emitting elements; The display panel also includes a plurality of second light-emitting elements located in the second display area; At least one pixel circuit of the plurality of second pixel circuits is connected to at least one light-emitting element of the plurality of second light-emitting elements; Both the first pixel circuit and the second pixel circuit are pixel circuits as described below: The pixel circuit includes a driving sub-circuit, a writing sub-circuit, a reset sub-circuit, a coupling sub-circuit, a storage sub-circuit, a second light-emitting control sub-circuit, and a light-emitting element, wherein: The driving sub-circuit is configured to provide driving current to the light-emitting element under the control of the signals of the first node and the second node; The write sub-circuit is configured to write the signal from the data signal terminal to the second node under the control of the signal from the scan signal terminal; The storage sub-circuit is configured to store the voltage of the first node; The coupling sub-circuit is configured to boost the voltage of the first node through coupling. The reset sub-circuit is configured to reset the fourth node under the control of the signal at the scanning signal terminal, and to reset the first node under the control of the signal at the reset control signal terminal, wherein the fourth node is the anode of the light-emitting element; The second light-emitting control sub-circuit is configured to form a path between the third node and the fourth node under the control of the signal at the light-emitting control signal terminal; The storage sub-circuit includes a first capacitor, and the coupling sub-circuit includes a second capacitor; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the third node; one end of the second capacitor is connected to the first node, and the other end of the second capacitor is connected to a first voltage terminal. The charging voltage at the data signal terminal of the first pixel circuit is The charging voltage at the data signal terminal of the second pixel circuit is ,in, C1 is the voltage at which the first light-emitting element emits light stably, C2 is the capacitance value of the second capacitor, and Cst is the capacitance value of the first capacitor.

9. The display panel according to claim 8, wherein, The scanning signal terminal includes a second scanning signal terminal, the light emission control signal terminal includes a second light emission control signal terminal, the reset control signal terminal includes a second reset control signal terminal, the pixel circuit further includes a first light emission control sub-circuit and a compensation sub-circuit, the compensation sub-circuit includes a second transistor, the driving sub-circuit includes a third transistor, the writing sub-circuit includes a fourth transistor, the first light emission control sub-circuit includes a fifth transistor, the second light emission control sub-circuit includes a sixth transistor, and the reset sub-circuit includes a first transistor and a seventh transistor; The control electrode of the second transistor is connected to the second scan signal terminal, the first electrode of the second transistor is connected to the third node, and the second electrode of the second transistor is connected to the first node; the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; the control electrode of the fourth transistor is connected to the second scan signal terminal, the first electrode of the fourth transistor is connected to the data signal terminal, and the second electrode of the fourth transistor is connected to the second node; the control electrode of the fifth transistor is connected to the second light emission control signal terminal, the first electrode of the fifth transistor is connected to the first voltage terminal, and the second electrode of the fifth transistor is connected to the second node; the control electrode of the sixth transistor is connected to the second light emission control signal terminal, the first electrode of the sixth transistor is connected to the third node, and the second electrode of the sixth transistor is connected to the fourth node; the control electrode of the first transistor is connected to the second reset control signal terminal, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the first initial signal terminal; the control electrode of the seventh transistor is connected to the second scan signal terminal, the first electrode of the seventh transistor is connected to the second initial signal terminal, and the second electrode of the seventh transistor is connected to the fourth node.

10. The display panel according to claim 9, wherein, The third transistor is an N-type thin-film transistor, the first transistor is a P-type or N-type thin-film transistor, the second transistor is a P-type or N-type thin-film transistor, the fourth transistor is a P-type or N-type thin-film transistor, the fifth transistor is a P-type or N-type thin-film transistor, the sixth transistor is a P-type or N-type thin-film transistor, and the seventh transistor is a P-type or N-type thin-film transistor.

11. A driving method for a display panel, used to drive the display panel as described in any one of claims 1 to 10, the driving method comprising: The reset sub-circuit resets the first node and the fourth node under the control of the reset control signal terminal and the scan signal terminal, wherein the fourth node is the anode of the light-emitting element; Under the control of the signal at the scanning signal terminal, the write sub-circuit writes the signal at the data signal terminal to the second node, wherein the charging voltage of the data signal terminal of the first pixel circuit is... The charging voltage at the data signal terminal of the second pixel circuit is ,in, C1 is the voltage at which the first light-emitting element emits light stably, C2 is the capacitance value of the second capacitor, and Cst is the capacitance value of the first capacitor. The storage sub-circuit stores the voltage of the first node; The coupler circuit increases the voltage of the first node through coupling. The driving sub-circuit provides driving current to the light-emitting element under the control of the signals from the first and second nodes.

12. A display device comprising a display panel and a photosensitive element, wherein the display panel is the display panel according to any one of claims 1 to 10.

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