Group iii nitride transistor with back-barrier structure and buried p-type layer and methods thereof

Abstract

An apparatus configured to reduce lag, comprising: a substrate; a group III-nitride back barrier layer on the substrate; a group III-nitride channel layer on the group III-nitride back barrier layer; a group III-nitride barrier layer on the group III-nitride channel layer, the group III-nitride barrier layer comprising a bandgap higher than a bandgap of the group III-nitride channel layer; a source electrically coupled to the group III-nitride barrier layer; a gate on the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region disposed at or below the group III-nitride barrier layer. Additionally, at least a portion of the p-region is disposed vertically below at least one of: the source, the gate, a region between the gate and the drain.

Description

Technical Field

[0001] This disclosure relates to a group III nitride transistor having a back barrier structure and a buried p-type layer, and methods thereof. This disclosure also relates to a group III nitride transistor having a back barrier structure and a buried p-type layer. This disclosure further relates to methods associated with a group III nitride transistor having a back barrier structure and a buried p-type layer. This disclosure also relates to methods for manufacturing a group III nitride transistor having a back barrier structure and a buried p-type layer. This disclosure further relates to methods for realizing a group III nitride transistor having a back barrier structure and a buried p-type layer. Background Technology

[0002] Group III nitride-based or gallium nitride (GaN)-based high electron mobility transistors (HEMTs) are outstanding representatives for high-power radio frequency (RF) applications, whether in discrete or MMIC (monolithic microwave integrated circuit) form. Current GaNHEMT designs use buffer layers including traps to achieve the desired breakdown. However, these traps lead to memory effects, which adversely affect performance. Specifically, these designs exhibit some trapping associated with the so-called "hysteresis effect."

[0003] Therefore, a solution is needed to address the hysteresis effect and / or other negative performance issues in group III nitride HEMTs and improve the performance of such devices. Summary of the Invention

[0004] One general aspect includes an apparatus comprising: a substrate; a group III nitride back barrier layer on the substrate; a group III nitride channel layer on the group III nitride back barrier layer; a group III nitride barrier layer on the group III nitride channel layer, the group III nitride barrier layer including a band gap higher than the band gap of the group III nitride channel layer; a source electrically coupled to the group III nitride barrier layer; a gate on the group III nitride barrier layer; a drain electrically coupled to the group III nitride barrier layer; and a p-region disposed at or below the group III nitride barrier layer, wherein at least a portion of the p-region is perpendicularly disposed below at least one of the following: the source, the gate, and a region between the gate and the drain.

[0005] One general aspect includes a method of manufacturing a device, the method comprising: setting a substrate; setting a group III nitride back barrier layer on the substrate; setting a group III nitride channel layer on the group III nitride back barrier layer; setting a group III nitride barrier layer on the group III nitride channel layer, the group III nitride barrier layer including a band gap higher than the band gap of the group III nitride channel layer; electrically coupling a source to the group III nitride barrier layer; arranging a gate on the group III nitride barrier layer; electrically coupling a drain to the group III nitride barrier layer; and setting a p-region disposed at or below the group III nitride barrier layer, wherein at least a portion of the p-region is vertically disposed below at least one of the following: a source, a gate, and a region between the gate and the drain.

[0006] One general aspect includes a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0007] One general aspect includes a method associated with a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0008] One general aspect includes a method for implementing a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0009] One general aspect includes a method for manufacturing a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0010] Additional features, advantages, and aspects of this disclosure will be set forth or become clear by considering the following detailed description, accompanying drawings, and claims. Furthermore, it should be understood that the foregoing summary of this disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the claimed disclosure. Attached Figure Description

[0011] The accompanying drawings, included to provide a further understanding of this disclosure and forming part of this specification, illustrate various aspects of the disclosure and, together with the specific embodiments, serve to explain the principles of the disclosure. No attempt is made to show the structural details of the disclosure in more detail than necessary for a basic understanding and practice of the disclosure. In the drawings: Figure 1 A cross-sectional view of one aspect of a transistor according to the present disclosure is shown.

[0012] Figure 2 It shows according to Figure 1 A cross-sectional view of one aspect of a transistor.

[0013] Figure 3 It shows according to Figure 1 A cross-sectional view of one aspect of a transistor.

[0014] Figure 4 A semiconductor device comprising a plurality of unit cell transistors is shown according to one aspect of the present disclosure.

[0015] Figure 5 It is along Figure 4 A schematic cross-sectional view of line VV.

[0016] Figure 6 The energy band diagram of the disclosed transistor is shown compared to that of a typical transistor at certain operating values.

[0017] Figure 7 The energy band diagram of the disclosed transistor is shown compared to that of a typical transistor at certain operating values.

[0018] Figure 8 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0019] Figure 9 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0020] Figure 10 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0021] Figure 11 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0022] Figure 12 A process for manufacturing a transistor according to this disclosure is shown. Detailed Implementation

[0023] The various aspects, features, and advantageous details of this disclosure are explained more fully with reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features shown in the drawings are not necessarily drawn to scale, and as those skilled in the art will recognize, features of one aspect may be used in conjunction with those of other aspects, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as not to unnecessarily obscure the aspects of this disclosure. The examples used herein are intended only to facilitate understanding of how this disclosure may be practiced and, further, to enable those skilled in the art to practice the aspects of this disclosure. Therefore, the embodiments and aspects herein should not be construed as limiting the scope of this disclosure solely by the appended claims and applicable law. Furthermore, it should be noted that similar reference numerals denote similar parts throughout the several views of the drawings and in the different aspects disclosed.

[0024] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," the element may be directly located on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," the element may be directly above or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, the element may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0026] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as shown in the figures. It should be understood that these terms, and those mentioned above, are intended to include different orientations of the device other than those depicted in the figures.

[0027] The terminology used herein is for descriptive purposes only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0029] Besides the type of structure, the properties of the semiconductor material forming the transistor can also affect the operating parameters. Among the properties that influence transistor operating parameters, electron mobility, saturated electron drift velocity, breakdown field strength, and thermal conductivity can affect the high-frequency and high-power characteristics of the transistor.

[0030] Electron mobility measures how quickly electrons are accelerated to their saturation velocity in the presence of an electric field. In the past, semiconductor materials with high electron mobility were preferred because more current could be generated with a smaller field, resulting in a faster response time when the field was applied. Saturation electron drift velocity is the maximum velocity that electrons can achieve in a semiconductor material. Materials with higher saturation electron drift velocities are preferred for high-frequency applications because the higher velocity translates to a shorter time from the source to the drain.

[0031] The breakdown field strength is the field strength at which a Schottky junction breaks down and the current through the device's gate suddenly increases. High breakdown field strength materials are preferred for high-power, high-frequency transistors because materials of a given size can typically support larger electric fields. Larger electric fields allow for faster transients because electrons are accelerated more quickly compared to smaller electric fields.

[0032] Thermal conductivity is the ability of a semiconductor material to dissipate heat. In typical operation, all transistors generate heat. In turn, high-power and high-frequency transistors typically generate more heat than small-signal transistors. As the temperature of a semiconductor material increases, the junction leakage current typically increases, and the current through a field-effect transistor typically decreases, because carrier mobility decreases with increasing temperature. Therefore, if heat is dissipated from the semiconductor, the material will remain at a lower temperature and be able to carry a larger current with a lower leakage current.

[0033] This disclosure includes both intrinsic and extrinsic semiconductors. Intrinsic semiconductors are undoped (pure). Doping an intrinsic semiconductor means that a reagent has been introduced to change the electron and hole carrier concentrations of the semiconductor under thermal equilibrium. Both p-type and n-type semiconductors are disclosed, wherein the p-type has a hole concentration greater than the electron concentration, and the n-type has an electron concentration greater than the hole concentration.

[0034] Silicon carbide (SiC) possesses superior physical and electronic properties, which theoretically should allow for the production of electronic devices that can operate at higher temperatures, higher power, and higher frequencies than devices fabricated from silicon (Si) or gallium arsenide (GaAs) substrates. Approximately 4 × 10⁻⁶ 6 High breakdown field strength of (4×E6) V / cm, approximately 2.0×10 7 The high saturated electron drift velocity of (2.0 × E7) cm / s and the high thermal conductivity of approximately 4.9 W / cm⁻¹°K indicate that SiC will be suitable for high-frequency and high-power applications. In some aspects, the transistors disclosed herein include Si, GaAs, or other suitable substrates.

[0035] GaN-based HEMTs are outstanding examples of high-power RF applications, whether discrete or MMIC-based. GaN HEMT designs can utilize buffer layers including traps to achieve the desired breakdown. However, these traps can lead to memory effects, which adversely affect performance. To overcome this limitation, structures with buried p-layers can be used to achieve breakdown with minimal trapping. These devices demonstrate reductions and / or elimination of drain hysteresis effects and portions of the trapping associated with this effect. However, they still exhibit some trapping associated with the so-called “gate hysteresis effect,” particularly at high negative gate voltages.

[0036] More specifically, the overall hysteresis in a transistor, such as a GaN-based HEMT, can be a combination of gate hysteresis and drain hysteresis. In certain aspects, implementing various methods to reduce the first type of hysteresis may lead to the second type of hysteresis becoming more prevalent, amplified, or more significant. Therefore, addressing the overall hysteresis in a transistor (such as a GaN-based HEMT) may require implementing structures to reduce the first type of hysteresis, which leads to the second type of hysteresis becoming more prevalent, amplified, or more significant, potentially requiring additional structures to address the second type of hysteresis. In certain aspects, addressing the overall hysteresis in a transistor (such as a GaN-based HEMT) may require implementing drain hysteresis reduction structures and / or processes to reduce drain hysteresis and additional gate hysteresis reduction structures and / or processes to reduce gate hysteresis.

[0037] This disclosure includes devices and / or processes for providing systematic methods to reduce hysteresis. More specifically, this disclosure includes devices and / or processes for implementing drain hysteresis reduction structures and / or processes for reducing drain hysteresis effects, as well as processes for adding gate hysteresis reduction structures and / or reducing gate hysteresis effects.

[0038] This disclosure includes devices and / or processes having structures that use buried p-layers to reduce trapping in GaN HEMTs. These devices and / or processes have been found to significantly reduce and / or eliminate trapping associated with drain hysteresis during a limited operating envelope and also reduce and / or eliminate gate hysteresis trapping. For example, for some implementations of GaN HEMTs, there is a reverse bias voltage up to about -8V (volts) on the gate. However, outside the limited operating envelope, gate hysteresis trapping effects may exist, for example, when the gate voltage is below -8V. In some applications, this gate hysteresis may be undesirable and needs to be reduced or eliminated.

[0039] Simulations have shown that when using conventional buffer structures, this gate hysteresis effect arises from the injection and trapping of electrons in the buffer layer under large negative gate voltages. For example, when using a conventional buffer structure with unintentionally doped GaN, electrons are injected and trapped in the buffer layer under large negative gate voltages.

[0040] This disclosure includes devices and / or processes for reducing and / or limiting gate hysteresis effects. For example, this disclosure includes devices and / or processes using a low-aluminum (Al) concentration aluminum gallium nitride (AlGaN) buffer layer to provide a barrier that reduces electron injection into the buffer layer. For example, an AlGaN buffer layer with approximately 4% Al concentration provides a barrier that reduces electron injection into the buffer layer. Simulations clearly illustrate the reduction of gate hysteresis using the disclosed buffer layer. Specifically, in some implementations, simulations clearly demonstrate that using the disclosed buffer layer reduces gate hysteresis to at least -15V gate bias.

[0041] Additionally, this disclosure includes devices and / or processes for reducing and / or limiting gate hysteresis effects by reducing the implantation of background impurities (such as silicon (Si), oxygen (O), carbon (C), etc.) in a buffer layer (such as the disclosed AlGaN buffer layer) through epitaxial growth. When using an AlGaN back barrier, it has been found that implanting high concentrations of high-level background impurities is a problem. The disclosed devices and / or processes can be implemented such that impurity implantation is significantly reduced. More specifically, aspects of this disclosure can achieve a back barrier with low background impurity levels. In one aspect, this disclosure can achieve an AlGaN back barrier with low background impurity levels. At this point, it has been found that impurities form complexes with dislocations (such as point defects), which also act as deep trap levels.

[0042] When GaN is grown in SiC, high-density crossing dislocations can form due to lattice mismatch. These defects can lead to current leakage, low breakdown voltage, carrier traps, etc. Another source of defects may be impurities, which can act as unintentional dopants and form trap centers, etc. To prevent deep penetration of electrons in the GaN buffer layer, an AlGaN buffer layer can be used to confine electrons in the GaN channel to the AlGaN barrier.

[0043] The devices and / or processes disclosed herein may include buried p-layer structures (such as GaNHEMT devices) in transistor implementations and exhibit very positive effects, wherein drain hysteresis has been significantly reduced and / or eliminated. However, these devices still suffer from gate hysteresis effects. For example, these devices still suffer from gate hysteresis effects at elevated negative gate voltages. Traps in the buffer layer can cause response delays. Simulations show that AlGaN buffer layers grown on buried p-layer substrates with very low background impurity levels of carbon, silicon, oxygen, etc., can significantly improve electron confinement and reduce and / or eliminate gate hysteresis, and can also reduce and / or eliminate overall hysteresis.

[0044] Figure 1 A cross-sectional view of one aspect of a transistor according to the present disclosure is shown.

[0045] Specifically, Figure 1 A cross-sectional view of transistor 100 is shown. Transistor 100 may include a substrate layer 102. The substrate layer 102 may be made of silicon carbide (SiC). In some aspects, the substrate layer 102 may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, etc. In some aspects, the substrate layer 102 may be very lightly doped. In one aspect, the background impurity level may be low. In another aspect, the background impurity level may be 1 × 10⁻⁶. 15 / cm 3 Or lower. In one aspect, the substrate layer 102 may be formed of SiC selected from the group consisting of 6H, 4H, 15R, 3C SiC, etc. In another aspect, the substrate layer 102 may be formed of SiC, which may be semi-insulating and doped with vanadium or any other suitable dopant, or high-purity undoped SiC with defects (providing semi-insulating properties).

[0046] In another aspect, substrate layer 102 may be GaAs, GaN, or other materials suitable for the applications described herein. In another aspect, substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of group III nitride materials. In a particular aspect, substrate layer 102 may include a flat upper surface that is generally parallel to... Figure 1The X-axis is shown and / or generally parallel to the Z-axis (perpendicular to the X and Y axes). In a particular aspect, substrate layer 102 may include a flat lower surface that is generally parallel to the Z-axis. Figure 1 The X-axis is shown and / or generally parallel to the Z-axis (perpendicular to both the X and Y axes). The upper and lower surfaces are defined along the Y-axis.

[0047] Transistor 100 may include a buried p-region or a p-type material layer 106 that may be formed within substrate layer 102. The p-type material layer 106 may be configured to at least partially form a drain hysteresis reduction structure, a drain hysteresis elimination structure, etc. The p-type material layer 106 may be disposed solely within substrate layer 102, may extend from substrate layer 102 to an epitaxial layer within transistor 100, and / or may be located solely within the epitaxial layer of transistor 100. Dopants may be incorporated into the epitaxial layer via individual ion implantation, epitaxial growth, a combination of both, etc. The p-type material layer 106 may span multiple layers and include multiple regions with different or hierarchical p-doped structures. According to other aspects of this disclosure, the p-type material layer 106 may also be formed below and / or within substrate layer 102 between barrier layer 108 and substrate layer 102.

[0048] According to various aspects of this disclosure, at least some portions of the substrate layer 102 may include a p-type material layer 106. According to various aspects of this disclosure, the p-type material layer 106 can be formed by ion implantation and annealing of aluminum (Al). In other aspects, the p-type material layer 106 can be formed by ion implantation of boron, gallium, or any other material or combination of these materials that can form a p-type layer. In one aspect, the p-type material layer 106 may be formed by Al implantation and annealing prior to the growth of any GaN layer. In one aspect, ion implantation may utilize channel implantation. In one aspect, channel implantation may include aligning an ion beam with the substrate layer 102. Alignment of the ion beam may result in increased implantation efficiency. In other aspects, ion implantation may not utilize channelization.

[0049] Various aspects of this disclosure allow for the controllable formation of implanted regions of a p-type material layer 106 in a silicon carbide implementation of a substrate layer 102 using channel implantation. These implanted regions are highly uniform in depth and also result in reduced lattice damage. Channelization occurs as ions are implanted along the crystal axis of the substrate layer 102. When the implantation direction is close to the principal axis of the lattice, the atoms in the lattice appear to be "aligned" relative to the implantation direction, and the implanted ions appear to travel downwards along the channels formed by the crystal structure to form the p-type material layer 106. This reduces the likelihood of collisions between the implanted ions and atoms in the lattice. Therefore, the implantation depth of the p-type material layer 106 can be significantly increased.

[0050] Typically, channelization occurs in silicon carbide when the implantation direction is within approximately ±0.2° of the crystal axis of the silicon carbide crystal. In some respects, implantation can be greater than ±0.2° of the crystal axis of the silicon carbide crystal; however, implantation may be less effective. For example, when the implantation direction is greater than approximately ±0.2° of the crystal axis of the silicon carbide crystal, the atoms in the lattice may appear to be randomly distributed relative to the implantation direction, which can reduce channeling effects. As used herein, the term "implantation angle" refers to the implantation direction relative to the crystal axis (such as the c-axis or sigma axis) of the semiconductor layer containing the implanted ions. <0001> The angle between the c-axis and the silicon carbide layer. Therefore, an implantation angle of less than approximately 2° relative to the c-axis of the silicon carbide layer can be expected to result in channelization. However, other implantation angles can also be utilized.

[0051] In one aspect, the p-type material layer 106 can be ion implanted in 4H-SiC. 27 Al was formed, and the injection was performed at 25°C with a dose of 1×10. 13 (1E13)cm 2 The implantation was carried out under channel conditions with an implantation energy of E1 = 100 keV. In one aspect, the p-type material layer 106 can be implanted by ion implantation in 4H-SiC. 27 Al was formed, and the injection was performed at 25°C with a dose of 1×10. 13 cm 2 The injection is performed under channel conditions with an injection energy of E2 = 300 keV. However, other injection energies and doses can also be considered. For example, in some aspects, the injection energy can be 20 keV to 80 keV, 80 keV to 120 keV, 120 keV to 160 keV, 160 keV to 200 keV, 200 keV to 240 keV, 240 keV to 280 keV, 280 keV to 340 keV, 340 keV to 400 keV, 20 keV to 400 keV, and / or 80 keV to 340 keV; and in some aspects, the injection dose can be 0.6 × 10⁻⁶. 13 cm 2 Up to 0.8×10 13 cm 2 0.8×10 13 cm 2 Up to 1.2×10 13 cm 2 1.2×10 13 cm 2 Up to 1.6×10 13 cm 2 1.6×10 13 cm 2 Up to 2×10 13 cm 2 0.6×10 13 cm2 Up to 2×10 13 cm 2 and / or 0.8 × 10 13 cm 2 Up to 1.2×10 13 cm 2 Furthermore, it should be noted that the p-type material layer 106 can be formed by implanting other materials (such as boron (B), gallium (Ga), etc.) and can then be subjected to high-temperature annealing.

[0052] In one aspect, ion implantation may result in a deep p-type material layer 106. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 1 µm or less. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.7 µm or less. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.5 µm or less. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.3 µm to 0.5 µm. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.2 µm to 0.6 µm. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.4 µm to 0.6 µm. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.6 µm to 0.8 µm. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.6 µm to 1.6 µm. In one aspect, ion implantation may result in a p-type material layer 106 thickness of 0.6 µm to 2.1 µm. In another aspect, ion implantation may result in a p-type material layer 106 thickness of 1 µm to 5 µm. In another aspect, the implantation and / or doping of the p-type material layer 106 may be 5 × 10⁻⁶ cm². 15 Up to 5×10 17 Within a certain range, and extending to depths of up to 5 µm.

[0053] In one aspect, ion implantation may result in the thickness of the p-type material layer 106 being 0.05% to 0.3% of the thickness of the substrate layer 102. In another aspect, ion implantation may result in the thickness of the p-type material layer 106 being 0.05% to 0.1% of the thickness of the substrate layer 102. In another aspect, ion implantation may result in the thickness of the p-type material layer 106 being 0.1% to 0.15% of the thickness of the substrate layer 102. In another aspect, ion implantation may result in the thickness of the p-type material layer 106 being 0.15% to 0.2% of the thickness of the substrate layer 102. In another aspect, ion implantation may result in the thickness of the p-type material layer 106 being 0.2% to 0.25% of the thickness of the substrate layer 102. In another aspect, ion implantation may result in the thickness of the p-type material layer 106 being 0.25% to 0.3% of the thickness of the substrate layer 102.

[0054] The p-type material layer 106 can be implanted into the substrate layer 102 and subsequently annealed. Annealing allows implantation to be activated. In one aspect, a masking layer material can be used during implantation. In some aspects, a capping layer material can be used to cover the wafer surface during the annealing of the p-type material layer 106 to prevent the substrate from delaminating at high temperatures. Once the p-type material layer 106 has been formed, the masking layer material can be removed. Annealing can be performed for 5 to 30 minutes in a temperature range of 1500°C–1850°C. Other annealing times and temperature distributions are also possible.

[0055] In some aspects, substrate layer 102 may be made of a p-type material SiC substrate. Furthermore, in this aspect, the SiC substrate of substrate layer 102, being a p-type material, may subsequently undergo the processes described herein, including implantation of an additional p-type layer. In various aspects of the transistor 100 of this disclosure, p-type material layer 106 may be neutralized to limit the length of p-type material layer 106. In one aspect, neutralization may include the implantation of impurities. In one aspect, neutralizing p-type material layer 106 may include absorbing the charge of p-type material layer 106 with a material of opposite polarity. Another way to limit the length of p-type material layer 106 may be by etching p-type material layer 106. Another way to limit the length of p-type material layer 106 may be by using a mask material to limit the area for implantation.

[0056] In various aspects of the transistor 100 of this disclosure, the p-type material layer 106 can be formed by growing a p-type material layer 106. For example, the growth can be epitaxial. To limit the length of the p-type material layer 106, it can be etched or otherwise neutralized. In various aspects of the transistor 100 of this disclosure, the substrate layer 102 can be etched and the p-type material layer 106 can be formed by growing it. In one aspect, the growth can be epitaxial.

[0057] In various aspects of the transistor 100 of this disclosure, the p-type material layer 106 may be an epitaxial layer and may be GaN. In some aspects, the p-type material layer 106 may be an epitaxial layer and may be GaN, and the p-type material layer 106 may include magnesium (Mg), carbon (C), and / or zinc. In some aspects, the p-type material layer 106 may be an epitaxial layer and may be GaN, and the p-type material layer 106 may include implantation of magnesium (Mg), carbon (C), and / or zinc.

[0058] In various aspects of the transistor 100 of this disclosure, the substrate layer 102 can be etched and the p-type material layer 106 can be formed by growing a p-type material layer 106. In one aspect, the growth can be epitaxial. In various aspects of the transistor 100 of this disclosure, the p-type material layer 106 can be an epitaxial layer formed of SiC. In some aspects, the p-type material layer 106 can be an epitaxial layer and can be SiC, and the p-type material layer 106 can include Al and / or Br. In some aspects, the p-type material layer 106 can be an epitaxial layer and can be SiC, and the p-type material layer 106 can include Al and / or Br implantation.

[0059] In some aspects, the thickness of the p-type material layer 106 can be less than 0.6 µm. In some aspects, the thickness of the p-type material layer 106 can be less than 0.5 µm. In some aspects, the thickness of the p-type material layer 106 can be less than 0.4 µm. In some aspects, the thickness of the p-type material layer 106 can be less than 0.3 µm. In some aspects, the thickness of the p-type material layer 106 can be less than 0.2 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.1 µm and 0.6 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.5 µm and 0.6 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.4 µm and 0.5 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.3 µm and 0.4 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.2 µm and 0.3 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.1 µm and 0.3 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.05 µm and 0.25 µm. In some aspects, the thickness of the p-type material layer 106 can be between 0.15 µm and 0.25 µm.

[0060] In various aspects of the transistor 100 of this disclosure, the p-type material layer 106 may be a gradient layer. In one aspect, the p-type material layer 106 may be a stepped gradient layer. In another aspect, the p-type material layer 106 may be multiple layers. In a particular aspect, the p-type material layer 106 may include a flat upper surface that is generally parallel to... Figure 1 The X-axis is shown and / or generally parallel to the Z-axis (perpendicular to the X and Y axes). In a particular aspect, the p-type material layer 106 may include a flat lower surface that is generally parallel to the Z-axis. Figure 1 The X-axis is shown and / or generally parallel to the Z-axis (perpendicular to both the X and Y axes). The upper and lower surfaces are defined along the Y-axis.

[0061] Depending on the material of the substrate layer 102, a nucleation layer 136 may be formed on the substrate layer 102 to reduce lattice mismatch between the substrate layer 102 and the next layer in the transistor 100. In one aspect, the nucleation layer 136 may be formed directly on the substrate layer 102. In other aspects, the nucleation layer 136 may be formed on the substrate layer 102 together with an intermediate layer (such as a SiC epitaxial layer formed on a SiC implementation of the substrate layer 102). In other aspects, the nucleation layer is aluminum nitride (AlN), such as undoped AlN.

[0062] The nucleation layer 136 may include or may be various suitable materials, such as group III nitride materials. For example, Al x In y1-x-y GaN (where 0≤x≤1, 0≤y≤1, x+y≤1), AlGaN, undoped AlGaN, etc. The nucleation layer 136 can be formed on the substrate layer 102 using known semiconductor growth techniques such as metal oxide chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), etc.

[0063] In various aspects of the transistor 100 of this disclosure, the back barrier layer 120 may be formed directly on the nucleation layer 136 or formed together with the intermediate layer on the nucleation layer 136. In various aspects of the transistor 100 of this disclosure, the back barrier layer 120 may be formed directly on the substrate layer 102 or formed together with the intermediate layer on the substrate layer 102. Specifically, the back barrier layer 120 may be at least partially configured as a gate hysteresis reduction structure, a gate hysteresis elimination structure, etc. Specifically, the back barrier layer 120, which is at least partially configured as a gate hysteresis reduction structure, a gate hysteresis elimination structure, etc., in conjunction with the p-type material layer 106 which is at least partially configured as a drain hysteresis reduction structure, a drain hysteresis elimination structure, etc., can operate synergistically to reduce the overall hysteresis of the transistor 100. As further described herein, this synergistic overall reduction of the hysteresis of the transistor 100 is an unexpected result of the combined structure of the back barrier layer 120 and the p-type material layer 106.

[0064] More specifically, a systematic approach to reducing hysteresis can be provided by incorporating the disclosed p-type material layer 106 and back barrier layer 120, their associated structures, and / or their associated processes. More specifically, the transistor 100 of this disclosure can implement the p-type material layer 106 and / or its processes as drain hysteresis reduction structures and / or processes for reducing drain hysteresis effects, and the transistor 100 of this disclosure can implement the back barrier layer 120 and / or its processes as gate hysteresis reduction structures and / or processes for reducing gate hysteresis effects.

[0065] In this respect, it has been determined that impurities (such as silicon, oxygen, carbon, etc.) in the back barrier layer 120 can increase gate hysteresis. Specifically, impurities provide trapping, leakage, etc. More specifically, aspects of this disclosure can realize a back barrier layer 120 with a low background impurity level. In one aspect, this disclosure can realize AlGaN for a back barrier layer 120 with a low background impurity level. In this respect, it has been found that impurities form complexes with dislocations (such as point defects), which also act as deep trap levels.

[0066] More specifically, this disclosure enables AlGaN for use in a back barrier layer 120 with a low background impurity level, wherein the low background impurity level can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter, or less than 1×10 15 Impurities per cubic centimeter. Furthermore, this disclosure enables the realization of AlGaN with a back barrier layer 120 having low background impurity levels of silicon, oxygen, carbon, etc., wherein the low background impurity levels of silicon, oxygen, carbon, etc., can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter, or less than 1×10 15 Impurities such as silicon, oxygen, and carbon per cubic centimeter.

[0067] Furthermore, this disclosure enables the implementation of AlGaN with a back barrier layer 120 having low background impurity levels of silicon and oxygen, wherein the low background impurity levels of silicon and oxygen can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter, or less than 1×10 15 Impurities per cubic centimeter. In one aspect, low background impurity levels of silicon and oxygen, wherein the low background impurity levels of silicon and oxygen can be defined as less than 1 × 10⁻⁶. 16The silicon and oxygen impurities. Furthermore, this disclosure enables the realization of AlGaN with a back barrier layer 120 having a low background carbon impurity level, wherein the low background carbon impurity level can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter or less than 1×10 15 Impurities per cubic centimeter. In one aspect, the low background impurity level of carbon, wherein the low background impurity level of carbon can be defined as less than 5 × 10⁻⁶. 16 Carbon impurities.

[0068] Alternatively, the low background impurity level can be defined as being between 1 × 10⁻⁶. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities between 1 × 10⁻⁶ per cubic centimeter. Specifically, low background impurity levels can be defined as between 1 × 10⁻⁶ per cubic centimeter. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per square centimeter and 1×10 16 Between per cubic centimeter, 1×10 16 per square centimeter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities such as silicon, oxygen, and carbon per square centimeter.

[0069] Specifically, the low background impurity level can be defined as being between 1×10⁻⁶. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities of silicon and oxygen per cubic centimeter.

[0070] Specifically, the low background impurity level can be defined as being between 1×10⁻⁶. 15 per cubic centimeter and 1×1017 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Low background impurities are defined as silicon and oxygen impurities between 1 × 10⁻⁶ per cubic centimeter. Specifically, low background impurity levels can be defined as between 1 × 10⁻⁶ per cubic centimeter. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities of carbon per cubic centimeter.

[0071] Additionally, the back barrier layer 120 can be configured to provide a sharp interface to the channel layer 104. This interface can serve as a barrier for electrons. In various aspects of the transistor 100 of this disclosure, the back barrier layer 120 can be a gradient layer. In one aspect, the back barrier layer 120 can be a stepped gradient layer. In another aspect, the back barrier layer 120 can be multiple layers.

[0072] In a specific aspect, the back barrier layer 120 can be a low-Al-concentration AlGaN buffer layer to provide a barrier to reduce electron injection into the buffer layer. In this respect, the barrier to reduce electron injection into the buffer layer leads to gate hysteresis reduction structures, gate hysteresis elimination structures, etc. For example, the back barrier layer 120 can be implemented using AlGaN with an Al concentration of approximately 4% to provide a barrier to reduce electron injection into the buffer layer. In this respect, it can be approximately within the range of 0.5%, 1%, 1.5%, or 2%. In certain aspects, the back barrier layer 120 can be implemented using AlGaN having an Al concentration of 1% to 6%, 1% to 1.5%, 1.5% to 2%, 2% to 2.5%, 2.5% to 3%, 3% to 3.5%, 3.5% to 4%, 3.5% to 4.5%, 3.8% to 4.2%, 4% to 4.5%, 4.5% to 5%, 5% to 5.5%, or 5.5% to 6% to provide a barrier, gate hysteresis reduction structure, gate hysteresis elimination structure, etc., to reduce electron injection into the buffer layer.

[0073] In various respects, transistor 100 can have finite gate hysteresis during a finite operating envelope. For example, in some implementations of GaN HEMT, there is a reverse bias of up to about -8V (volts) on the gate. However, for implementations outside the finite operating envelope where a gate hysteresis trapping effect may exist, the back barrier layer 120 can be configured to reduce gate hysteresis, eliminate gate hysteresis, etc. For example, in an implementation of transistor 100 where the gate voltage becomes below -8V. Specifically, the back barrier layer 120, which is at least partially configured as a gate hysteresis reduction structure, gate hysteresis elimination structure, etc., operates synergistically with the p-type material layer 106, which is at least partially configured as a drain hysteresis reduction structure, drain hysteresis elimination structure, etc., to reduce the overall hysteresis of transistor 100 during such low gate voltage conditions. As further described herein, this synergistic overall reduction of the hysteresis of transistor 100 is an unexpected result of the combined structure of the back barrier layer 120 and the p-type material layer 106.

[0074] Furthermore, the back barrier layer 120 of transistor 100 can be further configured and / or processed to reduce and / or limit gate hysteresis effects by achieving its epitaxial growth. Specifically, the back barrier layer 120 of transistor 100 can be further configured and / or processed to reduce and / or limit gate hysteresis effects by achieving epitaxial growth while reducing the incorporation of background impurities (such as silicon (Si), oxygen (O), carbon (C), etc.) in the AlGaN of the implementation mode of the back barrier layer 120. More specifically, aspects of this disclosure can realize a back barrier layer 120 with a low background impurity level. In one aspect, this disclosure can realize AlGaN for a back barrier layer 120 with a low background impurity level. At this point, it has been found that impurities form complexes with dislocations (such as point defects), which also act as deep trap levels. At this point, it has been found that when using AlGaN as the back barrier layer 120, implanting a high concentration of high-level background impurities in the back barrier layer 120 is a problem. The back barrier layer 120 enables epitaxial growth with significantly reduced impurity implantation. More specifically, the back barrier layer 120 can be achieved through epitaxial growth of AlGaN, which reduces the implantation of background impurities such as silicon (Si), oxygen (O), and carbon (C).

[0075] More specifically, this disclosure enables AlGaN for use in a back barrier layer 120 with a low background impurity level, wherein the low background impurity level can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter, or less than 1×10 15Impurities per cubic centimeter. Furthermore, this disclosure enables the realization of AlGaN with a back barrier layer 120 having low background impurity levels of silicon, oxygen, carbon, etc., wherein the low background impurity levels of silicon, oxygen, carbon, etc., can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter, or less than 1×10 15 Impurities such as silicon, oxygen, and carbon per cubic centimeter.

[0076] Furthermore, this disclosure enables the implementation of AlGaN with a back barrier layer 120 having low background impurity levels of silicon and oxygen, wherein the low background impurity levels of silicon and oxygen can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter, or less than 1×10 15 Impurities per cubic centimeter. In one aspect, low background impurity levels of silicon and oxygen, wherein the low background impurity levels of silicon and oxygen can be defined as less than 1 × 10⁻⁶. 16 The silicon and oxygen impurities. Furthermore, this disclosure enables the realization of AlGaN with a back barrier layer 120 having a low background carbon impurity level, wherein the low background carbon impurity level can be limited to less than 1 × 10⁻⁶. 17 per cubic centimeter (cm), less than 5×10 16 per cubic centimeter, less than 1×10 16 per cubic centimeter or less than 1×10 15 Impurities per cubic centimeter. In one aspect, the low background impurity level of carbon, wherein the low background impurity level of carbon can be defined as less than 5 × 10⁻⁶. 16 Carbon impurities.

[0077] Alternatively, the low background impurity level can be defined as being between 1 × 10⁻⁶. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities between 1 × 10⁻⁶ per cubic centimeter. Specifically, low background impurity levels can be defined as between 1 × 10⁻⁶ per cubic centimeter. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per square centimeter and 1×1016 Between per cubic centimeter, 1×10 16 per square centimeter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities such as silicon, oxygen, and carbon per square centimeter.

[0078] Specifically, the low background impurity level can be defined as being between 1×10⁻⁶. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities of silicon and oxygen per cubic centimeter.

[0079] Specifically, the low background impurity level can be defined as being between 1×10⁻⁶. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Low background impurities are defined as silicon and oxygen impurities between 1 × 10⁻⁶ per cubic centimeter. Specifically, low background impurity levels can be defined as between 1 × 10⁻⁶ per cubic centimeter. 15 per cubic centimeter and 1×10 17 Between per cubic centimeter, 1×10 15 per cubic meter and 1×10 16 Between per cubic centimeter, 1×10 16 per cubic meter and 5×10 16 Between per cubic centimeter or 5×10 16 per cubic centimeter and 1×10 17 Impurities of carbon per cubic centimeter.

[0080] In this respect, it has been found that the source of defects can be impurities, which can act as unintentional dopants and form trap centers in transistor 100, etc. To prevent deep penetration of electrons in the GaN buffer layer or channel layer 104 of transistor 100, the back barrier layer 120 can be implemented as an AlGaN buffer layer as described herein, and can be used to confine electrons in the channel layer 104 to the back barrier layer 120. The disclosed implementation and configuration of the back barrier layer 120 have further been shown to improve the breakdown voltage in transistor 100 and / or the GaN HEMT implementation of transistor 100.

[0081] Therefore, transistor 100 may include a p-type material layer 106 as described herein to significantly reduce and / or eliminate drain hysteresis. However, transistor 100 may still suffer from gate hysteresis. For example, transistor 100 may still suffer from gate hysteresis under elevated negative gate voltage. Traps in the buffer layer of transistor 100 may cause this delay. Therefore, back barrier layer 120 may be implemented using AlGaN grown on p-type material layer 106 with very low background impurity levels of carbon, silicon, oxygen, etc., to significantly improve electron confinement and reduce and / or eliminate gate hysteresis, and may also reduce and / or eliminate overall hysteresis.

[0082] In certain aspects, the back barrier layer 120 may include a generally parallel structure as shown below. Figure 1 The X-axis and / or a flat upper surface generally parallel to the Z-axis (perpendicular to the X and Y axes) is shown. In certain aspects, the back barrier layer 120 may include a generally parallel surface as shown. Figure 1 The shown surface is a flat lower surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X and Y axes). The upper and lower surfaces are defined along the Y-axis.

[0083] In some aspects, the channel layer 104 may be formed directly on the back barrier layer 120 or together with the intermediate layer on the back barrier layer 120. In one aspect, the channel layer 104 is formed of GaN.

[0084] Depending on this aspect, the channel layer 104 can be formed of different suitable materials, such as group III nitrides, such as Al. x Ga y In (1-x-y) N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1), such as GaN, AlGaN, AlN, etc., or another suitable material. The channel layer 104 or a portion thereof may be doped with dopants, such as Fe and / or C, or alternatively may be completely or partially undoped.

[0085] In certain aspects, the channel layer 104 may include a generally parallel surface as shown in the image. Figure 1The X-axis and / or a flat upper surface generally parallel to the Z-axis (perpendicular to the X and Y axes) is shown. In certain aspects, the channel layer 104 may include a generally parallel surface as shown. Figure 1 The shown surface is a flat lower surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X and Y axes). The upper and lower surfaces are defined along the Y-axis.

[0086] In one aspect, the channel layer 104 may be high-purity GaN. In another aspect, the channel layer 104 may be high-purity GaN, which may be lightly doped n-type. In one aspect, the combined thickness of the channel layer 104 and the back barrier layer 120 may be defined as the distance between the upper surface of the substrate layer 102 and the lower surface of the barrier layer 108. In one aspect, the combined thickness of the channel layer 104 and the back barrier layer 120 along the Y-axis between the upper surface of the channel layer 104 and the lower surface of the back barrier layer 120 may be 10%-20%, 20%-30%, 30%-40%, 40%-50%, 50%-60%, 60%-70%, 70%-80%, or 80%-90% of the thickness of the substrate layer 102. In one aspect, the combined thickness of the channel layer 104 and the back barrier layer 120 may be less than 0.8 μm, less than 0.7 μm, less than 0.6 μm, less than 0.5 μm, or less than 0.4 μm. In one aspect, the combined thickness of the channel layer 104 and the back barrier layer 120 can range from 0.8 μm to 0.6 μm, 0.7 μm to 0.5 μm, 0.6 μm to 0.4 μm, 0.5 μm to 0.3 μm, 0.4 μm to 0.2 μm, or 0.7 μm to 0.3 μm. In one aspect, the back barrier layer 120 can be thicker than the channel layer 104 along the Y-axis between the upper and lower surfaces of each. In one aspect, the back barrier layer 120 can be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 120%, 140%, or 160% thicker than the channel layer 104 along the Y-axis between the upper and lower surfaces of each. In one aspect, the back barrier layer 120 may be 10%-20%, 20%-30%, 30%-40%, 40%-50%, 50%-60%, 60%-70%, 70%-80%, 80%-90%, 90%-100%, 100%-120%, 120%-140%, or 140%-160% thicker than the channel layer 104 along the Y-axis between the upper and lower surfaces of each layer.

[0087] In one aspect, the transistor 100 may have an intermediate layer thickness defined as the length between the upper surface of the substrate layer 102 and the lower surface of the barrier layer 108. In one aspect, the thickness of the intermediate layer may be less than 0.8 micrometers, less than 0.7 micrometers, less than 0.6 micrometers, less than 0.5 micrometers, or less than 0.4 micrometers. In another aspect, the thickness of the intermediate layer may range from 0.8 micrometers to 0.6 micrometers, 0.7 micrometers to 0.5 micrometers, 0.6 micrometers to 0.4 micrometers, 0.5 micrometers to 0.3 micrometers, or 0.4 micrometers to 0.2 micrometers.

[0088] A barrier layer 108 can be formed on the channel layer 104. In one aspect, the barrier layer 108 can be formed directly on the channel layer 104, while in other aspects, the barrier layer 108 is formed on the channel layer 104 using an intermediate layer. Depending on this aspect, the channel layer 104 can be formed of different suitable materials, such as group III nitrides, such as Al. x Ga y In (1-x-y) N (where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, x + y ≤ 1), for example, AlGaN, AlN, or InAlGaN, or another suitable material. In one aspect, the barrier layer 108 may be AlGaN, and in another aspect, the barrier layer 108 may be AlN. In one aspect, the barrier layer 108 may be undoped. In one aspect, the barrier layer 108 may be doped. In one aspect, the barrier layer 108 may be an n-type material. In some aspects, the barrier layer 108 may have multiple n-type material layers with different carrier concentrations. In one aspect, the barrier layer 108 may be a group III nitride or a combination thereof. In a particular aspect, the barrier layer 108 may include materials generally parallel to, such as Figure 1 The shown surface is a flat upper surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X and Y axes). In certain aspects, the barrier layer 108 may include a generally parallel surface to the Z-axis. Figure 1 The shown surface is a flat lower surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X and Y axes). The upper and lower surfaces are defined along the Y-axis.

[0089] In one aspect, the band gap of the channel layer 104 may be smaller than the band gap of the barrier layer 108 to form a two-dimensional electron gas (2DEG) at the heterojunction 152 between the channel layer 104 and the barrier layer 108 when biased to an appropriate level. In another aspect, the band gap of the channel layer 104, which may be GaN, may be smaller than the band gap of the barrier layer 108, which may be AlGaN, to form a two-dimensional electron gas (2DEG) at the heterojunction 152 between the channel layer 104 and the barrier layer 108 when biased to an appropriate level.

[0090] In various aspects of this disclosure, the heterointerface 152 may be located between the barrier layer 108 and the channel layer 104. In one aspect, the source 110 and drain 112 may be formed to create an ohmic contact such that when the gate 114 is biased to an appropriate level, current flows between the source 110 and the drain 112 via a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between the channel layer 104 and the barrier layer 108. In one aspect, the heterointerface 152 may be in the range of 0.005 µm to 0.007 µm, 0.007 µm to 0.009 µm, and 0.009 µm to 0.011 µm.

[0091] In one aspect, source 110, drain 112, and gate 114 may be formed on barrier layer 108. Source 110, drain 112, and / or gate 114 may be disposed directly on barrier layer 108, or on an intermediate layer on barrier layer 108, such as an AlGaN layer on an AlN barrier layer. Other or additional intermediate layers are possible. For example, spacer layer 116 of SiN, AlO, SiO, SiO2, AlN, or combinations thereof may be disposed on barrier layer 108 or other intermediate layers. In one aspect, barrier layer 108 may include an N+ material region 164 beneath source 110 and / or drain 112. In one aspect, barrier layer 108 may include a Si-doped region 164 beneath source 110 and / or drain 112. In one aspect, an n-type dopant is implanted into region 164.

[0092] In one aspect, the source 110, drain 112, and gate 114 may be formed on the channel layer 104. The source 110, drain 112, and / or gate 114 may be directly disposed on the channel layer 104 or may be located on an intermediate layer on the channel layer 104, such as an AlGaN layer on an AlN barrier layer. In one aspect, the channel layer 104 may include an N+ material region 164 below the source 110 and / or drain 112. In one aspect, the channel layer 104 may include a Si-doped region 164 below the source 110 and / or drain 112. In one aspect, an n-type dopant is implanted into the region 164.

[0093] In some aspects, the source 110 and drain 112 may be symmetrical with respect to the gate 114. In some aspects, the source 110 and drain 112 may be symmetrical with respect to the gate 114. In some aspects, the source 110 and drain 112 may be asymmetrical with respect to the gate 114. In one aspect, the gate 114 may be a T-gate. In one aspect, the gate 114 may be a non-T-gate.

[0094] To protect and separate the gate 114 and drain 112, a spacer layer 116 may be disposed on the barrier layer 108 on the side adjacent to the gate 114, drain 112, and source 110, opposite to the channel layer 104. The spacer layer 116 may be a passivation layer made of SiN, AlO, SiO, SiO2, AlN, etc., or a combination including multiple layers thereof. In one aspect, the spacer layer 116 is a passivation layer made of SiN. In one aspect, the spacer layer 116 may be deposited using MOCVD, plasma chemical vapor deposition (CVD), hot-filament CVD, or sputtering. In one aspect, the spacer layer 116 may include the deposition of Si3N4. In one aspect, the spacer layer 116 forms an insulating layer. In one aspect, the spacer layer 116 forms an insulator. In one aspect, the spacer layer 116 may be a dielectric. In one aspect, the spacer layer 116 may be disposed on the barrier layer 108. In one aspect, the spacer layer 116 may include a non-conductive material, such as a dielectric. In one aspect, spacer layer 116 may comprise a plurality of different dielectric layers or combinations of dielectric layers. In one aspect, spacer layer 116 may have a number of different thicknesses, with a suitable thickness range of about 0.05 micrometers to 2 micrometers. In one aspect, spacer layer 116 may comprise a material such as a group III nitride material having alloys of different group III elements (such as Al, Ga, or In), with a suitable spacer layer material being AlxInyGa1-xy (where 0 ≤ x ≤ 1 and 0 ≤ y ≤ 1, x + y ≤ 1).

[0095] In some respects, gate 114 can be deposited in a channel formed in spacer layer 116 and can be formed using semiconductor processing techniques understood by those skilled in the art. Other gate configurations are also possible and are conceivable.

[0096] In various aspects of the transistor 100 of this disclosure, the substrate layer 102 may be silicon carbide and include a carbon facet. In one aspect, the substrate layer 102 may be silicon carbide and include a carbon facet disposed adjacent to the channel layer 104. In another aspect, the substrate layer 102 may be silicon carbide and include a carbon facet, and the substrate layer 102 may be flipped to be disposed adjacent to the channel layer 104. In this aspect, the channel layer 104 may be GaN having a nitrogen facet adjacent to the carbon facet of the substrate layer 102. In another aspect, the channel layer 104 may be GaN having alternating GaN and N layers, wherein the N layer and / or the nitrogen facet is adjacent to the carbon facet of the substrate layer 102.

[0097] In various aspects of the transistor 100 of this disclosure, the channel layer 104 may include nonpolar GaN. In one aspect, the channel layer 104 may include semipolar GaN. In one aspect, the channel layer 104 may include a hot-wall epitaxial layer. In one aspect, the channel layer 104 may include a hot-wall epitaxial layer with a thickness ranging from 0.15 μm to 0.25 μm, 0.2 μm to 0.3 μm, 0.25 μm to 0.35 μm, 0.3 μm to 0.35 μm, 0.35 μm to 0.4 μm, 0.4 μm to 0.45 μm, 0.45 μm to 0.5 μm, 0.5 μm to 0.55 μm, or 0.15 μm to 0.55 μm. The p-type material layer 106 can help avoid problems with breakdown and material impurities. For example, without the p-type material layer 106, the transistor 100 may require impurities that cannot discharge well. A p-type material layer 106 can be formed below the gate 114 and can extend toward the source 110 and drain 112 of the device.

[0098] In various aspects of the transistor 100 of this disclosure, the channel layer 104 can be designed to be of a high-purity type, in which the Fermi level is located in the upper half of the bandgap, which reduces the slow trapping effect typically observed in GaN HEMTs. At this point, traps below the Fermi level are always filled, and thus slow transients are prevented. In some respects, the channel layer 104 can be as thin as possible to achieve good crystallinity. The applicant has demonstrated that a 0.4 µm layer exhibits good quality.

[0099] In various aspects of the transistor 100 of this disclosure, Al can be grown on substrate layer 102 via epitaxial crystal growth methods (such as metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE)). x In y Ga 1-x-y (Where 0≤x≤1 and 0≤y≤1, x+y≤1) Nucleation layer 136 or channel layer 104. The formation of nucleation layer 136 may depend on the material of substrate layer 102.

[0100] In various aspects of the transistor 100 of this disclosure, the channel layer 104 may be formed with lateral epitaxial overgrowth (LEO). For example, LEO can improve the crystal quality of the GaN layer. When the semiconductor layer of the HEMT is epitaxial, each layer grown on it may affect the characteristics of the device. For example, LEO can reduce the dislocation density in the epitaxial GaN layer.

[0101] refer to Figure 8 As described, transistor 100 may include a second spacer layer 117, which may be formed on spacer layer 116 and gate 114. (See reference...) Figure 9As described above, transistor 100 may include field plate 132. (See reference...) Figure 10 According to the description, transistor 100 may include connection 154 to field plate 132.

[0102] Figure 2 It shows according to Figure 1 A cross-sectional view of one aspect of a transistor.

[0103] In one aspect of this disclosure, the p-type material layer 106 may not extend over the entire area of ​​the transistor 100. In this respect, the p-type material layer 106 may be selectively arranged as described herein, the p-type material layer 106 may be arranged over its entire length and selectively removed as described herein, the p-type material layer 106 may be arranged over its entire length and selectively electrically neutralized as described herein, etc. Therefore, the specific configuration of the p-type material layer 106 described below includes any of these processes that result in the p-type material layer 106 having the following operational configuration and arrangement. In other words, the length and / or dimensions of the p-type material layer 106 do not include portions that are partially electrically neutralized, partially etched, etc. The length and / or dimensions of the p-type material layer 106 may depend on the application of the transistor 100, the requirements for the transistor 100, etc. Limiting the length of the p-type material layer 106 reduces gate hysteresis effects, drain hysteresis effects, and avoids adverse effects on RF performance for certain transistor applications, etc.

[0104] like Figure 2 As shown, the p-type material layer 106 can exist in a limited region, as described in further detail below. In some aspects, the p-type material layer 106 can exist in the gate-source region. In some aspects, the p-type material layer 106 can exist in the gate-source region and also partially below the gate 114. In some aspects, the p-type material layer 106 can be at least partially disposed below the gate 114 and / or the source 110. In some aspects, the p-type material layer 106 can be at least partially disposed below the gate 114 and / or not disposed below the source 110.

[0105] In one aspect, the p-type material layer 106 may be disposed at least partially perpendicularly below the gate 114 along the Y-axis and may extend partially toward the source 110 and drain 112 along the X-axis. In this aspect, no portion of the p-type material layer 106 may be perpendicularly located below the source 110 along the Y-axis; and no portion of the p-type material layer 106 may be perpendicularly located below the source 110 along the Y-axis. In this aspect, a portion of the substrate layer 102 may be without the p-type material layer 106 on the source side of the transistor 100; and a portion of the substrate layer 102 may be without the p-type material layer 106 on the drain side of the transistor 100. In this respect, the source side of the transistor 100 is defined as the side of the transistor 100 extending from the gate 114 toward the source 110 and passing through the source 110, as... Figure 2 As shown; and the drain side of transistor 100 is defined as the side of transistor 100 that extends from gate 114 toward drain 112 and passes through drain 112, as shown. Figure 2 As shown.

[0106] In one aspect, the p-type material layer 106 may be disposed at least partially vertically below the gate 114 along the Y-axis and may extend partially toward the source 110 and drain 112 along the X-axis. In this aspect, only a portion of the p-type material layer 106 may be located vertically below the source 110 along the Y-axis; and no portion of the p-type material layer 106 may be located vertically below the source 110 along the Y-axis. In this aspect, a portion of the substrate layer 102 may not include the p-type material layer 106 located vertically below the source 110 along the Y-axis. In this aspect, a portion of the substrate layer 102 may not have the p-type material layer 106 on the source side of the transistor 100; and a portion of the substrate layer 102 may not have the p-type material layer 106 on the drain side of the transistor 100.

[0107] In one aspect, the p-type material layer 106 may be disposed at least partially perpendicularly below the gate 114 along the Y-axis and may extend partially toward the source 110 and drain 112 along the X-axis. In this aspect, a portion of the p-type material layer 106 may be completely perpendicularly below the source 110 along the Y-axis; and no portion of the p-type material layer 106 may be perpendicularly below the drain 112 along the Y-axis. In this aspect, a portion of the substrate layer 102 may not include the p-type material layer 106 perpendicularly located behind the source 110 along the Y-axis. In this aspect, a portion of the substrate layer 102 may not have the p-type material layer 106 on the source side of the transistor 100; and a portion of the substrate layer 102 may not have the p-type material layer 106 on the drain side of the transistor 100.

[0108] In one aspect, the p-type material layer 106 may be disposed perpendicularly below the gate 114 along the Y-axis and may extend partially toward the source 110 and drain 112 along the X-axis. In this aspect, a portion of the p-type material layer 106 may be completely perpendicularly below the source 110 along the Y-axis; and no portion of the p-type material layer 106 may be perpendicularly below the source 110 along the Y-axis. In this aspect, a portion of the substrate layer 102 may not include the p-type material layer 106 perpendicularly located behind the source 110 along the Y-axis. In this aspect, a portion of the substrate layer 102 may not have the p-type material layer 106 on the source side of the transistor 100; and a portion of the substrate layer 102 may not have the p-type material layer 106 on the drain side of the transistor 100.

[0109] refer to Figure 2 Various dimensions of the components of transistor 100 will be described to define the dimensions of the p-type material layer 106. Gate 114 may have a width LG along its lower surface, adjacent to barrier layer 108, which is parallel to the X-axis. Specifically, the width LG may extend from one lower corner of gate 114 to the other lower corner. The width LG is defined in… Figure 2 As shown in the figure. In some aspects, the length of the width LG along the X-axis can be between 0.05 µm and 0.6 µm, between 0.5 µm and 0.6 µm, between 0.4 µm and 0.5 µm, between 0.3 µm and 0.4 µm, between 0.2 µm and 0.3 µm, between 0.1 µm and 0.2 µm, or between 0.1 µm and 0.05 µm. In some aspects, the width of the gate 114 above the lower surface can be greater than the width LG, such as... Figure 2 As shown.

[0110] The distance from gate 114 to source 110 can be defined as distance LGS. Specifically, distance LGS can be defined as the distance from the lower corner of gate 114 on the source side to the lower corner of source 110 on the gate side. The distance LGS is defined as follows: Figure 2 As shown in the image.

[0111] The distance from gate 114 to drain 112 can be defined as distance LGD. Specifically, distance LGD can be defined as the distance from the lower corner of gate 114 on the drain side to the lower corner of drain 112 on the gate side. The distance LGD is defined as follows: Figure 2 As shown in the image.

[0112] In one aspect, the p-type material layer 106 may extend laterally along the X-axis from at least below the lower corner of the gate 114 on the source side toward the source 110 by a distance LGPS. The distance LGPS is defined as follows: Figure 2As shown in the figure. In some respects, the length of the distance LGPS along the X-axis can be between 1 µm and 6 µm, between 5 µm and 6 µm, between 4 µm and 5 µm, between 3 µm and 4 µm, between 2 µm and 3 µm, or between 1 µm and 3 µm.

[0113] In one aspect, the p-type material layer 106 may extend laterally along the X-axis from at least below the lower corner of the gate 114 on the drain side toward the drain 112 by a distance from LGPD. In some aspects, the length of the distance from LGPD along the X-axis may be between 0.1 µm and 0.6 µm, between 0.5 µm and 0.6 µm, between 0.4 µm and 0.5 µm, between 0.3 µm and 0.4 µm, between 0.2 µm and 0.3 µm, or between 0.1 µm and 0.3 µm.

[0114] Therefore, the length of the p-type material layer 106 can be the sum of the distance LGPD, the width LG, and the distance LGPS. In this respect, the length of the p-type material layer 106 reduces the gate hysteresis effect and avoids adverse effects on RF performance in certain transistor applications.

[0115] In one respect, the length LGPS can be 100% to 700% of LG, 100% to 200% of LG, 200% to 300% of LG, 300% to 400% of LG, 400% to 500% of LG, 500% to 600% of LG, or 600% to 700% of LG.

[0116] In one aspect, the length LG can be 10% to 180% of LGPD, 10% to 20% of LGPD, 20% to 30% of LGPD, 30% to 40% of LGPD, 40% to 50% of LGPD, 50% to 60% of LGPD, 60% to 70% of LGPD, 70% to 80% of LGPD, 80% to 90% of LGPD, 90% to 100% of LGPD, 100% to 110% of LGPD, 110% to 120% of LGPD, 110% to 130% of LGPD, 130% to 140% of LGPD, 140% to 150% of LGPD, 150% to 160% of LGPD, 160% to 170% of LGPD, or 170% to 180% of LGPD.

[0117] In one aspect, the length LGS can be 10% to 180% of LGPS, 10% to 20% of LGPS, 20% to 30% of LGPS, 30% to 40% of LGPS, 40% to 50% of LGPS, 50% to 60% of LGPS, 60% to 70% of LGPS, 70% to 80% of LGPS, 80% to 90% of LGPS, 90% to 100% of LGPS, 100% to 110% of LGPS, 110% to 120% of LGPS, 110% to 130% of LGPS, 130% to 140% of LGPS, 140% to 150% of LGPS, 150% to 160% of LGPS, 160% to 170% of LGPS, or 170% to 180% of LGPS.

[0118] In one aspect, the length LG can be 10% to 180% of LGPD, 10% to 20% of LGPD, 20% to 30% of LGPD, 30% to 40% of LGPD, 40% to 50% of LGPD, 50% to 60% of LGPD, 60% to 70% of LGPD, 70% to 80% of LGPD, 80% to 90% of LGPD, 90% to 100% of LGPD, 100% to 110% of LGPD, 110% to 120% of LGPD, 110% to 130% of LGPD, 130% to 140% of LGPD, 140% to 150% of LGPD, 150% to 160% of LGPD, 160% to 170% of LGPD, or 170% to 180% of LGPD.

[0119] In one or more aspects, a portion of the source side of the substrate layer 102 may be without the p-type material layer 106. In one or more aspects, a portion of the drain side of the substrate layer 102 may be without the p-type material layer 106. In one or more aspects, a portion of the source side of the substrate layer 102 may be without the p-type material layer 106, and a portion of the drain side of the substrate layer 102 may be without the p-type material layer 106. In one or more aspects, the p-type material layer 106 may be disposed below the gate 114 and span the length of the gate, and may extend toward the source 110 and the drain 112.

[0120] In one or more aspects, the distance LGD can be the distance from the lower corner of the gate 114 on the drain 112 side to the lower corner of the drain 112 on the gate side; the distance LGS can be the distance from the lower corner of the gate 114 on the source 110 side to the lower corner of the source 110 on the gate side; and the distance LGD can be greater than the distance LGS. In one or more aspects, the distance LGPS can define the length of the p-type material layer 106 extending from the lower corner of the gate 114 on the source 110 side toward the source 110; the distance LGPD can define the length of the p-type material layer 106 extending from the lower corner of the gate 114 on the drain 112 side toward the drain 112; and the distance LGPS can be equal to the distance LGPD. In one or more aspects, the distance LGPS may define the length of a portion of the p-type material layer 106 extending from the lower corner of the gate 114 on the source 110 side toward the source 110; the distance LGPD may define the length of a portion of the p-type material layer 106 extending from the lower corner of the gate 114 on the drain 112 side toward the drain 112; and the distance LGPS may be greater than the distance LGPD. In one or more aspects, the distance LGPS may define the length of a portion of the p-type material layer 106 extending from the lower corner of the gate 114 on the source 110 side toward the source 110; the distance LGPD may define the length of a portion of the p-type material layer 106 extending from the lower corner of the gate 114 on the drain 112 side toward the drain 112; and the distance LGPD may be greater than the distance LGPS.

[0121] In one or more aspects, the p-type material layer 106 may extend toward the source 110 but not perpendicularly overlap with the source 110. In one or more aspects, the p-type material layer 106 may perpendicularly overlap with the source 110. In one or more aspects, the p-type material layer 106 may extend toward the drain 112 but not perpendicularly overlap with the drain 112. In one or more aspects, the p-type material layer 106 may perpendicularly overlap with the drain 112. In one or more aspects, the p-type material layer 106 may be electrically connected to the gate 114. In one or more aspects, the gate 114 may be electrically connected to any external circuit or voltage. In one or more aspects, the p-type material layer 106 may not have a direct electrical connection. In one or more aspects, the p-type material layer 106 may be electrically connected to the source 110.

[0122] In some respects, a portion of the voltage from drain 112 to source 110 can be reduced in the region of p-type material layer 106. This can also deplete the channel in the lateral direction. Lateral depletion can reduce the lateral field and increase the breakdown voltage. Alternatively, a more compact structure can be obtained for the desired breakdown voltage. p-type material layer 106 can eliminate the need for C or Fe doping of the buffer layer required to maintain the applied drain voltage. Eliminating C and Fe results in reduced current reduction under operating conditions (no trapping). Additionally, in some respects, p-type material layer 106 can support the field.

[0123] In some aspects, the p-type material layer 106 can also be configured to have a doping and / or implantation distribution that varies perpendicular to the surface. In some aspects, the p-type material layer 106 can also be configured to have a distribution that varies perpendicular to the surface in the cross-sectional view extending into the figures. This distribution can be configured to achieve desired breakdown voltage, device size, switching time, etc.

[0124] Figure 3 It shows according to Figure 1 A cross-sectional view of one aspect of a transistor.

[0125] In one respect, the p-type material layer 106 may not extend over the entire area of ​​the substrate layer 102, such as... Figure 3 The length P is indicated by the arrow in the diagram. At this point, the p-type material layer 106 can be selectively arranged as described in detail below, the p-type material layer 106 can be arranged along its entire length and selectively removed as described in detail below, the p-type material layer 106 can be arranged along its entire length and selectively electrically neutralized as described in detail below, etc. Therefore, the specific configuration of the p-type material layer 106 described below includes any of these configurations that result in the p-type material layer 106 having the following operational configuration and arrangement. In other words, the length and / or size of the p-type material layer 106 does not include the portion that is partially electrically neutralized or partially etched. The length and / or size of the p-type material layer 106 may depend on the application of the transistor 100, the requirements for the transistor 100, etc.

[0126] Referring to the aspects further described below, the p-type material layer 106 may extend horizontally along the X-axis parallel to the arrow length P. Additionally, the p-type material layer 106 may extend horizontally parallel to the arrow length P to a point defined by a line perpendicular to the arrow length P (parallel to the Y-axis) and extending through the components of the transistor 100 as shown.

[0127] In one aspect of this disclosure, the p-type material layer 106 may extend laterally from at least below the source 110 to a position below a first edge 124 of the gate 114. Specifically, the first edge 124 may be an edge of the gate 114 on the side of the gate 114 adjacent to the drain 112, and the edge may also be the lowest surface of the gate 114.

[0128] In some aspects of this disclosure, the p-type material layer 106 may extend to a point within about 0 µm to about 0.7 µm of the first edge 124 of the gate 114. In some aspects of this disclosure, the p-type material layer 106 may extend to a point within about 0 µm to about 0.5 µm of the first edge 124 of the gate 114. In some aspects of this disclosure, the p-type material layer 106 may extend to a point within about 0 µm to about 0.3 µm of the first edge 124 of the gate 114.

[0129] In one aspect of this disclosure, the p-type material layer 106 may extend laterally from at least below the source 110 to a position below the second edge 122 of the gate 114. Specifically, the second edge 122 may be the edge of the gate 114 on the side of the gate 114 adjacent to the source 110, and the edge may also be the lowest surface of the gate 114.

[0130] In some aspects of this disclosure, the p-type material layer 106 may extend to a point within about 0 µm to about 0.7 µm of the second edge 122 of the gate 114. In some aspects of this disclosure, the p-type material layer 106 may extend to a point within about 0 µm to about 0.5 µm of the second edge 122 of the gate 114. In some aspects of this disclosure, the p-type material layer 106 may extend to a point within about 0 µm to about 0.3 µm of the second edge 122 of the gate 114.

[0131] In other aspects, it can also be seen that the length P of the p-type material layer 106 is related to the position and / or length of other components based on the length SD, such as Figure 3 As shown. In this case, the length SD can be the length between the edge 142 of the source 110 and the edge 144 of the drain 112, as... Figure 3 As shown. Specifically, edge 142 may be defined as an edge or surface on source 110 that is parallel to the Y-axis on the side of source 110 opposite to gate 114; and edge 144 may be defined as an edge or surface on drain 112 that is parallel to the Y-axis on the side of drain 112 opposite to gate 114.

[0132] In one aspect, the length of the p-type material layer 106 can extend from 10% to 20% of the length of the SD, meaning that the p-type material layer 106 can extend 10% to 20% towards the drain 112 past the edge 142 of the source 110. In another aspect, the length of the p-type material layer 106 can extend from 20% to 30% of the length of the SD, meaning that the p-type material layer 106 can extend 20% to 30% towards the drain 112 past the edge 142 of the source 110. In another aspect, the length of the p-type material layer 106 can extend from 30% to 40% of the length of the SD, meaning that the p-type material layer 106 can extend 30% to 40% towards the drain 112 past the edge 142 of the source 110. In another aspect, the length of the p-type material layer 106 can extend from 40% to 50% of the length of the SD, meaning that the p-type material layer 106 can extend 40% to 50% towards the drain 112 past the edge 142 of the source 110. In one aspect, the length of the p-type material layer 106 can extend from 50% to 60% of the length of the SD, meaning that the p-type material layer 106 can extend 50% to 60% towards the drain 112 past the edge 142 of the source 110. In another aspect, the length of the p-type material layer 106 can extend from 60% to 70% of the length of the SD, meaning that the p-type material layer 106 can extend 60% to 70% towards the drain 112 past the edge 142 of the source 110. In yet another aspect, the length of the p-type material layer 106 can extend from 70% to 80% of the length of the SD, meaning that the p-type material layer 106 can extend 70% to 80% towards the drain 112 past the edge 142 of the source 110.

[0133] Figure 4 A semiconductor device comprising a plurality of unit cell transistors is shown according to one aspect of the present disclosure.

[0134] like Figure 4 As shown, aspects of this disclosure may include a semiconductor device 400, which may include a plurality of transistors 100. Specifically, a transistor 100 may be one of a plurality of unit cells 430 implemented in the semiconductor device 400.

[0135] Specifically, Figure 4 A transistor 100 is shown, which may include any one or more aspects of the present disclosure described herein. Specifically, Figure 4 The transistor 100 may include a p-type material layer 106 as described above. At this point, Figure 4 The transistor 100 achieves the length of the p-type material layer 106 as described herein, which reduces drain hysteresis; and Figure 4 The transistor 100 implements a back barrier layer 120 to reduce gate hysteresis as described herein.

[0136] Semiconductor device 400 may include a gate bus 402 that can be connected to a plurality of gate fingers 406, the plurality of gate fingers being in a first direction (e.g., Figure 4 Extending in parallel along the Z direction (as shown in the diagram), the first direction connects to or forms part of the gate 114. The source bus 410 may be connected to a plurality of parallel source contacts 416, which connect to or form part of the source 110. In some aspects, the source bus 410 may be connected to a ground voltage node on the underside of the semiconductor device 400. The drain bus 420 may be connected to a plurality of drain contacts 426, which connect to or form part of the drain 112.

[0137] As in Figure 4 As can be seen, each gate finger 406 can extend along the Z direction between a pair of adjacent source and drain contacts in source contact 416 and drain contact 426. The semiconductor device 400 may include a plurality of unit cells 430, wherein each of the plurality of unit cells 430 includes an implementation of transistor 100. One of the unit cells 430 is composed of... Figure 4 The dashed box in the figure shows and includes a gate finger 406 extending between adjacent source and drain contacts in source contact 416 and drain contact 426.

[0138] "Gate width" refers to the distance by which the gate finger 406 overlaps with one of its associated source contact 416 and drain contact 426 in the Z direction. That is, the "width" of the gate finger 406 refers to the dimension (distance along the Z direction) by which the gate finger 406 extends parallel to and adjacent to the implementation of the source contact 416 and drain contact 426. Each of the plurality of unit cells 430 may share one of the source contact 416 and / or drain contact 426 with one or more adjacent unit cells of the plurality of unit cells 430. Although Figure 4 A specific number of multiple unit cells 430 are shown, but it should be understood that the semiconductor device 400 may include more or fewer unit cells than the multiple unit cells 430.

[0139] Figure 5 It is along Figure 4 A schematic cross-sectional view of line VV.

[0140] refer to Figure 5Semiconductor device 400 may include semiconductor structure 440, which includes substrate layer 102, back barrier layer 120, channel layer 104, barrier layer 108, etc., as described herein. Source contact 416 and drain contact 426 may be on barrier layer 108, as described herein. Gate finger 406 may be on substrate layer 102 between source contact 416 and drain contact 426, as described herein. Although gate finger 406, source contact 416 and drain contact 426 are located on... Figure 4 and Figure 5 All are schematically shown as having similar "sizes", but it should be understood that each gate finger may have a different shape and size according to this disclosure.

[0141] Figure 6 The energy band diagram of the disclosed transistor is shown compared to that of a typical transistor at certain operating values.

[0142] Specifically, Figure 6 An energy band diagram 600 of the transistor 100 of this disclosure and a HEMT transistor implemented without a back barrier layer 120 is shown. This diagram graphically illustrates various key electronic energy levels according to spatial dimensions at zero gate voltage and zero drain voltage. The vertical axis of the energy band diagram represents the energy of electrons; and the horizontal axis relates to the two different spatial dimensions of the transistor.

[0143] More specifically, the band structure diagram 600 includes an Ec curve 602 for implementing the transistor 100 disclosed herein, wherein a back barrier layer 120 and a p-type material layer 106 are disposed below the gate; and the band structure diagram 600 includes an Ec curve 652 for implementing a HEMT transistor without the back barrier layer 120.

[0144] Additionally, the band structure diagram 600 includes an Ev curve 604 for implementing the transistor 100 as disclosed herein, wherein a back barrier layer 120 and a p-type material layer 106 are disposed below the gate; and the band structure diagram 600 includes an Ev curve 654 for implementing a HEMT transistor without the back barrier layer 120.

[0145] refer to Figure 6 It should be noted that Ec curve 602 illustrates the rise in negative charge between the channel layer 104 and the back barrier layer 120 of the transistor 100 of this disclosure. Specifically, Ec curve 602 illustrates the rise in negative charge to confine and partially deplete the 2DEG. It should be further noted that Ec curve 652 for the HEMT transistor implemented without the back barrier layer 120 includes a minimal rise in negative charge.

[0146] Further reference Figure 6It should be noted that Ev curve 604 shows the rise in negative charge between the channel layer 104 and the back barrier layer 120 of the transistor 100 of this disclosure. It should be further noted that the Ev curve 654 of the HEMT transistor implemented without the back barrier layer 120 includes a minimum rise in negative charge.

[0147] Figure 7 The energy band diagram of the disclosed transistor is shown compared to that of a typical transistor at certain operating values.

[0148] Specifically, Figure 7 An energy band diagram 700 of the transistor 100 of this disclosure and a HEMT transistor implemented without a back barrier layer 120 is shown. This diagram graphically illustrates various key electronic energy levels according to spatial dimensions at a gate voltage of -15V and a drain voltage of 10V. The vertical axis of the energy band diagram represents the energy of the electrons; and the horizontal axis relates to the spatial dimensions of the two different transistors.

[0149] More specifically, the band structure diagram 700 includes an Ec curve 702 for implementing the transistor 100 disclosed herein, wherein a back barrier layer 120 and a p-type material layer 106 are disposed below the gate; and the band structure diagram 700 includes an Ec curve 752 for implementing a HEMT transistor without the back barrier layer 120.

[0150] Additionally, the band structure diagram 700 includes an Ev curve 704 for implementing the transistor 100 as disclosed herein, wherein a back barrier layer 120 and a p-type material layer 106 are disposed below the gate; and the band structure diagram 700 includes an Ev curve 754 for implementing a HEMT transistor without the back barrier layer 120.

[0151] refer to Figure 7 It should be noted that Ec curve 702 shows the field near the interface between channel layer 104 and back barrier layer 120, preventing electrons from penetrating deeper into the back barrier layer 120 of transistor 100. It should be further noted that Ec curve 752 for a HEMT transistor implemented without back barrier layer 120 does not include such a field. Similarly, it should be noted that Ev curve 704 shows the field near the interface between channel layer 104 and back barrier layer 120, preventing electrons from penetrating deeper into the back barrier layer 120 of transistor 100; and Ev curve 754 for a HEMT transistor implemented without back barrier layer 120 does not include such a field.

[0152] Furthermore, in transistors with conventional buffer layers, bands such as the Ec curve 752 on the Ev curve 754 bend downwards under large negative voltages. This allows electrons to flow deeply downwards into the buffer layer and be trapped. In the disclosed implementation of transistor 100 with a p-type material layer 106 and a back barrier layer 120, there are flat or slightly upward-curving bands on the Ec curve 702 and Ev curve 704 near the channel layer 104. This prevents electron injection and trapping in the buffer layer of transistor 100.

[0153] Figure 8 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0154] Figure 8 The transistor 100 can be configured to be similar to Figure 1 transistors, Figure 2 transistors, and / or Figure 3 The transistors are consistent and may include any one or more aspects as described herein. Specifically, they combine the p-type material layer 106 and the back barrier layer 120 as disclosed. Figure 8 The transistor 100, its associated structure, and / or its associated process can provide a systematic approach to reducing hysteresis. More specifically, the transistor 100 of this disclosure can be implemented with a p-type material layer 106 and / or its process as a drain hysteresis reduction structure and / or a process for reducing drain hysteresis effects in the transistor 100, and the transistor 100 of this disclosure can be implemented with a back barrier layer 120 and / or its process as a gate hysteresis reduction structure and / or a process for reducing gate hysteresis effects in the transistor 100.

[0155] Figure 8 The implementation of the second spacer layer 117 is further illustrated. The second spacer layer 117 may be disposed below the gate 114 and / or above the spacer layer 116. The second spacer layer 117 may be a passivation layer made of SiN, AlO, SiO, SiO2, AlN, etc., or a combination of multiple such layers.

[0156] In one aspect, the second spacer layer 117 is a passivation layer made of SiN. In one aspect, the second spacer layer 117 can be deposited using MOCVD, plasma chemical vapor deposition (CVD), hot-filament CVD, or sputtering. In one aspect, the second spacer layer 117 may comprise a deposition of Si3N4. In one aspect, the second spacer layer 117 forms an insulating layer. In one aspect, the second spacer layer 117 forms an insulator. In one aspect, the second spacer layer 117 may be a dielectric. In one aspect, the second spacer layer 117 may be disposed on spacer layer 116. In one aspect, the second spacer layer 117 may comprise a non-conductive material, such as a dielectric. In one aspect, the second spacer layer 117 may comprise a plurality of different dielectric layers or a combination of dielectric layers. In one aspect, the second spacer layer 117 may have many different thicknesses, wherein a suitable thickness range is approximately 0.05 micrometers to 2 micrometers. In one aspect, the second spacer layer 117 may comprise a material such as a group III nitride material with different group III elements (such as alloys of Al, Ga, or In), with Al being a suitable spacer layer material. x In y Ga 1-x-y (where 0≤x≤1 and 0≤y≤1, x+y≤1).

[0157] Figure 9 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0158] Figure 9 The transistor 100 can be configured to be similar to Figure 1 transistors, Figure 2 transistors, and / or Figure 3 The transistors are consistent and may include any one or more aspects as described herein. Specifically, they combine the p-type material layer 106 and the back barrier layer 120 as disclosed. Figure 9 The transistor 100, its associated structure, and / or its associated process can provide a systematic approach to reducing hysteresis. More specifically, the transistor 100 of this disclosure can be implemented with a p-type material layer 106 and / or its process as a drain hysteresis reduction structure and / or a process for reducing drain hysteresis effects in the transistor 100, and the transistor 100 of this disclosure can be implemented with a back barrier layer 120 and / or its process as a gate hysteresis reduction structure and / or a process for reducing gate hysteresis effects in the transistor 100.

[0159] Figure 9Further implementations of the field plate 132 are shown. In one aspect, the field plate 132 may be disposed on a second spacer layer 117 between the gate 114 and the drain 112. In another aspect, the field plate 132 may be deposited on the second spacer layer 117 between the gate 114 and the drain 112. In one aspect, the field plate 132 may be electrically connected to one or more other components in the transistor 100. In one aspect, the field plate 132 may not be electrically connected to any other component of the transistor 100. In some aspects, the field plate 132 may be adjacent to the gate 114 and may include at least partially a second spacer layer 117 of dielectric material over the gate 114 to space the gate 114 from the field plate 132. In some aspects, the field plate 132 may overlap the gate 114 and may include at least partially a second spacer layer 117 of dielectric material over the gate 114 to space the gate 114 from the field plate 132.

[0160] Field plate 132 can extend from the edge of gate 114 at varying distances, with a suitable distance range of approximately 0.1 micrometers to 2 micrometers. In some aspects, field plate 132 may comprise a variety of different conductive materials, with suitable materials being metals or combinations of metals deposited using standard metallization methods. In one aspect, field plate 132 may comprise titanium, gold, nickel, titanium / gold, nickel / gold, etc.

[0161] In one aspect, field plate 132 may be formed on a second spacer layer 117 between gate 114 and drain 112, wherein field plate 132 is close to gate 114 but does not overlap with gate 114. In another aspect, the space between gate 114 and field plate 132 may be wide enough to space gate 114 and field plate 132 apart, while the space may be small enough to maximize the field effect provided by field plate 132.

[0162] In some respects, field plate 132 can reduce the peak operating electric field in transistor 100. In some respects, field plate 132 can reduce the peak operating electric field in transistor 100 and increase the breakdown voltage of transistor 100. In some respects, field plate 132 can reduce the peak operating electric field in transistor 100 and reduce trapping in transistor 100. In some respects, field plate 132 can reduce the peak operating electric field in transistor 100 and reduce leakage current in transistor 100.

[0163] In other respects, for example, spacer layer 116 is formed on barrier layer 108 and gate 114. In these respects, field plate 132 may be formed directly on spacer layer 116. Other multiple field plate configurations are possible, wherein field plate 132 may overlap or not overlap with gate 114 and / or multiple field plates 132 used.

[0164] Figure 10A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0165] Figure 10 The transistor 100 can be configured to be similar to Figure 1 transistors, Figure 2 transistors, and / or Figure 3 The transistors are consistent and may include any one or more aspects as described herein. Specifically, they combine the p-type material layer 106 and the back barrier layer 120 as disclosed. Figure 10 The transistor 100, its associated structure, and / or its associated process can provide a systematic approach to reducing hysteresis. More specifically, the transistor 100 of this disclosure can be implemented with a p-type material layer 106 and / or its process as a drain hysteresis reduction structure and / or a process for reducing drain hysteresis effects in the transistor 100, and the transistor 100 of this disclosure can be implemented with a back barrier layer 120 and / or its process as a gate hysteresis reduction structure and / or a process for reducing gate hysteresis effects in the transistor 100.

[0166] In such Figure 10 In one aspect, connection 154 may be formed on spacer layer 116 and / or second spacer layer 117 to extend between source 110 and field plate 132. In some aspects, connection 154 may include a conductive material, many different conductive materials, with suitable materials being metals or combinations of metals deposited using standard metallization methods. In one aspect, the material may include one or more of titanium, gold, nickel, etc.

[0167] Specifically, Figure 10 Transistor 100 shows a field plate 132 connected to source 110 via a connection 154 (source-field plate interconnect). Alternatively or concurrently, field plate 132 may be connected to gate 114 via a connection (gate-field plate interconnect (not shown)). In one aspect, connection 154 may be formed on spacer layer 116 and / or second spacer layer 117 to extend between field plate 132 and source 110. In one aspect, connection 154 may be formed together with field plate 132 during the same manufacturing step. In one aspect, multiple connections 154 and / or multiple gate-field plate interconnects may be used. In one aspect, multiple field plates 132 may be used. In one aspect, multiple field plates 132 may be used, and each of the multiple field plates 132 may be stacked together and have a dielectric material therebetween. In some aspects, connection 154 and / or multiple gate-field plate interconnects may include conductive materials, many different conductive materials, suitable materials being metals or combinations of metals deposited using standard metallization methods. In one aspect, the material may include one or more of titanium, gold, nickel, etc.

[0168] In one aspect, the gate-field interconnect may be formed on spacer layer 116 and / or second spacer layer 117 to extend between gate 114 and field plate 132. In some aspects, the gate-field interconnect may include a conductive material, a variety of different conductive materials, with suitable materials being metals or combinations of metals deposited using standard metallization methods. In one aspect, the material may include one or more of titanium, gold, nickel, etc.

[0169] In one aspect of the transistor 100 described herein, the gate 114 may be formed of platinum (Pt), nickel (Ni), and / or gold (Au); however, other metals known to those skilled in the art for achieving the Schottky effect may be used. In one aspect, the gate 114 may include Schottky gate contacts that may have a three-layer structure. Such a structure may be advantageous due to the high adhesion of some materials. In one aspect, the gate 114 may further include a capping layer of a highly conductive metal. In one aspect, the gate 114 may be configured as a T-shaped gate.

[0170] In one aspect of the transistor 100 described herein, one or more metal capping layers may be disposed on one or more of the source 110, drain 112, and gate 114. The capping layer may be Au, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used for the capping layer. In another aspect, the source 110, drain 112, and gate 114 may comprise Au, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used.

[0171] In one aspect of the transistor 100 described herein, a second channel layer may be deposited or grown on a first implementation of a channel layer 104, the first implementation of which is on the side of the channel layer 104 opposite to the substrate layer 102. In one aspect, the second channel layer may be formed directly on the first implementation of the channel layer 104. In one aspect, the second channel layer may be a high-purity material such as gallium nitride (GaN), AlN, etc. In one aspect, the second channel layer may be high-purity GaN. In one aspect, the second channel layer may be high-purity AlN. The second channel layer may be a p-type material or an n-type material. In another aspect, the second channel layer may be undoped.

[0172] In various aspects of the transistor 100 of this disclosure, the contacts of the source 110, gate 114, and / or drain 112 may include Al, Ti, Si, Ni, and / or Pt. In this respect, using the same materials may be advantageous because manufacturing may be easier, simpler, and / or less costly. In other aspects, the materials of the contacts of the source 110, gate 114, and drain 112 may be different.

[0173] Figure 11 A cross-sectional view of another aspect of the transistor according to the present disclosure is shown.

[0174] Figure 11 The transistor 100 can be configured to be similar to Figure 1 transistors, Figure 2 transistors, and / or Figure 3 The transistors are consistent and may include any one or more aspects as described herein. Specifically, they combine the p-type material layer 106 and the back barrier layer 120 as disclosed. Figure 11 The transistor 100, its associated structure, and / or its associated process can provide a systematic approach to reducing hysteresis. More specifically, the transistor 100 of this disclosure can be implemented with a p-type material layer 106 and / or its process as a drain hysteresis reduction structure and / or a process for reducing drain hysteresis effects in the transistor 100, and the transistor 100 of this disclosure can be implemented with a back barrier layer 120 and / or its process as a gate hysteresis reduction structure and / or a process for reducing gate hysteresis effects in the transistor 100.

[0175] In various aspects of this disclosure, the p-type material layer 106 of transistor 100 may be buried within substrate layer 102 and otherwise may not be electrically connected to any part of transistor 100. Figure 11 In one aspect, transistor 100 may include p-type material contacts 118, which can be electrically connected to receive external signals, bias, etc. The p-type material contacts 118 may be electrically connected and disposed in substrate layer 102, p-type material layer 106, channel layer 104, barrier layer 108, etc. The p-type material contacts 118 may be formed in recesses 119 in substrate layer 102, p-type material layer 106, channel layer 104, barrier layer 108, etc. The recesses 119 may extend down into p-type material layer 106 to allow the formation of the p-type material contacts 118 there. The recesses 119 may be formed by etching, and material may also be used to define the recesses 119. The material may be removed after the recesses 119 have been formed.

[0176] Specifically, the groove 119 can remove any material above the p-type material layer 106 within a portion of the region associated with the source 110, thereby exposing the p-type material layer 106 on the side opposite to the substrate layer 102. In another aspect of this disclosure, to form the location of the p-type material contact point 118, the groove 119 can be formed by removing at least a portion of the substrate layer 102, the p-type material layer 106, the channel layer 104, the barrier layer 108, etc.

[0177] In some embodiments, source 110 can be electrically connected to p-type material contact 118 via connection 138. In some embodiments, field plate 132 can be electrically connected to source 110 via connection 154. In some embodiments, field plate 132 can be connected to source 110, and source 110 can be connected to p-type material contact 118 via connection 138.

[0178] In some embodiments, gate 114 may be electrically connected to p-type material contact 118 via a connection (not shown). In some embodiments, field plate 132 may be electrically connected to gate 114 via a connection. In some embodiments, field plate 132 may be connected to gate 114, and gate 114 may be connected to p-type material contact 118 via a connection.

[0179] Figure 11 This invention aims to broadly describe different embodiments of the invention (e.g., different p-layer and / or field plate configurations), but for clarity, not all embodiments are explicitly depicted. It should be understood that the back barrier layer 120 structure of the invention can be used with various p-type material layer 106 structures as described herein, as well as other structures. In some embodiments, the p-type material layer 106 structure may be electrically connected to a separate bias voltage / control signal, electrically connected to the source 110, or electrically connected to the gate 114, or not electrically connected to the source 110, gate 114, and separate bias / control signal. Such electrical connections can be made through vias in the epitaxial material and / or through connections at the exterior and / or edges of the epitaxial material. For example, vias may be constructed within recesses 119. The p-type material layer 106 may be formed or structured in any of the different variations or other modifications described herein. Depending on the embodiment, various field plate 132 configurations are possible. For example, the field plate 132 may be integral with the gate 114, and single or multiple field plates 132 are possible, with or without dielectric spacers between the field plates 132. Field plate 132 may be perpendicularly overlapped or not perpendicularly overlapped with gate 114 or the field plate 132 below it. Field plate 132 may be electrically connected to gate 114 or source 110, or one or more field plates 132 may be connected to gate 114, one or more field plates 132 may be connected to source 110, and / or one or more field plates 132 may be neither connected to source 110 nor to gate 114.

[0180] Figure 12 A process for manufacturing a transistor according to this disclosure is shown.

[0181] Specifically, Figure 12 An exemplary process 500 for manufacturing the transistor 100 of this disclosure is shown. It should be noted that process 500 is merely exemplary and can be modified according to the various aspects described herein. Specifically, process 500 may include any one or more aspects of this disclosure described herein.

[0182] Specifically, process 500 may include fabricating the p-type material layer 106 and the back barrier layer 120 as described above. In this respect, process 500 implements the disclosed p-type material layer 106 and back barrier layer 120, their associated structures, and / or their associated processes, which can provide a systematic approach to reducing hysteresis. More specifically, process 500 may implement its p-type material layer 106 as a drain hysteresis reduction structure and / or a process for reducing drain hysteresis effects in transistor 100, and process 500 of this disclosure may implement the back barrier layer 120 as a gate hysteresis reduction structure and / or a process for reducing gate hysteresis effects in transistor 100.

[0183] Process 500 can begin at step 502 by forming substrate layer 102. Substrate layer 102 can be formed according to this disclosure. For example, substrate layer 102 can be made of silicon carbide (SiC). In some aspects, substrate layer 102 can be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, etc. In some aspects, substrate layer 102 can be very lightly doped. In one aspect, the background impurity level can be low. In one aspect, the background impurity level can be 1 × 10⁻⁶. 15 / cm 3 Or lower. The substrate layer 102 may be formed of SiC selected from the group consisting of 6H, 4H, 15R, 3C, SiC, etc. Alternatively, the substrate layer 102 may be GaAs, GaN, or other materials suitable for the applications described herein. Alternatively, the substrate layer 102 may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of group III nitride materials.

[0184] Process 500 may include step 504 of forming a p-type material layer 106. The p-type material layer 106 may be formed as described in this disclosure. This may include implanting Al into a substrate layer 102 to form the p-type material layer 106 in the substrate layer 102. For example, the p-type material layer 106 may be formed by ion implantation and annealing of Al. In one aspect, the p-type material layer 106 may be formed by Al implantation and annealing prior to the growth of any GaN layer. In one aspect, ion implantation may utilize channel implantation. In one aspect, channel implantation may include aligning an ion beam with the substrate layer 102. Alignment of the ion beam may result in increased implantation efficiency. In some aspects, process 500 may further include implanting Al into the substrate layer 102 to form the p-type material layer 106 in the substrate layer 102. Subsequently, the substrate layer 102 may be annealed as defined herein. In one aspect, the p-type material layer 106 may be formed by ion implantation in 4H-SiC. 27 Al was formed, and the injection was performed at 25°C with a dose of 1×10. 13 cm2 The implantation was carried out under channel conditions with an implantation energy of E1 = 100 keV. In one aspect, the p-type material layer 106 can be implanted by ion implantation in 4H-SiC. 27 Al was formed, and the injection was performed at 25°C with a dose of 1×10. 13 cm 2 The injection was performed under channel conditions with an injection energy of E2 = 300 keV. However, other injection energies and doses can also be considered.

[0185] Process 500 may include step 506 of forming a back barrier layer 120 on substrate layer 102 and / or nucleation layer 136. The back barrier layer 120 may be grown or deposited on substrate layer 102 and / or nucleation layer 136 as described in this disclosure. In one aspect, nucleation layer 136 may be formed on substrate layer 102, and the back barrier layer 120 may be formed on nucleation layer 136 in step 506.

[0186] Step 506 of forming the back barrier layer 120 may include forming the back barrier layer 120 to confine and / or avoid impurities such as silicon, oxygen, carbon, etc., to reduce gate hysteresis. Specifically, impurities provide trapping, leakage, etc. More specifically, aspects of this disclosure can realize a back barrier layer 120 having a low background impurity level. In one aspect, this disclosure can realize AlGaN for a back barrier layer 120 having a low background impurity level. At this point, it has been found that impurities form complexes with dislocations (such as point defects), which also act as deep trap levels. Step 506 of forming the back barrier layer 120 may be configured to provide a sharp interface to the channel layer 104. This interface can serve as a barrier for electrons. In aspects of the transistor 100 of this disclosure, the back barrier layer 120 may be a gradient layer. In one aspect, the back barrier layer 120 may be a stepped gradient layer. In one aspect, the back barrier layer 120 may be multiple layers.

[0187] Step 506, forming the back barrier layer 120, may include forming a back barrier layer 120 having a low Al concentration AlGaN buffer layer to provide a barrier to reduce electron injection into the buffer layer. In this respect, the barrier to reduce electron injection into the buffer layer leads to gate hysteresis reduction structures, gate hysteresis elimination structures, etc. For example, the back barrier layer 120 may be implemented using AlGaN with an Al concentration of approximately 4% to provide a barrier to reduce electron injection into the buffer layer. In this respect, it may be within approximately 0.5%, 1%, 1.5%, or 2%. In certain aspects, the back barrier layer 120 can be implemented using AlGaN having an Al concentration of 1% to 6%, 1% to 1.5%, 1.5% to 2%, 2% to 2.5%, 2.5% to 3%, 3% to 3.5%, 3.5% to 4%, 3.5% to 4.5%, 3.8% to 4.2%, 4% to 4.5%, 4.5% to 5%, 5% to 5.5%, or 5.5% to 6% to provide a barrier, gate hysteresis reduction structure, gate hysteresis elimination structure, etc., to reduce electron injection into the buffer layer.

[0188] Process 500 may include step 508 of forming a channel layer 104 on the back barrier layer 120. The channel layer 104 may be grown or deposited on the back barrier layer 120 as described in this disclosure. In one aspect, the channel layer 104 may be GaN.

[0189] Furthermore, during process 500 (as part of step 510), a barrier layer 108 may be formed on the channel layer 104. The barrier layer 108 may be formed as described in this disclosure. For example, the barrier layer 108 may be an n-type conductive layer or it may be undoped. In one aspect, the barrier layer 108 may be AlGaN.

[0190] Furthermore, during process 500 (as part of step 512), to form the location of the p-type material contact 118 and the p-type material layer 106, a groove 119 can be formed by removing at least a portion of the barrier layer 108, at least a portion of the channel layer 104, at least a portion of the back barrier layer 120, etc. Process 500 for forming the connection 154 may include removing any material above the p-type material layer 106, exposing the p-type material layer 106 on the side opposite to the substrate layer 102. In another aspect of this disclosure, to form the location of the p-type material contact 118 and the p-type material layer 106, a connection 138 can be formed by removing at least a portion of the barrier layer 108, at least a portion of the channel layer 104, and / or the back barrier layer 120. The groove forming process may remove any material above the p-type material layer 106 within a portion of the region associated with the source 110, thereby exposing the p-type material layer 106 on the side opposite to the substrate layer 102.

[0191] Furthermore, during process 500 (as part of step 514), the source 110 may be disposed on the barrier layer 108. The source 110 may be an ohmic contact of a suitable material that can be annealed. For example, the source 110 may be annealed at a temperature of about 500°C to about 800°C for about 2 minutes. However, other times and temperatures may also be used. For example, times from about 30 seconds to about 10 minutes may be acceptable. In some aspects, the source 110 may comprise Al, Ti, Si, Ni, and / or Pt. In one aspect, a region 164 of N+ material below the source 110 may be formed in the barrier layer 108. In one aspect, the region 164 below the drain 112 may be Si-doped.

[0192] Furthermore, during process 500 (as part of step 514), the drain 112 can be disposed on the barrier layer 108. Like the source 110, the drain 112 can be an ohmic contact of Ni or another suitable material, and can also be annealed in a similar manner. In one aspect, N+ implantation can be used in conjunction with the barrier layer 108, forming a contact with the implantation. In one aspect, a region 164 of N+ material beneath the drain 112 can be formed in the barrier layer 108. In one aspect, the region 164 beneath the drain 112 can be Si-doped.

[0193] Furthermore, during process 500 (as part of step 514), gate 114 may be disposed on barrier layer 108 between source 110 and drain 112. Layers of Ni, Pt, Au, etc., may be formed for gate 114 by evaporation deposition or another technique. The gate structure can then be completed by depositing Pt and Au or other suitable materials. In some aspects, the contacts of gate 114 may include Al, Ti, Si, Ni, and / or Pt.

[0194] Furthermore, during process 500 (as part of step 514), a spacer layer 116 may be formed. The spacer layer 116 may be a passivation layer (such as SiN, AlO, SiO, SiO2, AlN, etc.) or a combination thereof with multiple layers thereof, which may be deposited on the exposed surface of the barrier layer 108.

[0195] Source 110 and drain 112 can be formed to create an ohmic contact, such that when gate 114 is biased to an appropriate level, current flows between source 110 and drain 112 via a two-dimensional electron gas (2DEG) induced at the heterojunction 152 between channel layer 104 and barrier layer 108. In one aspect, source 110 can be electrically coupled to barrier layer 108, drain 112 can be electrically coupled to barrier layer 108, and gate 114 can be electrically coupled to barrier layer 108, such that when gate 114 is biased to an appropriate level, current flows between source 110 and drain 112 via a two-dimensional electron gas (2DEG) induced at the heterojunction 152 between channel layer 104 and barrier layer 108. In one aspect, source 110 may be electrically coupled to transistor 100, drain 112 may be electrically coupled to transistor 100, and gate 114 may be electrically coupled to transistor 100, such that when gate 114 is biased to an appropriate level, current flows between source 110 and drain 112 via a two-dimensional electron gas (2DEG) induced at the heterointerface 152 between channel layer 104 and barrier layer 108. In another aspect, the electron flow in the 2DEG can be controlled based on a signal and / or bias voltage placed on gate 114. At this point, transistor 100 may be normally turned on or normally turned off without bias voltage or signal on the gate, depending on the composition and / or doping of the layers. In one aspect, heterointerface 152 may be in the range of 0.005 µm to 0.007 µm, 0.007 µm to 0.009 µm, and 0.009 µm to 0.011 µm.

[0196] Gate 114 may extend on top of spacer body or spacer layer 116. Spacer layer 116 may be etched and gate 114 deposited such that the bottom of gate 114 is located on the surface of barrier layer 108. The metal forming gate 114 may be patterned to extend across spacer layer 116 such that a field plate 132 is formed on top of gate 114.

[0197] Furthermore, during some aspects of process 500 (as part of step 514), a second spacer layer 117 may be formed, and a field plate 132 may be disposed on top of the second spacer layer 117 and may be spaced apart from the gate 114. In one aspect, the field plate 132 may be deposited on the second spacer layer 117 between the gate 114 and the drain 112. In some aspects, the field plate 132 may comprise a variety of different conductive materials, wherein suitable materials are metals or combinations of metals deposited using standard metallization methods. In one aspect, the field plate 132 may comprise titanium, gold, nickel, titanium / gold, nickel / gold, etc.

[0198] In one aspect, connection 154 can be formed together with field plate 132 during the same manufacturing step (see [link]). Figure 10 In one aspect, multiple field plates 132 may be used. In another aspect, multiple field plates 132 may be used, and each of the multiple field plates 132 may be stacked together and have a dielectric material therebetween. In one aspect, the field plate 132 extends toward the edge of the gate 114 and toward the drain 112. In one aspect, the field plate 132 extends toward the source 110. In another aspect, the field plate 132 extends toward the drain 112 and toward the source 110. In another aspect, the field plate 132 does not extend toward the edge of the gate 114. Finally, the structure may be covered with a dielectric spacer layer such as silicon nitride. The dielectric spacer layer may also be implemented similarly to spacer layer 116. Additionally, it should be noted that the cross-sectional shape of the gate 114 shown in the figure is exemplary. For example, in some aspects, the cross-sectional shape of the gate 114 may not include the T-shaped extension. Other configurations of the gate 114 may be utilized.

[0199] It should be noted that, according to the aspects described above, the steps of process 500 can be performed in different orders. Furthermore, according to the aspects disclosed herein, process 500 can be modified to have more or fewer process steps. In one aspect of process 500, transistor 100 can be implemented using only the p-type material layer 106.

[0200] In one aspect of the transistor 100 as described herein, the p-type material layer 106 can be doped as high as possible with minimal achievable sheet resistance. In another aspect, the implantation concentration of the p-type material layer 106 can be less than 10. 19 In one respect, the implantation concentration of the p-type material layer 106 can be less than 10. 20 In one respect, the implantation concentration of the p-type material layer 106 can be 10. 17 -10 20 10 19 -10 20 10 18 -10 19 , or 10 17 -10 18 In one respect, the implantation concentration of the p-type material layer 106 can be 10. 19 Or even higher. In one respect, the implantation concentration of the p-type material layer 106 can be 10. 18 -10 20 10 18 -10 19 , or 10 19 -10 20 .

[0201] In one aspect of the transistor 100 as described herein, the p-type material layer 106 doping can be less than 1 × 10⁶. 17 cm 3 In one respect, the doping of the p-type material layer 106 can be less than 2 × 10⁶. 17 cm 3 In one respect, the doping of the p-type material layer 106 can be less than 6 × 10⁶. 17 cm 3 In one respect, the doping of the p-type material layer 106 can be less than 2 × 10⁶. 18 cm 3 In one aspect, the doping density of the p-type material layer 106 can reach 5 × 10⁶ per cubic centimeter. 15 Up to 5×10 17 Within these ranges. In these respects, the doping concentration of the p-type material layer 106 can be greater than the doping concentration of the p-type material layer 106.

[0202] One aspect of transistor 100 can be implemented as a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer. One aspect includes a method associated with transistor 100, which can be implemented as a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer. One aspect includes a method of implementing transistor 100 as a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer. One aspect includes a method of manufacturing transistor 100 as a group III nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0203] Therefore, this disclosure provides solutions to address the hysteresis effect in group III nitride HEMTs and improve the performance of such devices. Additionally, this disclosure provides solutions to traps that lead to memory effects, which adversely affect performance. Specifically, this disclosure provides implementations of a transistor 100 combining a p-type material layer 106 and a back barrier layer 120, its associated structure, and / or its associated process, which can provide a systematic approach to reducing latency. More specifically, the transistor 100 of this disclosure can implement the p-type material layer 106 and / or its process as a drain hysteresis reduction structure and / or a process for reducing drain hysteresis effects, and the transistor 100 of this disclosure can implement the back barrier layer 120 and / or its process as a gate hysteresis reduction structure and / or a process for reducing gate hysteresis effects.

[0204] Specifically, this disclosure provides implementations of a transistor 100 combining a p-type material layer 106 and a back barrier layer 120, their associated structures and / or their associated processes, which can provide a synergistic overall reduction in hysteresis of the transistor 100, which is an unexpected result of the combined structure of the back barrier layer 120 and the p-type material layer 106.

[0205] According to various aspects of this disclosure, one or more aspects of the disclosed transistor 100 can be used to implement amplifiers, radar amplifiers, radar components, microwave radar amplifiers, power modules, gate drivers, components such as general broadband components, telecommunications components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, Doherty configurations, etc. The L-band is the Institute of Electrical and Electronics Engineers (IEEE) designation for the frequency range of 1 to 2 GHz in the radio spectrum. The S-band is the IEEE designation for a portion of the microwave frequency band of the electromagnetic spectrum from 2 to 4 GHz. The X-band is the designation for a band in the microwave radio region of the electromagnetic spectrum set indefinitely in the range of approximately 7.0–11.2 GHz. The C-band refers to the radio frequency designation from 500 to 1000 MHz. The Ku-band is a portion of the electromagnetic spectrum in the microwave range of 12 to 18 GHz.

[0206] According to various aspects of this disclosure, one or more aspects of the disclosed transistor 100 can be configured in a package, and the package can be implemented as an RF package, an MMIC RF package, etc., and can accommodate RF devices. Specifically, the RF device can implement one or more of the following: resistors, inductors, capacitors, metal-oxide-semiconductor (MOS) capacitors, impedance matching circuits, matching circuits, input matching circuits, output matching circuits, intermediate matching circuits, harmonic filters, harmonic terminations, couplers, baluns, power combiners, power dividers, radio frequency (RF) circuits, radial stub circuits, transmission line circuits, baseband matching circuits, baseband termination circuits, second-order harmonic termination circuits, integrated passive devices (IPDs), matching networks, etc., to support various functional technologies as input, output, and / or inter-stage functions of the package. A package implemented as an MMIC package may further include transistor 100. A package implemented as an MMIC package may include a connection, support (or similar means) for a radar transmitter, radar transmitter function, microwave radar transmitter, microwave radar transmitter function, radar receiver, radar receiver function, microwave radar receiver, microwave radar receiver function, etc.

[0207] While this disclosure has been described with reference to exemplary aspects, those skilled in the art will recognize that this disclosure can be practiced with modifications made within the spirit and scope of the appended claims. The examples given above are merely exemplary and are not intended to be an exhaustive list of all possible designs, aspects, applications, or modifications of this disclosure.

Claims

1. A device for reducing hysteresis, comprising: substrate; The group III nitride back barrier layer on the substrate; The group III nitride back barrier layer on the group III nitride channel layer; The group III nitride barrier layer on the group III nitride channel layer, wherein the group III nitride barrier layer includes a band gap higher than that of the group III nitride channel layer; The source electrode is electrically coupled to the group III nitride barrier layer; Gate, on the group III nitride barrier layer; The drain is electrically coupled to the group III nitride barrier layer; and The p-region is disposed within the substrate or below the group III nitride barrier layer between the group III nitride barrier layer and the substrate. Wherein, at least a portion of the p region is vertically disposed below at least one of the following: the source, the gate, and the region between the gate and the drain. The group III nitride back barrier layer is configured with a low background impurity level; and The low background impurity level is defined as less than 1×10⁻⁶. 15 Impurities per cubic centimeter.

2. The device according to claim 1, wherein, The group III nitride back barrier layer is at least partially configured as a gate hysteresis reduction structure.

3. The device according to claim 1, wherein, The p region is at least partially configured as a drain hysteresis reduction structure, and wherein the group III nitride back barrier layer is on the nucleation layer.

4. The device according to claim 1, wherein, The group III nitride back barrier layer is at least partially configured as a gate hysteresis reduction structure, the p region is at least partially configured as a drain hysteresis reduction structure, and the group III nitride back barrier layer and the p region reduce overall hysteresis.

5. The device according to claim 1, wherein, The combined thickness of the group III nitride channel layer and the group III nitride back barrier layer is defined as the thickness of the distance between the upper surface of the substrate and the lower surface of the group III nitride barrier layer.

6. The device according to claim 1, wherein, The group III nitride back barrier layer is configured with a low background impurity level of at least one of the following: silicon, oxygen, and carbon.

7. The device according to claim 1, wherein, The group III nitride back barrier layer is configured to provide a sharp interface to the group III nitride channel layer.

8. The device according to claim 1, wherein, The group III nitride back barrier layer includes AlGaN.

9. The device according to claim 1, wherein, The group III nitride back barrier layer comprises AlGaN with an Al concentration of 1% to 4.5%.

10. The device according to claim 1, wherein, The group III nitride back barrier layer is structured by epitaxial growth having a low background impurity level of at least one of the following: silicon (Si), oxygen (O), and carbon (C).

11. The device according to claim 1, further comprising: A nucleation layer is formed on the substrate. The group III nitride back barrier layer is arranged on the nucleation layer.

12. The device according to claim 1, wherein: A portion of the source side of the substrate lacks the p region; and A portion of the drain side of the substrate lacks the p region.

13. The device according to claim 1, wherein: A portion of the substrate includes the p region located vertically below the source electrode; and Another portion of the substrate does not include the p region located vertically below the source electrode.

14. The device according to claim 13, wherein: The substrate does not include the p region located vertically below the source electrode; and The substrate does not include the p region located vertically below the drain electrode.

15. The device according to claim 1, wherein, The p-region is constructed and arranged such that no part of the p-region is perpendicularly located below the drain.

16. The device according to claim 1, further comprising: Field board, Specifically, the p region is injected.

17. The device according to claim 1, further comprising: A field plate, wherein the field plate is electrically coupled to the source electrode.

18. The device according to claim 17, wherein, The p-region is constructed and arranged to extend a finite length parallel to the group III nitride barrier layer, such that the p-region is not perpendicular to the region extending beyond the source and drain.

19. The device according to claim 1, wherein, The p-region is disposed below the gate and spans the length of the gate, and extends toward the source and the drain.

20. The device according to claim 1, wherein, The p region extends toward the source electrode, but does not overlap perpendicularly with the source electrode.

21. The device according to claim 1, wherein, The p region overlaps perpendicularly with the source electrode.

22. The device according to claim 1, wherein, The p region extends toward the drain electrode, but does not overlap the drain electrode perpendicularly.

23. The device according to claim 1, wherein, The p region overlaps perpendicularly with the drain electrode.

24. The device according to claim 1, wherein, The p region does not include direct electrical connections.

25. A method of manufacturing a device, comprising: Set up a substrate; A group III nitride back barrier layer is disposed on the substrate; A group III nitride channel layer is formed on the group III nitride back barrier layer; A group III nitride barrier layer is disposed on the group III nitride channel layer, wherein the group III nitride barrier layer includes a band gap that is higher than the band gap of the group III nitride channel layer; The source electrode is electrically coupled to a group III nitride barrier layer; A gate is disposed on the group III nitride barrier layer; The drain is electrically coupled to the group III nitride barrier layer; and A p-region is provided, wherein the p-region is disposed within the substrate or below the group III nitride barrier layer between the group III nitride barrier layer and the substrate. Wherein, at least a portion of the p region is vertically disposed below at least one of the following: the source, the gate, and the region between the gate and the drain. The group III nitride back barrier layer is configured with a low background impurity level; and The low background impurity level is defined as less than 1×10⁻⁶. 15 Impurities per cubic centimeter.

26. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer is at least partially configured as a gate hysteresis reduction structure.

27. The method of manufacturing a device according to claim 25, wherein, The p region is at least partially configured as a drain hysteresis reduction structure, and wherein the group III nitride back barrier layer is on the nucleation layer.

28. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer is at least partially configured as a gate hysteresis reduction structure, the p region is at least partially configured as a drain hysteresis reduction structure, and the group III nitride back barrier layer and the p region reduce overall hysteresis.

29. The method of manufacturing a device according to claim 25, wherein, The combined thickness of the group III nitride channel layer and the group III nitride back barrier layer is defined as the thickness of the distance between the upper surface of the substrate and the lower surface of the group III nitride barrier layer.

30. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer is configured with low background impurity levels for silicon, oxygen, and carbon.

31. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer is configured to provide a sharp interface to the group III nitride channel layer.

32. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer includes AlGaN.

33. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer comprises AlGaN with an Al concentration of 1% to 4.5%.

34. The method of manufacturing a device according to claim 25, wherein, The group III nitride back barrier layer is structured by epitaxial growth having a low background impurity level of at least one of the following: silicon (Si), oxygen (O), and carbon (C).

35. The method of manufacturing a device according to claim 25, further comprising: A nucleation layer is formed on the substrate. The group III nitride back barrier layer is arranged on the nucleation layer.

36. The method of manufacturing a device according to claim 25, wherein: A portion of the source side of the substrate lacks the p region; and A portion of the drain side of the substrate lacks the p region.

37. The method of manufacturing a device according to claim 25, wherein: A portion of the substrate includes the p region located vertically below the source electrode; and Another portion of the substrate does not include the p region located vertically below the source electrode.

38. The method of manufacturing a device according to claim 37, wherein: The substrate does not include the p region located vertically below the source electrode; and The substrate does not include the p region located vertically below the drain electrode.

39. The method of manufacturing a device according to claim 25, further comprising: The p-region is formed such that no part of the p-region is perpendicularly located below the drain.

40. The method of manufacturing a device according to claim 25, further comprising: Inject into the p region.

41. The method of manufacturing a device according to claim 25, further comprising: Set up the field board.

42. The method of manufacturing a device according to claim 25, further comprising: A field plate is provided, wherein the field plate is electrically coupled to the source electrode.

43. The method of manufacturing a device according to claim 42, wherein, The p-region is constructed and arranged to extend a finite length parallel to the group III nitride barrier layer, such that the p-region is not perpendicular to the region extending beyond the source and drain.

44. The method of manufacturing a device according to claim 25, wherein, The p-region is disposed below the gate and spans the length of the gate, and extends toward the source and the drain.

45. The method of manufacturing a device according to claim 25, wherein, The p region extends toward the source electrode, but does not overlap perpendicularly with the source electrode.

46. ​​The method of manufacturing a device according to claim 25, wherein, The p region overlaps perpendicularly with the source electrode.

47. The method of manufacturing a device according to claim 25, wherein, The p region extends toward the drain electrode, but does not overlap the drain electrode perpendicularly.

48. The method of manufacturing a device according to claim 25, wherein, The p region overlaps perpendicularly with the drain electrode.

49. The method of manufacturing a device according to claim 25, wherein, The p region does not include direct electrical connections.

50. The method of manufacturing a device according to claim 25, wherein, The p region is electrically connected to the source electrode.

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