An infrared focal plane irregularly shaped readout unit circuit with high sensitivity and large dynamic range

Abstract

The application discloses a high-sensitivity and large-dynamic-range infrared focal plane irregular readout unit circuit, and specifically comprises four CTIA input stage modules surrounding a mixed input stage module to input photo-generated current or voltage signals, which bear different functions respectively. In the middle of every 2*2 CTIA input stage module array, there is a mixed input stage module with switchable direct input mode / logarithmic mode, that is, four high-sensitivity CTIA input pixels and one large-dynamic-range mixed input stage pixel, and the five pixels constitute an irregular circuit pixel. Corresponding photosensitive chip interconnection PADs are reserved on each pixel unit. The application has the advantages that the CTIA input stage module has the characteristics of high injection efficiency and high sensitivity, and the mixed input stage module has the characteristics of large dynamic range, small area and low power consumption.

Description

Technical Field

[0001] This invention relates to an infrared focal plane readout circuit, and more particularly to a high-sensitivity, large dynamic range infrared focal plane irregular readout unit circuit. Background Technology

[0002] Infrared detection technology is widely used in various industries and sectors. Infrared focal plane arrays, in particular, have important applications in aerospace remote sensing and military detection. Readout circuit chips are a crucial component of infrared focal plane arrays, and their development is currently moving towards higher integration, higher sensitivity, wider dynamic range, lower power consumption, multicolor capabilities, digitalization, and intelligence. High-sensitivity, wide dynamic range readout circuits represent a significant research direction within this field.

[0003] The dynamic range of the readout circuit is defined as the ratio of output swing to output noise, or the ratio of maximum unsaturated current to minimum detectable current, where the minimum current is defined as the noise current or detector dark current under no-light conditions. Assume the integral current of the readout circuit can be expressed as I... MAX =Q MAX / T INT The dynamic range is defined as follows:

[0004] DR = 20log(I MAX / I MIN ) = 20log(Q MAX / Q MIN (4)

[0005] Current solutions to the problem of insufficient dynamic range in infrared readout circuits mainly include: logarithmic pixels that extend the dynamic range by utilizing nonlinear compression of the photoelectric response curve; multiple exposure techniques; lateral overflow gate pixel structures that extend the dynamic range by increasing the well capacity; and selective reset methods. Among these, logarithmic pixel structures are significantly affected by process conditions and exhibit low photoresponse sensitivity in low light; multiple exposure techniques increase circuit processing time, leading to a decrease in speed; lateral overflow gate pixel structures, while extending the dynamic range, result in a decrease in signal-to-noise ratio; and selective reset structures also involve the addition of memory and reconfiguration circuitry.

[0006] Sensitivity is defined as the output signal voltage of a device under a unit exposure, i.e.:

[0007]

[0008] In the formula, V0 is the signal voltage output by the readout circuit, and H V It is the amount of exposure received by the detector unit.

[0009] Q INT =I SIG ×TINT Sensitivity can be improved by reducing the integrating capacitor or extending the integration time, but reducing the integrating capacitor will reduce the charge capacity of the readout circuit, thus reducing the dynamic range of the readout circuit. Summary of the Invention

[0010] This patent proposes a design method for a high-sensitivity, large dynamic range irregularly shaped readout circuit, which can achieve both high-sensitivity detection and meet the requirements of large dynamic range detection. Its principle draws inspiration from the two types of photoreceptor cells used in the human eye to identify objects. These two types of cells have different photosensitivity, and by using them together to identify objects, a large dynamic range can be obtained. Therefore, in the readout circuit, two input stages with high and low sensitivity detection capabilities can be integrated simultaneously in a single pixel to simulate this mechanism of the human eye and achieve a large dynamic range. Under bright conditions, the large dynamic range photodetector performs better, while in dark environments, the high-sensitivity photodetector performs better. By enabling both circuit structures to operate simultaneously, high-sensitivity, large dynamic range circuit readout can be achieved.

[0011] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0012] A high-sensitivity, wide dynamic range infrared focal plane array irregularly shaped readout unit circuit includes a CTIA input stage structure and a hybrid input stage structure switchable between direct input mode and logarithmic mode. Four CTIA input stage structures are arranged around a hybrid input stage structure to provide input and form a single pixel. The circuit composed of the CTIA input stage structures includes a two-stage gain-selectable integrating amplifier circuit, a correlation double sampling circuit, and an output buffer stage circuit. Figure 2As shown, the photocurrent flows into the PAD terminal, which is also the inverting input of the operational amplifier. The non-inverting input of the operational amplifier is connected to a reference voltage, typically 2V-3.3V. The integrating amplifier circuit composed of the operational amplifier also includes two optional capacitors, typically 1fF-20fF, to provide the two gain levels; and a reset transistor connected at one end to the PAD terminal and the other end to the operational amplifier output terminal, which controls the reset of each frame signal. A MIM capacitor is connected to the output of the operational amplifier, serving as both a load capacitor and a filter capacitor. This capacitor is connected to a correlated double sampling circuit, consisting of two pairs of sample-and-hold circuits, which reduces noise by sampling signals with correlated time intervals. This is followed by an output buffer stage circuit composed of two pairs of common-drain amplifier circuits. The timing of these two output stages can be controlled by the ROWSEL, with signals output at the VOUT1 and VOUT2 ports respectively. The hybrid input stage structure, switchable between direct input and logarithmic modes, mainly includes an injection transistor M21 with an adjustable gate voltage VDI, a reset transistor M22, switching transistors M23 and M24, a MOSFET replacing capacitor M25, and output buffer stages M26 and M27. When VDI is changed to put transistor M21 in the linear region and the capacitor switch is turned on, the circuit operates in direct input mode, and the signal input to the PAD terminal is the photocurrent signal. When VDI is changed to put transistor M21 in the subthreshold region and the capacitor switch is turned off, the circuit operates in logarithmic mode, and the signal input to the PAD terminal is the photovoltage signal. The RESET transistor controls the reset of the signal for each frame, transistor M27 is an output buffer stage circuit composed of a common-drain amplifier, and ROWSEL controls when to output; the signal is output at the VOUT port.

[0013] The circuit's wide dynamic range capability allows it to detect photocurrents in the pA-μA range.

[0014] The logarithmic mode of this circuit does not involve capacitor integration, thus enabling accurate instantaneous temperature measurement.

[0015] When operating in the direct input mode, transistor M21 is in the subthreshold region, and the operating current and gate-source voltage satisfy the following:

[0016]

[0017] |V GS |=V S -V DI (2)

[0018] V S,DI =ζV T ln(I D / I0)+V DI (3)

[0019] In the formula, the bias voltage V of the deviceS Only with the injected current I D V DI It is related to the gate voltage. When the gate voltage V DI Fixed injection current I D When constant, even if the voltage across the integrating capacitor changes continuously, the bias voltage V of the device remains constant. S It will not change, thus providing a stable bias for the device. Where V T Thermoelectric voltage;

[0020] When operating in logarithmic mode, the voltage generated in the photodiode is directly output without passing through the M25 sampling capacitor, which is based on the device characteristics of the photodiode.

[0021] The advantages of this invention are: the CTIA input level module is characterized by high injection efficiency and high sensitivity; the hybrid input level module is characterized by large dynamic range, small area and low power consumption. Attached Figure Description

[0022] To further illustrate the specific content of this invention, see the appendix. Figure 4 The details are as follows:

[0023] Figure 1 This is a schematic diagram of an irregularly shaped circuit pixel structure proposed in this invention.

[0024] Figure 2 This is a circuit structure diagram of a CTIA circuit proposed in this invention.

[0025] Figure 3 This is a structural diagram of a hybrid input level that can switch between direct input mode and logarithmic mode, as proposed in this invention.

[0026] Figure 4 This is a graph showing the logarithmic relationship between incident light power and photogenerated electromotive force in the photodiode mentioned in this invention. Detailed Implementation

[0027] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0028] The circuit of this invention can be completed using the CMOS standard 180nm process to draw the circuit diagram and layout with a pixel pitch of 15μm.

[0029] In the CTIA circuit of this invention, the smaller the integrating capacitor, the faster the output voltage changes with the input current. Therefore, a smaller integrating capacitor results in higher sensitivity of the focal plane array. Using a small integrating capacitor can effectively improve the sensitivity of the focal plane detector. In this circuit, a minimum integrating capacitor of 1fF-5fF is generally suitable.

[0030] The photocurrent detected by the CTIA input stage circuit of this invention is generally in the pA range, the photocurrent detected by the circuit in direct input mode is generally in the pA-nA range, and the photocurrent detected by the circuit in logarithmic mode is generally in the pA-μA range.

[0031] The output voltage range of the circuit in logarithmic mode of this invention is generally 0.4V. The photogenerated electromotive force tends to saturate at around 0.4V.

Claims

1. A high-sensitivity, wide dynamic range infrared focal plane array irregularly shaped readout unit circuit, comprising four CTIA input stage modules and a hybrid input stage module switchable between direct input mode and logarithmic mode, characterized in that: In the aforementioned unit circuit, four CTIA input level modules surround a mixed input level module; The CTIA input stage module includes a two-stage gain-selectable integrating amplifier circuit, a correlated double sampling circuit, and an output buffer stage circuit. The hybrid input stage module includes a gate voltage V DI The module includes an adjustable injection transistor M21, a reset transistor M22, switching transistors M23 and M24, a sampling capacitor M25, and an output buffer circuit. In the mixed input stage module, the gate of the injection transistor M21 is connected to an adjustable gate voltage V. DI The source of transistor M22 is connected to the signal input PAD, and the drain is connected to the common intermediate node N. The gate of reset transistor M22 receives the reset control signal RESET, the drain is connected to the common intermediate node N, and the source is grounded to GND. Switches M23 and M24 share one end connected to the common intermediate node N, and the other end is connected to the upper plate of sampling capacitor M25. The lower plate of M25 is grounded to GND. The output buffer circuit consists of M26 and M27. The gate of M27 is connected to the common intermediate node N, and the drain of M27 is connected to the source of M26. The source of M26 serves as the module output terminal VOUT; the gate of M26 is connected to the horizontal selection control signal ROWSEL, and the drain of M26 is connected to the power supply VDDA; the common intermediate node N is simultaneously connected to the drains of M21 and M22, one end of the switching pair M23 and M24, and the gate of the output buffer circuit M27; when the switching pair M23 and M24 are turned on, the common intermediate node N is connected to the sampling capacitor M25; when the switching pair M23 and M24 are turned off, the sampling capacitor M25 is disconnected from the common intermediate node N; The injection transistor M21 is a MOS injection transistor, the reset transistor M22 is a MOS reset switch transistor, the switch pair M23 and M24 are complementary MOS switch pairs, the M26 is a row selection MOS switch transistor, and the M27 is a source follower buffer MOS transistor. The CTIA input stage module and the hybrid input stage module of the unit circuit are each configured with corresponding photosensitive chip interconnect PADs to input signals; VOUT1 and VOUT2 are the output ports of the CTIA input stage module, and VOUT is the output port of the hybrid input stage module; When operating in the direct input mode, the injection transistor M21 is in the subthreshold region, and the operating current and gate-source voltage satisfy the following: （1） （2） （3） V S,DI I is the source voltage of the injection transistor M21 in direct input mode. D Let I0 be the injected current, ζ be the non-ideal factor, and V be the unit current. T For thermal voltage, V GS This is the gate-source voltage; The bias voltage of the device in the formula Only with injected current Gate voltage Yes, there is a relationship; when the gate voltage Fixed and injected current When constant, even if the voltage across the integrating capacitor of the CTIA input stage module changes continuously, the device's bias voltage remains constant. It will not change, thus providing a stable bias for the device; When the logarithmic mode is working, the voltage generated in the photodiode is directly output without passing through the sampling capacitor M25, which is based on the device characteristics of the photodiode.

2. The infrared focal plane array irregular readout unit circuit with high sensitivity and large dynamic range according to claim 1, characterized in that: The operational amplifier of the CTIA input stage module is a common-source common-gate amplifier (CRB). The reset transistor M1 is connected between the inverting input terminal PAD of the CRB and the output terminal of the operational amplifier, with its gate receiving the RESET control signal. Switches M2 and M3 are complementary control switches used to select the integrating capacitors C2 and C1 connected to the feedback loop. When the switches are off, only capacitor C2 is connected to the feedback loop; when the switches are on, the sum of capacitors C2 and C1 is connected to the feedback loop. M4 is a load capacitor, with one end connected to the output terminal of the CRB and the other end grounded. The MOS switch M5 and the MOS capacitor M6 constitute the first sampling path. The second sample-and-hold branch consists of MOS switch M7 and MOS capacitor M8. The inputs of both sample-and-hold branches are connected to the output of the common-source common-gate amplifier to achieve correlated double sampling. MOS switch M9 and MOS source follower M10 form the first output buffer, and MOS switch M11 and MOS source follower M12 form the second output buffer. The gate of MOS source follower M10 is connected to the sampling output node of MOS switch M5 and MOS capacitor M6, and the gate of MOS source follower M12 is connected to the sampling output node of MOS switch M7 and MOS capacitor M8. The gates of MOS switch M9 and MOS switch M11 jointly receive the row selection control signal ROWSEL. The source output of MOS source follower M10 is VOUT1, and the source output of MOS source follower M12 is VOUT2. The reset transistor M1 is a MOS switch transistor, and the switch pair M2 and M3 are complementary MOS switch pairs.

3. The high-sensitivity, large dynamic range infrared focal plane array irregular readout unit circuit according to claim 1, characterized in that: The direct input mode / logarithmic mode switchable hybrid input stage module changes the gate voltage V. DI The switching pairs M23 and M24 allow the circuit to operate in different modes by changing the gate voltage V. DI When the injection transistor M21 is in the subthreshold region and the switching pairs M23 and M24 are turned on, the circuit operates in direct input mode; when the gate voltage V is changed... DI When the injection tube M21 is in the linear region and the switching pairs M23 and M24 are turned off, the circuit operates in logarithmic mode.

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