Method of monitoring a polishing table for light leakage

Abstract

The application provides a method for monitoring light leakage of a polishing machine table, comprising the following steps: providing a substrate; forming a semiconductor structure on the substrate, wherein the semiconductor structure is formed with a PN junction conduction loop, a first conductive plug and a second conductive plug; forming a metal layer; polishing the metal layer on the surface of the semiconductor structure by using the polishing machine table; obtaining a defect map of the surface of the semiconductor structure; monitoring whether there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure by using the defect map, and if there are metal precipitation defects and / or pit defects, diagnosing that there is a light leakage fault in the HCLU pressure sensor in the polishing machine table. By using the semiconductor structure with the PN junction conduction loop to perform the CMP process in the polishing machine table, the application realizes accurate monitoring of the light leakage of the polishing machine table, avoids the false detection or missed detection caused by the macroscopic detection method, and improves the monitoring efficiency and the monitoring accuracy.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for monitoring light leakage in a grinding machine. Background Technology

[0002] In existing offline monitoring of metal CMP (Chemical Mechanical Polishing) equipment, a semiconductor structure consisting of stacked wafer dies and TEOS film layers is used to monitor for abnormalities in the wafer and the equipment. However, this monitoring method lacks monitoring of the light source of the HCLU pressure sensor within the equipment. If the HCLU pressure sensor has a light leakage fault, it can easily cause abnormal connections in local metal layers, affecting product yield. Therefore, monitoring the light source of the HCLU pressure sensor within the equipment is crucial. Currently, some R&D personnel use macroscopic detection methods such as infrared and visual inspection to detect light leakage faults within the equipment. However, these macroscopic detection methods cannot accurately reflect light leakage phenomena within the equipment and are prone to false positives or false negatives. Summary of the Invention

[0003] This application provides a method for monitoring light leakage in a grinding machine, which can solve the problem that light leakage faults of the HCLU pressure sensor of the grinding machine cannot be accurately monitored.

[0004] This application provides a method for monitoring light leakage in a grinding machine, including:

[0005] Provide a substrate;

[0006] A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and an insulating dielectric layer covering the first conductive plug and the second conductive plug are formed; wherein a plurality of trenches are formed in the insulating dielectric layer, and the trenches expose the top ends of the first conductive plug and the second conductive plug respectively;

[0007] A metal layer is formed, which fills the trench;

[0008] The metal layer on the surface of the semiconductor structure is ground using a grinding machine.

[0009] Defect maps of the semiconductor structure surface are obtained using a wafer inspection machine; and

[0010] The defect map is used to monitor whether there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure. If the defect map indicates that there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure, then the light leakage fault of the HCLU pressure sensor in the polishing machine is diagnosed.

[0011] Optionally, in the method for monitoring light leakage in a grinding machine, the semiconductor structure includes: a memory region and a peripheral logic region adjacent to the memory region, wherein,

[0012] A first well region is formed in the substrate at the bottom of the storage area, and a second well region is formed in the substrate of the peripheral logic area;

[0013] A first doped region is formed in the first well region, and a second doped region is formed in the second well region;

[0014] The first conductive plug is located in the storage area and connected to the first heavily doped region; the second conductive plug is located in the peripheral logic area and connected to the second heavily doped region.

[0015] Optionally, in the method for monitoring light leakage in the grinding machine, the conductivity type of the doped ions in the first heavily doped region is N-type, and the conductivity type of the doped ions in the second heavily doped region is P-type.

[0016] Optionally, in the method for monitoring light leakage in the grinding machine, the conductivity type of the doped ions in the first well region is P-type, and the conductivity type of the doped ions in the second well region is N-type.

[0017] Optionally, in the method for monitoring light leakage in the grinding machine, the first heavily doped region, the first well region, the second well region, and the second heavily doped region constitute the PN junction conduction loop.

[0018] Optionally, in the method for monitoring light leakage in the grinding machine, the metal layer is formed in the trench by an electrochemical plating process.

[0019] Optionally, in the method for monitoring light leakage in the grinding machine, both the first conductive plug and the second conductive plug are made of tungsten.

[0020] Optionally, in the method for monitoring light leakage in the grinding machine, the metal layer is made of copper.

[0021] The technical solution of this application has at least the following advantages:

[0022] This application forms a semiconductor structure on a substrate, wherein a PN junction conduction loop, a first conductive plug, and a second conductive plug are formed in the semiconductor structure; a metal layer is formed at the top of the first conductive plug and the second conductive plug; this application utilizes the semiconductor structure with the PN junction conduction loop to perform CMP process in a polishing machine. Because the PN junction in the semiconductor structure generates electron flow under photon irradiation, metal atoms in the metal layer are transferred from the P-doped end to the N-doped end, realizing the conduction of the PN junction loop, thereby causing metal precipitation defects to be generated on the surface of the metal layer connected to the N-doped end and pit defects to be generated on the surface of the metal layer connected to the P-doped end. Therefore, if there is light leakage abnormality in the polishing machine, the presence of light leakage fault in the HCLU pressure sensor in the polishing machine can be diagnosed by the metal precipitation defects and / or pit defects reflected in the defect diagram, thereby realizing accurate monitoring of light leakage in the polishing machine, avoiding false detection or missed detection caused by macroscopic detection methods, and improving monitoring efficiency and accuracy. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart of a method for monitoring light leakage in a grinding machine according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a semiconductor structure used to monitor whether there is light leakage abnormality in a grinding machine according to an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention, in which the surface of a semiconductor structure is polished to generate metal precipitation defects and pit defects.

[0027] The reference numerals in the attached figures are explained as follows:

[0028] 10-Substrate, 11-Shallow trench isolation structure, 12-First well region, 13-Second well region;

[0029] 21-First heavily doped region, 22-Lightly doped drain region one, 23-Self-aligned doped region one, 24-Self-aligned doped region two;

[0030] 31 - Second heavily doped region, 32 - Lightly doped drain region two;

[0031] 40 - Insulating dielectric layer, 51 - First conductive plug, 52 - Second conductive plug, 53 - Third conductive plug, 60 - Metal layer. Detailed Implementation

[0032] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0035] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0036] This application provides a method for monitoring light leakage in a grinding machine, referring to... Figure 1 , Figure 1 This is a flowchart of a method for monitoring light leakage in a grinding machine according to an embodiment of the present invention. The method for monitoring light leakage in a grinding machine includes:

[0037] Step S1: Provide a substrate;

[0038] Step S2: A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and an insulating dielectric layer covering the first conductive plug and the second conductive plug are formed in the semiconductor structure; wherein a plurality of trenches are formed in the insulating dielectric layer, and the trenches expose the top ends of the first conductive plug and the second conductive plug respectively;

[0039] Step S3: Form a metal layer that fills the trench;

[0040] Step S4: Grind the metal layer on the surface of the semiconductor structure using a grinding machine;

[0041] Step S5: Obtain a defect map of the semiconductor structure surface using a wafer inspection machine; and

[0042] Step S6: Monitor the surface of the semiconductor structure for metal precipitation defects and / or pit defects using the defect map. If the defect map indicates that the surface of the semiconductor structure has metal precipitation defects and / or pit defects, then diagnose that the HCLU pressure sensor in the polishing machine has a light leakage fault.

[0043] For details, please refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure used to monitor whether there is light leakage in a grinding machine according to an embodiment of the present invention. The following describes the method for monitoring light leakage in a grinding machine provided in this application, taking a portion of the semiconductor structure as an example.

[0044] First, perform step S1: provide a substrate 10.

[0045] The substrate 10 can be one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 10 can also be gallium arsenide, gallium silicon compound, etc. The substrate 100 can also have a silicon-on-insulator or silicon-on-epitaxy layer structure. The substrate 10 can also be other semiconductor materials, which will not be listed here.

[0046] Then, step S2 is performed: a semiconductor structure is formed on the substrate.

[0047] Specifically, the semiconductor structure includes: a flash memory structure (flash memory cell) of the memory region and a peripheral logic circuit structure of the peripheral logic region adjacent to the memory region. A first well region 12 is formed in the substrate 10 at the bottom of the memory region, and a second well region 13 is formed in the substrate of the peripheral logic region. Different well regions are isolated by a shallow trench isolation structure 11. Furthermore, a first heavily doped region 21 is formed in the first well region 12, and multiple lightly doped drain regions 22, self-aligned doped regions 23 and 24, and other ion implantation regions of various types are also formed in the first well region 12.

[0048] Furthermore, a second heavily doped region 31 is formed in the second well region 13, and multiple lightly doped drain regions 32 and other types of ion implantation regions are also formed in the second well region 13.

[0049] In this embodiment, the conductivity type of the doped ions in self-aligned doping region 23 is P-type; the conductivity type of the doped ions in self-aligned doping region 24 is N-type; and the conductivity type of the doped ions in lightly doped drain region 32 is P-type. For example, lightly doped drain region 32 is HV PLDD (high voltage P-type lightly doped drain region).

[0050] It is worth noting that this application does not limit the specific type of flash memory structure, nor does it limit the type and number of ion implantation regions (ion doping regions) in each flash memory structure. The storage area and peripheral logic area in the examples of this application can be any existing flash memory structure and peripheral logic circuit structure in 55NOR flash memory devices.

[0051] Preferably, a PN junction conduction loop is formed in the semiconductor structure.

[0052] Specifically, in this embodiment, the conductivity type of the doped ions in the first well region 12 is P-type, and the conductivity type of the doped ions in the first heavily doped region 21 is N-type; from Figure 2 As can be seen, the first well region 12 is an HVPW (high-voltage P-type well region), and the first heavily doped region 21 is an N+ doped region; the conductivity type of the doped ions in the second well region 13 is N-type, and the conductivity type of the doped ions in the second heavily doped region 31 is P-type; from Figure 2 As can be seen, the second well region 13 is an HVNW (high voltage N-type well region), and the second heavily doped region 31 is a P+ doped region.

[0053] The first heavily doped region 21, the first well region 12, the second well region 13, and the second heavily doped region 31 constitute a PN junction conduction loop. Alternatively, it can be understood that the first heavily doped region 21, the first well region 12, the second well region 13, the lightly doped drain region 32, and the second heavily doped region 31 constitute a PN junction conduction loop.

[0054] Furthermore, a first conductive plug 51 connected to one end of the PN junction conduction loop is formed in the storage area; a second conductive plug 52 connected to the other end of the PN junction conduction loop is formed in the peripheral logic area. The first conductive plug 51 is connected to the first heavily doped region 21 to bring the first heavily doped region 21 out to the device surface; the second conductive plug 52 is connected to the second heavily doped region 31 to bring the second heavily doped region 31 out to the device surface.

[0055] In this embodiment, both the first conductive plug 51 and the second conductive plug 52 are located within the insulating dielectric layer 40. Furthermore, a third conductive plug 53 is also formed within the insulating dielectric layer 40 of the peripheral logic region. The first conductive plug 51 and the second conductive plug 52 are covered by the insulating dielectric layer 40. (Reference) Figure 2 Grooves are formed in the insulating dielectric layer 40 at the top of the first conductive plug 51, the top of the second conductive plug 52, and the top of the third conductive plug 53. The grooves are then used to form metal layers that are electrically connected to the top of the first conductive plug 51, the second conductive plug 52, and the third conductive plug 53, respectively, and further lead the first heavily doped region 21 and the second heavily doped region 31 to the device surface.

[0056] Preferably, the insulating dielectric layer 40 may comprise multiple stacked dielectric layers of different materials.

[0057] In this embodiment, the insulating dielectric layer 40 may include, from bottom to top, a silicon oxide layer and a TEOS layer.

[0058] In this embodiment, the top end 51 of the first conductive plug, the second conductive plug 52, and the third conductive plug 53 are all made of tungsten.

[0059] Next, step S3 is performed: forming a metal layer 60, which fills the trench.

[0060] Preferably, the metal layer 60 is formed in the trench by an electrochemical plating process.

[0061] In this embodiment, the metal layer 60 is made of copper.

[0062] Further, step S4 is performed: the metal layer 60 on the surface of the semiconductor structure is subjected to CMP (chemical mechanical polishing) using a polishing machine to planarize the surface of the semiconductor structure.

[0063] In this embodiment, a grinding machine is used to grind... Figure 2The metal layer 60 on the surface of the semiconductor structure shown is subjected to CMP.

[0064] Next, step S5 is performed: a defect map of the semiconductor structure surface is obtained using a wafer inspection machine.

[0065] In this embodiment, a defect map of the semiconductor structure surface can be obtained using a CYDFIK* type KLA machine.

[0066] Finally, step S6 is executed: the defect map is used to monitor whether there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure. If the defect map indicates that there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure, then the light leakage fault of the HCLU (Head Clean Load / Unload, grinding head cleaning and silicon wafer loading and unloading unit) pressure sensor in the grinding machine is diagnosed; otherwise, if the defect map indicates that there are no metal precipitation defects and pit defects on the surface of the semiconductor structure, then the light leakage fault of the HCLU (Head Clean Load / Unload, grinding head cleaning and silicon wafer loading and unloading unit) pressure sensor in the grinding machine is diagnosed.

[0067] refer to Figure 3 , Figure 3 This is a schematic diagram of a semiconductor device that grinds the surface of a semiconductor structure to generate metal precipitation defects and pit defects according to an embodiment of the present invention. If the HCLU pressure sensor in the grinding machine has light leakage, the PN junction in the semiconductor structure generates electron flow under photon irradiation, causing copper atoms in the metal layer 60 to transfer from the P-doped end to the N-doped end, realizing the conduction of the PN junction circuit. This results in metal precipitation defects on the surface of the metal layer connected to the first (N+) doped region 21 and pit defects on the surface of the metal layer connected to the second (P+) doped region 31. After obtaining the defect map of the semiconductor structure surface using a wafer inspection machine, the light leakage fault of the HCLU pressure sensor in the grinding machine can be diagnosed by the metal precipitation defects and pit defects or at least one of the defects reflected in the defect map. This achieves accurate monitoring of light leakage in the grinding machine and avoids false detection or missed detection caused by macroscopic detection methods. Compared with traditional macroscopic detection methods such as infrared and visual inspection, the method for monitoring light leakage in the grinding machine provided in this application embodiment improves monitoring efficiency and accuracy.

[0068] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for monitoring light leakage in a grinding machine, characterized in that, include: Provide a substrate; A semiconductor structure is formed on the substrate, wherein a PN junction conduction loop, a first conductive plug connected to one end of the PN junction conduction loop, a second conductive plug connected to the other end of the PN junction conduction loop, and an insulating dielectric layer covering the first conductive plug and the second conductive plug are formed; wherein a plurality of trenches are formed in the insulating dielectric layer, and the trenches expose the top ends of the first conductive plug and the second conductive plug respectively; A metal layer is formed, which fills the trench; The metal layer on the surface of the semiconductor structure is ground using a grinding machine. Defect maps of the semiconductor structure surface are obtained using a wafer inspection machine; and The defect map is used to monitor whether there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure. If the defect map indicates that there are metal precipitation defects and / or pit defects on the surface of the semiconductor structure, then the light leakage fault of the HCLU pressure sensor in the polishing machine is diagnosed.

2. The method for monitoring light leakage in a grinding machine according to claim 1, characterized in that, The semiconductor structure includes: a memory region and a peripheral logic region adjacent to the memory region, wherein, A first well region is formed in the substrate at the bottom of the storage area, and a second well region is formed in the substrate of the peripheral logic area; A first doped region is formed in the first well region, and a second doped region is formed in the second well region; The first conductive plug is located in the storage area and connected to the first heavily doped region; the second conductive plug is located in the peripheral logic area and connected to the second heavily doped region.

3. The method for monitoring light leakage in a grinding machine according to claim 2, characterized in that, The conductivity type of the doped ions in the first heavily doped region is N-type, and the conductivity type of the doped ions in the second heavily doped region is P-type.

4. The method for monitoring light leakage in a grinding machine according to claim 3, characterized in that, The conductivity type of the doped ions in the first well region is P-type, and the conductivity type of the doped ions in the second well region is N-type.

5. The method for monitoring light leakage in a grinding machine according to claim 4, characterized in that, The first heavily doped region, the first well region, the second well region, and the second heavily doped region constitute the PN junction conduction loop.

6. The method for monitoring light leakage in a grinding machine according to claim 1, characterized in that, The metal layer is formed in the trench by an electrochemical plating process.

7. The method for monitoring light leakage in a grinding machine according to claim 1, characterized in that, Both the first conductive plug and the second conductive plug are made of tungsten.

8. The method for monitoring light leakage in a grinding machine according to claim 1, characterized in that, The metal layer is made of copper.

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