Chip io electrical characteristic automatic testing device, method and computer storage medium

Abstract

The application provides a chip IO electrical characteristic automatic testing device, method and computer storage medium, and relates to the technical field of chip testing.The chip IO electrical characteristic automatic testing device comprises a control module, a high-level output testing module, a low-level output testing module, an input testing module and a first multiplexing switch; the control module is connected with the high-level output testing module, the low-level output testing module, the input testing module and the first multiplexing switch through a plurality of different pins; and the high-level output testing module, the low-level output testing module and the input testing module are connected with different pins of the first multiplexing switch. The chip IO electrical characteristic automatic testing device can realize automatic testing of chip VIL, VIH, VIL and VOH.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to an automated testing device, method, and computer storage medium for chip I / O electrical characteristics. Background Technology

[0002] During the chip design process, the chip contains numerous IO (input / output) pin interfaces. Completing verification quickly and with high coverage helps to discover defects in a timely manner and improve chip quality.

[0003] Existing testing and verification techniques for VIL (input low level) and VIH (input high level) of chips involve inputting a threshold voltage to the chip's I / O pins and then reading the I / O level status to determine if it matches the input voltage. If it matches, the chip meets electrical specifications. Testing techniques for VOL (output low level) and VOH (output high level) are as follows: Figure 1 As shown, when testing and verifying VOL, MOS (field-effect transistor)_2 is turned off and MOS_1 is turned on. VDD injects a set current into the chip's IO through MOS_1. If the IO level is less than VOL, the electrical specifications are met. When testing and verifying VOH, MOS_1 is turned off and MOS_2 is turned on. The set current is drawn through MOS_2. If the IO level is greater than VOH, the electrical specifications are met.

[0004] However, the existing technical solutions mentioned above require manual measurement when testing IO pins, and can only test each pin individually, making it impossible to automate the entire testing process. Summary of the Invention

[0005] The main objective of this application is to provide an automated testing device, method, and computer storage medium for the electrical characteristics of chip I / O pins, aiming to solve the technical problem in the prior art that automated centralized testing is not possible when testing I / O pins.

[0006] To achieve the above objectives, this application provides an automated testing device for the electrical characteristics of chip I / O, the automated testing device for the electrical characteristics of chip I / O includes: a control module, a high-level output testing module, a low-level output testing module, an input testing module, and a first multiplexer switch;

[0007] The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins.

[0008] The control module is used to output DAC analog signals to the high-level output test module, the low-level output test module and the input test module, acquire the ADC voltage values ​​output by the high-level output test module and the low-level output test module, and output a channel selection signal to the first multiplexer switch;

[0009] The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer. The high-level output test module is used to test the electrical characteristics of the high-level output pin of the chip under test. The low-level output test module is used to test the electrical characteristics of the low-level output pin of the chip under test. The input test module is used to test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test. The first multiplexer is used to switch test modes.

[0010] Optionally, the automated testing device for the electrical characteristics of chip I / O further includes: a second multiplexer switch;

[0011] The second multiplexer is connected to the first multiplexer and the control module respectively, and is connected to multiple I / O pins of the chip under test through multiple different pins;

[0012] The second multiplexer is used to select the target I / O pin of the chip under test according to the channel selection signal output by the control module.

[0013] Optionally, the high-level output test module includes: a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first field-effect transistor;

[0014] The first terminal of the first amplifier is connected to the first terminal of the second resistor, the second terminal of the first amplifier is grounded, the third terminal of the first amplifier is connected to the control module, the fourth terminal of the first amplifier is connected to the first terminal of the fourth resistor, and the fifth and sixth terminals of the first amplifier are both connected to the first power supply. The DAC analog signal output by the control module is input to the high-level output test module from the third terminal of the first amplifier.

[0015] The second end of the second resistor is connected to the gate of the first field-effect transistor. The second end of the fourth resistor and the first end of the first resistor are both connected to the source of the first field-effect transistor. The second end of the first resistor is grounded. The drain of the first field-effect transistor is connected to the first end of the third resistor. The second end of the third resistor is connected to the first multiplexer. The first end and the second end of the third resistor are respectively connected to different pins of the control module.

[0016] Optionally, the high-level output test module further includes: a high-level output ADC_N terminal and a high-level output ADC_P terminal;

[0017] The first end of the third resistor is also connected to the high-level output ADC_N terminal, and the second end of the third resistor is also connected to the high-level output ADC_P terminal. The high-level output ADC_N terminal and the high-level output ADC_P terminal are respectively connected to different pins of the control module. The control module samples the voltage across the third resistor through the high-level output ADC_N terminal and the high-level output ADC_P terminal.

[0018] Optionally, the low-level output test module includes: a second amplifier, a third amplifier, a second field-effect transistor, a third field-effect transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor;

[0019] The first terminal of the second amplifier is connected to the first terminal of the sixth resistor, the second terminal of the second amplifier is connected to the first terminal of the seventh resistor, the third terminal of the second amplifier is connected to the control module, the fourth terminal of the second amplifier is grounded, and the fifth terminal of the second amplifier is connected to the first power supply. The DAC analog signal output by the control module is input to the low-level output test module through the third terminal of the second amplifier.

[0020] The first terminal of the fifth resistor is grounded, the second terminals of the fifth resistor and the seventh resistor are connected to the source of the second field-effect transistor, the second terminal of the sixth resistor is connected to the gate of the second field-effect transistor, and the first terminal of the eighth resistor is connected to the second power supply.

[0021] The first terminal of the third amplifier is connected to the first terminal of the tenth resistor, the second terminal of the third amplifier is connected to the first terminal of the ninth resistor, the third terminal of the third amplifier is connected to the drain of the second field-effect transistor and the second terminal of the eighth resistor, and the fourth and fifth terminals of the third amplifier are left floating.

[0022] The second end of the ninth resistor is connected to the first end of the eleventh resistor and the source of the third field-effect transistor, the second end of the tenth resistor is connected to the gate of the third field-effect transistor, and the second end of the eleventh resistor is connected to the second power supply.

[0023] Optionally, the low-level output test module further includes: a low-level output ADC_N terminal and a low-level output ADC_P terminal;

[0024] The first end of the eleventh resistor is also connected to the low-level output ADC_N terminal, and the low-level output ADC_N terminal is connected to the control module. The control module samples the voltage at the first end of the seventh resistor through the low-level output ADC_N terminal.

[0025] The gate of the third field-effect transistor is connected to the low-level output ADC_P terminal, and the low-level output ADC_P terminal is connected to the control module. The control module samples the voltage of the gate of the third field-effect transistor through the low-level output ADC_P terminal.

[0026] The gate of the third field-effect transistor is also connected to the first multiplexer.

[0027] Optionally, the first multiplexer switch includes: a first channel terminal, a second channel terminal, and a third channel terminal;

[0028] The first channel terminal is connected to the gate of the third field-effect transistor, the second channel terminal is connected to the second terminal of the third resistor, and the third channel terminal is connected to the IO status terminal of the input test module.

[0029] The first multiplexer is used to select the test mode of the chip under test according to the channel selection signal output by the control module.

[0030] In addition, to achieve the above objectives, this application also provides an automated testing method for the electrical characteristics of chip I / O, which is applied to an automated testing device for the electrical characteristics of chip I / O. The automated testing device for the electrical characteristics of chip I / O includes: a control module, a high-level output testing module, a low-level output testing module, an input testing module, and a first multiplexer switch.

[0031] The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins.

[0032] The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer;

[0033] The automated testing method for the electrical characteristics of chip I / O includes:

[0034] The control module controls the first multiplexer to select the target test mode of the chip under test, and determines the target module corresponding to the target test mode among the high-level output test module, the low-level output test module, and the input test module.

[0035] The control module outputs a test signal to the target module and collects the result signal generated by the target module in response to the test signal.

[0036] Based on the result signal and the preset parameters of the chip under test, the test result of the chip under test in the target test mode is output.

[0037] Optionally, the automated testing device for the electrical characteristics of chip I / O further includes: a second multiplexer switch;

[0038] The second multiplexer is connected to the first multiplexer and the control module respectively, and is connected to multiple I / O pins of the chip under test through multiple different pins;

[0039] Before the step of controlling the first multiplexer switch via the control module to select the target test mode for the chip under test, the method further includes:

[0040] The control module controls the second multiplexer to select the I / O pin to be tested of the chip under test.

[0041] This application also provides a computer storage medium storing an automated test program for the electrical characteristics of chip I / O, which, when executed by a processor, implements the steps of the automated test method for the electrical characteristics of chip I / O as described above.

[0042] This application provides an automated testing device, method, and computer storage medium for the electrical characteristics of chip I / O. The automated testing device for the electrical characteristics of chip I / O includes: a control module, a high-level output test module, a low-level output test module, an input test module, and a first multiplexer switch. The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins. The control module is used to output DAC analog signals to the high-level output test module, the low-level output test module, and the input test module, and to acquire signals from the high-level output test module and the input test module. The low-level output test module outputs the ADC voltage value, and outputs a channel selection signal to the first multiplexer; the high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer; the high-level output test module is used to test the electrical characteristics of the high-level output pin of the chip under test; the low-level output test module is used to test the electrical characteristics of the low-level output pin of the chip under test; the input test module is used to test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test; and the first multiplexer is used to switch test modes.

[0043] Compared to existing technologies that manually test the VIL, VIH, VIL, and VOH of chips individually, the automated testing device for the electrical characteristics of chip I / O in this application includes: a control module, a high-level output test module, a low-level output test module, an input test module, and a first multiplexer switch. The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins. The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer switch. The control module is used to output DAC analog signals to the high-level output test module, the low-level output test module, and the input test module; to acquire the ADC voltage values ​​output by the high-level output test module and the low-level output test module; and to output a channel selection signal to the first multiplexer switch. The first multiplexer switch selects to turn on different pins based on the received channel selection signal, thereby enabling testing of VIL, VIH, VIL, and VOH. Different items can be selected for testing in L and VOH. When the first multiplexer is connected to the high-level output test module, it can test the electrical characteristics of the high-level output pin of the chip under test. When the first multiplexer is connected to the low-level output test module, it can test the electrical characteristics of the low-level output pin of the chip under test. When the first multiplexer is connected to the input test module, it can test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test.

[0044] Thus, based on the aforementioned device that selects the conducting test modules by controlling the first multiplexer switch through the control module, compared with the traditional method of manually testing the VIL, VOH, VIL and VOH of the chip separately, the automated test device for the electrical characteristics of the chip I / O of this application integrates the test modules for the VIL, VOH, VIL and VOH of the chip into one device, and can automatically control the switching of the test modules through the control module, thereby realizing the automated testing of the VIL, VOH and VOH of the chip. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0047] Figure 1 This is a circuit diagram of a VOL and VOH testing scheme;

[0048] Figure 2 This is a schematic diagram of the system scheme of the automated testing device for the electrical characteristics of chip I / O involved in the embodiments of this application;

[0049] Figure 3 This is a schematic diagram of the high-level output test module of the automated testing device for the electrical characteristics of chip I / O involved in the embodiments of this application;

[0050] Figure 4 This is a schematic diagram of the low-level output test module of the automated testing device for the electrical characteristics of chip I / O involved in the embodiments of this application;

[0051] Figure 5 This is a schematic diagram of the structure of an automated testing device for the chip I / O electrical characteristics of the device hardware operating environment involved in the embodiments of this application;

[0052] Figure 6 This is a schematic diagram illustrating the implementation process of an embodiment of the automated testing method for the electrical characteristics of chip I / O in this application.

[0053] Explanation of icon numbers:

[0054]

[0055] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0056] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0057] It should be noted that during the chip design process, the chip contains a large number of IO (input / output) pins. Completing verification quickly and with high coverage is beneficial for timely detection of defects and improving chip quality.

[0058] Existing testing and verification techniques for VIL (input low) and VOH (input high) of chips involve inputting a threshold voltage to the chip's I / O pins and then reading the I / O level status to determine if it matches the input voltage. If it matches, the chip meets electrical specifications. Testing techniques for VOL (output low) and VOH (output high) are as follows: Figure 1As shown, when testing and verifying VOL, MOS (field-effect transistor)_2 is turned off and MOS_1 is turned on. VDD injects a set current into the chip's IO through MOS_1. If the IO level is less than VOL, the electrical specifications are met. When testing and verifying VOH, MOS_1 is turned off and MOS_2 is turned on. The set current is drawn through MOS_2. If the IO level is greater than VOH, the electrical specifications are met.

[0059] However, the existing technical solutions mentioned above adjust the load current through a resistor when testing VOL / VOH. The resistor has accuracy errors and cannot set an accurate load current value. After applying the load current, the existing solutions require manual measurement of the VOL / VOH voltage using a testing instrument to see if it meets the requirements. They cannot be automatically detected and can only be tested individually for each pin. The entire testing process cannot be automated.

[0060] To address the aforementioned problems, this application provides an automated testing device, method, and computer storage medium for the electrical characteristics of chip I / O. The automated testing device for the electrical characteristics of chip I / O includes: a control module, a high-level output test module, a low-level output test module, an input test module, and a first multiplexer. The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer via multiple different pins. The control module is used to output DAC analog signals to the high-level output test module, the low-level output test module, and the input test module, and to acquire the high-level output test signal. The module and the low-level output test module output ADC voltage values, and output channel selection signals to the first multiplexer switch; the high-level output test module, the low-level output test module and the input test module are respectively connected to different pins of the first multiplexer switch; the high-level output test module is used to test the electrical characteristics of the high-level output pin of the chip under test; the low-level output test module is used to test the electrical characteristics of the low-level output pin of the chip under test; the input test module is used to test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test; the first multiplexer switch is used to switch test modes.

[0061] Compared to existing technologies that manually test the VIL, VIH, and VOH of chips individually, the automated testing device for the electrical characteristics of chip I / O in this application includes: a control module, a high-level output test module, a low-level output test module, an input test module, and a first multiplexer switch; the control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch through multiple different pins, and the high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer switch; the control module is used to output DA to the high-level output test module, the low-level output test module, and the input test module. The system collects analog signals, acquires the ADC voltage values ​​output by the high-level output test module and the low-level output test module, and outputs a channel selection signal to the first multiplexer. The first multiplexer selects to turn on different pins based on the received channel selection signal, thereby enabling different items to be tested among VIL, VIH, VIL, and VOH. When the first multiplexer is connected to the high-level output test module, it can test the electrical characteristics of the high-level output pin of the chip under test. When the first multiplexer is connected to the low-level output test module, it can test the electrical characteristics of the low-level output pin of the chip under test. When the first multiplexer is connected to the input test module, it can test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test.

[0062] Thus, based on the aforementioned device that selects the conducting test modules by controlling the first multiplexer switch through the control module, compared with the traditional method of manually testing the VIL, VIH, VIL, and VOH of the chip individually, the automated test device for the chip IO electrical characteristics of this application integrates the test modules for the chip's VIL, VIH, VIL, and VOH into one device, and can automatically control the selection of the test modules through the control module, thereby realizing automated testing of the chip's VIL, VIH, VIL, and VOH.

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0064] This application provides an automated testing device for the electrical characteristics of chip I / O. In the first embodiment of this automated testing device for the electrical characteristics of chip I / O, please refer to... Figure 2 , Figure 2This is a schematic diagram of the system scheme of the automated testing device for the electrical characteristics of chip I / O involved in the embodiments of this application. The automated testing device for the electrical characteristics of chip I / O includes: a controller module, a high-level output test module (VOH TESTModule), a low-level output test module (VOL TESTModule), an input test module (VIH&VIL TESTModule), and a first multiplexer switch (MUX1).

[0065] The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins.

[0066] The control module is used to output DAC analog signals to the high-level output test module, the low-level output test module and the input test module, acquire the ADC voltage values ​​output by the high-level output test module and the low-level output test module, and output a channel selection signal to the first multiplexer switch;

[0067] The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer. The high-level output test module is used to test the electrical characteristics of the high-level output pin of the chip under test. The low-level output test module is used to test the electrical characteristics of the low-level output pin of the chip under test. The input test module is used to test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test. The first multiplexer is used to switch test modes.

[0068] It should be noted that in this embodiment, the control module can use controllers such as MCU (Micro Controller Unit), CPLD (complex programmable logic device), and FPGA (Field-Programmable Gate Array). The chip under test can be any chip capable of outputting high and low levels, and each chip and component in the device can be replaced by a device with the same performance and function. In this embodiment and the following embodiments, only one feasible device structure is proposed, and no limitation is made on the model and function of the components and chips.

[0069] In this embodiment, as Figure 2As shown, the first DAC (Digital to Analog Converter) signal pin DAC_OUT_CH1 of the control module is connected to the low-level output DAC signal pin VOL_DAC_OUT of the low-level output test module. The first ADC signal pin ADC_CH1 of the control module is connected to the low-level output ADC_P terminal VOL_ADC_P of the low-level output test module. The second ADC signal pin ADC_CH2 of the control module is connected to the low-level output ADC_N terminal VOL_ADC_N of the low-level output test module. The control module outputs a DAC signal for testing the electrical characteristics of VOL to the low-level output test module through the connection between the first DAC signal pin and the low-level output DAC signal pin. It also acquires the ADC signal generated by the low-level output test module in response to the DAC signal through the first and second ADC signal pins. Based on each ADC signal and the IO parameters of the chip under test, the test result is determined to be either FAIL (failure) or PASS (pass).

[0070] Similarly, the second DAC signal pin DAC_OUT_CH2 of the control module is connected to the high-level output DAC signal pin VOH_DAC_OUT of the high-level output test module, the third ADC signal pin ADC_CH3 of the control module is connected to the high-level output ADC_P terminal VOH_ADC_P of the high-level output test module, and the fourth ADC signal pin ADC_CH4 of the control module is connected to the high-level output ADC_N terminal VOH_ADC_N of the high-level output test module. The control module outputs a DAC signal to the high-level output test module to test the electrical characteristics of VOH through the connection between the second DAC signal pin and the high-level output DAC signal pin, and acquires the ADC signal generated by the high-level output test module in response to the DAC signal through the third and fourth ADC signal pins. The test result is determined as FAIL or PASS based on each ADC signal and the IO parameters of the chip under test.

[0071] The third DAC signal pin DAC_OUT_CH3 of the control module is connected to the input DAC signal pin VIH_VIL_DAC_OUT of the input test module. Based on this connection, the control module outputs a DAC signal to the input test module to test the electrical characteristics of VIH and VIL. The control module compares the output DAC signal with the IO read by the chip to determine whether the test result is FAIL or PASS. For example, if the voltage output by the control module is low, and the IO read by the chip is low, it is judged as PASS; if it is high, it is judged as FAIL.

[0072] The first channel terminal IO_CH1 of the first multiplexer is connected to the low-level output IO pin VOL_DUT_IO of the low-level output test module. Based on this connection, the first multiplexer connects the low-level output test module to the IO pin of the chip under test, thereby enabling the chip under test to output a low level to the low-level output test module.

[0073] Similarly, the second channel terminal IO_CH2 of the first multiplexer is connected to the high-level output IO pin VOH_DUT_IO of the high-level output test module. Based on this connection, the first multiplexer connects the high-level output test module to the IO pin of the chip under test, thereby enabling the chip under test to output a high level to the high-level output test module.

[0074] The third channel terminal IO_CH3 of the first multiplexer is connected to the IO status terminal VIH_VIL_DUT_IO of the input test module. Based on this connection, the first multiplexer connects the input test module to the IO pin of the chip under test, thereby enabling the input test module to output a level signal corresponding to the DAC signal to the chip under test.

[0075] The first selection signal pin MUX1_SEL of the control module is connected to the selection signal pin SEL1 of the first multiplexer. Based on this connection, the control module outputs a selection signal to the first multiplexer, enabling the first multiplexer to select the corresponding pin to conduct according to the target test module selected by the technician at the first channel, second channel and third channel, thereby achieving the effect of controlling the target test mode.

[0076] Furthermore, in one feasible embodiment, the automated testing device for the electrical characteristics of the chip I / O further includes: a second multiplexer MUX2;

[0077] The second multiplexer is connected to the first multiplexer and the control module respectively, and is connected to multiple I / O pins of the chip under test through multiple different pins;

[0078] The second multiplexer is used to select the target I / O pin of the chip under test based on the channel selection signal output by the control module.

[0079] In this embodiment, as Figure 2As shown, the IO input pin IO_IN2 of the second multiplexer is connected to the IO input pin IO_IN1 of the first multiplexer. The second multiplexer also includes x+1 IO connection pins (i.e., GPIO2_0, GPIO2_1 to GPIO2_x). Each IO connection pin is connected to each IO pin under test (i.e., GPIO1_0, GPIO1_1 to GPIO1_x) of the chip under test. The selection signal pin SEL2 of the second multiplexer is connected to the second selection signal pin MUX2_SEL of the control module. Based on this connection, the control module outputs a selection signal to the second multiplexer, enabling the second multiplexer to select from the IO connection pins according to the IO pin under test selected by the technician, thereby achieving the effect of automatically traversing all IO pins of the chip under test for testing.

[0080] Furthermore, in one feasible embodiment, the high-level output test module includes: a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first field-effect transistor;

[0081] The first terminal of the first amplifier is connected to the first terminal of the second resistor, the second terminal of the first amplifier is grounded, the third terminal of the first amplifier is connected to the control module, the fourth terminal of the first amplifier is connected to the first terminal of the fourth resistor, and the fifth and sixth terminals of the first amplifier are both connected to the first power supply. The DAC analog signal output by the control module is input to the high-level output test module from the third terminal of the first amplifier.

[0082] The second end of the second resistor is connected to the gate of the first field-effect transistor. The second end of the fourth resistor and the first end of the first resistor are both connected to the source of the first field-effect transistor. The second end of the first resistor is grounded. The drain of the first field-effect transistor is connected to the first end of the third resistor. The second end of the third resistor is connected to the first multiplexer. The first end and the second end of the third resistor are respectively connected to different pins of the control module.

[0083] The high-level output test module also includes: a high-level output ADC_N terminal and a high-level output ADC_P terminal;

[0084] The first end of the third resistor is also connected to the high-level output ADC_N terminal, and the second end of the third resistor is also connected to the high-level output ADC_P terminal. The high-level output ADC_N terminal and the high-level output ADC_P terminal are respectively connected to different pins of the control module. The control module samples the voltage across the third resistor through the high-level output ADC_N terminal and the high-level output ADC_P terminal.

[0085] In this embodiment, as Figure 3 As shown, the control module outputs a DAC voltage signal to the high-level output test module via VOH_DAC_OUT. Utilizing the virtual short and virtual open principle of the operational amplifier, the voltage across the high-precision first resistor R1 is equal to the DAC voltage, and the current flowing through R1 is I. R1 =VOH_DAC_OUT / R1. The current flowing through the fourth resistor R4 is 0A, therefore the current through the first field-effect transistor Q1 is equal to I. R1 In other words, when the chip's I / O pin outputs a high level, I is pulled from VOH_DUT_IO. R1 The load current can be adjusted by regulating the voltage of the DAC, avoiding the technical problem in existing solutions where the load current is adjusted by a resistor when testing VOL / VOH, which has accuracy errors and cannot set an accurate load current value.

[0086] Then, the control module samples the voltage at VOH_ADC_P to obtain the IO load I. R1 After the high-level voltage value, the control module can automatically give a PASS or FAI result by comparing VOH_ADC_P with the VOH electrical characteristics of the chip under test itself, which solves the technical problem that manual comparison is still required in the existing technology to give the test result.

[0087] When the chip's I / O is pulled by I R1 When the current is applied, a voltage drop will be formed across the third resistor R3. The control module uses the ADC to sample the voltage at VOH_ADC_P and VOH_ADC_N. The actual load current value can be obtained by using the formula (VOH_ADC_P-VOH_ADC_N) / R3. By comparing the set and actual load current, the control module can dynamically adjust the actual load to the preset value, avoiding errors caused by circuit losses.

[0088] Furthermore, in one feasible embodiment, the low-level output test module includes: a second amplifier, a third amplifier, a second field-effect transistor, a third field-effect transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor;

[0089] The first terminal of the second amplifier is connected to the first terminal of the sixth resistor, the second terminal of the second amplifier is connected to the first terminal of the seventh resistor, the third terminal of the second amplifier is connected to the control module, the fourth terminal of the second amplifier is grounded, and the fifth terminal of the second amplifier is connected to the first power supply. The DAC analog signal output by the control module is input to the low-level output test module through the third terminal of the second amplifier.

[0090] The first terminal of the fifth resistor is grounded, the second terminals of the fifth resistor and the seventh resistor are connected to the source of the second field-effect transistor, the second terminal of the sixth resistor is connected to the gate of the second field-effect transistor, and the first terminal of the eighth resistor is connected to the second power supply.

[0091] The first terminal of the third amplifier is connected to the first terminal of the tenth resistor, the second terminal of the third amplifier is connected to the first terminal of the ninth resistor, the third terminal of the third amplifier is connected to the drain of the second field-effect transistor and the second terminal of the eighth resistor, and the fourth and fifth terminals of the third amplifier are left floating.

[0092] The second end of the ninth resistor is connected to the first end of the eleventh resistor and the source of the third field-effect transistor, the second end of the tenth resistor is connected to the gate of the third field-effect transistor, and the second end of the eleventh resistor is connected to the second power supply.

[0093] The low-level output test module also includes: a low-level output ADC_N terminal and a low-level output ADC_P terminal;

[0094] The first end of the eleventh resistor is also connected to the low-level output ADC_N terminal, and the low-level output ADC_N terminal is connected to the control module. The control module samples the voltage at the first end of the seventh resistor through the low-level output ADC_N terminal.

[0095] The gate of the third field-effect transistor is connected to the low-level output ADC_P terminal, and the low-level output ADC_P terminal is connected to the control module. The control module samples the voltage of the gate of the third field-effect transistor through the low-level output ADC_P terminal.

[0096] The gate of the third field-effect transistor is also connected to the first multiplexer.

[0097] In this embodiment, as Figure 4 As shown, the low-level output test module works similarly to the high-level output test module described above. The control module outputs a DAC voltage signal to the low-level output test module via VOL_DAC_OUT and injects a current value I. in =VOL_DAC_OUT*R8 / (R5*R11), after the set current is injected into the chip IO, the control module samples the voltage of VOL_ADC_P through the ADC, and gives the result of PASS or FAI L by comparing it with the electrical characteristics of the chip's VOL.

[0098] When the chip's I / O is filled with I inWhen the current is applied, a voltage drop will form across the eleventh resistor R11. The control module uses an ADC to sample the voltage at VOL_ADC_N, and the actual applied current value can be obtained using the formula (1.2-VOL_ADC_N) / R11. By comparing the set value with the actual applied current, the control module can dynamically adjust the actual load to the preset value, avoiding errors caused by circuit losses.

[0099] Furthermore, in one feasible embodiment, the first multiplexer switch includes: a first channel terminal, a second channel terminal, and a third channel terminal;

[0100] The first channel terminal is connected to the gate of the third field-effect transistor, the second channel terminal is connected to the second terminal of the third resistor, and the third channel terminal is connected to the IO status terminal of the input test module.

[0101] The first multiplexer is used to select the test mode of the chip under test according to the channel selection signal output by the control module.

[0102] In this embodiment, as Figure 2 As shown, the first channel terminal IO_CH1 of the first multiplexer is connected to the low-level output IO pin VOL_DUT_IO of the low-level output test module, and is connected to the gate of the third field-effect transistor through the low-level output IO pin. Based on this connection, the first multiplexer connects the low-level output test module to the IO pin of the chip under test, thereby enabling the chip under test to output a low level to the low-level output test module.

[0103] Similarly, the second channel terminal IO_CH2 of the first multiplexer is connected to the high-level output IO pin VOH_DUT_IO of the high-level output test module, and is connected to the second terminal of the third resistor through the high-level output IO pin. Based on this connection, the first multiplexer connects the high-level output test module to the IO pin of the chip under test, thereby enabling the chip under test to output a high level to the high-level output test module.

[0104] The third channel terminal IO_CH3 of the first multiplexer is connected to the IO status terminal VI H_VI L_DUT_IO of the input test module. Based on this connection, the first multiplexer connects the input test module to the IO pin of the chip under test, thereby enabling the input test module to output a level signal corresponding to the DAC signal to the chip under test.

[0105] The first selection signal pin MUX1_SEL of the control module is connected to the selection signal pin SEL1 of the first multiplexer. Based on this connection, the control module outputs a selection signal to the first multiplexer, enabling the first multiplexer to select the corresponding pin to conduct according to the target test module selected by the technician at the first, second, and third channel terminals, thereby achieving the effect of controlling the target test mode.

[0106] Specifically, when multiple I / O pins of a chip need to be tested, all I / O pins of the chip under test are connected to the pins of a second multiplexer. The control module then outputs a second selection signal to the second multiplexer to control its selection. After the second multiplexer is selected, the control module outputs a first selection signal to the first multiplexer to control the test items for the I / O pins. Once the control module has selected the I / O pins, they can be connected to the designated test module through the two multiplexers. The control module then outputs a specified test signal to the designated test module. The control module collects the signal output by the test module in response to the test signal and compares the collected signal with the parameters of the chip's I / O pins. Based on the comparison result, the test result is output as FAIL or PASS. After testing the chip's I / O pins, the control module can complete the traversal test of all I / O pins of the chip under test by switching the selected pins of the first and second multiplexers.

[0107] Thus, based on the aforementioned device that selects the conducting test modules by controlling the first multiplexer through the control module, compared to the traditional method of manually testing the VIL, VIL, VIL, and VOH of a chip individually, the automated test device for the electrical characteristics of chip I / O in this application integrates the test modules for VIL, VIL, VIL, and VOH of the chip into one device, and can automatically control the selection of test modules through the control module, thereby realizing automated testing of the chip's VIL, VIL, VIL, and VOH. In addition, it can automatically traverse all I / O interfaces of the chip through the second multiplexer.

[0108] For further details, please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of an automated testing device for the chip I / O electrical characteristics of the device hardware operating environment involved in the embodiments of this application.

[0109] like Figure 5As shown, the automated testing equipment for the electrical characteristics of the chip's I / O may include: a processor 1001, such as a CPU, a memory 1005, and a communication bus 1002. The communication bus 1002 is used to establish communication between the processor 1001 and the memory 1005. The memory 1005 may be a high-speed RAM or a stable, non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0110] Optionally, the automated testing equipment for the electrical characteristics of the chip's I / O may also include a user interface 1003, a network interface 1004, a camera, RF (Radio Frequency) circuitry, sensors, audio circuitry, a WiFi module, etc. The user interface may include a display screen and an input submodule such as a keyboard. Optionally, the user interface may also include standard wired or wireless interfaces. The network interface may optionally include standard wired or wireless interfaces (such as a WiFi interface).

[0111] Those skilled in the art will understand that Figure 5 The structure of the automated test equipment for chip I / O electrical characteristics shown in the figure does not constitute a limitation on the automated test equipment for chip I / O electrical characteristics. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0112] like Figure 5 As shown, the memory 1005, serving as a computer storage medium, may include an operating system, a network communication module, and an automated testing program for the electrical characteristics of chip I / O. The operating system is a program that manages and controls the hardware and software resources of the automated testing equipment for chip I / O, supporting the execution of the automated testing program for chip I / O and other software and / or programs. The network communication module is used to enable communication between the various components within the memory 1005, as well as communication with other hardware and software in the automated testing device for chip I / O.

[0113] exist Figure 5 In the automated testing equipment for the electrical characteristics of chip I / O shown, the processor 1001 is used to execute the automated testing program for the electrical characteristics of chip I / O stored in the memory 1005, and to perform the following operations:

[0114] The control module controls the first multiplexer to select the target test mode of the chip under test, and determines the target module corresponding to the target test mode among the high-level output test module, the low-level output test module, and the input test module.

[0115] The control module outputs a test signal to the target module and collects the result signal generated by the target module in response to the test signal.

[0116] Based on the result signal and the preset parameters of the chip under test, the test result of the chip under test in the target test mode is output.

[0117] Furthermore, the processor 1001 can call the automated test program for the electrical characteristics of the chip I / O stored in the memory 1005, and also perform the following operations:

[0118] The control module controls the second multiplexer to select the I / O pin to be tested of the chip under test.

[0119] This application provides an automated testing method for the electrical characteristics of chip I / O. In the first embodiment of this automated testing method for the electrical characteristics of chip I / O, please refer to... Figure 6 The automated testing method for the electrical characteristics of chip I / O is applied to an automated testing device for the electrical characteristics of chip I / O, which includes: a control module, a high-level output testing module, a low-level output testing module, an input testing module, and a first multiplexer switch.

[0120] The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins.

[0121] The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer;

[0122] The automated testing method for the electrical characteristics of chip I / O includes:

[0123] Step S10: The control module controls the first multiplexer to select the target test mode of the chip under test, and determines the target module corresponding to the target test mode among the high-level output test module, the low-level output test module and the input test module.

[0124] In this embodiment, the control module outputs a control signal to the first multiplexer according to the needs of the technician, thereby controlling the first multiplexer to select the target test mode of the chip under test, and selecting the target module required by the tester from the high-level output test module, the low-level output test module, and the input test module.

[0125] Step S20: The control module outputs a test signal to the target module and collects the result signal generated by the target module in response to the test signal;

[0126] In this embodiment, after confirming the target test module, the control module outputs a test signal corresponding to the target test module to the target test module. The target module responds to the test signal and generates a result signal, which is then collected by the control module.

[0127] Step S30: Based on the result signal and the preset parameters of the chip under test, output the test result of the chip under test in the target test mode.

[0128] In this embodiment, after the control module acquires the result signal, it compares the result signal with the preset parameters of the chip IO to obtain the test result in the target test mode and outputs the test result.

[0129] Furthermore, in one feasible embodiment, the automated testing device for the electrical characteristics of the chip I / O also includes: a second multiplexer switch;

[0130] The second multiplexer is connected to the first multiplexer and the control module respectively, and is connected to multiple I / O pins of the chip under test through multiple different pins;

[0131] Before step S10 above, where the control module controls the first multiplexer switch to select the target test mode for the chip under test, the method further includes:

[0132] Step A10: The control module controls the second multiplexer to select the I / O pin of the chip under test.

[0133] In this embodiment, before the control module outputs a control signal to the first multiplexer according to the needs of the technician, the control module first outputs a control signal to the second multiplexer according to the needs of the technician to select the IO pins of the chip under test that need to be tested, so as to automatically perform traversal testing on all IO pins of the chip under test.

[0134] Specifically, when multiple I / O pins of a chip need to be tested, all I / O pins of the chip under test are connected to the pins of a second multiplexer. The control module then outputs a second selection signal to the second multiplexer to control its selection. After the second multiplexer is selected, the control module outputs a first selection signal to the first multiplexer to control the test items for the I / O pins. Once the control module has selected the I / O pins, they can be connected to the designated test module through the two multiplexers. The control module then outputs a specified test signal to the designated test module. The control module collects the signal output by the test module in response to the test signal and compares the collected signal with the parameters of the chip's I / O pins. Based on the comparison result, the test result is output as FAIL or PASS. After testing the chip's I / O pins, the control module can complete the traversal test of all I / O pins of the chip under test by switching the selected pins of the first and second multiplexers.

[0135] Thus, based on the aforementioned device that selects the conducting test modules by controlling the first multiplexer through the control module, compared to the traditional method of manually testing the VIL, VIL, VIL, and VOH of a chip individually, the automated test device for the electrical characteristics of chip I / O in this application integrates the test modules for VIL, VIL, VIL, and VOH of the chip into one device, and can automatically control the selection of test modules through the control module, thereby realizing automated testing of the chip's VIL, VIL, VIL, and VOH. In addition, it can automatically traverse all I / O interfaces of the chip through the second multiplexer.

[0136] In addition, this application also proposes a computer storage medium storing a program for automated testing of the electrical characteristics of chip I / O. When the automated testing program for the electrical characteristics of chip I / O is executed by a processor, it implements the steps of the automated testing method for the electrical characteristics of chip I / O described above.

[0137] The specific embodiments of the computer storage medium in this application are basically the same as the embodiments of the above-mentioned automated testing method for the electrical characteristics of chip I / O, and will not be described in detail here.

[0138] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0139] Furthermore, in the embodiments of this application, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this invention according to the specific circumstances.

[0140] In this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0141] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0142] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a computer storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0143] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An automated testing device for the electrical characteristics of chip I / O, characterized in that, The automated testing device for the electrical characteristics of chip I / O includes: a control module, a high-level output testing module, a low-level output testing module, an input testing module, and a first multiplexer switch; The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins. The control module is used to output DAC analog signals to the high-level output test module, the low-level output test module and the input test module, acquire the ADC voltage values ​​output by the high-level output test module and the low-level output test module, and output a channel selection signal to the first multiplexer switch; The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer. The high-level output test module is used to test the electrical characteristics of the high-level output pin of the chip under test. The low-level output test module is used to test the electrical characteristics of the low-level output pin of the chip under test. The input test module is used to test the electrical characteristics of the high-level input pin and the low-level input pin of the chip under test. The first multiplexer is used to switch test modes. The automated testing device for the electrical characteristics of chip I / O also includes: a second multiplexer switch; The second multiplexer is connected to the first multiplexer and the control module respectively, and is connected to multiple I / O pins of the chip under test through multiple different pins; The second multiplexer is used to select the target I / O pin of the chip under test according to the channel selection signal output by the control module. The high-level output test module includes: a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a first field-effect transistor; The first terminal of the first amplifier is connected to the first terminal of the second resistor, the second terminal of the first amplifier is grounded, the third terminal of the first amplifier is connected to the control module, the fourth terminal of the first amplifier is connected to the first terminal of the fourth resistor, and the fifth and sixth terminals of the first amplifier are both connected to the first power supply. The DAC analog signal output by the control module is input to the high-level output test module from the third terminal of the first amplifier. The second end of the second resistor is connected to the gate of the first field-effect transistor. The second end of the fourth resistor and the first end of the first resistor are both connected to the source of the first field-effect transistor. The second end of the first resistor is grounded. The drain of the first field-effect transistor is connected to the first end of the third resistor. The second end of the third resistor is connected to the first multiplexer. The first end and the second end of the third resistor are respectively connected to different pins of the control module. The high-level output test module also includes: a high-level output ADC_N terminal and a high-level output ADC_P terminal; The first end of the third resistor is also connected to the high-level output ADC_N terminal, and the second end of the third resistor is also connected to the high-level output ADC_P terminal. The high-level output ADC_N terminal and the high-level output ADC_P terminal are respectively connected to different pins of the control module. The control module samples the voltage across the third resistor through the high-level output ADC_N terminal and the high-level output ADC_P terminal.

2. The automated testing device for the electrical characteristics of chip I / O according to claim 1, characterized in that, The low-level output test module includes: a second amplifier, a third amplifier, a second field-effect transistor, a third field-effect transistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor; The first terminal of the second amplifier is connected to the first terminal of the sixth resistor, the second terminal of the second amplifier is connected to the first terminal of the seventh resistor, the third terminal of the second amplifier is connected to the control module, the fourth terminal of the second amplifier is grounded, and the fifth terminal of the second amplifier is connected to the first power supply. The DAC analog signal output by the control module is input to the low-level output test module through the third terminal of the second amplifier. The first terminal of the fifth resistor is grounded, the second terminals of the fifth resistor and the seventh resistor are connected to the source of the second field-effect transistor, the second terminal of the sixth resistor is connected to the gate of the second field-effect transistor, and the first terminal of the eighth resistor is connected to the second power supply. The first terminal of the third amplifier is connected to the first terminal of the tenth resistor, the second terminal of the third amplifier is connected to the first terminal of the ninth resistor, the third terminal of the third amplifier is connected to the drain of the second field-effect transistor and the second terminal of the eighth resistor, and the fourth and fifth terminals of the third amplifier are left floating. The second end of the ninth resistor is connected to the first end of the eleventh resistor and the source of the third field-effect transistor, the second end of the tenth resistor is connected to the gate of the third field-effect transistor, and the second end of the eleventh resistor is connected to the second power supply.

3. The automated testing device for the electrical characteristics of chip I / O according to claim 2, characterized in that, The low-level output test module also includes: a low-level output ADC_N terminal and a low-level output ADC_P terminal; The first end of the eleventh resistor is also connected to the low-level output ADC_N terminal, and the low-level output ADC_N terminal is connected to the control module. The control module samples the voltage at the first end of the seventh resistor through the low-level output ADC_N terminal. The gate of the third field-effect transistor is connected to the low-level output ADC_P terminal, and the low-level output ADC_P terminal is connected to the control module. The control module samples the voltage of the gate of the third field-effect transistor through the low-level output ADC_P terminal. The gate of the third field-effect transistor is also connected to the first multiplexer.

4. The automated testing device for the electrical characteristics of chip I / O according to any one of claims 1 to 3, characterized in that, The first multiplexer includes: a first channel terminal, a second channel terminal, and a third channel terminal; The first channel terminal is connected to the gate of the third field-effect transistor, the second channel terminal is connected to the second terminal of the third resistor, and the third channel terminal is connected to the IO status terminal of the input test module. The first multiplexer is used to select the test mode of the chip under test according to the channel selection signal output by the control module.

5. An automated testing method for the electrical characteristics of chip I / O using the automated testing device for chip I / O electrical characteristics as described in claim 1, characterized in that, The automated testing method for the electrical characteristics of chip I / O is applied to an automated testing device for the electrical characteristics of chip I / O, which includes: a control module, a high-level output testing module, a low-level output testing module, an input testing module, and a first multiplexer switch; The control module is connected to the high-level output test module, the low-level output test module, the input test module, and the first multiplexer switch via multiple different pins. The high-level output test module, the low-level output test module, and the input test module are respectively connected to different pins of the first multiplexer; The automated testing method for the electrical characteristics of chip I / O includes: The control module controls the first multiplexer to select the target test mode of the chip under test, and determines the target module corresponding to the target test mode among the high-level output test module, the low-level output test module, and the input test module. The control module outputs a test signal to the target module and collects the result signal generated by the target module in response to the test signal. Based on the result signal and the preset parameters of the chip under test, the test result of the chip under test in the target test mode is output.

6. The automated testing method for the electrical characteristics of chip I / O according to claim 5, characterized in that, The automated testing device for the electrical characteristics of chip I / O also includes: a second multiplexer switch; The second multiplexer is connected to the first multiplexer and the control module respectively, and is connected to multiple I / O pins of the chip under test through multiple different pins; Before the step of controlling the first multiplexer switch via the control module to select the target test mode for the chip under test, the method further includes: The control module controls the second multiplexer to select the I / O pin to be tested of the chip under test.

7. A computer storage medium, characterized in that, The computer storage medium stores an automated test program for the electrical characteristics of chip I / O, which, when executed by a processor, implements the steps of the automated test method for the electrical characteristics of chip I / O as described in any one of claims 5 to 6.

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