Array substrate and in-cell touch display panel

Abstract

The application discloses an array substrate and an in-cell touch display panel. The array substrate is provided with a plurality of scanning lines, a plurality of data lines, a plurality of touch wires, a plurality of pixel units and a plurality of common electrode blocks. The extension direction of the touch wires is parallel to the extension direction of the data lines. Each common electrode block is electrically connected with the corresponding touch wire. A touch partition gap is arranged between two adjacent common electrode blocks. The touch partition gap includes a longitudinal partition gap arranged between two adjacent columns of pixel units and a horizontal partition gap arranged between two adjacent rows of pixel units. The touch wire adjacent to the longitudinal partition gap is located between the two adjacent columns of pixel units and corresponds to the longitudinal partition gap. The data line adjacent to the longitudinal partition gap penetrates a column of pixel units electrically connected therewith. The application ensures that the storage capacitances in all the pixel units are the same, and the coupling capacitances between all the data lines and the common electrode blocks are the same, thereby improving the display quality.

Description

Technical Field

[0001] This invention relates to the field of touch display technology, and in particular to an array substrate and an embedded touch display panel. Background Technology

[0002] Liquid crystal display (LCD) panels have advantages such as high image quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, making them dominant in the flat panel display field. With the rapid development of display technology, touch display panels have become widely accepted and used, such as in smartphones and tablets. Touch display panels utilize embedded touch technology to combine the touch panel and LCD panel into one unit, embedding the touch panel functionality within the LCD panel, thus enabling the LCD panel to simultaneously display and sense touch input.

[0003] Depending on how the touch sensing layer is positioned within the display panel, touch display panels are categorized into add-on, in-cell, and on-cell structures. In-cell touchscreens integrate touch functionality into the display screen, effectively reducing the overall thickness of the display and simplifying the manufacturing process, resulting in thinner, lighter products with lower production costs, making them widely popular.

[0004] Currently, for in-cell touchscreens, the touchscreen structure is typically mounted directly on the array substrate. This mainly involves reusing some structural components used for transmitting display signals as touch electrodes within the array substrate, such as... Figure 1 and Figure 2As shown, a common approach is to reuse the common electrode block 21 as a touch electrode, and then control the common electrode block 21 to transmit common signals and touch signals through the touch trace 3. Since the common electrode block 21 is reused as a touch electrode, it needs to be divided into multiple blocks by the touch partition gap 211. To avoid the formation of coupling capacitance between the touch trace 3 and the data line 2, the spacing between the touch trace 3 and the data line 2 needs to be relatively wide. In the prior art, the touch trace 3 is usually located in the opening area of ​​the pixel unit SP. Simultaneously, to avoid differences in the coupling capacitance between different data lines 2 and the common electrode block 21, the vertical touch partition gap 211 is usually located at the touch trace 3. Therefore, the vertical touch partition gap 211 also needs to be located in the opening area of ​​the pixel unit SP. However, this will cause the storage capacitance (Cst) at the touch partition gap 211 to differ from the storage capacitance (Cst) of other areas, affecting the display quality. In existing technologies, the area of ​​the pixel electrode 22 at the touch partition gap 211 is typically increased. For example, the pixel electrode 22 at the touch partition gap 211 may have a compensation electrode 221 to compensate for the difference in storage capacitance between the touch partition gap 211 and other areas. Although this can compensate for the difference in storage capacitance, the design of the pixel electrode 22 is more difficult, and the electric field strength of the pixel electrode 22 at the touch partition gap 211 is relatively weak, resulting in poor display quality, which will be detected in the display quality assessment. Summary of the Invention

[0005] In order to overcome the shortcomings and deficiencies of the existing technology, the purpose of this invention is to provide an array substrate and an embedded touch display panel to solve the problem that the display quality of the touch partition gap is relatively poor due to the partition position of the common electrode block and the position of the touch wiring in the existing technology.

[0006] The objective of this invention is achieved through the following technical solution: This invention provides an array substrate, which has multiple scan lines, multiple data lines, multiple touch traces, multiple pixel units, and multiple common electrode blocks. The scan lines and data lines are mutually insulated and intersect each other. The extension directions of the touch traces are parallel to the extension directions of the data lines. Each common electrode block is electrically connected to a corresponding touch trace. A touch partition gap is provided between two adjacent common electrode blocks. The touch partition gap includes a vertical partition gap between two adjacent columns of pixel units and a horizontal partition gap between two adjacent rows of pixel units. The touch traces adjacent to the vertical partition gaps are located between two adjacent columns of pixel units and correspond to the vertical partition gaps. The data lines adjacent to the vertical partition gaps pass through a column of pixel units that are electrically connected to them.

[0007] Furthermore, all the touch traces are disposed between two adjacent columns of pixel units, and all the data lines pass through a column of pixel units that are electrically connected to it.

[0008] Furthermore, except for the vertical partition gaps, the touch traces pass through a corresponding column of pixel units, and the data lines except for the vertical partition gaps are all located between two adjacent columns of pixel units.

[0009] Furthermore, the touch traces adjacent to the longitudinal partition gaps are aligned with the center line of the longitudinal partition gaps.

[0010] Furthermore, the data line passing through a column of pixel units is aligned with the center line of the column of pixel units.

[0011] Furthermore, the touch traces and the data lines are located on the same layer; or the touch traces and the data lines are located on different layers.

[0012] Furthermore, the touch trace located at the longitudinal partition gap is an invalid touch trace, and the invalid touch trace is insulated from the common electrode block.

[0013] Furthermore, the array substrate has a pixel electrode in each pixel unit, and the pixel electrode is electrically connected to the corresponding scan line and data line through a thin-film transistor.

[0014] This application also provides an embedded touch display panel, including an array substrate, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate, wherein the array substrate is the array substrate described above.

[0015] Furthermore, the color filter substrate is provided with a plurality of color resist layers corresponding to the pixel unit and a black matrix that separates the plurality of color resist layers from each other, and the black matrix is ​​provided between any two adjacent columns and two rows of the pixel units.

[0016] The beneficial effects of this invention are as follows: by placing the touch traces at the adjacent vertical partition gaps between two adjacent columns of pixel units and corresponding to the vertical partition gaps, and by having the data lines at the adjacent vertical partition gaps pass through a column of pixel units electrically connected to them, it is ensured that the storage capacitance in all pixel units is the same, and the coupling capacitance between all data lines and the common electrode block is also the same, thus avoiding differences in storage capacitance or coupling capacitance between the common electrode block partitions and other areas, thereby improving the display quality. Attached Figure Description

[0017] Figure 1This is a schematic diagram of the planar structure of an array substrate in the prior art; Figure 2 This is a schematic diagram of the structure of an embedded touch display device in the prior art; Figure 3 This is a simulation diagram of the transmittance of an embedded touch display device in the prior art; Figure 4 This is a schematic diagram of the planar structure of the touch electrode in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the planar structure of the array substrate in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the embedded touch display device in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the transmittance simulation of the embedded touch display device in Embodiment 1 of the present invention; Figure 8 This is a simulation comparison chart of the transmittance of the existing technology and the embedded touch display device in Embodiment 1 of the present invention; Figure 9 This is a schematic diagram of the planar structure of the array substrate in Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of the planar structure of the touch electrode in Embodiment 3 of the present invention. Detailed Implementation

[0018] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate and embedded touch display panel proposed according to the present invention: [Example 1] Figure 4 This is a schematic diagram of the planar structure of the touch electrode in Embodiment 1 of the present invention. Figure 5 This is a schematic diagram of the planar structure of the array substrate in Embodiment 1 of the present invention. Figure 6 This is a schematic diagram of the embedded touch display device in Embodiment 1 of the present invention. Figures 4 to 6As shown in Embodiment 1 of the present invention, an array substrate 20 is provided, comprising multiple scan lines 1, multiple data lines 2, multiple touch traces 3, multiple pixel units SP, and multiple common electrode blocks 21. The multiple scan lines 1 and multiple data lines 2 are mutually insulated and intersect each other. Each pixel unit SP of the array substrate 20 is provided with a pixel electrode 22, which is electrically connected to the corresponding scan line 1 and data line 2 via a thin-film transistor 4. The thin-film transistor 4 includes a gate, an active layer, a drain, and a source. The gate is located on the same layer as the scan line 1 and is electrically connected. The gate is isolated from the active layer by an insulating layer. The source is electrically connected to the data line 2, and the drain is electrically connected to the pixel electrode 22 through a contact hole.

[0019] The extension direction of the touch trace 3 is parallel to the extension direction of the data line 2. Each common electrode block 21 is electrically connected to the corresponding touch trace 3. Common signals and touch signals are applied to the common electrode block 21 through the touch trace 3, so that the common electrode block 21 is multiplexed as a touch electrode.

[0020] A touch partition gap 211 is provided between two adjacent common electrode blocks 21. The touch partition gap 211 includes a vertical partition gap 211a between two adjacent columns of pixel units SP and a horizontal partition gap 211b between two adjacent rows of pixel units SP. That is, the vertical partition gap 211a is parallel to the data line 2, and the horizontal partition gap 211b is parallel to the scan line 1. The touch trace 3 adjacent to the vertical partition gap 211a is located between two adjacent columns of pixel units SP and corresponds to the vertical partition gap 211a. The data line 2 adjacent to the vertical partition gap 211a passes through a column of pixel units SP that are electrically connected to it, thereby ensuring that the storage capacitance in all pixel units SP is the same, and the coupling capacitance between all data lines 2 and the common electrode block 21 is also the same. This avoids differences in storage capacitance or coupling capacitance between the partition of the common electrode block 21 and other areas, thereby improving the display quality.

[0021] In this embodiment, the number of touch traces 3 and common electrode blocks 21 is the same, and each touch trace 3 is connected to one common electrode block 21. That is, the touch trace 3 located at the longitudinal partition gap 211a is also connected to the common electrode block 21, thereby minimizing the number of touch traces 3. Although the coupling capacitance between the touch trace 3 and the common electrode block 21 at the longitudinal partition gap 211a differs from that between the touch trace 3 and the common electrode block 21 in other areas, touch signals are applied to the touch traces 3. Touch signals do not have as many levels as grayscale signals. Therefore, the difference in coupling capacitance between the touch trace 3 and the common electrode block 21 has virtually no impact on the touch function.

[0022] like Figure 5As shown, in this embodiment, all touch traces 3 are disposed between two adjacent columns of pixel units SP, and all data lines 2 pass through a column of pixel units SP that are electrically connected to them, thereby making the circuit arrangement on the array substrate 20 more regular and facilitating the design of the mask.

[0023] Furthermore, the touch trace 3 adjacent to the vertical partition gap 211a is aligned with the center line of the vertical partition gap 211a. The data line 2 passing through a column of pixel units SP is aligned with the center line of the column of pixel units SP. This maximizes the distance between the data line 2 and the touch trace 3, avoiding the formation of coupling capacitance between the touch trace 3 and the data line 2.

[0024] In this embodiment, the touch trace 3 and the data line 2 are located on the same layer, which reduces one process step and simplifies the manufacturing process. Of course, the touch trace 3 and the data line 2 can also be located on different layers, that is, the touch trace 3 and the data line 2 can each be made of a single metal layer. The manufacturing process is slightly more complex, but this implementation method is not excluded.

[0025] In this embodiment, the common electrode block 21 and the pixel electrode 22 are located on different layers and are insulated from each other. The common electrode block 21 may be located above or below the pixel electrode 22. Figure 6 The diagram shows the common electrode block 21 located below the pixel electrode 22. Preferably, the common electrode block 21 is a planar electrode with its entire surface, and the pixel electrode 22 is a slit electrode with multiple electrode strips in each pixel unit SP to form a fringe field switching (FFS) mode.

[0026] This application also provides an embedded touch display panel, including an array substrate 20, a color filter substrate 10 disposed opposite to the array substrate 20, and a liquid crystal layer 30 located between the array substrate 20 and the color filter substrate 10. The array substrate 20 is the array substrate 20 described above.

[0027] The liquid crystal layer 30 uses positive liquid crystal molecules, that is, liquid crystal molecules with positive dielectric anisotropy, such as... Figure 6 As shown, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color filter substrate 10 and the array substrate 20, and the alignment direction of the positive liquid crystal molecules on the side closer to the color filter substrate 10 is parallel to that of the positive liquid crystal molecules on the side closer to the array substrate 20.

[0028] The color filter substrate 10 has multiple color resist layers 12 corresponding to pixel units SP on the side facing the liquid crystal layer 30, and black matrices (BM) 11 that space the multiple color resist layers 12 apart from each other. A black matrix 11 is provided between any two adjacent columns and two adjacent rows of pixel units SP. The color resist layers 12 include red (R), green (G), and blue (B) color resist materials, which respectively form red, green, and blue pixel units. The black matrices 11 are located between the red, green, and blue pixel units, so that adjacent pixel units are spaced apart by the black matrices 11.

[0029] Furthermore, an upper polarizer 41 is provided on the side of the color filter substrate 10 away from the liquid crystal layer 30, and a lower polarizer 42 is provided on the side of the array substrate 20 away from the liquid crystal layer 30. The light transmission axis of the upper polarizer 41 and the light transmission axis of the lower polarizer 42 are perpendicular to each other.

[0030] The color filter substrate 10 and the array substrate 20 can be made of transparent substrates such as glass, acrylic, and polycarbonate. The common electrode block 21 and the pixel electrode 22 can be made of transparent electrodes such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0031] Figure 3 This is a simulation diagram of the transmittance of an embedded touch display device in the prior art. Figure 7 This is a schematic diagram simulating the transmittance of the embedded touch display device in Embodiment 1 of the present invention. Figure 8 This is a simulation comparison chart of the transmittance of the existing technology and the embedded touch display device in Embodiment 1 of this invention. For example... Figure 3 , Figure 7 and Figure 8 As shown, Figure 3 Point A corresponds to the transmittance at touch trace 3 within pixel unit SP. Figure 7 Point B in the middle corresponds to the transmittance at data line 2 within pixel unit SP; Figure 8 The dashed curve represents the variation of transmittance with driving voltage in the prior art. Figure 8 The solid curve represents the change in transmittance with driving voltage in this application. Since the prior art touch partition gap 211 lacks a common electrode block 21 and is located within the pixel unit SP, the electric field strength of the pixel electrode 22 at the touch partition gap 211 is weak, and the liquid crystal molecules are essentially not deflected. Therefore, the edge of the touch trace 3 within the pixel unit SP ( Figure 3 The transmittance at point A in the middle will decrease. However, in this application, the touch partition gap 211 is located between two adjacent columns of pixel units SP. Therefore, the electric field between the pixel electrode 22 and the common electrode block 21 within each pixel unit SP is relatively uniform, and the liquid crystal molecules will all deflect. Therefore, the edge of the data line 2 within the pixel unit SP (… Figure 7 The penetration rate at point B is basically unaffected. Figure 8 It can be seen that the penetration rate in this application is improved compared to the prior art.

[0032] [Example 2] Figure 9 This is a schematic diagram of the planar structure of the array substrate in Embodiment 2 of the present invention. Figure 9 As shown, the array substrate and embedded touch display panel provided in Embodiment 2 of the present invention are similar to those in Embodiment 1. Figures 4 to 8 The array substrate and embedded touch display panel in this embodiment are basically the same, except that in this embodiment: Except for the adjacent vertical partition gap 211a, the touch traces 3 pass through a corresponding column of pixel units SP. Except for the adjacent vertical partition gap 211a, the data lines 2 are all arranged between two adjacent columns of pixel units SP. That is, except for the adjacent vertical partition gap 211a, the touch traces 3 and data lines 2 adopt the existing arrangement. Although this will reduce the regularity of the circuit on the array substrate 20, it does not exclude this implementation method.

[0033] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0034] [Example 3] Figure 10 This is a schematic diagram of the planar structure of the touch electrode in Embodiment 3 of the present invention. Figure 10 As shown, the array substrate and embedded touch display panel provided in Embodiment 3 of the present invention are similar to those in Embodiment 1. Figures 4 to 8 Example 2 Figure 9 The array substrate and embedded touch display panel in this embodiment are basically the same, except that in this embodiment: The number of touch traces 3 is greater than the number of common electrode blocks 21. The touch traces 3 located at the vertical partition gap 211a are invalid touch traces. Invalid touch traces are insulated from common electrode blocks 21, meaning that touch traces 3 located at the vertical partition gap 211a are not connected to common electrode blocks 21. Because the coupling capacitance between touch traces 3 at the vertical partition gap 211a and common electrode blocks 21 differs from the coupling capacitance between touch traces 3 and common electrode blocks 21 in other areas, setting the touch traces 3 at the vertical partition gap 211a as invalid touch traces can completely avoid affecting the touch function.

[0035] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1 and Embodiment 2, and will not be repeated here.

[0036] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, The array substrate (20) is provided with multiple scan lines (1), multiple data lines (2), multiple touch traces (3), multiple pixel units (SP), and multiple common electrode blocks (21). The multiple scan lines (1) and multiple data lines (2) are mutually insulated and intersect each other. The extension direction of the touch traces (3) is parallel to the extension direction of the data lines (2). Each common electrode block (21) is electrically connected to the corresponding touch trace (3). A touch partition gap (211) is provided between two adjacent common electrode blocks (21). The control partition gap (211) includes a vertical partition gap (211a) disposed between two adjacent columns of the pixel units (SP) and a horizontal partition gap (211b) disposed between two adjacent rows of the pixel units (SP). The touch trace (3) adjacent to the vertical partition gap (211a) is located between two adjacent columns of the pixel units (SP) and corresponds to the vertical partition gap (211a). The data line (2) adjacent to the vertical partition gap (211a) passes through a column of the pixel units (SP) electrically connected to it. All the touch traces (3) are disposed between two adjacent columns of pixel units (SP), and all the data lines (2) pass through a column of pixel units (SP) that are electrically connected to them. The touch traces (3) located at the vertical partition gap (211a) are invalid touch traces, and the invalid touch traces are insulated from the common electrode block (21).

2. The array substrate according to claim 1, characterized in that, The touch trace (3) located near the longitudinal partition gap (211a) is aligned with the center line of the longitudinal partition gap (211a).

3. The array substrate according to claim 1, characterized in that, The data line (2) passing through a column of pixel units (SP) is aligned with the center line of the column of pixel units (SP).

4. The array substrate according to claim 1, characterized in that, The touch trace (3) and the data line (2) are located on the same layer; or the touch trace (3) and the data line (2) are located on different layers.

5. The array substrate according to any one of claims 1-4, characterized in that, The array substrate (20) has a pixel electrode (22) in each pixel unit (SP), and the pixel electrode (22) is electrically connected to the corresponding scan line (1) and data line (2) through a thin film transistor (4).

6. An embedded touch display panel, comprising an array substrate (20), a color filter substrate (10) disposed opposite to the array substrate (20), and a liquid crystal layer (30) located between the array substrate (20) and the color filter substrate (10), characterized in that, The array substrate (20) is the array substrate (20) as described in any one of claims 1-5.

7. The embedded touch display panel according to claim 6, characterized in that, The color filter substrate (10) is provided with a plurality of color resist layers (12) corresponding to the pixel unit (SP) and a black matrix (11) that separates the plurality of color resist layers (12) from each other. The black matrix (11) is provided between any two adjacent columns and two rows of the pixel units (SP).

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