A multi-node data scheduling system based on FPGA

Abstract

With the development of digital phased array radar, the powerful radar function and the complex algorithm processing flow of signal processing lead to the increase of the hardware scale of signal processing system. Usually, multiple processing nodes are designed to process signals to meet the signal processing demand of large data volume and high data rate. The application provides a multi-node data scheduling system based on FPGA, which can schedule N (N>0) signal processing nodes (with expansion capability) at the same time, schedule data sent to each node according to the load of each processing node, and achieve the purpose of maximizing the processing capacity of each node. Users can change the configuration file to expand the signal processing nodes and adjust the busy threshold of each node, which can meet the scheduling demand of FPGA data processing in the field of radar signal processing.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing, specifically relating to a multi-node data scheduling system based on FPGA. Background Technology

[0002] With the development of digital phased array radar, radar products are becoming increasingly powerful, and radar signal processing algorithms are becoming increasingly complex. These trends have become inevitable in radar development. The increased power of radar functions and the complexity of signal processing algorithms have led to a larger hardware scale for signal processing systems. Typically, multiple processing nodes are designed to handle signal processing in order to meet the system's requirements for large data volumes and high data rates.

[0003] To fully utilize the processing capabilities of multiple signal processing nodes, the signal processing system must possess efficient data scheduling capabilities, enabling it to send data to the appropriate nodes for processing based on their real-time load. In the FPGA implementation of multi-node signal processing, a general-purpose multi-node data scheduling system needs to be designed. This system should be able to send data to nodes with lighter loads based on their load status, thereby maximizing the utilization of the computational and time resources of each processing node and improving the overall processing capacity of the signal processing system. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a multi-node data scheduling system based on FPGA. This system can simultaneously schedule N (N>0) signal processing nodes (with scalability), scheduling data sent to each node according to their load status to maximize the utilization of each node's processing capacity. Users can expand the number of signal processing nodes and adjust the busy / idle thresholds of each node by modifying configuration files, thus meeting the scheduling requirements of FPGA data processing in the radar signal processing field.

[0005] The present invention discloses a multi-node data scheduling system based on FPGA, which can simultaneously manage N signal processing nodes and schedule data sent to each signal processing node according to the load of each processing node, thereby maximizing the processing capacity of each signal processing node; the system includes multiple signal processing nodes, a scheduling node, and ZYNQ.

[0006] ZYNQ enumerates the nodes of the entire system, assigns IDs to each node according to the protocol, sends ID configuration packets to each node, and distinguishes between scheduling nodes and processing nodes.

[0007] The signal processing node receives the ID configuration packet sent by ZYNQ and parses it according to the protocol to obtain the signal processing node ID, scheduling node ID, busy / idle threshold, and status transmission frequency information.

[0008] The scheduling node receives the configuration packet sent by ZYNQ and parses it according to the protocol to obtain the signal processing node ID, scheduling node ID, and busy / idle threshold information.

[0009] The signal processing node determines its own load status and sends its busy / idle status to the scheduling node. The scheduling node receives and parses the busy / idle status sent by the signal processing node, and determines whether to send data to that signal processing node for processing based on the busy / idle status of each signal processing node.

[0010] The signal processing nodes specifically include:

[0011] Configuration parsing module: Receives and parses the ID configuration packet sent by ZYNQ, and sends different information to other modules on the node for use.

[0012] Data processing module: Receives data sent from the scheduling node and processes the signals, and sends the load information of this node to the main control module.

[0013] Main control module: Receives load information from the data processing module and determines the busy / idle status of nodes based on the busy / idle threshold sent by the configuration parsing module: when the load exceeds the busy / idle threshold, it sends a busy status to the status information packaging and sending module, indicating that the node can no longer receive data; when the load does not exceed the busy / idle threshold, it sends an idle status to the status information packaging and sending module, indicating that the node can continue to receive data.

[0014] Status information packaging and sending module: Receives busy / idle status information from the main control module, and receives scheduling node ID, local node ID, and status sending frequency information from the configuration parsing module. Packs the above information according to the protocol and sends it to the scheduling node according to the status sending frequency. A sending start signal is generated by a counter. When the counter accumulates to the sending frequency * local clock, the sending start signal becomes high and the counter is cleared.

[0015] The scheduling nodes specifically include:

[0016] Configuration parsing module: Receives and parses the ID configuration packet sent by ZYNQ, obtains the signal processing node ID, scheduling node ID, and busy / idle threshold information according to the protocol, and sends the different information to other modules within the node for use.

[0017] Busy / Idle Status Module: Receives the IDs of each signal processing node sent by the configuration parsing module, and receives the busy / idle information sent by each signal processing node, parses and determines the busy / idle status of each signal processing node.

[0018] Data scheduling module: Receives the busy / idle judgment result from the busy / idle judgment module, and uses a state machine to cyclically poll the busy / idle status of each signal processing node. If the current signal processing node is busy, it skips that node and continues polling until a signal processing node is idle. Then, it sends a scheduling command to that node and schedules data to that node. It also receives the busy / idle threshold from the configuration parsing module. When a signal processing node is always fully busy, it judges the system memory usage. When the cached frame information reaches the busy / idle threshold, it clears the data frame information cache and does not schedule the currently cached data to avoid data reading errors.

[0019] Data transmission module: Receives data scheduling instructions from the data scheduling module and sends the data to the designated signal processing node.

[0020] The beneficial effects of this invention are as follows:

[0021] 1. Multi-node control: It can simultaneously support N (N>0) signal processing nodes, and has backward compatibility and expansion capabilities.

[0022] 2. Polling Traversal Function: This function enables data scheduling based on the load of each processing node, maximizing the utilization of the computing and time resources of each processing node.

[0023] 3. Busy / idle thresholds can be configured in real time: The busy / idle thresholds of each processing node can be configured in real time through configuration packages. Different signal processing systems can be "adapted to local conditions". In different signal processing scenarios, the busy / idle thresholds of each processing node of the system can be configured in real time by modifying the configuration package.

[0024] 4. Frame information clearing function: By judging the system memory usage, when the cached frame information reaches the full threshold, the frame information cache is cleared and the currently cached data is not scheduled to avoid data reading errors.

[0025] 5. Standardized and universal interfaces: Status reception and transmission use the standard SRIO interface. The scheduling system can be extended by modifying the configuration package, which improves the compatibility and scalability of the scheduling system. Attached Figure Description

[0026] Figure 1 This is a framework diagram of a multi-node data scheduling system.

[0027] Figure 2 This is a diagram illustrating the working principle of the processing node.

[0028] Figure 3 This is a diagram illustrating the working principle of the scheduling node. Detailed Implementation

[0029] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] like Figure 1 As shown, the FPGA-based multi-node data scheduling system of the present invention can simultaneously manage N (N>0) signal processing nodes (with scalability). For ease of description, the following description uses a data scheduling system with 4 (N=4) signal processing nodes (with backward compatibility and scalability) as an example, including:

[0031] Four signal processing nodes (1, 2, 3, 4) determine the load status of each node and send their busy / idle status to the scheduling node. Each processing node contains: a. a configuration parsing module: parses the configuration packet sent by ZYNQ to obtain the node's ID, scheduling node ID, busy / idle threshold, and status transmission frequency; b. a data processing module: receives data from the scheduling node, processes it, and sends its load information to the main control module; c. the main control module: receives the load information from the data processing module and determines the node's busy / idle status based on the busy / idle threshold parsed by the configuration parsing module: when the load exceeds the threshold, it sends a busy status to the scheduling node, indicating that the node can no longer receive data; when the load does not exceed the threshold, it sends an idle status to the scheduling node, indicating that the node can continue receiving data; d. an information packaging module: receives the busy / idle status from the main control module, the scheduling node ID parsed by the configuration parsing module, and the status transmission frequency, packages the busy / idle status and scheduling node ID according to the SRIO protocol, and sends it to the scheduling node according to the parsed status transmission frequency.

[0032] A scheduling node (5) is used to analyze the busy / idle status of the four signal processing nodes and determine whether to send data to the node for processing based on the busy / idle status of each processing node.

[0033] The implementation method and steps of this system are as follows:

[0034] 1. For example Figure 1 ZYNQ enumerates the processing nodes of the entire system, assigns IDs to each node according to a specific protocol (such as slot number), and sends ID configuration packets to each node to distinguish between scheduling nodes and processing nodes. This is used for packaging and sending the busy / idle status of each node and sending data in the future.

[0035] 2. For example Figure 2The information processing node determines its busy / idle status and sends this information to the scheduling node. The specific implementation process is as follows:

[0036] Configuration parsing module: Receives configuration packets from ZYNQ, parses them according to the agreed protocol to obtain information such as the processing node ID, scheduling node ID, busy / idle threshold, and status sending frequency, and sends different information to different modules within the node for use.

[0037] Data Processing Module: This module receives data from the scheduling node, processes the signals, and sends its load information to the main control module. The data processing module integrates multiple data processing algorithm chains. The load of this node can be determined by the input algorithm chain's receive count, the output algorithm chain's output count, and the node's memory usage. The difference between the output count and the input count represents the amount of data this node still needs to process. When the memory occupied by this data is approaching the node's memory limit, it indicates a heavy processing load for this node.

[0038] Main control module: Receives load information from the data processing module and determines the busy / idle status of the node based on the busy / idle threshold parsed by the configuration parsing module: when the load exceeds the busy / idle threshold, it sends a busy status to the packaging module, indicating that the node can no longer receive data; when the load does not exceed the busy / idle threshold, it sends an idle status to the packaging module, indicating that the node can continue to receive data.

[0039] Status information packaging and transmission: The system receives busy / idle status information from the main control module, and information such as the scheduling node ID, local node ID, and status transmission frequency from the configuration module. This information is packaged according to the SRIO protocol and transmitted to the scheduling node at a certain frequency. A transmission start signal is generated using a counter. When the counter accumulates to the transmission frequency multiplied by the local clock, the transmission start signal goes high, and the counter is reset to zero. This allows the system to generate the transmission start signal according to the parsed status transmission frequency, thus controlling the transmission frequency of status information.

[0040] 3. For example Figure 3 The scheduling node parses the busy / idle information of the processing node and determines whether to send data to that node based on its busy / idle status. The specific implementation process is as follows:

[0041] Configuration parsing module: Receives configuration packets from ZYNQ, parses them according to the agreed protocol to obtain information such as the processing node ID, scheduling node ID, busy / idle threshold, etc., and sends different information to different modules within the node for use.

[0042] Busy / Idle Status Determination Module: This module receives node IDs from the configuration parsing module and receives busy / idle information from processing nodes. It then parses this information according to the agreed-upon protocol to determine the busy / idle status of each processing node. For example, according to the SRIO protocol, a busy doorbell is designated as 16'hABAB, and an idle doorbell as 16'hCDCD. If the busy / idle status determination module receives busy / idle information for a processing node as (doorbell 16'hCDCD, node ID 2), then according to the protocol, it can determine that the processing node with node ID 2 is idle.

[0043] Data Scheduling: The system receives the busy / idle status judgment result from the busy / idle judgment module and uses a state machine to cyclically poll each processing node to determine its busy / idle status. If the current node is busy, it skips that node and continues polling until a node is found to be idle. At this point, a scheduling command is sent, and data is dispatched to that node. The system also receives the busy / idle threshold from the configuration parsing module. If all processing nodes are constantly busy, downlink data from the front end cannot be sent, causing memory overwriting and resulting in data errors during subsequent reads. By judging system memory usage, when the cached frame information reaches the near-full threshold, the data frame information cache is cleared, and no data is scheduled for the currently cached data to avoid read errors.

[0044] Data transmission: Receives data scheduling instructions from the data scheduling module and sends data to the designated node.

[0045] This invention is not limited to the specific embodiments described above, and various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made to the above embodiments based on the technical essence of this invention should be included within the scope of protection of this invention.

Claims

1. A multi-node data scheduling system based on FPGA, characterized in that: Simultaneously managing N signal processing nodes, the system schedules data sent to each signal processing node based on their load status, thereby maximizing the processing capacity of each node. The system includes: multiple signal processing nodes, a scheduling node, and ZYNQ. ZYNQ enumerates the nodes of the entire system, assigns IDs to each node according to the protocol, sends ID configuration packets to each node, and distinguishes between scheduling nodes and processing nodes. The signal processing node receives the ID configuration packet sent by ZYNQ and parses it according to the protocol to obtain the signal processing node ID, scheduling node ID, busy / idle threshold and status transmission frequency information; The scheduling node receives the configuration packet sent by ZYNQ and parses it according to the protocol to obtain the signal processing node ID, scheduling node ID, and busy / idle threshold information. The signal processing node determines its own load status and sends its busy / idle status to the scheduling node. The scheduling node receives and parses the busy / idle status sent by the signal processing node, and determines whether to send data to that signal processing node for processing based on the busy / idle status of each signal processing node.

2. The FPGA-based multi-node data scheduling system according to claim 1, characterized in that: The signal processing node specifically includes: Configuration parsing module: Receives and parses the ID configuration packet sent by ZYNQ, and sends different information to other modules on the node for use; Data processing module: Receives data sent from the scheduling node and processes the signals, and sends the load information of this node to the main control module; The main control module receives load information from the data processing module and determines the busy / idle status of the nodes based on the busy / idle threshold sent by the configuration parsing module. When the load exceeds the busy / idle threshold, it sends a busy status to the status information packaging and sending module, indicating that the node can no longer receive data. When the load does not exceed the busy / idle threshold, it sends an idle status to the status information packaging and sending module, indicating that the node can continue to receive data. Status information packaging and sending module: Receives busy / idle status information from the main control module, and receives scheduling node ID, local node ID, and status sending frequency information from the configuration parsing module. Packs the above information according to the protocol and sends it to the scheduling node according to the status sending frequency. A sending start signal is generated by a counter. When the counter accumulates to the sending frequency * local clock, the sending start signal becomes high and the counter is cleared.

3. The FPGA-based multi-node data scheduling system according to claim 1, characterized in that: The scheduling node specifically includes: Configuration parsing module: Receives and parses the ID configuration packet sent by ZYNQ, obtains the signal processing node ID, scheduling node ID, and busy / idle threshold information according to the protocol, and sends the different information to other modules within the node for use; Busy / Idle Status Module: Receives the IDs of each signal processing node sent by the configuration parsing module, and receives the busy / idle information sent by each signal processing node, parses and determines the busy / idle status of each signal processing node; The data scheduling module receives the judgment result from the busy / idle judgment module, and uses a state machine to cyclically poll the busy / idle status of each signal processing node. If the current signal processing node is busy, it skips that node and continues polling until a signal processing node is idle. Then, it sends a scheduling command and sends the scheduled data to that node. The module also receives the busy / idle threshold from the configuration parsing module. When the signal processing nodes are always fully busy, it judges the system memory usage. When the cached frame information reaches the busy / idle threshold, it clears the data frame information cache and does not schedule the currently cached data to avoid data reading errors. Data transmission module: Receives data scheduling instructions from the data scheduling module and sends the data to the designated signal processing node.

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