A method for addressing and playing back on-board high-speed parallel storage NAND flash

Abstract

The application provides a kind of on-orbit high-speed parallel storage NAND flash memory addressing playback method, which is a kind of addressing playback algorithm based on effective data amount addressing, including logical mapping reproduction of effective page address to actual physical storage space and determination of starting page address of multi-chip flash memory parallel playback, to reproduce the serial data stream storage process in the parallel computing mode storage, efficiently determine the actual playback pointer of each flash memory, and the addressing playback function based on data source addressing is more user-friendly, which can enable users to completely separate from the storage architecture of flash memory when applying for playback to determine the data address of addressing playback.

Description

Technical Field

[0001] This invention belongs to the field of NAND flash memory playback technology, and particularly relates to a method for NAND flash memory addressing and playback in high-speed parallel storage on satellite. Background Technology

[0002] NAND flash memory, as a type of flash memory, boasts advantages such as large storage capacity and fast write speed, making it widely used in various storage systems. NAND flash memory is a non-volatile storage medium, meaning that sudden power outages do not result in the loss of stored data. Furthermore, compared to NOR flash memory, it offers significant advantages in terms of operation speed and erase cycle limits. Therefore, NAND flash memory is frequently used as the storage medium in systems requiring large-capacity, high-speed, continuous data storage for spacecraft.

[0003] A NAND flash memory chip's memory architecture is divided into seven levels from top to bottom: Device, Target, Logic Unit (LUN), Plane, Block, Page, and Cell. The Device level corresponds to an entire NAND flash memory chip; a chip contains several substrates, each substrate being an independently selectable unit; each substrate contains several blocks, each block being the basic unit for flash erase operations; each block contains several pages, each page being the basic unit for flash read and write operations; and each page contains several cells for storing actual data bits.

[0004] To meet the high-speed throughput requirements of spacecraft data storage, NAND flash memory requires storing a page of data in its internal cache before transferring the cached data to the physical storage cell after a relatively long programming time. A single flash chip is clearly insufficient for this application, necessitating the use of multiple NAND flash chips for parallel storage. The existing patent from the Shanghai Microsatellite Engineering Center, "FLASH Management System and Method for Onboard Data Management" (patent number: CN201610982919.4), employs a design approach of shared storage and playback across multiple flash chips. This is achieved by uniformly addressing multiple flash memory blocks, but this method has limited storage speed and does not support addressing and playback functionality based on the amount of effective data. For parallel storage solutions in high-speed input data stream scenarios, independently storing each flash chip completely separates the data source from the flash memory hardware, maximizing compatibility with data stream input speeds. However, due to the randomness of bad blocks, the specific playback pointer for each flash chip needs to be calculated independently during addressing and playback.

[0005] For parallel storage solutions of NAND flash memory, a common approach is to treat multiple flash memory chips as a whole, integrating the storage resources of multiple flash memory chips and centrally encoding the storage addresses. Taking a scenario with four flash memory chips in parallel storage as an example, this solution extends the storage address of one flash memory chip by two bits in the least significant bits, using these extended two bits to indicate the flash memory index where the current page of data is located. During storage, if the storage block where a page of data is to be stored is a bad block, the current flash memory is skipped, and the bad block table of the next flash memory chip is checked. If multiple flash memory chips encounter bad blocks consecutively, multiple flash memory chips will be skipped continuously. However, the data source is still continuously inputting data, so there is a certain risk of input buffer overwriting and loss. In addition, during address selection and playback, the centralized addressing scheme requires traversing all flash memory chips in a loop to determine the playback start position, which is inefficient. Summary of the Invention

[0006] To address the above problems, this invention provides a method for NAND flash memory addressing and playback in high-speed parallel storage on satellites, which reproduces the storage process of the serial data stream during storage in a parallel computing mode and efficiently determines the actual playback pointer of each flash memory.

[0007] A method for addressing and replaying NAND flash memory in high-speed parallel storage on satellite is proposed. Assuming the number of NAND flash memory chips is N, the input data stream to be stored is divided into multiple data segments according to the page capacity of the NAND flash memory. Then, the data segments with indices (k-1)N+1 to kN are sequentially stored in the k-th page of the N NAND flash memory chips, where k = 1, 2, ..., K. in, To round up, L is the length of the input data stream;

[0008] When it is necessary to replay data after a specified address in the input data stream, obtain the replay pointer Pn corresponding to N NAND flash memory chips, where n = 1, 2, ..., N. The information contained in the replay pointer Pn is: the block index m of the storage block in the NAND flash memory where the data corresponding to the specified address in the input data stream is located, and the page address of the page in the NAND flash memory where the data corresponding to the specified address in the input data stream is located.

[0009] According to the playback pointer Pn corresponding to the N NAND flash memory chips, the data after the specified address is sequentially output from each NAND flash memory chip to the downstream data receiving end in a ping-pong buffer manner until all data after the specified address has been played back or a stop playback instruction is received.

[0010] Furthermore, the method for obtaining the playback pointer Pn corresponding to N NAND flash memory chips is as follows:

[0011] The algorithm continuously checks whether the determination flags of all NAND flash memory playback pointers are determined. If they are determined, the acquisition of the playback pointer Pn corresponding to N NAND flash memory chips is completed. If they are not determined, it means that at least one NAND flash memory chip has not yet successfully acquired the corresponding playback pointer Pn.

[0012] For NAND flash memory that still fails to obtain the corresponding playback pointer Pn, perform the following steps:

[0013] S1: Shift the specified address right by Q bits and add one to obtain the target global block index T, where the target global block index T represents the number of valid storage blocks to be found;

[0014] S2: Take the storage block with block number 1 in the current page of the current NAND flash memory as the current storage block, and then send a bad block table query request to the MRAM that stores bad block table information of N NAND flash memory chips for the current storage block in the current page;

[0015] S3: Wait for the MRAM response signal, and determine whether the current storage block is a bad block based on the response signal. If it is, then the current global block index m of the current NAND flash memory is... n If the value remains unchanged, proceed to step S4. If not, it indicates that the current storage block is a valid storage block. Then, set the current global block index m of the current NAND flash memory chip. n Add one, then proceed to step S4;

[0016] S4: Determine whether the unchanged or incremented global block index has exceeded the storage range of the current substrate to which the current storage block belongs. If yes, it means that all storage blocks in the current substrate have completed bad block lookup. Initiate a bad block table lookup request to MRAM for block number 1 in the next substrate, and repeat step S3 until the current global block index is equal to the target global block index T. If no, it means that all storage blocks in the current substrate have not completed bad block lookup. Initiate a bad block table lookup request to MRAM for the next block in the current substrate, and repeat step S3 until the global block index has exceeded the storage range of the current substrate to which the current storage block belongs.

[0017] S5: When the current global block index is equal to the target global block index T, it indicates that the specified number of valid storage blocks have been found in the current NAND flash memory. Then, the final current global block index and the page address of the page where the last found valid storage block is located are used as the playback pointer Pn corresponding to the current NAND flash memory. At the same time, the determination flag of the NAND flash memory playback pointer is modified to "determined".

[0018] Furthermore, the data after the specified address is sequentially output from each NAND flash memory chip to the receiving end using a ping-pong buffering method, specifically as follows:

[0019] C1: Replay the specified page data in N NAND flash memory chips using the currently determined N page addresses as the playback addresses, and store the specified page data into their respective output ping-pong buffers;

[0020] C2: Determine the starting index s of the NAND flash output cache that needs to be output to the downstream data receiving end based on the flash index corresponding to the lower two bits of the specified address given by the user, where s∈[1,N];

[0021] C3: When replaying the first page data of N NAND flash memory chips transmitted from N ping-pong caches to the downstream data receiving end, the cached data in the first page of the NAND flash memory chips from the s-th to the N-th chips are transmitted sequentially, and the cached data in the first page of the NAND flash memory chips from the 1-s-1 chips are discarded; when transmitting data of other pages besides the first page, the downstream data receiving end controls each NAND flash memory chip to move the cached data in each page outward in the order of index s increasing from 1 to N.

[0022] Furthermore, there are four NAND flash memory chips, numbered NAND1, NAND2, NAND3, and NAND4. One page of data from the input data stream is extracted each time according to the page capacity of the NAND flash memory, and then stored into the pages of the four NAND flash memory chips in the order of NAND1, NAND2, NAND3, NAND4, NAND1, NAND2, NAND3, NAND4...

[0023] Furthermore, each NAND flash memory chip contains multiple substrates, each substrate includes P memory blocks, and each memory block contains 2 Q If each of the four NAND flash memory chips independently stores the input data stream starting from the first page of the first storage block of the first substrate, and skips the storage block if it is a bad block.

[0024] Beneficial effects:

[0025] 1. This invention provides a method for addressing and replaying NAND flash memory in high-speed parallel storage on satellites. It is an addressing and replaying algorithm based on effective data volume addressing, including logical mapping and reproduction of effective page addresses to actual physical storage space and determination of the starting page address for parallel replaying of multiple flash memory chips. It reproduces the serial data stream storage process during storage in a parallel computing mode, efficiently determines the actual replay pointer of each flash memory chip, and its addressing and replaying function based on data source addressing is more user-friendly, allowing users to completely detach from the flash memory storage architecture when requesting replay to determine the data address for addressing and replaying.

[0026] 2. This invention provides a method for NAND flash memory addressing and playback for high-speed parallel storage on satellites, and gives a specific method for obtaining the playback pointer. It supports high-speed data storage, playback from zero, sequential playback, and effective page address addressing and playback based on data source addressing. It is suitable for the storage and playback of high-speed data streams from various types, lengths, and formats of data sources.

[0027] 3. This invention provides a method for NAND flash memory addressing and playback in high-speed parallel storage on satellite. It designs a high-speed parallel playback architecture based on parallel storage, establishes a one-to-one playback channel between the downstream data receiver and a single flash memory chip, and maximizes the data playback rate by detecting the start signal of the data receiver and using ping-pong buffer. It is also compatible with and supports general zero-playback and sequential playback functions. Attached Figure Description

[0028] Figure 1 Hardware architecture for NAND flash memory addressing and playback device for high-speed parallel storage on satellite;

[0029] Figure 2 To illustrate the bad block table storage format of 4 flash memory chips in MRAM;

[0030] Figure 3 This is the block index iteration process;

[0031] Figure 4 This involves independently replaying the pointer iteration calculation process.

[0032] Figure 5 To determine the parallel playback process of the pointer. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0034] For parallel storage schemes where each NAND flash memory chip is independently stored, this invention aims to design and implement a scheme for playback at a specified address. The specified address is defined as the starting address of the page from which data playback begins, specified by the user without considering bad block information. This invention maintains a separate storage pointer for each NAND flash memory chip, adopts the approach of reproducing the parallel storage process of multiple flash memory chips, and iteratively updates the temporary playback pointer of each NAND flash memory chip to ultimately determine the starting playback pointer of each NAND flash memory chip in a specified address playback scenario based on data source addressing.

[0035] A method for addressing and replaying NAND flash memory in high-speed parallel storage on satellite is proposed. Assuming the number of NAND flash memory chips is N, the input data stream to be stored is divided into multiple data segments according to the page capacity of the NAND flash memory. Then, the data segments with indices (k-1)N+1 to kN are sequentially stored in the k-th page of the N NAND flash memory chips, where k = 1, 2, ..., K. in, To round up, L is the length of the input data stream.

[0036] In other words, based on considerations of data security and system reliability, this invention allows multiple flash memory chips to store data independently. The input data stream can be continuously and cyclically stored in the input cache corresponding to each flash memory chip. For example, assuming there are four NAND flash memory chips, numbered NAND1, NAND2, NAND3, and NAND4, one page of the input data stream is extracted each time according to the page capacity of the NAND flash memory, and then stored sequentially into the pages of the four NAND flash memory chips in the order of NAND1, NAND2, NAND3, NAND4, NAND1, NAND2, NAND3, NAND4… The back-end flash memory only needs to check the validity of the page address to be stored and initiate the storage operation when it finds that the corresponding cache content meets the storage requirement of one page.

[0037] It should be noted that, to more clearly illustrate the implementation idea of ​​this invention, it is assumed that the current storage medium uses four NAND flash memory chips for independent parallel storage. The four NAND flash memory chips are of the same specification, each NAND flash memory chip has eight independent chip select signals, corresponding to eight memory substrates, each substrate corresponds to P memory blocks, and each memory block has 2... Q See Appendix for the hardware architecture of the page. Figure 1 Therefore, each of the four NAND flash memory chips independently stores the input data stream starting from the first page of the first memory block on the first substrate. If a memory block is bad, it is skipped. This scheme completely separates the input data end from the storage flash memory end, maximizing the input data rate at the data source end.

[0038] It should be noted that the storage format of all flash memory bad block table information in MRAM (Magnetoresistive Random Access Memory) is shown in the appendix. Figure 2 Bad block information for each storage block is stored using a 4-byte address, with the low-order bytes representing flash memory 1 through flash memory 4, respectively.

[0039] When it is necessary to replay data after a specified address in the input data stream, obtain the replay pointer Pn corresponding to N NAND flash memory chips, where n = 1, 2, ..., N. The information contained in the replay pointer Pn is: the block index m of the storage block in the NAND flash memory where the data corresponding to the specified address in the input data stream is located, and the page address of the page in the NAND flash memory where the data corresponding to the specified address in the input data stream is located.

[0040] It should be noted that the page address is the low Q bit of the specified address given by the user. The specified address is defined as: the starting address of the page from which the user begins to replay data without considering bad block information. In other words, the specified address can directly determine which page of the input data stream the user wants to replay is located on, but it cannot directly determine which page of the NAND flash memory the user wants to replay is stored on. The present invention aims to determine which page of the NAND flash memory the first page of data corresponding to the specified address is stored on, and also to determine which storage block the first page of data corresponding to the specified address is stored on, after excluding bad blocks.

[0041] According to the playback pointer Pn corresponding to the N NAND flash memory chips, the data after the specified address is sequentially output from each NAND flash memory chip to the downstream data receiving end in a ping-pong buffer manner until all data after the specified address has been played back or a stop playback instruction is received.

[0042] The method for obtaining the playback pointer Pn corresponding to N NAND flash memory chips is as follows:

[0043] The algorithm continuously checks whether the determination flags of all NAND flash memory playback pointers are determined. If they are determined, the acquisition of the playback pointer Pn corresponding to N NAND flash memory chips is completed. If they are not determined, it means that at least one NAND flash memory chip has not yet successfully acquired the corresponding playback pointer Pn.

[0044] For NAND flash memory that still fails to obtain the corresponding playback pointer Pn, perform the following steps:

[0045] S1: Shift the specified address right by Q bits and add one to obtain the target global block index T, where the target global block index T represents the number of valid storage blocks to be found;

[0046] S2: Take the storage block with block number 1 in the current page of the current NAND flash memory as the current storage block, and then send a bad block table query request to the MRAM that stores bad block table information of N NAND flash memory chips for the current storage block in the current page;

[0047] S3: Wait for the MRAM response signal, and determine whether the current storage block is a bad block based on the response signal. If it is, then the current global block index m of the current NAND flash memory is... nIf the value remains unchanged, proceed to step S4. If not, it indicates that the current storage block is a valid storage block. Then, set the current global block index m of the current NAND flash memory chip. n Add one, then proceed to step S4;

[0048] S4: Determine whether the unchanged or incremented global block index has exceeded the storage range of the current substrate to which the current storage block belongs. If yes, it means that all storage blocks in the current substrate have completed bad block lookup. In this case, initiate a bad block table lookup request to MRAM for block number 1 in the next substrate, and repeat step S3 until the current global block index is equal to the target global block index T, indicating that a sufficient number of valid storage blocks have been found. If no, it means that not all storage blocks in the current substrate have completed bad block lookup. In this case, initiate a bad block table lookup request to MRAM for the next block in the current substrate, and repeat step S3 until the global block index has exceeded the storage range of the current substrate to which the current storage block belongs.

[0049] S5: When the current global block index is equal to the target global block index T, it indicates that the specified number of valid storage blocks have been found in the current NAND flash memory. Then, the final current global block index and the page address of the page where the last found valid storage block is located are used as the playback pointer Pn corresponding to the current NAND flash memory. At the same time, the determination flag of the NAND flash memory playback pointer is modified to "determined".

[0050] The specific method of outputting data from each NAND flash memory chip to the receiving end in sequence using a ping-pong buffer is as follows:

[0051] C1: Replay the specified page data in N NAND flash memory chips using the currently determined N page addresses as the playback addresses, and store the specified page data into their respective output ping-pong buffers;

[0052] C2: Determine the starting index s of the NAND flash output cache that needs to be output to the downstream data receiving end based on the flash index corresponding to the lower two bits of the specified address given by the user, where s∈[1,N];

[0053] C3: When replaying the first page data of N NAND flash memory chips transmitted from N ping-pong buffers to the downstream data receiving end, the buffer data in the first page of the N NAND flash memory chips from the s-th to the N-th chips are transmitted sequentially, and the buffer data in the first page of the NAND flash memory chips from the 1-s-1 chips are discarded (that is, if N=4 and s=3, then buffer data 3 and 4 are transmitted, and buffer data 1 and 2 will be discarded); when transmitting data of other pages besides the first page, the downstream data receiving end controls each NAND flash memory chip to move the buffer data in each page outward in the order of index s increasing from 1 to N.

[0054] For example, suppose a user needs to input data starting from page 3 of the data stream, and this page's data is stored in page 1 of the first storage block of the first substrate of the third NAND flash memory. Following the steps described above, find the pointers corresponding to the four NAND flash memories, and assume the four playback pointers are P1, P2, P3, and P4, where P1 is the address of page 1 of the first storage block of the first substrate of the first NAND flash memory, P2 is the address of page 1 of the first storage block of the first substrate of the second NAND flash memory, P3 is the address of page 1 of the first storage block of the first substrate of the third NAND flash memory, and P4 is the address of page 1 of the first storage block of the first substrate of the fourth NAND flash memory. However, the user needs data starting from page 3 onwards, so it's necessary to access the first storage block of the first substrate of the first NAND flash memory... The data from the first page of the first storage block of the first substrate of the second NAND flash memory is discarded. Starting from the first page of the first storage block of the first substrate of the third NAND flash memory, the data is output to the buffer. Then, the data from the first page of the first storage block of the first substrate of the fourth NAND flash memory is read, along with the address of the second page of the first storage block of the first substrate of the first NAND flash memory, the address of the second page of the first storage block of the first substrate of the first NAND flash memory, the address of the second page of the first storage block of the first substrate of the second NAND flash memory, the address of the second page of the first storage block of the first substrate of the third NAND flash memory, the address of the second page of the first storage block of the first substrate of the fourth NAND flash memory, and so on. After reading all the pages of a storage block, the data of each page in the next storage block is read, until all the stored data is played back or a stop playback command is received.

[0055] It should be noted that in this invention, four NAND flash memory chips read one page together. That is, each time a page is read, the four NAND flash memory chips read one page at the same time and put it into their respective corresponding caches. However, when moving the data downstream from these four caches, the data in the first and second caches is discarded (considered as invalid data).

[0056] In summary, the present invention provides a method for NAND flash memory addressing and playback in high-speed parallel storage on satellite. The playback principle is as follows: Figure 3 The block index iteration process shown is as follows: Figure 4 The independent playback pointer iteration calculation process shown and as follows Figure 5 The illustrated parallel playback process for determining pointers involves the first two processes working together to obtain the pointer to be played back for each flash memory, while the third process is the specific playback implementation for the pointer to be played back, including the following steps:

[0057] A. Block index iteration process:

[0058] A1. In the idle state, all relevant global and intermediate quantities need to be cleared to zero, including the target global block index T, the current global chip select signal index C, and the current global block index M, in order to prepare for the next addressing playback calculation process.

[0059] A2. After determining the valid replay page address (the page address is the page index calculated based on the actual amount of stored data), calculate the target global block index T, where the target global block index T is the source valid page address shifted right by Q bits and then incremented by one, and initiate a bad block table query request for block number 1 to MRAM.

[0060] A3. When not all start playback pointers are obtained, meaning that the determination flags of all flash memory playback pointers in process 2 are not all "determined", it is necessary to loop and wait for the MRAM's response signal. After obtaining the bad block table information of the current block, it is determined whether the playback pointers of all flash memory in process B have been calculated. If all have been calculated, all relevant quantities in the process are cleared to zero; otherwise, the current global block index M is incremented by one, and a query request for the bad block table information of the next block is initiated to the MRAM. At this time, it is necessary to simultaneously determine whether the incremented current global block index exceeds the storage range corresponding to the current chip select signal C. If it exceeds the range, the current global chip select signal index C needs to be incremented by one.

[0061] A4. Repeat process A3 until the determination flag of all flash memory playback pointers in process B is "determined".

[0062] B. Independent playback pointer iteration calculation process:

[0063] B1. In idle state, all relevant intermediate values ​​must be cleared to zero, and the previous calculation results must be cleared, including the current block index m corresponding to each of the four flash memory chips. i (i = 1, 2, 3, 4) and the final playback pointer p corresponding to each of the four flash memory chips. i (i = 1, 2, 3, 4), at this time the playback pointers of the 4 flash memory chips are all in the "undetermined" state;

[0064] B2. When iteratively calculating the final playback pointer of the four flash memory chips, four sub-processes need to be performed independently, that is, each sub-process independently performs the following B3-B4 playback pointer calculation process.

[0065] B3. In each sub-process, when the final playback pointer determination flag of the flash memory is "undetermined", the MRAM acknowledge signal is continuously identified as the start flag for this sub-process; after obtaining the MRAM acknowledge signal, the current block index m is checked. n Check if it is equal to the target global block index T; if they are equal, then obtain the final playback pointer p of this flash memory. i (p i= {current global block index M, target page address P}), where the target page address P is the address of the Pth page to which the last found valid storage block (current global block index M) belongs, and the replay pointer confirmation flag is also updated; if they are not equal, the bad block table information returned by MRAM is used to determine whether the current block is a bad block. If it is not a bad block, the current block index m is set to {current global block index M, target page address P}. n Increment by one; otherwise, the current block index remains unchanged, and the system waits for the next MRAM response signal.

[0066] B4. Each sub-process repeats the execution of process B3 until the current block index and the global block index M corresponding to the flash memory are equal, that is, the determination flag of the final playback pointer corresponding to the flash memory is "determined".

[0067] It is important to note that the final playback pointer of each flash memory corresponds to four consecutive pages of data, while the starting cache for the data to be played back downstream should be the output cache of the flash memory corresponding to the lower two bits of the source page address given by the user.

[0068] C. Determine the parallel playback process of the pointer:

[0069] C1, waiting for all flash memory playback pointers p i Once (i = 1, 2, 3, 4) is determined, it is first checked whether all playback pointers are valid pointers, i.e., the current storage pointer should be greater than the playback pointer, indicating that there is currently readable data. Then, the parallel playback process of the flash memory is started immediately. At this time, all flash memory simultaneously start page playback operation, playing back one page of data at the pointer page address to the output buffer corresponding to each cache.

[0070] C2. The downstream data receiver first determines whether the first page of data in all flash memory modules is valid. Assuming the user sets data playback to start from flash memory module 3, the first page of data in flash memory modules 1 and 2 is invalid. This invalid data will be filtered out, and data will be continuously output to the downstream data receiver starting from the valid starting position. To further improve the playback data rate, the output buffer of each flash memory module can be designed as a ping-pong buffer. In this case, the playback operation of the next page of flash memory can be started simultaneously when data is transferred from the buffer to the data receiver.

[0071] C3. Replay page data from page 2 onwards are continuously output to the backend in ascending order of flash memory index number.

[0072] C4. Repeat step C3 until all stored data has been played back or a stop playback command is received.

[0073] Therefore, the advantages of this invention over existing technical solutions are as follows:

[0074] (1) An addressing and playback algorithm based on effective data volume addressing is designed to reproduce the serial data stream storage process during storage in parallel computing mode, and efficiently determine the actual playback pointer of each flash memory.

[0075] (2) A high-speed parallel playback architecture was designed, which realizes high-speed data playback by establishing a one-to-one channel between each flash memory and the corresponding output ping-pong buffer. Functionally, it not only supports specific addressing playback tasks, but also supports general zero-based playback and sequential playback functions.

[0076] (3) The addressing playback function based on data source addressing is more user-friendly, allowing users to determine the data address for playback completely independent of the flash storage architecture when requesting playback.

[0077] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A method for NAND flash memory addressing and playback in high-speed parallel storage on satellite, characterized in that, Assuming there are N NAND flash memory chips, the input data stream to be stored is divided into multiple data segments according to the page capacity of the NAND flash memory. The data segments numbered (k-1)N+1 to kN are sequentially stored into the k-th page of each of the N NAND flash memory chips, where k = 1, 2, ..., K, and K = ... L / N ,in, To round up, L is the length of the input data stream; When it is necessary to replay data after a specified address in the input data stream, obtain the replay pointer Pn corresponding to N NAND flash memory chips, where n=1,2,…,N. The information contained in the replay pointer Pn is: the block index m of the storage block in the NAND flash memory where the data corresponding to the specified address in the input data stream is located, and the page address of the page in the NAND flash memory where the data corresponding to the specified address in the input data stream is located. According to the playback pointer Pn corresponding to the N NAND flash memory chips, the data after the specified address is sequentially output from each NAND flash memory chip to the downstream data receiving end in a ping-pong buffer manner until all data after the specified address has been played back or a stop playback instruction is received. The specific method of outputting data from each NAND flash memory chip to the receiving end in sequence using a ping-pong buffer is as follows: C1: Replay the specified page data in N NAND flash memory chips using the currently determined N page addresses as the playback addresses, and store the specified page data into their respective output ping-pong buffers; C2: Determine the starting index s of the NAND flash output cache that needs to be output to the downstream data receiving end based on the flash index corresponding to the lower two bits of the specified address given by the user, where s∈[1,N]; C3: When replaying the first page data of N NAND flash memory chips transmitted from N ping-pong caches to the downstream data receiving end, the cached data in the first page of the NAND flash memory chips from the s-th to the N-th chips are transmitted sequentially, and the cached data in the first page of the NAND flash memory chips from the 1-s-1 chips are discarded; when transmitting data of other pages besides the first page, the downstream data receiving end controls each NAND flash memory chip to move the cached data in each page outward in the order of index s increasing from 1 to N.

2. The method for NAND flash memory addressing and playback in high-speed parallel storage on satellite as described in claim 1, characterized in that, The method for obtaining the playback pointer Pn corresponding to N NAND flash memory chips is as follows: The algorithm continuously checks whether the determination flags of all NAND flash memory playback pointers are determined. If they are determined, the acquisition of the playback pointer Pn corresponding to N NAND flash memory chips is completed. If they are not determined, it means that at least one NAND flash memory chip has not yet successfully acquired the corresponding playback pointer Pn. For NAND flash memory that still fails to obtain the corresponding playback pointer Pn, perform the following steps: S1: Shift the specified address to the right. Add one to the last bit to get the target global block index T, where the target global block index T represents the number of valid storage blocks to be found; S2: Take the storage block with block number 1 in the current page of the current NAND flash memory as the current storage block, and then send a bad block table query request to the MRAM that stores bad block table information of N NAND flash memory chips for the current storage block in the current page; S3: Wait for the MRAM response signal, and determine whether the current storage block is a bad block based on the response signal. If it is, then the current global block index of the current NAND flash memory chip is... If the value remains unchanged, proceed to step S4. If not, it indicates that the current storage block is a valid storage block, and the current global block index of the current NAND flash memory is set. Add one, then proceed to step S4; S4: Determine whether the global block index, which remains unchanged or is incremented by one, exceeds the storage range of the current substrate to which the current storage block belongs. If yes, it indicates that all storage blocks in the current substrate have completed bad block lookup. Initiate a bad block table lookup request to MRAM for block number 1 in the next substrate, and repeat step S3 until the current global block index is equal to the target global block index T. If no, it indicates that all storage blocks in the current substrate have not completed bad block lookup. Initiate a bad block table lookup request to MRAM for the next block in the current substrate, and repeat step S3 until the global block index exceeds the storage range of the current substrate to which the current storage block belongs. S5: When the current global block index is equal to the target global block index T, it indicates that the specified number of valid storage blocks have been found in the current NAND flash memory. Then, the final current global block index and the page address of the page where the last found valid storage block is located are used as the playback pointer Pn corresponding to the current NAND flash memory. At the same time, the determination flag of the NAND flash memory playback pointer is modified to "determined".

3. The method for NAND flash memory addressing and playback in high-speed parallel storage on satellite as described in claim 2, characterized in that, The NAND flash memory consists of four chips, numbered NAND1, NAND2, NAND3, and NAND4. One page of data from the input data stream is extracted each time according to the page capacity of the NAND flash memory, and then stored into the pages of the four NAND flash memory chips in the order of NAND1, NAND2, NAND3, NAND4, NAND1, NAND2, NAND3, NAND4...

4. The method for NAND flash memory addressing and playback in high-speed parallel storage on satellite as described in claim 3, characterized in that, Each NAND flash memory chip contains multiple substrates, each substrate includes P memory blocks, and each memory block contains... If each of the four NAND flash memory chips independently stores the input data stream starting from the first page of the first storage block of the first substrate, and skips the storage block if it is a bad block.

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