Random number detection device, system on chip, random number detection and encryption method

Abstract

Embodiments of the present application provide a random number detection device, a system on chip, and a random number detection and encryption method. The random number detection device comprises: a shifter configured to obtain a current random bit sequence based on a sequence increment of a previous random bit sequence shifted by a preset number of bits; a first register configured to store a plurality of previous occurrence times of a plurality of bit arrangement features in the previous random bit sequence; a second register configured to store a previous sum of squares of the plurality of previous occurrence times; an adder configured to perform a sum operation based on at least the previous sum of squares and the previous occurrence times to obtain a current sum of squares, and update the current sum of squares in the second register; and a comparator configured to compare the current sum of squares with a preset sum of squares threshold, and perform random number detection of the current random bit sequence. The scheme of the embodiments of the present application reduces the hardware performance requirement in the sum of squares calculation process, and improves the efficiency of the random number detection.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a random number detection device, a system-on-a-chip, and a random number detection and encryption method. Background Technology

[0002] In the field of information security, random numbers, such as random bit sequences, are frequently used, for example, in key processing based on encryption algorithms, signature processing based on encryption algorithms, filling random bits, or random masking, etc. The quality of random numbers directly affects the security of information security processing.

[0003] A random number generator comprises various components, including an entropy source, post-processing, and online detection, to generate random numbers. To achieve efficient online detection, a chi-square test, with its complex mathematical expression, is typically used for random number generation.

[0004] However, using software for random number detection results in low computational efficiency, while using hardware circuits for random number detection results in high power consumption. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a random number detection device, a system-on-a-chip, and a random number detection and encryption method to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the present invention, a random number detection apparatus is provided, comprising: a shifter, which shifts a previous random bit sequence by a sequence increment of a preset number of bits to obtain a current random bit sequence, wherein the preset number of bits corresponds to multiple bit permutation features; a first register, which stores multiple previous occurrence counts of the multiple bit permutation features in the previous random bit sequence; a second register, which stores a previous sum of squares of the multiple previous occurrence counts; an adder, which obtains the previous occurrence counts of the bit permutation features of the sequence increment from the first register and obtains the previous sum of squares from the second register, performs a summation operation based at least on the previous sum of squares and the previous occurrence counts to obtain a current sum of squares, and updates the current sum of squares in the second register, wherein the current sum of squares indicates the sum of squares of the multiple current occurrence counts of the multiple bit permutation features in the current random bit sequence; and a comparator, which compares the current sum of squares with a preset sum of squares threshold and performs random number detection on the current random bit sequence.

[0007] In another implementation of the invention, the shifter is a shift register. The shift register stores the previous random bit sequence and updates the previous random bit sequence with the current random bit sequence.

[0008] In another implementation of the present invention, the shift register stores a previous random bit sequence with a sequence length of m*(n-1), where m is a preset number of bits, and n is an identifier for sequence sorting. The shift register adds a sequence increment of m bits on the basis of the previous random bit sequence to obtain a current random bit sequence with a sequence length of m*n.

[0009] In another implementation of the present invention, the first register stores a plurality of previous occurrence counts f(i) of the plurality of bit permutation features, the number of the plurality of bit permutation features is M, n= , 1≤i≤M.

[0010] In another implementation of the present invention, the adder acquires the bit permutation feature i0 of the sequence increment from the first register, and calculates the previous occurrence count f(i0) of the bit permutation feature i0 in the previous random bit sequence.

[0011] In another implementation of the present invention, the second register stores F(n-1) as the previous sum of squares of the previous random bit sequence with the sequence length of m*(n-1); the adder calculates F(n)=F(n-1)+2f(i0)+1 as the current sum of squares.

[0012] In another implementation of the present invention, the shift register determines whether n=N, and in the case that n=N, causes the comparator to output a random number detection result of the current random bit sequence, where 1≤n≤N, and N is a positive integer.

[0013] In another implementation of the present invention, in the case that n<N, the shift register updates the current random bit sequence by shifting the sequence increment of the preset number of bits based on the current random bit sequence.

[0014] In another implementation of the present invention, the random number detection is chi-square detection, and the sum-of-squares threshold is determined based on the expected occurrence count E of the M bit permutation features in a random bit sequence with a sequence length of N*M.

[0015] According to a second aspect of the present invention, a random number detection method is provided, comprising: obtaining a current random bit sequence based on a sequence increment by shifting a previous random bit sequence by a preset number of bits, wherein the preset number of bits corresponds to multiple bit permutation features; determining multiple previous occurrence counts of the multiple bit permutation features in the previous random bit sequence, and a previous sum of squares of the multiple previous occurrence counts; performing a summation operation based at least on the previous sum of squares and the previous occurrence counts of the bit permutation features in the sequence increment to obtain a current sum of squares, wherein the current sum of squares indicates the sum of squares of multiple current occurrence counts of the multiple bit permutation features in the current random bit sequence; comparing the current sum of squares with a preset sum of squares threshold, and performing random number detection on the current random bit sequence.

[0016] According to a third aspect of the present invention, an encryption method is provided, comprising: acquiring a pre-stored object to be encrypted; obtaining a current random bit sequence by incrementing the sequence by a preset number of bits; performing a chi-square test on the current random bit sequence to obtain a target random bit sequence; and processing the object to be encrypted by applying the target random bit sequence to an encryption algorithm.

[0017] According to a third aspect of the present invention, a system-on-a-chip is provided, including the random number detection device according to the first aspect.

[0018] In the embodiment of the present invention, the adder obtains the previous occurrence count and previous sum of squares of the bit arrangement feature of the sequence increment from the register, and processes the previous occurrence count and previous sum of squares through summation operation to obtain the current sum of squares, thereby reducing the hardware performance requirements in the sum of squares calculation process and improving the efficiency of random number detection. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0020] Figure 1A This is a schematic block diagram of an example on-chip system.

[0021] Figure 1B To set Figure 1A A schematic block diagram of a random number generation device in a system-on-a-chip.

[0022] Figure 1C for Figure 1B A schematic diagram of an example of an online detector from an embodiment.

[0023] Figure 2 This is a schematic structural diagram of a random number detection device according to an embodiment of the present invention.

[0024] Figure 3 for Figure 2 A flowchart illustrating the steps of a specific implementation of the chi-square detection process in this embodiment.

[0025] Figure 4 This is a flowchart of the encryption method according to another embodiment of the present invention.

[0026] Figure 5 This is a flowchart of the steps of a random number detection method according to another embodiment of the present invention. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0028] The specific implementation of the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0029] Figure 1A This is a schematic structural diagram of a system-on-a-chip (SoC) based on an example. The SoC 1000 includes a memory 1210, a processing unit cluster 1220, and an arithmetic unit cluster 1100 connected by a bus. The processing unit cluster 1220 includes multiple processing units 222. The processing units 222 can take various forms, such as a processor (CPU), an application-specific integrated circuit (ASIC), or a field-programmable gate matrix (FPGA). The arithmetic unit 232 in this application is a dedicated arithmetic unit designed primarily to improve the security of data processing based on the results of dot product operations.

[0030] Processing unit 222 can be physically implemented using analog and / or digital circuitry (e.g., logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and can optionally be driven by firmware and / or software. For example, the circuitry can be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting the block can be implemented using dedicated hardware or processors (e.g., one or more programmable microprocessors and associated circuitry), or a combination of dedicated hardware for performing some functions of the block and processors for performing other functions of the block.

[0031] Figure 1B This is a schematic block diagram of a random number generation device based on an example. Figure 1B The random number generation device can be implemented using a processing unit 222, including a random number generator 10 and an entropy source 20. The random number generator 10 may include a random seed generator 110, a post-processor 120, and an online detector 130. The entropy source 20 can generate an entropy signal Ent and output the generated entropy signal Ent to the random seed generator 110. The entropy source 20 can generate the entropy signal Ent based on randomness. For example, the entropy signal Ent can represent an analog electrical signal generated due to user movement, thermal noise of resistors, short-range noise of semiconductor PN junctions, short-range noise caused by photon generation, and radiation generation.

[0032] Furthermore, the random seed generator 110 can generate a random seed (RS) for a digital region based on the entropy signal Ent received from the entropy source 20. For example, the random seed generator 110 can generate a random seed RS by amplifying the entropy signal Ent and sampling the entropy signal Ent after amplification.

[0033] Furthermore, the post-processor 120 can generate a random number (RN) by performing post-processing on the received random seed RS. The post-processor 120 can generate a random number RN from the random seed RS using a specific algorithm. The bias attribute is used to represent the positional bias "1" or "0" of the random number RN generated by applying the random seed RS to the algorithm. The post-processor 120 can generate random numbers RN by applying the random seed RS to multiple algorithms with different bias attributes, thereby increasing the unbiasedness of the random number RN.

[0034] In addition, the online detector 130 is used to perform online detection on the generated random number RN, such as chi-square test. After the online detector completes the online detection, the random number RN is output to the encryption circuit, such as for signature processing or encryption processing.

[0035] Specifically, the chi-square detection is based on the chi-square detection algorithm. For a target random bit sequence of mN, the target random bit sequence is generated based on m as the bit increment. That is, the random seed generator 110 generates m sequence increments N times.

[0036] Furthermore, Figure 1C An example of an online detector 130 is shown. As shown, the online detector includes a shift register 131, an adder 132, a sum of squares calculator 133, and a comparator 134.

[0037] It should be understood that the shift register 131, adder 132, sum of squares calculator 133, and comparator 134 mentioned above can all be implemented using digital circuits, which improves the processing efficiency of online detection.

[0038] The following will combine Figure 1C The online detector describes the chi-square detection process. First, the chi-square detection algorithm is as follows: S=∑(C di -E d ) 2 / E d Where i is the identifier of the random bit sequence, and the number of bit permutation features of the sequence increment is 2. m , 1≤i≤2 m C di E represents the current occurrence count of various bit permutation features in a random bit sequence. d =N / 2 m The expected number of occurrences as a feature of various bit permutations.

[0039] For example, when m = 4 (bits) and m * N = 512 (bits), N equals 128, E d =8, when performing the chi-square test, the threshold for the chi-square test is 65, and correspondingly, S=∑(C di -E d ) 2 / E d <65, chi-square test completed.

[0040] When the online detector 130 performs chi-square detection, it shifts m=4 bits each time through the shift register 131 to generate a random bit sequence. The adder 132 directly or indirectly obtains the output of the shift register 131 for performing operations such as C. di -E d The logical operations are performed, and the calculation results are output to the square sum calculator 133, which executes (C di -E d ) 2Then, the comparator compares the result calculated by the sum of squares calculator 133 with the threshold for chi-square detection to perform chi-square detection.

[0041] In this example, the sum of squares calculator 133 in the online detector 130 needs to perform 2 4 =Calculation of the sum of squares to the 16th power, which means that when the online detector 130 performs chi-square detection, the circuit performance requirements of the sum of squares calculator 133 are relatively high.

[0042] Figure 2 A random number detection device according to an embodiment of the present invention is illustrated. The random number detection device can be physically implemented by analog and / or digital circuitry and can optionally be driven by firmware and / or software. For example, the circuitry can be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting the block can be implemented by dedicated hardware or a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block.

[0043] The random number detection device in this embodiment can be such as Figure 1B The online detector 130 is implemented, including a shifter 210, a first register 220, a second register 230, an adder 240, and a comparator 250.

[0044] The shifter 210 obtains the current random bit sequence by shifting the previous random bit sequence by a preset number of bits as a sequence increment. The preset number of bits corresponds to various bit permutation features.

[0045] For example, the shifter can be a bit shifter configured to shift bits in shift units. In one example, the shift unit is equal to a preset number of bits, such as 4 bits. In another example, the shift unit can be a divisor of the preset number of bits, thus allowing for bit shifters with different shift units. Furthermore, the preset number of bits can be a composite number or a prime number; preferably, it is a composite number, so that the current random bit sequence can be generated by shifting the composite number by a divisor of bits each time.

[0046] Furthermore, bit arrangement features, also known as bit sorting patterns, can be the number of all possible values ​​that can appear in a sequence increment of a preset number of bits. For example, a 2-bit sequence increment includes four bit arrangement features: 00, 01, 10, and 11. Different bit arrangement features produce different electromagnetic waveforms. As another example, for a 4-bit sequence increment, there are theoretically 24 possible bit arrangement features, thus corresponding to 24 possible bit arrangement features.

[0047] The first register 220 stores the number of previous occurrences of various bit permutation features in a previous random bit sequence. For example, the number of previous occurrences here can be represented as f(i0), where f(i) represents a counting function, the current occurrence count of each bit permutation feature, where 1 ≤ i ≤ M, and f(i0) is the function value at i = i0. In one example, M = 2. m Furthermore, for a random bit sequence of n predetermined bits, n = .

[0048] For example, the first register can be implemented as M counters, each used to count the M bit permutation features. When updating the current random bit sequence based on the sequence increment, the counter corresponding to the bit permutation feature of the sequence increment is incremented by 1.

[0049] The second register 230 stores the sum of squares of previous occurrences. For example, F(n) is the sum of squares of the current occurrences of each bit permutation feature for a random bit sequence of n preset bit numbers. A linear calculation of the previous occurrences yields 2f(i0) + 1. This linear calculation can be implemented using hardware digital circuitry, for example, using adders and registers.

[0050] Adder 240 obtains the previous occurrence counts of the bit permutation features of the sequence increment from the first register and the previous sum of squares from the second register. It performs a summation operation based at least on the previous sum of squares and the previous occurrence counts to obtain the current sum of squares and updates the second register with the current sum of squares. The current sum of squares indicates the sum of squares of multiple current occurrence counts of various bit permutation features in the current random bit sequence. For example, if the previous sum of squares is F(n-1), then F(n) = F(n-1) + 2f(i0) + 1, where F(n-1) includes f... 2 (i0), f 2 (i0)+2f(i0)+1=(f(i0)+1) 2 .

[0051] Comparator 250 compares the current sum of squares with a preset sum of squares threshold and performs random number detection on the current random bit sequence.

[0052] In some examples, random number detection is a chi-square test, and the sum of squares threshold is determined based on the expected occurrence count E of M bit permutation features in a random bit sequence of length N*M. For example, the expected occurrence count of multiple bit permutation features varies depending on the length of the random bit sequence, and the expected occurrence count of multiple bit permutation features in the target random bit sequence when the current random bit sequence reaches the target random bit sequence has high reference value. Furthermore, the expected occurrence count of multiple bit permutation features in the current random bit sequence can also be used as the expected occurrence count of multiple bit permutation features.

[0053] Even if the current random bit sequence has not reached the target random bit sequence, it is still permissible to use the expected number of occurrences of the target random bit sequence. For example, if the current random bit sequence is 512 bits, the sequence increment is 4 bits, and the target random bit sequence is 516 bits, chi-square detection of the current random bit sequence can still be achieved.

[0054] In chi-square detection, it is necessary to calculate the square of the difference between the occurrence frequency of various bit permutation features and the expected occurrence frequency, i.e., = +2E +E 2 = +3E 2 For a random bit sequence of n predetermined bits, F(n) = Thus, chi-square detection based on the chi-square detection threshold can be converted into an iterative process of the sum of squares. Accordingly, when performing the chi-square detection process of the present invention, if the sum of squares is less than the preset sum of squares threshold, the chi-square detection passes; if the sum of squares is greater than the preset sum of squares threshold, the chi-square detection fails.

[0055] It should be understood that the sum of squares threshold here can be calculated based on the chi-square detection threshold and the expected number of occurrences E, achieving an equivalent transformation to chi-square detection based on the chi-square detection threshold.

[0056] In one example, when the current random bit sequence is the target random bit sequence, the chi-square detection result is obtained by comparing the current sum of squares with the preset sum of squares.

[0057] In the embodiment of the present invention, the adder obtains the previous occurrence count and previous sum of squares of the bit arrangement characteristics of the sequence increment from the register, and processes the previous occurrence count and previous sum of squares through a summation operation to obtain the current sum of squares. This reduces the hardware performance requirements in the sum of squares calculation process and improves the efficiency of random number detection. In some examples, the shifter is implemented as a shift register, the shift register stores a previous random bit sequence, and updates the previous random bit sequence with a current random bit sequence, and the use of the shift register improves the efficiency of both shift operations and storage operations.

[0058] In other examples, the shift register stores a previous random bit sequence with a sequence length of m*(n-1). m is a preset number of bits, and n is an identifier for sequence sorting. The shift register adds a sequence increment of m bits on the basis of the previous random bit sequence to obtain a current random bit sequence with a sequence length of m*n. Specifically, the shift unit of the shift register may be m or a divisor of m.

[0059] Further, the first register may store a plurality of previous occurrence counts f(i) of multiple bit arrangement features, the number of the multiple bit arrangement features is M, and n= , 1≤i≤M. The first register may be implemented as M counters, which respectively store M bit arrangement features.

[0060] Correspondingly, the adder may acquire the bit arrangement feature i0 of the sequence increment from the first register, and calculate the previous occurrence count f(i0) of the bit arrangement feature i0 in the previous random bit sequence.

[0061] When calculating the current sum of squares, F(n-1) may be stored through the second register as the previous sum of squares of the previous random bit sequence with a sequence length of m*(n-1), then the adder calculates F(n)=F(n-1)+2f(i0)+1 as the current sum of squares. Accordingly, based on the sum of squares formula, there is no need for the digital circuit of the sum of squares calculator to perform cumbersome and inefficient calculations, and the sum of squares calculation is efficiently implemented only by using the adder.

[0062] In addition, the cooperation between the shift register and the comparator is as follows: the shift register determines whether n=N, and causes the comparator to output a random number detection result of the current random bit sequence when n=N, where 1≤n≤N, and N is a positive integer. Correspondingly, when n<N, the shift register updates the current random bit sequence based on the sequence increment obtained by shifting the current random bit sequence by a preset number of bits, and then the above process can be continued for the next random bit sequence until the length of the random bit sequence is m*N.

[0063] An embodiment of the present invention further provides a system on chip, comprising Figure 2 the random number detection apparatus described above.

[0064] In the following, chi-square detection is taken as an example in conjunction with Figure 3 further describing Figure 2The operation process of the random number detection device. The chi-square detection method in this example can be performed by an online detection device or component such as online detector 130, and includes the following steps: S310: Start online detection.

[0065] S320: Shift i bits using a shift register and continue execution of S330. It should be understood that i is equal to m or a divisor of m.

[0066] S330: Determine if the current shifted bit count has reached m bits. If yes, proceed to S340; otherwise, return to S320. That is, when m bits are reached, obtain the current random bit sequence; if m bits are not reached, continue shifting until the accumulated shifted bit count reaches the sequence increment. As an example, m is 4.

[0067] S340: Obtain f(i) from the i-th counter among the M counters and continue to S350. Specifically, the M counters can be an example of a first register. For example, the occurrence counts of the M bit permutation features are counted by M counters (e.g., registers), and are respectively labeled 1 to M. Whenever the current shift bit number reaches m bits, that is, determine which of the M-th bit permutation features formed by these m bits corresponds to, and increment the corresponding counter by 1 accordingly. In addition, a second register can be maintained to store F(n), and the value of F(n) is updated in each iteration (i.e., every m-bit shift). The second register can also be implemented as a counter.

[0068] This step can serve as an example of determining the increment of the previous occurrence count, which is stored in the i-th counter. Then, a linear calculation can be performed based on the increment of the occurrence count to obtain the sum of squares increment 2f(i) + 1 between the current sum of squares and the previous sum of squares. The first and second registers can be connected to the adder respectively. The second register is used by the adder to read F(n-1) and then write F(n). The first register is used by the adder to read the previous occurrence count of the bit permutation feature of the current sequence increment and increment the previous occurrence count of the corresponding bit permutation feature by 1, updating the previous occurrence count.

[0069] The first register is used to store f(i), and it can be connected to an adder. To calculate 2f(i) + 1, the adder can read f(i) twice from the first register and the resulting binary bit with a value of 1 for summation, i.e., f(i) + f(i) + 1.

[0070] S350: Calculate F(n) and continue to S360. This step can serve as an example of determining the current sum of squares based on the previous sum of squares and the increment of that sum of squares. The second register is connected to the adder. Before or after calculating 2f(i) + 1, the adder reads F(n-1) from the second register, and then sums 2f(i) + 1 and F(n-1) to obtain F(n). Further, as n = n + 1, the current random bit sequence is updated to the next random bit sequence, and the above calculation is recursively performed to obtain F(n+1) until F(N) of the target random bit sequence is calculated.

[0071] It should also be understood that the first register, the second register, and the adder mentioned above can all be physical digital circuits, avoiding complex digital circuits used for square calculations, and greatly reducing the area overhead of hardware circuits while ensuring computing performance.

[0072] S360: Determine whether the current sum of squares F(N) of the target random bit sequence satisfies the sum of squares threshold. If yes, proceed to S390; otherwise, proceed to S380. This step can be implemented using a comparator. As an example of performing chi-square detection on the current random bit sequence, the sum of squares threshold can be determined based on the variance threshold of the chi-square detection and the expected number of occurrences.

[0073] S370: Detection passed, and detection ended.

[0074] S380: The test failed. Return to execute S310.

[0075] In addition, based on the execution result of the shifter in step S330, it can be determined whether the length of the current random bit sequence has reached the length of the target random bit sequence. If so, a control command to output the detection result is sent to the comparator. When the random number detection passes, the comparator directly outputs the detection result.

[0076] In addition, the shifter can also receive a restart detection command sent by the comparator when the random number detection fails, and the shifter is reset to zero accordingly.

[0077] Furthermore, embodiments of the present invention also provide encryption methods corresponding to the chi-square detection method, such as... Figure 4 As shown. The encryption method can be physically implemented using analog and / or digital circuits, and can optionally be driven by firmware and / or software. For example, the circuit can be implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The encryption method of this embodiment can be integrated with... Figure 2 The random number detection methods used, such as the chi-square test, include: S410: Retrieve the pre-stored object to be encrypted.

[0078] S420: Obtain the current random bit sequence by incrementing the sequence by a preset number of bits.

[0079] S430: Perform chi-square detection on the current random bit sequence of the sequence increment to obtain the target random bit sequence.

[0080] S440: Based on the application of the target random bit sequence of the sequence increment to the encryption algorithm, the sequence increment is processed on the object to be encrypted.

[0081] It should be understood that the chi-square test here can be used... Figure 2 The random number detection device executes a detection method, and the encryption method includes, but is not limited to, encryption methods that employ the target random bit sequence, such as the signature process and encryption process, for example, elliptic curve cryptography algorithms such as the SM2 encryption algorithm. The sum of squares increment between the current sum of squares and the previous sum of squares is obtained by linearly calculating the number of previous occurrences of the target bit permutation feature of the sequence increment, which reduces the hardware performance requirements in the sum of squares calculation process. In addition, based on the sum of squares increment, chi-square detection can be performed iteratively on the current random bit sequence, that is, it is not necessary to perform chi-square detection after obtaining the target random bit sequence, which improves the efficiency of chi-square detection. Correspondingly, it improves the efficiency of generating the target random bit sequence, and thus improves the encryption processing efficiency of applying the target random bit sequence.

[0082] Figure 5 This is a flowchart illustrating the steps of a random number detection method according to another embodiment of the present invention. The random number detection method of this embodiment can be physically implemented using analog and / or digital circuitry, and can optionally be driven by firmware and / or software. For example, the circuitry can be implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry constituting the block can be implemented by dedicated hardware or a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block.

[0083] The random number detection method in this embodiment includes: S510: Based on the sequence increment of shifting a previous random bit sequence by a preset number of bits, the current random bit sequence is obtained, wherein the preset number of bits corresponds to various bit permutation features.

[0084] S520: Determine the number of previous occurrences of various bit permutation features in a previous random bit sequence, and the sum of the squares of the previous occurrences.

[0085] S530: Perform a summation operation based at least on the previous occurrence counts of the bit permutation features of the previous sum of squares and the sequence increment to obtain the current sum of squares, wherein the current sum of squares indicates the sum of the squares of the multiple current occurrence counts of various bit permutation features in the current random bit sequence.

[0086] S540: Compare the current sum of squares with the preset sum of squares threshold, and perform random number detection on the current random bit sequence.

[0087] In other examples, the random number detection method further includes: storing the previous random bit sequence and updating the previous random bit sequence with the current random bit sequence.

[0088] In other examples, storing the previous random bit sequence includes: storing a previous random bit sequence of length m*(n-1), where m is a preset number of bits and n is a sequence arrangement identifier. Obtaining the current random bit sequence by shifting the previous random bit sequence by a preset number of bits includes: adding an m-bit sequence increment to the previous random bit sequence to obtain the current random bit sequence of length m*n.

[0089] In other examples, determining the number of previous occurrences of multiple bit permutation features in a previous random bit sequence includes: obtaining the number of previous occurrences f(i) of a stored set of multiple bit permutation features, where the number of multiple bit permutation features is M, and n = , 1≤i≤M.

[0090] In other examples, the random number detection method further includes: obtaining the bit permutation feature i0 of the sequence increment, and calculating the number of previous occurrences f(i0) of the bit permutation feature i0 in the previous random bit sequence.

[0091] In other examples, the random number detection method further includes: obtaining the stored F(n-1) as the previous sum of squares of a previous random bit sequence of length m*(n-1); and calculating F(n) = F(n-1) + 2f(i0) + 1 as the current sum of squares.

[0092] In other examples, the current sum of squares is compared with a preset sum of squares threshold, and random number detection of the current random bit sequence is performed, including: determining whether n=N, and outputting the random number detection result of the current random bit sequence if n=N, where 1≤n≤N and N is a positive integer.

[0093] In other examples, comparing the current sum of squares with a preset sum-of-squares threshold to perform random number detection on the current random bit sequence further comprises: in the case of n<N, updating the current random bit sequence based on a sequence increment obtained by shifting the current random bit sequence by the preset number of bits.

[0094] In other examples, the random number detection is a chi-square detection, and the sum-of-squares threshold is determined based on the expected occurrence count E of M bit permutation features in a random bit sequence with a sequence length of N*M.

[0095] The random number detection method of this embodiment corresponds to a random number detection apparatus, and has the corresponding beneficial effects of the method embodiment, which will not be repeated herein.

[0096] It should be noted that according to implementation requirements, each component / step described in the embodiments of the present invention may be split into more components / steps, or two or more components / steps or partial operations of components / steps may be combined into a new component / step, so as to achieve the purpose of the embodiments of the present invention.

[0097] The method according to the above embodiments of the present invention may be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as computer code that is originally stored on a remote recording medium or a non-transitory machine-readable medium to be downloaded via a network and to be stored in a local recording medium, such that the methods described herein can be processed by such software stored on the recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (for example, RAM, ROM, flash memory, etc.) that can store or receive software or computer code, which when accessed and executed by the computer, processor or hardware, implements the methods described herein. In addition, when a general-purpose computer accesses code for implementing the methods shown herein, execution of the code converts the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0098] A person of ordinary skill in the art may realize that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software mode depends on the specific application and design constraint conditions of the technical solution. A person skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to fall beyond the scope of the embodiments of the present invention.

[0099] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A random number detection apparatus, comprising: a shifter, configured to shift a sequence increment of a preset number of bits based on a previous random bit sequence to obtain a current random bit sequence, wherein the preset number of bits corresponds to a plurality of bit permutation features; a first register, configured to store a plurality of previous occurrence counts of the plurality of bit permutation features in the previous random bit sequence; a second register, configured to store a previous sum of squares of the plurality of previous occurrence counts; an adder, configured to obtain the previous occurrence count of the bit permutation feature of the sequence increment from the first register, obtain the previous sum of squares from the second register, perform a summation operation at least based on the previous sum of squares and the previous occurrence count to obtain a current sum of squares, and update the current sum of squares into the second register, wherein the current sum of squares indicates a sum of squares of a plurality of current occurrence counts of the plurality of bit permutation features in the current random bit sequence; a comparator, configured to compare the current sum of squares with a preset sum-of-squares threshold, and perform random number detection on the current random bit sequence.

2. The random number detection device according to claim 1, wherein, The shifter is a shift register: the shift register stores the previous random bit sequence, and updates the previous random bit sequence with the current random bit sequence.

3. The random number detection device according to claim 2, wherein, The shift register stores the previous random bit sequence with a sequence length of m*(n-1), wherein m is the preset number of bits, and n is an identifier of sequence sorting; wherein the shift register adds a sequence increment of m bits on the basis of the previous random bit sequence, to obtain the current random bit sequence with a sequence length of m*n.

4. The random number detection device according to claim 3, wherein, The first register stores multiple previous occurrence counts f(i) of the various bit arrangement features, where the number of such features is M, and n = , 1≤i≤M.

5. The random number detection device according to claim 4, wherein, The adder acquires the bit permutation feature i0 of the sequence increment from the first register, and calculates the previous occurrence count f(i0) of the bit permutation feature i0 in the previous random bit sequence.

6. The random number detection device according to claim 3, wherein, The second register stores F(n-1) as the previous sum of squares of the previous random bit sequence with the sequence length of m*(n-1); The adder calculates F(n)=F(n-1)+2f(i0)+1 as the current sum of squares.

7. The random number detection device according to claim 3, wherein, The shift register determines whether n=N, and in response to n=N, causes the comparator to output a random number detection result of the current random bit sequence, wherein 1≤n≤N, and N is a positive integer.

8. The random number detection device according to claim 7, wherein, In response to n<N, the shift register shifts the sequence increment of the preset number of bits based on the current random bit sequence, to update the current random bit sequence.

9. The random number detection device according to claim 7, wherein, The random number detection is chi-square detection, and the sum-of-squares threshold is determined based on the expected occurrence count E of M bit permutation features in a random bit sequence with a sequence length of N*M.

10. A system on chip, comprising: the random number detection apparatus according to any one of claims 1 to 9.

11. A random number detection method, comprising: shifting a sequence increment of a preset number of bits based on a previous random bit sequence to obtain a current random bit sequence, wherein the preset number of bits corresponds to a plurality of bit permutation features; Determine the number of previous occurrences of the various bit arrangement features in the preceding random bit sequence, and the sum of the squares of the previous occurrences; A summation operation is performed based at least on the previous sum of squares and the previous occurrence counts of the bit arrangement features of the sequence increment to obtain the current sum of squares, wherein the current sum of squares indicates the sum of squares of the multiple current occurrence counts of the various bit arrangement features in the current random bit sequence; Compare the current sum of squares with a preset sum of squares threshold, and perform random number detection on the current random bit sequence.

12. An encryption method, comprising: Retrieve the pre-stored object to be encrypted; The current random bit sequence is obtained by incrementing the sequence by a preset number of bits. A random number detection device is used to perform chi-square detection on the current random bit sequence to obtain a target random bit sequence, wherein the random number detection device is the random number detection device according to any one of claims 1-9; The target random bit sequence is applied to the encryption algorithm to process the object to be encrypted.

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