Method and apparatus for generating a simulation stimulus file

Abstract

Provided in the embodiments of the present disclosure are a simulation excitation file generation method and device, relating to the technical field of semiconductors, comprising: determining a timing characteristic text corresponding to a circuit under test, the timing characteristic text comprising an excitation start identifier and an excitation end identifier; simulating the circuit under test based on the timing characteristic text, and obtaining an excitation start time and an excitation end time according to the time corresponding to the excitation start identifier and the excitation end identifier in the simulation result; generating an excitation sampling file according to the excitation start time, the excitation end time, and a preset excitation signal list; and sampling the preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file. The simulation excitation file generation method and device provided in the embodiments of the present disclosure can efficiently and accurately generate a simulation excitation file, and improve the efficiency of integrated circuit verification.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for generating simulation stimulus files. Background Technology

[0002] Currently, when verifying integrated circuits, simulation stimulus files are typically used as inputs to the integrated circuit. Then, the functionality of the integrated circuit is determined by comparing its output data with the expected simulation data.

[0003] As integrated circuit design and verification systems become increasingly large and complex, existing methods for generating simulation stimulus files are revealing more and more shortcomings, such as long generation times, high labor costs, and susceptibility to errors. Therefore, how to efficiently and accurately generate simulation stimulus files is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a method and apparatus for generating simulation stimulus files, which can generate simulation stimulus files efficiently and accurately, thereby improving the efficiency of integrated circuit verification.

[0005] In a first aspect, embodiments of this disclosure provide a method for generating simulation stimulus files, the method comprising:

[0006] The circuit under test is simulated based on the timing feature text, and the excitation start time and excitation end time are obtained according to the time corresponding to the excitation start marker and the excitation end marker in the simulation results.

[0007] An excitation sampling file is generated based on the excitation start time, the excitation end time, and a preset excitation signal list;

[0008] The preset excitation signal is sampled according to the excitation sampling file to generate the corresponding simulation excitation file.

[0009] In one feasible implementation, determining the timing feature text corresponding to the circuit under test includes:

[0010] Obtain the original timing feature text corresponding to the circuit under test, and add the excitation start identifier and the excitation end identifier to the timing start position and the timing end position of the original timing feature text, respectively, to obtain the timing feature text.

[0011] In one feasible implementation, the step of sampling the preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file includes:

[0012] The preset excitation signal is sampled based on the excitation sampling file to generate a first file;

[0013] The first file is adjusted according to the simulation stimulus file format that the target simulation tool can recognize to obtain the simulation stimulus file.

[0014] In one feasible implementation, before simulating the circuit under test based on the timing feature text, the method further includes:

[0015] The simulation clock signal of the circuit under test is determined during the simulation process. The frequency of the simulation clock signal is N times the frequency of the clock signal used when the circuit under test is in a preset working mode; where N is a positive integer.

[0016] In one feasible implementation, adjusting the first file according to a simulation stimulus file format recognizable by the target simulation tool includes:

[0017] Delete the sampled value corresponding to the simulation clock signal in the first file;

[0018] Adjust the excitation times in the first file according to the duration of the initialization process corresponding to the target simulation tool;

[0019] Add vector timing feature definition data and waveform parameter setting data to the first file.

[0020] In one feasible implementation, it further includes:

[0021] Determine the operation time of each command in the time-series feature text;

[0022] Based on the operation time of each command and the various excitation times in the simulation excitation file, the commands are added to the simulation excitation file.

[0023] In one feasible implementation, before simulating the circuit under test based on the timing feature text, the method further includes:

[0024] Determine the expected simulation data corresponding to the time series feature text, and add the expected simulation data to the time series feature text;

[0025] After simulating the circuit under test based on the timing feature text, the method further includes:

[0026] Based on the keywords corresponding to the expected simulation data, the expected simulation data is obtained from the simulation results.

[0027] In one feasible implementation, it further includes:

[0028] The simulation stimulus file is verified based on the command truth table corresponding to the preset excitation signal and / or the expected simulation data.

[0029] Secondly, embodiments of this disclosure provide an apparatus for generating simulation stimulus files, comprising:

[0030] The determination module is used to determine the timing feature text corresponding to the circuit under test, wherein the timing feature text includes an excitation start identifier and an excitation end identifier;

[0031] The simulation module is used to simulate the circuit under test based on the timing feature text, and to obtain the excitation start time and excitation end time according to the time corresponding to the excitation start marker and the excitation end marker in the simulation results.

[0032] The first processing module is used to generate an excitation sampling file based on the excitation start time, the excitation end time, and a preset excitation signal list;

[0033] The second processing module is used to sample the preset excitation signal according to the excitation sampling file and generate the corresponding simulation excitation file.

[0034] In one feasible implementation, the determining module is used to:

[0035] Obtain the original timing feature text corresponding to the circuit under test, and add the excitation start identifier and the excitation end identifier to the timing start position and the timing end position of the original timing feature text, respectively, to obtain the timing feature text.

[0036] In one feasible implementation, the second processing module is used to:

[0037] The preset excitation signal is sampled based on the excitation sampling file to generate a first file;

[0038] The first file is adjusted according to the simulation stimulus file format that the target simulation tool can recognize to obtain the simulation stimulus file.

[0039] In one feasible implementation, a clock module is also included for:

[0040] The simulation clock signal of the circuit under test is determined during the simulation process. The frequency of the simulation clock signal is N times the frequency of the clock signal used when the circuit under test is in a preset working mode; where N is a positive integer.

[0041] In one feasible implementation, the second processing module is used to:

[0042] Delete the sampled value corresponding to the simulation clock signal in the first file;

[0043] Adjust the excitation times in the first file according to the duration of the initialization process corresponding to the target simulation tool;

[0044] Add vector timing feature definition data and waveform parameter setting data to the first file.

[0045] In one feasible implementation, the second processing module is further configured to:

[0046] Determine the operation time of each command in the time-series feature text;

[0047] Based on the operation time of each command and the various excitation times in the simulation excitation file, the commands are added to the simulation excitation file.

[0048] In one feasible implementation, the determining module is further configured to:

[0049] Determine the expected simulation data corresponding to the time series feature text, and add the expected simulation data to the time series feature text;

[0050] The simulation module is also used for:

[0051] Based on the keywords corresponding to the expected simulation data, the expected simulation data is obtained from the simulation results.

[0052] In one feasible implementation, a verification module is also included, for:

[0053] The simulation stimulus file is verified based on the command truth table corresponding to the preset excitation signal and / or the expected simulation data.

[0054] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;

[0055] The memory stores computer-executed instructions;

[0056] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to execute the simulation stimulus file generation method provided in the first aspect.

[0057] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the simulation stimulus file generation method provided in the first aspect.

[0058] The simulation stimulus file generation method and apparatus provided in this disclosure add stimulus start and stimulus end markers to the timing feature text corresponding to the circuit under test. After simulating the circuit under test based on the timing feature text, the stimulus start time and stimulus end time can be obtained according to the times corresponding to the stimulus start and stimulus end markers in the simulation results. Based on the stimulus start time, stimulus end time and a preset stimulus signal list, a stimulus sampling file is generated. By sampling the preset stimulus signals according to the stimulus sampling file, the corresponding simulation stimulus file can be automatically generated. This can effectively save a lot of time and manpower, reduce the possibility of errors, and improve the efficiency of integrated circuit verification. Attached Figure Description

[0059] Figure 1 This is a flowchart illustrating the steps of a method for generating simulation stimulus files provided in this embodiment. Figure 1 ;

[0060] Figure 2 This is a flowchart illustrating the steps of a method for generating simulation stimulus files provided in this embodiment. Figure 2 ;

[0061] Figure 3 This is a flowchart illustrating the steps of a method for generating simulation stimulus files provided in this embodiment. Figure 3 ;

[0062] Figure 4 This is a schematic diagram of the program modules of a simulation stimulus file generation device provided in an embodiment of the present disclosure;

[0063] Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0065] It should be noted that the brief description of terms in the present disclosure is only for facilitating understanding of the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise stated, these terms shall be understood according to their ordinary and common meanings.

[0066] In the present disclosure, the terms "first", "second", etc. in the description, claims, and the above drawings are used to distinguish similar or homogeneous objects or entities, and do not necessarily mean limiting a specific order or sequence, unless otherwise stated. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, for example, the implementation can be performed according to an order other than that illustrated or described in the embodiments of the present disclosure.

[0067] In addition, the terms "comprise" and "have", and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a product or device comprising a series of components is not necessarily limited to those components explicitly listed, but may include other components not explicitly listed or inherent to the product or device.

[0068] The term "module" used in the embodiments of the present disclosure refers to any currently known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or a combination of hardware and / or software code that can perform the function related to the element.

[0069] The embodiments of the present disclosure can be applied to the technical field of semiconductors, for example, can be applied to the design and verification process of integrated circuits.

[0070] Among them, design and verification of integrated circuits is an important link in integrated circuit production, and all integrated circuits can only be put on the market after it is confirmed that their functions and performance meet the requirements.

[0071] At present, when performing integrated circuit verification, a simulation stimulus file is usually used as the input of the integrated circuit, and then the output data of the integrated circuit is compared with expected simulation data. If the output data of the integrated circuit is consistent with the expected simulation data, the test result is determined to be qualified; if the output result of a certain signal in a certain cycle is different from the expected simulation data, the test result is determined to be unqualified.

[0072] Among them, the simulation stimulus (also called testbench) file is very important for the design and verification of integrated circuits, and it is the basis and input file for the entire verification process. The most basic structure of a simulation stimulus file includes Vector Pattern Definition, Waveform Parameter Settings and Tabular Data.

[0073] As integrated circuit design and verification systems become increasingly large and complex, existing methods for generating simulation stimulus files are revealing more and more shortcomings, such as long generation time, high manpower costs, and susceptibility to errors.

[0074] To address the aforementioned technical problems, this disclosure provides a method for generating simulation stimulus files, which can quickly generate simulation stimulus files, thereby effectively saving significant time and manpower, reducing the possibility of errors, and improving the efficiency of integrated circuit verification. Detailed procedures can be found in the following embodiments.

[0075] Reference Figure 1 , Figure 1 This is a flowchart illustrating the steps of a method for generating simulation stimulus files provided in this embodiment. Figure 1 In some embodiments of this disclosure, the method for generating the simulation stimulus file includes:

[0076] S101. Determine the timing feature text corresponding to the circuit under test. The timing feature text includes an excitation start marker and an excitation end marker.

[0077] The aforementioned timing feature text, also known as the pattern text, contains the command timing sequence corresponding to the circuit under test (DUT). During the DUT simulation process, the Automated Test Equipment (ATE) sends a series of commands to the DUT and then compares the output timing sequence of the DUT with the expected simulation data to determine whether the DUT meets its functional requirements.

[0078] In one feasible implementation, a start excitation marker and an end excitation marker are pre-added to the timing feature text corresponding to the circuit under test. The start excitation marker is added to the timing feature text at the start of the simulation, and the end excitation marker is added to the timing feature text at the end of the simulation.

[0079] In some embodiments of this disclosure, the timing feature text includes a simulation start command and a simulation end command. During the simulation of the circuit under test (DUT), when the simulation tool reaches the simulation start command, it begins inputting waveforms to the DUT; when the simulation tool reaches the simulation end command, it stops inputting waveforms to the DUT, thereby ending the simulation. Optionally, the excitation start identifier can be located in the line containing the simulation start command in the timing feature text, and the excitation end identifier can be located in the line containing the simulation end command in the timing feature text.

[0080] In some embodiments of this disclosure, the aforementioned time-series feature text can be written based on the Verilog language.

[0081] S102. Based on the above timing feature text, the circuit under test is simulated, and the excitation start time and excitation end time are obtained according to the time corresponding to the excitation start flag and excitation end flag in the simulation results.

[0082] In some embodiments of this disclosure, a pre-set simulation tool can be used to simulate the circuit under test based on the aforementioned timing feature text, and simulation results can be obtained.

[0083] Optionally, the simulation tools mentioned above can be sign-off tools capable of performing logic and timing verification, such as the Finesim simulator, etc., which are not limited here.

[0084] In some embodiments of this disclosure, after obtaining the simulation results, the above-mentioned stimulus start identifier and stimulus end identifier are found in the simulation result log file. Based on the time points corresponding to the above-mentioned stimulus start identifier and stimulus end identifier in the simulation result log file, the above-mentioned stimulus start time and stimulus end time are determined.

[0085] S103. Generate an excitation sampling file based on the excitation start time, excitation end time, and preset excitation signal list.

[0086] In some embodiments of this disclosure, the above-mentioned stimulus sampling file can be a script file written in Verilog language.

[0087] In some embodiments of this disclosure, the above-mentioned excitation sampling file defines a sampling start time, a sampling end time, and the names of the signals to be sampled. The sampling start time is the same as the excitation start time, and the sampling end time is the same as the excitation end time; the names of the signals to be sampled are consistent with the names in the preset excitation signal list.

[0088] S104. Sample the preset excitation signal according to the excitation sampling file to generate the corresponding simulation excitation file.

[0089] In some embodiments of this disclosure, the simulation waveform of the preset excitation signal can be sampled based on the above-mentioned excitation sampling file, and a first file can be generated according to the sampling results. Then, the format of the first file can be adjusted according to the simulation excitation file format that the target simulation tool can recognize, so as to obtain the corresponding simulation excitation file.

[0090] In some embodiments, the first file described above can be a comma-separated values ​​(CSV) file. A CSV file typically stores tabular data (numbers and text) in plain text format, meaning the file is a sequence of characters and does not contain data that must be interpreted like binary numbers. Furthermore, a CSV file typically consists of any number of records, separated by some kind of newline character; each record consists of fields, separated by other characters or strings, most commonly commas or tabs, and all records have the exact same sequence of fields.

[0091] For example, the target simulation tool mentioned above can be the Finesim simulator. Since the generated first file is not a stimulus file format that the Finesim simulator can directly recognize, the first file can be adjusted according to a stimulus file format that the Finesim simulator can recognize, and the adjusted first file can be used as a simulation stimulus file that the simulator can recognize.

[0092] It is understandable that the above steps S102 to S104 can be executed automatically by script programs without human intervention. Therefore, for generating a large number of simulation stimuli, the automated mode can effectively save manpower and reduce the possibility of errors.

[0093] The simulation stimulus file generation method provided in this embodiment adds stimulus start and stimulus end markers to the timing feature text corresponding to the circuit under test. After simulating the circuit under test based on the timing feature text, the stimulus start time and stimulus end time can be obtained according to the times corresponding to the stimulus start and stimulus end markers in the simulation results. Based on the stimulus start time, stimulus end time, and a preset stimulus signal list, a stimulus sampling file is generated, and the preset stimulus signals are sampled according to the stimulus sampling file. The corresponding simulation stimulus file can be automatically generated, thereby effectively saving a lot of time and manpower, reducing the possibility of errors, and improving the efficiency of integrated circuit verification.

[0094] Based on the content described in the above embodiments, referring to Figure 2 , Figure 2 This is a flowchart illustrating the steps of a method for generating simulation stimulus files provided in this embodiment. Figure 2 In some embodiments of this disclosure, the method for generating the simulation stimulus file includes:

[0095] S201. Complete the preset preparation work.

[0096] In one feasible implementation, the above-mentioned preparatory work includes:

[0097] 1. Determine the simulation clock signal of the circuit under test during the simulation process. The frequency of the simulation clock signal is N times the frequency of the clock signal used when the circuit under test is in the preset working mode; where N is a positive integer.

[0098] Optionally, the frequency of the simulated clock signal can be twice the frequency of the clock signal used when the circuit under test is in its fastest operating mode.

[0099] It is understood that the embodiments of this disclosure use a frequency-doubled simulated clock signal to simulate the circuit under test, which can increase the number of signal sampling points in the simulation process, ensure the integrity of the sampling points, and obtain the timing sequence of the excitation signal more accurately.

[0100] 2. Obtain the original timing feature text corresponding to the circuit under test, and add excitation start marker and excitation end marker to the timing start position and timing end position of the original timing feature text respectively to obtain the timing feature text.

[0101] In some embodiments of this disclosure, it is assumed that the timing feature text includes the simulation start command "PWRUP4FSM(150)" and the simulation end command (DESELECT_CMD(20)). During the simulation of the circuit under test, when the simulation tool reaches the simulation start command, it begins to input corresponding commands to the circuit under test, including Mode Register Setting (MRS) initialization, read / write commands, etc.; when the simulation tool reaches the simulation end command, it stops inputting commands to the circuit under test, thereby ending the simulation. The excitation start identifier can be located in the line containing the simulation start command in the timing feature text, and the excitation end identifier can be located in the line containing the simulation end command in the timing feature text.

[0102] For example, assuming the above-mentioned stimulus start identifier is "Simulation Start" and the above-mentioned stimulus end identifier is "Simulation Done", then the above-mentioned time-series feature text may contain the following:

[0103]

[0104]

[0105] In some embodiments of this disclosure, after determining the timing feature text corresponding to the circuit under test, the expected simulation data corresponding to the timing feature text can be further determined.

[0106] In some embodiments of this disclosure, the aforementioned expected simulation data can be added to the aforementioned time-series feature text.

[0107] 3. Determine the list of excitation signals that need to be generated.

[0108] In some embodiments of this disclosure, the signals involved in the simulation stimulus file to be generated can be determined in advance, and then a list of stimulus signals can be determined. The list of stimulus signals includes the signal names of each signal involved in the simulation stimulus file, so as to extract the corresponding signals from the simulation waveform.

[0109] S202, Simulate the circuit under test.

[0110] In some embodiments of this disclosure, a pre-set simulation tool can be used to simulate the circuit under test based on the aforementioned timing feature text, and simulation results can be obtained.

[0111] Optionally, the simulation tool mentioned above can be the Finesim simulator.

[0112] S203. Process the simulation results to obtain the excitation start time and excitation end time.

[0113] In some embodiments of this disclosure, after obtaining the simulation results, the above-mentioned stimulus start identifier and stimulus end identifier are found in the simulation result log file, and the above-mentioned stimulus start time and stimulus end time are determined according to the time points corresponding to the above-mentioned stimulus start identifier and stimulus end identifier in the simulation result log file.

[0114] For example, suppose the simulation result log file is as follows:

[0115] 203988125.0ps:top.PWRUP4FSM DESELECT cycle is 170

[0116] 203988125.0ps:top.PWRUP4FSM Simulation Start

[0117] ...

[0118] 205135625.0ps:top.sample_Simulation===Simulation Done===

[0119] ...

[0120] The excitation start time can be determined as "203988125.0ps" by identifying the excitation start marker "Simulation Start" in the simulation results; and the excitation end time can be determined as "205135625ps" by identifying the excitation end marker "Simulation Done" in the simulation results.

[0121] In some embodiments of this disclosure, when the expected simulation data is added to the time-series feature text, the expected simulation data can also be obtained from the simulation results by identifying the keywords (such as FINESIM_CHECKER) corresponding to the expected simulation data in the simulation results.

[0122] S204. Generate an excitation sampling file based on the excitation start time, excitation end time, and preset excitation signal list.

[0123] In some embodiments of this disclosure, the above-mentioned stimulus sampling file can be a script file written in Verilog language.

[0124] The aforementioned excitation sampling file defines the sampling start time, sampling end time, and the names of the signals to be sampled. Specifically, the sampling start time is the same as the excitation start time, and the sampling end time is the same as the excitation end time; the names of the signals to be sampled are consistent with the names in the aforementioned preset excitation signal list.

[0125] S205. Based on the above-mentioned excitation sampling file, the preset excitation signal is sampled, and a first file is generated according to the sampling results.

[0126] In some embodiments, the first file mentioned above may be a CSV file.

[0127] S206. Adjust the first file according to the simulation stimulus file format that the target simulation tool can recognize to obtain the simulation stimulus file.

[0128] In some embodiments of this disclosure, the target simulation tool can be the Finesim simulator. Since the generated CSV file is not a stimulus file format that the Finesim simulator can directly recognize, the first file can be adjusted according to a stimulus file format that the Finesim simulator can recognize, and the adjusted first file can be used as a simulation stimulus file that the simulator can recognize.

[0129] In one feasible implementation, if the first file is a CSV file and the target simulation tool is the Finesim simulator, the first file can be adjusted according to the stimulus file format recognizable by the Finesim simulator using the following modifications:

[0130] (1) Delete the redundant identifier in the first line of the first file mentioned above.

[0131] (2) Replace the commas in the first file above with spaces.

[0132] (3) Delete the sampled values ​​corresponding to the above-mentioned simulation clock signal in the first file.

[0133] Since the simulated clock signal does not exist in the circuit under test and is only used to increase the number of sampling points, the two columns of sampled values ​​corresponding to the simulated clock signal in the first file can be deleted.

[0134] (4) Adjust the excitation times in the first file according to the duration of the initialization process corresponding to the target simulation tool.

[0135] In some embodiments of this disclosure, the various excitation times in the first file can be transformed into the time points of the initialization process corresponding to the deletion of the target simulation tool.

[0136] (5) Add vector pattern definition data and waveform parameter setting data to the first file.

[0137] After making the above modifications, you can obtain a simulation stimulus file that the Finesim simulator can recognize.

[0138] It is understandable that the above steps S202 to S106 can be executed automatically by script programs without human intervention. Therefore, for generating a large number of simulation stimuli, the automated mode can effectively save manpower and reduce the possibility of errors.

[0139] In some embodiments of this disclosure, a command truth table can be used to verify the generated simulation stimulus file and determine whether the generated simulation stimulus file is accurate.

[0140] The command truth table mentioned above can be used to define the relationship between the bits of the physical address and the command. The command includes activation command, read operation command, and write operation command, etc.

[0141] In some embodiments of this disclosure, the expected simulation data obtained from the simulation results can also be used to verify the generated simulation stimulus file and determine whether the generated simulation stimulus file is accurate.

[0142] In some embodiments of this disclosure, the above-mentioned command truth table and the above-mentioned expected simulation data can also be used simultaneously to verify the generated simulation stimulus file and determine whether the generated simulation stimulus file is accurate.

[0143] In some embodiments of this disclosure, if the generated simulation stimulus file contains errors, the generated simulation stimulus file can be corrected based on the above-described command truth table or the above-described expected simulation data.

[0144] The simulation stimulus file generation method provided in this disclosure can automatically generate and check the simulation stimulus file corresponding to the simulation waveform, thereby effectively saving a lot of time and manpower, reducing the possibility of errors, and improving the efficiency of integrated circuit verification.

[0145] Based on the content described in the above embodiments, referring to Figure 3 , Figure 3 This is a flowchart illustrating the steps of a method for generating simulation stimulus files provided in this embodiment. Figure 3 In some embodiments of this disclosure, the method for generating the simulation stimulus file includes:

[0146] S301. Determine the timing feature text corresponding to the circuit under test. The timing feature text includes an excitation start marker and an excitation end marker.

[0147] S302. Based on the above timing feature text, the circuit under test is simulated, and the excitation start time and excitation end time are obtained according to the time corresponding to the excitation start flag and excitation end flag in the simulation results.

[0148] S303. Generate an excitation sampling file based on the excitation start time, excitation end time, and preset excitation signal list.

[0149] S304. Sample the preset excitation signal according to the above excitation sampling file to generate the corresponding simulation excitation file.

[0150] The content executed in steps S301 to S304 is the same as that executed in steps S101 to S104, and can be referred to the description in the above embodiments, which will not be repeated here.

[0151] S305. Determine the operation time of each command in the above-mentioned timing feature text, and add the above-mentioned commands to the above-mentioned simulation stimulus file according to the operation time of each command and the stimulus time in the above-mentioned simulation stimulus file.

[0152] Understandably, one of the purposes of integrated circuit design verification is to detect bugs in the program running on the integrated circuit. In traditional techniques, during the debugging process after simulation, it is usually necessary to examine the signals in the simulation waveform of the circuit under test to determine what the command in the stimulus is at a certain moment, which is inefficient.

[0153] In some embodiments of this disclosure, each command is added to the simulation stimulus file based on the operation time of each command in the timing feature text. This allows for the determination of the command at a certain moment and the expected result directly from the simulation stimulus file without having to examine the signals in the simulation waveform during the troubleshooting process.

[0154] The simulation stimulus file generation method provided in this embodiment adds various commands from the timing feature text to the simulation stimulus file. Compared with ordinary simulation stimulus files, it can provide a reference for later circuit debugging and effectively improve debugging efficiency.

[0155] Based on the content described in the above embodiments, this disclosure also provides a device for generating simulation stimulus files, with reference to... Figure 4 , Figure 4 This is a schematic diagram of a program module for a simulation stimulus file generation device provided in this embodiment of the present disclosure. The simulation stimulus file generation device includes:

[0156] The determination module 401 is used to determine the timing feature text corresponding to the circuit under test, wherein the timing feature text includes an excitation start identifier and an excitation end identifier.

[0157] The simulation module 402 is used to simulate the circuit under test based on the timing feature text, and to obtain the excitation start time and excitation end time according to the time corresponding to the excitation start marker and the excitation end marker in the simulation results.

[0158] The first processing module 403 is used to generate an excitation sampling file based on the excitation start time, the excitation end time, and a preset excitation signal list.

[0159] The second processing module 404 is used to sample the preset excitation signal according to the excitation sampling file and generate the corresponding simulation excitation file.

[0160] In some embodiments of this disclosure, the determining module 401 is used to:

[0161] Obtain the original timing feature text corresponding to the circuit under test, and add the excitation start identifier and the excitation end identifier to the timing start position and the timing end position of the original timing feature text, respectively, to obtain the timing feature text.

[0162] In some embodiments of this disclosure, the second processing module 404 is used for:

[0163] The preset excitation signal is sampled based on the excitation sampling file to generate a first file;

[0164] The first file is adjusted according to the simulation stimulus file format that the target simulation tool can recognize to obtain the simulation stimulus file.

[0165] In some embodiments of this disclosure, a clock module is also included, for:

[0166] The simulation clock signal of the circuit under test is determined during the simulation process. The frequency of the simulation clock signal is N times the frequency of the clock signal used when the circuit under test is in a preset working mode; where N is a positive integer.

[0167] In some embodiments of this disclosure, the second processing module 404 is used for:

[0168] Delete the sampled value corresponding to the simulation clock signal in the first file;

[0169] Adjust the excitation times in the first file according to the duration of the initialization process corresponding to the target simulation tool;

[0170] Add vector timing feature definition data and waveform parameter setting data to the first file.

[0171] In some embodiments of this disclosure, the second processing module 404 is further configured to:

[0172] Determine the operation time of each command in the time-series feature text;

[0173] Based on the operation time of each command and the various excitation times in the simulation excitation file, the commands are added to the simulation excitation file.

[0174] In some embodiments of this disclosure, the determining module 401 is further configured to:

[0175] Determine the expected simulation data corresponding to the time series feature text, and add the expected simulation data to the time series feature text;

[0176] Simulation module 402 is also used for:

[0177] Based on the keywords corresponding to the expected simulation data, the expected simulation data is obtained from the simulation results.

[0178] In some embodiments of this disclosure, the above-described apparatus further includes a verification module, used for:

[0179] The simulation stimulus file is verified based on the command truth table corresponding to the preset excitation signal and / or the expected simulation data.

[0180] It should be noted that the specific execution of the determination module 401, simulation module 402, first processing module 403, and second processing module 404 in this embodiment can be found in the [reference needed]. Figures 1 to 3 The relevant content in the illustrated embodiments will not be repeated here.

[0181] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the simulation stimulus file generation method described in the above embodiments, which will not be repeated here.

[0182] To better understand the embodiments of this disclosure, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0183] like Figure 5 As shown, the electronic device 50 of this embodiment includes: a processor 501 and a memory 502; wherein:

[0184] Memory 502 is used to store instructions executed by the computer;

[0185] The processor 501 is used to execute computer execution instructions stored in the memory to implement the various steps in the simulation stimulus file generation method described in the above embodiments, and for details, please refer to the relevant descriptions in the foregoing method embodiments.

[0186] Alternatively, the memory 502 can be either standalone or integrated with the processor 501.

[0187] When the memory 502 is set up independently, the device also includes a bus 503 for connecting the memory 502 and the processor 501.

[0188] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When the processor executes the computer-executable instructions, it implements the various steps in the simulation stimulus file generation method described in the above embodiments. This embodiment will not repeat the details here.

[0189] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0190] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0191] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0192] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for generating simulation stimulus files, characterized in that, The method includes: Determine the timing feature text corresponding to the circuit under test, wherein the timing feature text includes an excitation start identifier and an excitation end identifier; The circuit under test is simulated based on the timing feature text, and the excitation start time and excitation end time are obtained according to the time corresponding to the excitation start marker and the excitation end marker in the simulation results. An excitation sampling file is generated based on the excitation start time, the excitation end time, and a preset excitation signal list; The preset excitation signal is sampled according to the excitation sampling file to generate the corresponding simulation excitation file.

2. The method according to claim 1, characterized in that, The determination of the timing feature text corresponding to the circuit under test includes: Obtain the original timing feature text corresponding to the circuit under test, and add the excitation start identifier and the excitation end identifier to the timing start position and the timing end position of the original timing feature text, respectively, to obtain the timing feature text.

3. The method according to claim 1, characterized in that, The step of sampling the preset excitation signal according to the excitation sampling file to generate a corresponding simulation excitation file includes: The preset excitation signal is sampled based on the excitation sampling file to generate a first file; The first file is adjusted according to the simulation stimulus file format that the target simulation tool can recognize to obtain the simulation stimulus file.

4. The method according to claim 3, characterized in that, Before simulating the circuit under test based on the timing feature text, the method further includes: The simulation clock signal of the circuit under test is determined during the simulation process. The frequency of the simulation clock signal is N times the frequency of the clock signal used when the circuit under test is in a preset working mode; where N is a positive integer.

5. The method according to claim 4, characterized in that, The step of adjusting the first file according to the simulation stimulus file format recognizable by the target simulation tool includes: Delete the sampled value corresponding to the simulation clock signal in the first file; Adjust the excitation times in the first file according to the duration of the initialization process corresponding to the target simulation tool; Add vector timing feature definition data and waveform parameter setting data to the first file.

6. The method according to claim 1, characterized in that, Also includes: Determine the operation time of each command in the time-series feature text; Based on the operation time of each command and the various excitation times in the simulation excitation file, the commands are added to the simulation excitation file.

7. The method according to claim 1, characterized in that, Before simulating the circuit under test based on the timing feature text, the method further includes: Determine the expected simulation data corresponding to the time series feature text, and add the expected simulation data to the time series feature text; After simulating the circuit under test based on the timing feature text, the method further includes: Based on the keywords corresponding to the expected simulation data, the expected simulation data is obtained from the simulation results.

8. The method according to claim 7, characterized in that, Also includes: The simulation stimulus file is verified based on the command truth table corresponding to the preset excitation signal and / or the expected simulation data.

9. A device for generating simulation stimulus files, characterized in that, include: The determination module is used to determine the timing feature text corresponding to the circuit under test, wherein the timing feature text includes an excitation start identifier and an excitation end identifier; The simulation module is used to simulate the circuit under test based on the timing feature text, and to obtain the excitation start time and excitation end time according to the time corresponding to the excitation start marker and the excitation end marker in the simulation results. The first processing module is used to generate an excitation sampling file based on the excitation start time, the excitation end time, and a preset excitation signal list; The second processing module is used to sample the preset excitation signal according to the excitation sampling file and generate the corresponding simulation excitation file.

10. The apparatus according to claim 9, characterized in that, The determining module is used for: Obtain the original timing feature text corresponding to the circuit under test, and add the excitation start identifier and the excitation end identifier to the timing start position and the timing end position of the original timing feature text, respectively, to obtain the timing feature text.

11. The apparatus according to claim 9, characterized in that, The second processing module is used for: The preset excitation signal is sampled based on the excitation sampling file to generate a first file; The first file is adjusted according to the simulation stimulus file format that the target simulation tool can recognize to obtain the simulation stimulus file.

12. The apparatus according to claim 11, characterized in that, It also includes a clock module, used for: The simulation clock signal of the circuit under test is determined during the simulation process. The frequency of the simulation clock signal is N times the frequency of the clock signal used when the circuit under test is in a preset working mode; where N is a positive integer.

13. The apparatus according to claim 12, characterized in that, The second processing module is used for: Delete the sampled value corresponding to the simulation clock signal in the first file; Adjust the excitation times in the first file according to the duration of the initialization process corresponding to the target simulation tool; Add vector timing feature definition data and waveform parameter setting data to the first file.

14. The apparatus according to claim 9, characterized in that, The second processing module is also used for: Determine the operation time of each command in the time-series feature text; Based on the operation time of each command and the various excitation times in the simulation excitation file, the commands are added to the simulation excitation file.

15. The apparatus according to claim 9, characterized in that, The determining module is also used for: Determine the expected simulation data corresponding to the time series feature text, and add the expected simulation data to the time series feature text; The simulation module is also used for: Based on the keywords corresponding to the expected simulation data, the expected simulation data is obtained from the simulation results.

16. The apparatus according to claim 15, characterized in that, It also includes a verification module, used for: The simulation stimulus file is verified based on the command truth table corresponding to the preset excitation signal and / or the expected simulation data.

17. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method for generating simulation stimulus files as described in any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by the processor, implement the method for generating simulation stimulus files as described in any one of claims 1 to 8.

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