Memory and operating method thereof, memory system

Abstract

The embodiments of the present disclosure provide a memory and an operating method thereof, and a memory system. The memory comprises a register configured to mark whether a row hammer row exists in a memory array, and to enter a row hammer refresh mode if the row hammer row exists; and to mark any refresh type in the row hammer refresh mode, the row hammer refresh mode comprising at least two refresh types; and a refresh management module configured to read a mark bit of the register, and to obtain a victim row corresponding to the row hammer row based on a row address contained in a row activation command and the refresh type marked by the register if the mark bit indicates that the register marks the existence of the row hammer row, and to refresh the victim row.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, and a memory system. Background Technology

[0002] Memory devices such as Dynamic Random Access Memory (DRAM) store data by storing charge in capacitors within memory cells. Because the charge stored in the capacitors leaks over time, DRAM requires periodic refresh operations. In practice, data is periodically rewritten into the capacitors. As memory device manufacturing processes scale down, the spacing between word lines decreases, and the voltage distribution within a word line can cause an increase in charge in memory cells connected to adjacent word lines. When a word line is accessed intensively, a row hammer effect can occur, where data stored in memory cells connected to adjacent word lines is lost due to the voltage of the active state of that word line. Summary of the Invention

[0003] To address the existing technical problems, this disclosure proposes a memory, its operation method, and a memory system.

[0004] This disclosure provides a memory, including:

[0005] The register is used to indicate whether a row hammer row exists in the storage array. If the row hammer row exists, the row hammer refresh mode is entered. The register is also used to indicate any refresh type in the row hammer refresh mode, which includes at least two refresh types.

[0006] The refresh management module is used to read the flag bit of the register. If the flag bit indicates that the register flag exists after the row hammer row, then the victim row corresponding to the row hammer row is obtained based on the row address contained in the row activation command and the refresh type of the register flag, and the victim row is refreshed.

[0007] In the above scheme, the refresh type includes at least a first type, a second type, and a third type, wherein:

[0008] The victim behavior in the first type is the row adjacent to the hammer row;

[0009] The victim behavior in the second type is the row adjacent to the row number of the hammer;

[0010] The victim behavior in the third type is the row adjacent to the hammer row and the next adjacent row.

[0011] In the above scheme, the refresh management module is used to detect whether each victim row corresponding to the refresh type has been refreshed within a preset time before refreshing based on the refresh type. If some of the victim rows have been refreshed, the remaining victim rows are refreshed. The preset time is less than the data retention time.

[0012] In the above scheme, the memory is used to receive a row hammer refresh instruction sent by the memory controller, and according to the row hammer refresh instruction, to set the corresponding flag of the register to a first value, the first value indicating that the row hammer row exists in the memory array; or,

[0013] The memory also includes a counter, which is used to count the different row addresses corresponding to the row activation commands received by the memory within a unit time period; when the count value of any row address exceeds a preset value, the corresponding flag of the register is set to the first value.

[0014] In the above scheme, the memory is used to set the corresponding flag of the register to a second value after the refresh management module refreshes the victim row, the second value indicating exiting the row hammer refresh mode;

[0015] The refresh management module is used to read the flag bit of the register. If the flag bit indicates that the row hammer refresh mode has been exited, the corresponding row is activated based on the row activation command.

[0016] This disclosure provides a memory system including one or more memories as described in the above embodiments; and

[0017] The storage controller is used to detect whether a row hammer row exists in the memory; if the row hammer row exists, it sends a row hammer refresh command to the memory.

[0018] This disclosure provides a method for operating a memory, including:

[0019] The register reads a flag bit, which is used to indicate whether a row hammer row exists in the storage array. If the row hammer row exists, the register enters the row hammer refresh mode. The register also indicates any refresh type in the row hammer refresh mode, which includes at least two refresh types.

[0020] If the flag indicates that the register flag exists after the row hammer line, then the victim line corresponding to the row hammer line is obtained based on the row address contained in the row activation command and the refresh type of the register flag; and

[0021] Refresh the affected row.

[0022] In the above scheme, the method further includes: configuring the refresh type; configuring the refresh type includes:

[0023] The refresh type is determined at least based on the spacing between adjacent character lines and the number of times the hammer line is accessed within a unit time period; and

[0024] The value corresponding to the determined refresh type is stored in the corresponding flag bit of the register.

[0025] In the above scheme, the refresh type includes at least a first type, a second type, and a third type, wherein:

[0026] The victim behavior in the first type is the row adjacent to the hammer row;

[0027] The victim behavior in the second type is the row adjacent to the row number of the hammer;

[0028] The victim behavior in the third type is the row adjacent to the hammer row and the next adjacent row.

[0029] In the above scheme, determining the refresh type includes:

[0030] The first preset number of times is determined based on the spacing between adjacent character lines;

[0031] If the number of times the row hammer is accessed within the unit time period exceeds the first preset number but does not exceed the second preset number, then the refresh type is determined to be the first type; wherein, the second preset number is greater than twice the first preset number;

[0032] If the number of times the row hammer is accessed within the unit time period exceeds the second preset number, then the refresh type is determined to be one of the first type, the second type, or the third type.

[0033] In the above scheme, determining the refresh type further includes:

[0034] If the number of times the row hammer is accessed in the unit time period exceeds the second preset number, it is determined whether the row adjacent to the row hammer or the row next to the row hammer is refreshed within a preset time period, where the preset time period is less than the data retention time.

[0035] If all rows adjacent to the hammer row are refreshed, then the refresh type is determined to be the second type.

[0036] If all rows adjacent to the row number of the hammer are refreshed, then the refresh type is determined to be the first type.

[0037] If at least a portion of the rows adjacent to the hammer row are not refreshed, and at least a portion of the rows next to the hammer row are not refreshed, then the refresh type is determined to be the third type.

[0038] In this embodiment, the refresh management module determines whether a row hammer row exists in the memory array by checking the refresh mode flag in the register. If a row hammer row exists, it obtains the refresh type to be performed based on the refresh type flag in the register. Then, based on the row address included in the row activation command and the refresh type, it determines the row address of the affected row. Finally, it refreshes the affected row to improve the row hammer phenomenon. It is understood that since the affected row address is directly obtained from the row address included in the row activation command, it does not require querying the internal physical mapping relationship of the memory. Therefore, the row hammer refresh method executed in this embodiment has good adaptability. Furthermore, since the affected row is specifically determined based on the refresh type, the row hammer refresh executed in this embodiment is more targeted and accurate. Attached Figure Description

[0039] Figure 1 A schematic diagram of a control circuit using a 1T1C architecture provided for an embodiment of this disclosure;

[0040] Figure 2 A schematic diagram of row addresses provided for embodiments of this disclosure;

[0041] Figure 3 A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0042] Figure 4 A schematic diagram of a memory provided in an embodiment of this disclosure;

[0043] Figure 5 A schematic diagram of a register flag type provided for an embodiment of this disclosure;

[0044] Figure 6 This is a schematic flowchart of an operation method for a memory provided in an embodiment of the present disclosure;

[0045] Figure 7 This is a functional flowchart of a row hammer refresh circuit provided in an embodiment of the present disclosure.

[0046] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0047] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0049] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0050] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0053] The memory involved in the embodiments of this disclosure includes, but is not limited to, dynamic random access memory. The specific types of memory involved in the embodiments of this disclosure will be described in detail below. The following only uses dynamic random access memory as an example to explain and analyze the hammer phenomenon.

[0054] Dynamic random access memory (DRAM) consists of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (capacitor) controlled by the transistor. That is, DRAM includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0055] Figure 1 This is a schematic diagram of a control circuit using a 1T1C architecture provided in an embodiment of this disclosure; as shown... Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source region of transistor T is electrically connected to one of the electrode plates of capacitor C, and the other electrode plate of capacitor C can be connected to a reference voltage, which can be ground voltage or other voltages. The gate of transistor T is connected to the word line (WL). The voltage applied through the word line WL controls the transistor T to be turned on or off. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0056] A dynamic random access memory (DRAM) cell is a capacitor that stores electrical charge. During read, write, and refresh operations, leakage can occur in the capacitor, and the read process itself is destructive. Therefore, the value needs to be refreshed immediately after a read operation, or, if the cell is not accessed for an extended period, its value needs to be refreshed at a predetermined frequency.

[0057] The data stored in a memory cell is determined by the charge in a capacitor, and this charge is easily affected between refresh cycles. Drifting electrons can migrate into the memory cell, thus altering the charge within it. If too many accesses occur in a short period, enough charge can accumulate to change the perceived state of the stored value. This is where the Hammer part of Row Hammer comes in. Before a refresh occurs, repeated tiny bursts of these erroneous electrons (drifting electrons) alter the data stored in adjacent rows under a certain cumulative effect. In fact, as the size decreases, the affected rows (rows where the stored value changes) may not only be adjacent rows. As the distance between adjacent words gets closer, even nearby rows (two or more rows apart) may be affected.

[0058] Figure 2 This diagram illustrates multiple row addresses provided in this embodiment of the disclosure. Specifically, during periodic refresh, the read frequencies of multiple row addresses (such as the active row, adjacent rows (row+1, row-1), and next adjacent rows (row+2, row-2)) are basically the same. In other words, the probability of encountering row hammers is very low for rows that can be refreshed and written within a refresh cycle—that is, rows that are normally read / written or periodically refreshed. However, when a row address (such as the active row) is read / written multiple times within a very short period, if the periodic refresh operation fails to refresh the adjacent rows (such as adjacent rows (row+1, row-1) and next adjacent rows (row+2, row-2)) in a timely manner, row hammers will occur on those adjacent rows.

[0059] It should be noted that in the multiple banks of a dynamic random access memory (DRAM), each bank includes multiple row addresses. Repeatedly activating a row address can cause the values ​​of some bits in physically adjacent rows to be reversed. In this case, the row that has been overactivated is called the hammer row, and the rows near the hammer row that produce the hammer phenomenon are called the victim rows.

[0060] In practical applications, various solutions can be adopted to mitigate or improve the effects of row hammering, such as: manufacturing chips with larger row spacing that are less prone to row hammering; using error checking and correction codes (ECC) to correct error bits caused by row hammering; increasing the refresh frequency of all row addresses; analyzing and statically remapping / removing cells prone to row hammering after manufacturing; dynamically remapping / removing cells prone to row hammering during system operation; and accurately identifying the hammered row and refreshing its nearby rows during operation.

[0061] Specifically, the various embodiments of this disclosure provide a memory and its operation method, and a memory system, which accurately identify the row being hammered and precisely determine the affected row according to the refresh type during memory operation, and refresh the affected row, thereby mitigating the row hammering phenomenon in a more targeted and precise manner.

[0062] Figure 3 This is a schematic diagram of a memory system provided as an embodiment of the present disclosure. Figure 3 As shown, the memory system 3 provided in this embodiment may include a memory controller 30 and a memory 40; wherein the memory controller 30 is electrically connected to the memory 40 and is used to issue instructions to the memory 40 to control the memory 40 to perform corresponding operations.

[0063] The storage controller 30 can provide various signals to the storage 40 via the storage interface to control storage operations (e.g., write and read). For example, the storage controller 30 can access the data DATA of the storage array 400 by providing the storage 30 with the command CMD and the address ADDR. As an example, the command CMD may include an activation command for normal storage operations (e.g., write and read data), a precharge command, and / or a refresh command for refresh operations.

[0064] For example, the activation command instructs the storage array 400 to switch to an active state so that data can be written to or read from the storage array 400, and row addresses in the storage array 400 are opened based on the activation command.

[0065] The storage controller 30 can also access the storage 40 according to a request from a host outside the storage system 3.

[0066] Based on the memory system 3 described above, this embodiment of the present disclosure also provides a memory 40, including: a register 401, used to indicate whether a row hammer row exists in the memory array; if the row hammer row exists, then enter the row hammer refresh mode; and used to indicate any refresh type in the row hammer refresh (RSR) mode, the row hammer refresh mode including at least two refresh types; a refresh management module 402, used to read the flag bit of the register 401; if the flag bit indicates that the register indicates the existence of the row hammer row, then obtain the victim row corresponding to the row hammer row based on the row address included in the row activation command and the refresh type indicated by the register, and refresh the victim row.

[0067] Figure 4 This is a schematic diagram of a memory provided for an embodiment of this disclosure. For example... Figure 4As shown, the memory 40 includes a register 401 and a refresh management module 402. The memory device 40 may also include: a memory array 400, a command decoder 403, an address buffer 404, a row address multiplexer 406, multiple row decoders 407, memory bank control logic 408, a column address latch 409, multiple column decoders 410, an input / output gating circuit 411, and a data input / output buffer 412.

[0068] The memory array 400 may include multiple memory banks and multiple sense amplifiers corresponding to each memory bank; each memory bank includes multiple row addresses; each row address is connected to a corresponding word line.

[0069] Address buffer 404 can be used to receive row or column addresses of the memory array. The address buffer can send row addresses to the row decoder and column addresses to the column decoder. The row decoder selects at least one of a plurality of word lines connected to the memory bank based on the row address received from the address buffer, and activates the selected word line in response to a control signal. The column decoder selects at least one of a plurality of bit lines connected to the memory array, and activates the selected bit line in response to a control signal. Here, each memory bank includes a plurality of memory cells connected to the word lines and bit lines. A sense amplifier senses a voltage change in the activated bit line and amplifies the voltage change to generate output data. An input / output buffer outputs data to an external device, such as a memory controller, via a data line based on the voltage amplified by the sense amplifier.

[0070] In some specific embodiments, reference is made to Figure 4 Address buffer 403 can receive address ADDR provided from the storage controller. Address ADDR may include bank address BA. Furthermore, address ADDR may include row address ROW_ADDR for indicating rows of the storage array and column address COL_ADDR for indicating columns of the storage array. Row address ROW_ADDR may be provided to multiple row decoders via a row address selector, while column address COL_ADDR may be provided to multiple column decoders via a column address latch. Additionally, bank address BA may be provided to bank control logic. Bank control logic 404 can generate a bank control signal in response to bank address BA. Furthermore, in response to the bank control signal, the row decoder corresponding to bank address BA among the multiple row decoders may be activated, and the column decoder corresponding to bank address BA among the multiple column decoders may be activated.

[0071] It should be noted that, Figure 4The various components of the memory 40 shown are only for the purpose of more clearly illustrating the working principle of the memory 40 and the working environment of the register 401 and the refresh management module 402, and are not intended to limit the composition structure of the memory 40.

[0072] The following section focuses on register 401 and refresh management module 402.

[0073] Here, register 401 can be a mode register used to store information about setting the operating environment of the memory. In this embodiment of the disclosure, the flag bits of register 401 include at least a row hammer refresh mode flag bit and a refresh type flag bit.

[0074] The row hammer refresh mode flag is used to indicate whether a row hammer row exists in the storage array. The row hammer refresh mode flag may include at least one binary bit. For example, the row hammer refresh mode flag may include a first value and a second value. When a row hammer row exists in the storage array, the row hammer refresh mode flag is set to the first value, meaning the storage array subsequently enters row hammer refresh mode and refreshes the adjacent affected rows. After refreshing the adjacent affected rows, the row hammer refresh mode flag is set to the second value, meaning the row hammer refresh mode is exited. It should be noted that when the storage array is performing normal periodic refreshes and no row hammer row exists, the row hammer refresh mode flag is set to the second value; that is, the default value or default value of the row hammer refresh mode flag is the second value.

[0075] The refresh type flag is used to characterize multiple refresh types in the hammer refresh mode. The hammer refresh mode includes at least two refresh types. The number of bits in the refresh type flag can be set according to the number of refresh types. It is understood that the number of states provided by the number of bits in the refresh type flag needs to be greater than or equal to the number of refresh types. For example, if the refresh types include three, then the number of bits in the refresh type flag is at least two.

[0076] In some embodiments, the refresh type includes at least a first type, a second type, and a third type, wherein: in the first type, the affected behavior is the row adjacent to the hammer row; in the second type, the affected behavior is the row next to the hammer row; and in the third type, the affected behavior is the row adjacent to the hammer row and the row next to it.

[0077] Understandably, the row address defined as the victim row, or the row address of the neighboring rows being refreshed, differs across refresh types. In the first type, the victim row is the row adjacent to the hammer row; in the second type, the victim row is the row next to the hammer row; and in the third type, the victim row is both adjacent to and next to the hammer row. The configuration criteria for these types will be explained in detail later.

[0078] It should be noted that when the row hammer is located at the outermost edge of the storage array (the first or last row), the row addresses adjacent to and / or second to the row hammer are one row; when the row hammer is not located at the outermost edge of the storage array, in all types, the row addresses adjacent to and / or second to the row hammer are two rows.

[0079] In some specific examples, when the row hammer refresh mode flag is 1 bit and the refresh type flag is 2 bits, the refresh type includes the three types mentioned above; furthermore, it can be utilized... Figure 5 The example registers are used to indicate whether a row hammer row exists in the memory array, and to indicate the refresh type. Specifically:

[0080] Figure 5 The register shown is an 8-bit register. One bit in this register, OP[0], is used to indicate whether there is a row hammer in the memory array: when OP[0] = 0, it can be understood as the second value mentioned above, indicating that there is no row hammer in the memory array. At this time, the row hammer refresh mode is not entered or the row hammer refresh mode is exited. When the activation command is received, the corresponding row is activated normally. When OP[0] = 1, it can be understood as the first value mentioned above, indicating that there is a row hammer in the memory array. At this time, the row hammer refresh mode is entered. Two bits in this register, OP[1] and OP[2], are used to indicate the refresh type of the row hammer refresh mode. If the row hammer is row: when OP[2:1] = 00, it indicates the victim row+1 and row-1; when OP[2:1] = 01, it indicates the victim row+2 and row-2; when OP[2:1] = 10, it indicates the victim row+1, row-1, row+2 and row-2. The remaining five bits in this register, OP[3]--OP[8], can be reserved. It is understandable that other types of registers can also be used to implement the row hammer refresh mode and refresh type flags, as long as their bit length meets the requirements.

[0081] Here, the refresh management module 402 reads the row hammer refresh mode flag and refresh type flag of the register. When the row hammer refresh mode flag indicates that the memory has entered the row hammer refresh mode, the address of the row hammer row is determined according to the row activation command issued by the memory controller, and the victim row is determined according to the refresh type in the refresh type flag, and then the victim row is refreshed.

[0082] It should be noted that the row activation command here can be received either after determining that a row hammer row exists in memory, or before determining that a row hammer row exists in memory.

[0083] In some embodiments, the refresh management module 402 is configured to detect whether each victim row corresponding to the refresh type has been refreshed within a preset time period before refreshing based on the refresh type; if some of the victim rows have been refreshed, then refresh the remaining victim rows.

[0084] Here, there are multiple victim rows. The refresh management module 402 detects each victim row and determines whether each victim row has been refreshed within a preset time period based on the detection results. If a victim row has already been refreshed within the preset time period, after entering the row hammer refresh mode, no further refresh is performed on that victim row; that is, refresh is only performed on victim rows that have not been refreshed within the preset time period. Here, the preset time period is less than the data retention time period, which is the refresh cycle when the memory performs normal refresh at a certain frequency. The preset time period can be selected and set according to actual needs.

[0085] Understandably, checking the refresh status of each affected row before performing row hammer refresh can avoid repeated refreshes, thereby reducing memory power consumption while avoiding row hammer phenomenon.

[0086] It should be noted that the refresh detected here can be either a normal refresh operation or a row hammer refresh operation. For example, when multiple affected rows share the same row hammer row, the detected refresh may be from a row hammer refresh operation.

[0087] It should be noted that if the refresh type is the third type, if only one of the two adjacent rows was refreshed previously, then the remaining adjacent row and the two next adjacent rows must also be refreshed. If the refresh management module detects that all affected rows have been refreshed within the preset time, it can receive a new row activation command to be used as the new row hammer. Alternatively, if the row with the highest number of repeated visits was previously used as the row hammer, the row with the second highest number of repeated visits can now be used as the new row hammer.

[0088] In some embodiments, the memory 40 is configured to receive a row hammer refresh instruction sent by the memory controller 30, and, according to the row hammer refresh instruction, set the corresponding flag of the register to a first value, the first value indicating that the row hammer row exists in the memory array; or, the memory 40 further includes a counter 405, the counter 405 being configured to count the different row addresses corresponding to the row activation commands received by the memory 40 within a unit time period; when the count value of any row address exceeds a preset value, the corresponding flag of the register is set to the first value.

[0089] Here, the presence of the row hammer row in the storage array can be determined in several ways, thereby setting the row hammer refresh mode flag of the register to the first value. Two examples are given below:

[0090] The first type:

[0091] The storage controller 30 can record and detect the row activation command to be issued, determine whether there is a row hammer row in the memory based on the number of repetitions of the row address corresponding to the issued row activation command, and issue a row hammer refresh command to the memory when it is determined that there is a row hammer row in the memory array. The row hammer refresh command is used to indicate that there is a row hammer row in the memory array. Then, the corresponding flag in the register is set to the first value mentioned above, so that the memory array enters the row hammer refresh mode.

[0092] The second type:

[0093] The presence of a row hammer row in the memory array can be determined by the number of times the row address corresponding to the row activation command received by the memory is repeated within a unit time period, as recorded by the counter 405 in the memory 40. When the number of repetitions of the row address recorded by the counter exceeds a preset value, it indicates that a row hammer row exists in the memory array. Then, the corresponding flag in the register is set to the aforementioned first value, so that the memory array enters the row hammer refresh mode.

[0094] In some embodiments, the memory 40 is used to set the corresponding flag bit of the register to a second value after the refresh management module 402 refreshes the victim row, the second value indicating exiting the row hammer refresh mode; the refresh management module 402 is used to read the flag bit of the register, and if the flag bit indicates exiting the row hammer refresh mode, then activate the corresponding row based on the row activation command.

[0095] In this embodiment, the refresh management module determines whether a row hammer row exists in the memory array by checking the refresh mode flag in the register. If a row hammer row exists, it obtains the refresh type to be performed based on the refresh type flag in the register. Then, based on the row address included in the row activation command and the refresh type, it determines the row address of the affected row. Finally, it refreshes the affected row to improve the row hammer phenomenon. It is understood that since the affected row address is directly obtained from the row address included in the row activation command, it does not require querying the internal physical mapping relationship of the memory. Therefore, the row hammer refresh method executed in this embodiment has good adaptability. Furthermore, since the affected row is specifically determined based on the refresh type, the row hammer refresh executed in this embodiment is more targeted and accurate.

[0096] In some embodiments of this disclosure, a method for operating a memory is also provided, the method comprising the following steps:

[0097] Step S601: Read the flag bit of the register, which is used to indicate whether there is a row hammer row in the storage array. If the row hammer row exists, enter the row hammer refresh mode; and to indicate any refresh type in the row hammer refresh mode, which includes at least two refresh types.

[0098] Step S602: If the flag indicates that the register flag exists after the row hammer line, then obtain the victim line corresponding to the row hammer line based on the row address included in the row activation command and the refresh type of the register flag; and

[0099] Step S603: Refresh the affected row.

[0100] It should be understood that Figure 6 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 6 The steps shown can be adjusted in order according to actual needs.

[0101] In some embodiments, the method further includes: configuring the refresh type; configuring the refresh type includes:

[0102] The refresh type is determined at least based on the spacing between adjacent character lines and the number of times the hammer line is accessed within a unit time period; and

[0103] The value corresponding to the determined refresh type is stored in the corresponding flag bit of the register.

[0104] In some embodiments, the refresh type includes at least a first type, a second type, and a third type, wherein:

[0105] The victim behavior in the first type is the row adjacent to the hammer row;

[0106] The victim behavior in the second type is the row adjacent to the row number of the hammer;

[0107] The victim behavior in the third type is the row adjacent to the hammer row and the next adjacent row.

[0108] In some embodiments, determining the refresh type includes:

[0109] The first preset number of times is determined based on the spacing between adjacent character lines;

[0110] If the number of times the row hammer is accessed within the unit time period exceeds the first preset number but does not exceed the second preset number, then the refresh type is determined to be the first type; wherein, the second preset number is greater than twice the first preset number;

[0111] If the number of times the row hammer is accessed within the unit time period exceeds the second preset number, then the refresh type is determined to be one of the first type, the second type, or the third type.

[0112] In some embodiments, determining the refresh type further includes:

[0113] If the number of times the row hammer is accessed in the unit time period exceeds the second preset number, it is determined whether the row adjacent to the row hammer or the row next to the row hammer is refreshed within a preset time period, where the preset time period is less than the data retention time.

[0114] If all rows adjacent to the hammer row are refreshed, then the refresh type is determined to be the second type.

[0115] If all rows adjacent to the row number of the hammer are refreshed, then the refresh type is determined to be the first type.

[0116] If at least a portion of the rows adjacent to the hammer row are not refreshed, and at least a portion of the rows next to the hammer row are not refreshed, then the refresh type is determined to be the third type.

[0117] Figure 7 This is a functional flowchart of a horizontal hammer refresh circuit provided in an embodiment of this disclosure. The following is in conjunction with… Figure 6 , Figure 7 The operation method of the memory provided in the embodiments of this disclosure will be described in detail.

[0118] refer to Figure 7 , Figure 7 The above-mentioned register will still be used as an example for explanation.

[0119] First, configure the refresh mode flag and refresh type flag in the register.

[0120] When the counter or memory controller in the memory detects that a row address has been accessed multiple times in a short period of time, it determines that a row hammer row exists in the memory array. That is, when the memory detects that the count value exceeds the preset value or receives a row hammer refresh instruction, it sets the refresh mode flag bit OP[0] of the register to 1 and enters the row hammer refresh mode. Otherwise, it sets the refresh mode flag bit OP[0] to 0.

[0121] Here, based at least on the spacing between adjacent character lines, the refresh status of nearby lines at the physical location of the hammer line, and the number of times the hammer line is accessed within a unit time period, the hammer line refresh mode is configured into three types: the first type, the second type, and the third type. For example, the refresh type flag value OP[2:1] = 00 for the first type, the refresh type flag value OP[2:1] = 01 for the second type, and the refresh type flag value OP[2:1] = 10 for the third type.

[0122] Specifically, when the memory is manufactured, its word line spacing is fixed, and the charge leakage or drift electrons generated by each access can also be quantified. In this case, a first preset number of accesses can be determined based on the spacing between adjacent word lines and the quantized parameters. That is, it is considered that when the number of accesses to a certain row address in a unit time period exceeds the first preset number of accesses, the drift electrons generated are sufficient to cause the charge of the memory cells in adjacent rows to change, thereby leading to data errors.

[0123] Understandably, the first preset number of times is also related to factors such as the amplification performance of the memory. The better the amplification performance of the memory, the less charge needs to be stored in the capacitor, or in other words, the smaller the base voltage difference required for amplification, the greater the charge change that the memory cell can tolerate, and the larger the first preset number of times. In addition, it may also be related to the conduction capability of the transistor connecting the memory and the bit line. The stronger the conduction capability, the smaller the threshold voltage, the less charge needs to be stored in the capacitor, and the greater the charge change that the memory cell can tolerate.

[0124] Meanwhile, considering that when the number of accesses reaches the first preset number, a row hammer effect is generated on the rows within the first preset interval in the memory; when the number of accesses reaches the second preset number, a row hammer effect is generated on the rows within the second preset interval in the memory; at this time, the second preset interval may be less than twice the first preset interval; the reason is that adjacent rows will play a certain role in blocking the interference caused by frequent accesses, thereby reducing the impact of the row hammer phenomenon on the next adjacent row; for example, if frequent accesses of 500 times will cause word line leakage in the memory within a range of 5nm, when frequent accesses of 1000 times, it may only cause word line leakage in the memory within a range of 8nm, that is to say, adjacent rows play a certain protective role for the next adjacent row.

[0125] Here, as can be seen from the above analysis, the row hammer phenomenon will only affect the adjacent rows and the next adjacent rows when the second preset number is more than twice the first preset number.

[0126] When the storage controller detects that the number of accesses to the row hammer within a unit time period is greater than the first preset number and less than the second preset number, it determines that the leakage current effect will only extend to the adjacent rows. At this time, the refresh type is determined to be the first type, and the refresh type flag value OP[2:1] is set to 00.

[0127] When the storage controller detects that the number of accesses to the row hammer within a unit time period exceeds a second preset number, the leakage range of the word line may involve adjacent rows and the next adjacent rows. In this case, it can be further determined whether the rows adjacent to or the next adjacent to the row hammer have been refreshed within a preset time period. The preset time period can be set according to actual needs; the data retention time can be the interval between two adjacent refresh operations when performing periodic refresh operations. Specifically:

[0128] When all rows adjacent to the hammer row are refreshed within a preset time period, only the next adjacent row is refreshed, i.e., the refresh type is determined to be the second type, and the refresh type flag OP[2:1] is set to 01. When all rows next to the hammer row are refreshed within a preset time period, only the adjacent rows are refreshed, i.e., the refresh type is determined to be the first type, and the refresh type flag OP[2:1] is set to 00. When at least some rows adjacent to the hammer row are not refreshed within a preset time period, and at least some rows next to the hammer row are not refreshed, both the adjacent and next adjacent rows are refreshed, and the refresh type flag OP[2:1] is set to 10.

[0129] Here, the execution entity of steps S601 to S603 can be the aforementioned refresh management module; in addition, it can be understood that the above-mentioned unit time period should be less than the data retention time, and the preset data duration should be less than the unit time period, so as to avoid errors in the data of a certain row address due to charge leakage before the next regular refresh arrives.

[0130] In step S601, the refresh management module reads the values ​​of the refresh mode flag and refresh type flag in the register.

[0131] Next, proceed to step S602, refer to Figure 7 If OP[0] = 1 is obtained, it indicates that there is a row hammer in the storage array, and the memory enters the row hammer refresh mode. The refresh management module determines the refresh type based on the value of the refresh type flag bit, i.e., OP[2:1], which is the relative position relationship between the victim row and the row hammer. After receiving the activation command, the memory decodes the command to obtain the bank address and row address information of the row hammer. Then, it performs address conversion calculation on the obtained bank address and row address to obtain the four row addresses that are physically near the row hammer, which are denoted as row+1, row-1, row+2 and row-2 respectively. Then, according to OP[2:1], it selects which rows to refresh, i.e., determines the physical address of the victim row. In other words, after obtaining the bank address and row address of the row hammer, it performs address conversion according to the information of OP[2:1] to obtain only the physical address of the victim row to be refreshed. When OP[2:1] = 00, it indicates the victim behaviors row+1 and row-1; when OP[2:1] = 01, it indicates the victim behaviors row+2 and row-2; when OP[2:1] = 10, it indicates the victim behaviors row+1, row-1, row+2 and row-2.

[0132] Next, step S603 is executed to refresh the affected row.

[0133] When refreshing the affected rows, each affected row is refreshed sequentially. For details, refer to... Figure 7 When the refresh type flag OP[2:1] is set to 00, the rows adjacent to the row hammer are refreshed sequentially. For example, the refresh order can be to refresh the next row (row+1) adjacent to the row hammer first, and then refresh the previous row (row-1) adjacent to the row hammer. The refresh time is at least the sum of the time (tRC) between activating one row and activating the next row and the precharge time (tRPpb) required to activate the next row, i.e., tRC+tRPpb. At the same time, the count value of the counter in the memory used to record the number of normal refreshes will not increase or decrease.

[0134] When the refresh type flag is set to 01, the rows adjacent to the row number of the hammer are refreshed sequentially; for example, the refresh order can be to refresh the row above the row number of the hammer first (row-2), and then refresh the row below the row number of the hammer (row+2).

[0135] When the refresh type flag is set to OP[2:1], the rows adjacent to the hammer row and the next adjacent row are refreshed sequentially. For example, the refresh order can be to refresh the next row (row+1) adjacent to the hammer row first, and then refresh the previous row (row-1) adjacent to the hammer row. Next, refresh the next row (row+2) next to the hammer row, and then refresh the previous row (row-2) adjacent to the hammer row.

[0136] Understandably, considering that adjacent rows are more affected, when refreshing in the third mode, the adjacent rows can be refreshed first, and then the next adjacent rows can be refreshed.

[0137] When the affected row refresh is completed, exit the row hammer refresh mode and set OP[0] to 0, and the entire memory returns to normal operation.

[0138] It should be noted that terms such as "first" and "second" are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0139] Furthermore, the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0140] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: The register is used to indicate whether a row hammer row exists in the storage array. If the row hammer row exists, the row hammer refresh mode is entered. and for identifying any refresh type in the hammer refresh mode, the hammer refresh mode including at least two refresh types; The refresh management module is used to read the flag bit of the register. If the flag bit indicates that the register flag exists after the row hammer row, then the victim row corresponding to the row hammer row is obtained based on the row address contained in the row activation command and the refresh type of the register flag, and the victim row is refreshed.

2. The memory according to claim 1, characterized in that, The refresh types include at least a first type, a second type, and a third type, wherein: The victim behavior in the first type is the row adjacent to the hammer row; The victim behavior in the second type is the row adjacent to the row number of the hammer; The victim behavior in the third type is the row adjacent to the hammer row and the next adjacent row.

3. The memory according to claim 2, characterized in that, The refresh management module is used to detect whether each victim row corresponding to the refresh type has been refreshed within a preset time before refreshing based on the refresh type. If some of the victim rows have been refreshed, the remaining victim rows are refreshed. The preset time is less than the data retention time.

4. The memory according to claim 1, characterized in that, The memory is used to receive row hammer refresh instructions sent by the memory controller, and, according to the row hammer refresh instructions, to set the corresponding flag of the register to a first value, the first value indicating that the row hammer row exists in the memory array; or, The memory also includes a counter, which is used to count the different row addresses corresponding to the row activation commands received by the memory within a unit time period; when the count value of any row address exceeds a preset value, the corresponding flag of the register is set to the first value.

5. The memory according to claim 1, characterized in that, The memory is used to set the corresponding flag of the register to a second value after the refresh management module refreshes the victim row, the second value indicating exiting the row hammer refresh mode; The refresh management module is used to read the flag bit of the register. If the flag bit indicates that the row hammer refresh mode has been exited, the corresponding row is activated based on the row activation command.

6. A memory system, characterized in that, The memory system includes one or more memories as described in any one of claims 1 to 5; as well as The storage controller is used to detect whether a row hammer row exists in the memory; if the row hammer row exists, it sends a row hammer refresh command to the memory.

7. A method for operating a memory, characterized in that, include: The flag bit of the read register is used to indicate whether there is a row hammer row in the storage array. If the row hammer row exists, the row hammer refresh mode is entered. and for identifying any refresh type in the hammer refresh mode, the hammer refresh mode including at least two refresh types; If the flag indicates that the register flag exists after the row hammer row, then the victim row corresponding to the row hammer row is obtained based on the row address contained in the row activation command and the refresh type of the register flag; as well as Refresh the affected row.

8. The method of operating the memory according to claim 7, characterized in that, The method further includes: configuring the refresh type; configuring the refresh type includes: The refresh type is determined at least based on the spacing between adjacent character lines and the number of times the hammer line is accessed within a unit time period; and The value corresponding to the determined refresh type is stored in the corresponding flag bit of the register.

9. The method of operating the memory according to claim 8, characterized in that, The refresh types include at least a first type, a second type, and a third type, wherein: The victim behavior in the first type is the row adjacent to the hammer row; The victim behavior in the second type is the row adjacent to the row number of the hammer; The victim behavior in the third type is the row adjacent to the hammer row and the next adjacent row.

10. The method of operating the memory according to claim 9, characterized in that, Determining the refresh type includes: The first preset number of times is determined based on the spacing between adjacent character lines; If the number of times the row hammer is accessed within the unit time period exceeds the first preset number but does not exceed the second preset number, then the refresh type is determined to be the first type; wherein, the second preset number is greater than twice the first preset number; If the number of times the row hammer is accessed within the unit time period exceeds the second preset number, then the refresh type is determined to be one of the first type, the second type, or the third type.

11. The method of operating the memory according to claim 10, characterized in that, Determining the refresh type also includes: If the number of times the row hammer is accessed in the unit time period exceeds the second preset number, it is determined whether the row adjacent to the row hammer or the row next to the row hammer is refreshed within a preset time period, where the preset time period is less than the data retention time. If all rows adjacent to the hammer row are refreshed, then the refresh type is determined to be the second type. If all rows adjacent to the row number of the hammer are refreshed, then the refresh type is determined to be the first type. If at least a portion of the rows adjacent to the hammer row are not refreshed, and at least a portion of the rows next to the hammer row are not refreshed, then the refresh type is determined to be the third type.

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