Memory chip testing method and device, medium and equipment

Abstract

The present disclosure relates to a memory chip testing method, a memory chip testing device, a computer readable storage medium and an electronic device, and relates to the technical field of integrated circuits. The memory chip testing method comprises: sending a mode register write command to a memory chip, controlling the memory chip to enter a read-write clock equalization test mode; setting a first preset time, after waiting for the first preset time, sending a read-write clock signal to the memory chip; determining a predicted value of read-write clock equalization according to the first preset time and a system clock period; waiting for a second preset time after the read-write clock signal is sent, detecting a test data output port of the memory chip, and obtaining a test value; comparing the test value and the predicted value to determine whether the memory chip has an abnormality. The present disclosure provides a method for testing the read-write clock equalization function.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a memory chip testing method, a memory chip testing apparatus, a computer-readable storage medium, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low price, it has been widely used in the computer field and the electronics industry.

[0003] LPDDR5 (Low Power Double Data Rate 5) is a design specification in DRAM. It typically requires the use of automated testing methods to verify the functionality of the designed chip, such as Wck2ck Leveling (write clock (WCK) to clock leveling).

[0004] Since the Wck2ck Leveling function in LPDDR5 is mainly used to detect the phase relationship between the system clock CK and the read / write clock WCK, it is difficult for a computer to directly measure the phase between the two clocks to obtain the verification result of Wck2ck Leveling.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a memory chip testing method, a memory chip testing device, a computer-readable storage medium, and an electronic device to verify the Wck2ck Leveling read / write clock equalization function.

[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.

[0008] According to a first aspect of the present disclosure, there is provided a memory chip testing method, comprising: sending a mode register write command to a memory chip, and controlling the memory chip to enter a read / write clock equalization test mode; setting a first preset time, and sending a read / write clock signal to the memory chip after waiting for the first preset time; determining a predicted value of the read / write clock equalization according to the first preset time and a system clock period; waiting for a second preset time after sending the read / write clock signal, detecting a test data output port of the memory chip, and obtaining a test value; and comparing the test value with the predicted value to determine whether the memory chip is abnormal.

[0009] In an exemplary embodiment of the present disclosure, said setting a first preset time comprises: setting the length of said first preset time tWCKIS to satisfy tWCKIS = N*tCK + tis, wherein tCK is the system clock period, N is a positive integer, tis is the remaining time, and the cut-off time point of the remaining time is in a non-rising edge and non-falling edge interval of tCK.

[0010] In an exemplary embodiment of the present disclosure, said determining a predicted value of the read / write clock equalization according to the first preset time and the system clock period comprises: taking a value of tCK corresponding to the cut-off time point of the remaining time as the predicted value.

[0011] In an exemplary embodiment of the present disclosure, the method further comprises: when tis > tCK*5 / 8 and tis < tCK*7 / 8, determining the predicted value as 0; and when tis > tCK / 8 and tis < tCK*3 / 8, determining the predicted value as 1.

[0012] In an exemplary embodiment of the present disclosure, said comparing the test value with the predicted value to determine whether the memory chip is abnormal comprises: if the test value does not match the predicted value, determining that the memory chip is abnormal.

[0013] In an exemplary embodiment of the present disclosure, the read / write clock signal is a read / write clock signal with a length of 7.5 cycles.

[0014] In an exemplary embodiment of the present disclosure, the second preset time is less than or equal to 20ns.

[0015] According to a second aspect of the present disclosure, there is provided a memory chip testing apparatus, the apparatus comprising: a signal transmitting module configured to send a mode register write command to a memory chip, and control the memory chip to enter a read / write clock equalization test mode; set a first preset time, and after waiting for the first preset time, send a read / write clock signal to the memory chip; a predicted value determining module configured to determine a predicted value of the read / write clock equalization according to the first preset time and a system clock cycle; a test value determining module configured to wait for a second preset time after finishing sending the read / write clock signal, detect a test data output port of the memory chip, and obtain a test value; and a determining module configured to compare the test value with the predicted value and judge whether the memory chip has an abnormality.

[0016] In an exemplary embodiment of the present disclosure, the signal transmitting module is configured to set a length tWCKIS of the first preset time satisfying tWCKIS = N*tCK + tis, wherein tCK is the system clock cycle, N is a positive integer, tis is a remaining time, and a cut-off time point of the remaining time is in a non-rising edge and non-falling edge interval of tCK.

[0017] In an exemplary embodiment of the present disclosure, the predicted value determining module is configured to use a value of tCK corresponding to the cut-off time point of the remaining time as the predicted value.

[0018] In an exemplary embodiment of the present disclosure, the predicted value determining module is configured to determine that the predicted value is 0 when tis > tCK*5 / 8 and tis < tCK*7 / 8; and determine that the predicted value is 1 when tis > tCK / 8 and tis < tCK*3 / 8.

[0019] In an exemplary embodiment of the present disclosure, the determining module is configured to determine that the memory chip has an abnormality if the test value is inconsistent with the predicted value.

[0020] In an exemplary embodiment of the present disclosure, the read / write clock signal is a read / write clock signal comprising a 7.5-cycle length.

[0021] In an exemplary embodiment of the present disclosure, the second preset time is less than or equal to 20ns.

[0022] According to a third aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, which when executed by a processor implements the above memory chip testing method.

[0023] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described memory chip testing method by executing the executable instructions.

[0024] The technical solution provided in this disclosure may include the following beneficial effects:

[0025] In an exemplary embodiment of this disclosure, by sending a mode register write command to the memory chip, the memory chip can be controlled to enter the read / write clock balancing test mode. After entering the read / write clock balancing test mode, wait for a first preset time, and then send the read / write clock to the memory chip. Then, the predicted value of read / write clock balancing can be determined according to the set first preset time and the system clock cycle. Using the predicted value and the test value at the test data output port of the memory chip, it is possible to determine whether there is an abnormality in the memory chip, thereby realizing the test of the read / write clock balancing function of the memory chip.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0028] Figure 1 The flowchart illustrating an exemplary embodiment of a memory chip testing method according to the present disclosure is shown schematically.

[0029] Figure 2 This schematically illustrates the timing of a read / write clock equalization function according to an exemplary embodiment of the present disclosure. Figure 1 ;

[0030] Figure 3 The timing diagram illustrates the read / write clock equalization function according to an exemplary embodiment of the present disclosure. Figure 2 ;

[0031] Figure 4 A schematic diagram illustrating the correspondence between reference values ​​and predicted values ​​according to exemplary embodiments of the present disclosure is provided.

[0032] Figure 5 A block diagram schematically illustrates a memory chip testing apparatus according to an exemplary embodiment of the present disclosure;

[0033] Figure 6 The illustration schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0035] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0036] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0037] Semiconductor memory chips are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A semiconductor memory chip includes multiple memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such semiconductor memory. This solution is preferably used in DRAM. Therefore, the following description of embodiments is made with reference to DRAM as a non-limiting example.

[0038] In DRAM integrated circuit devices, especially LPDDR5 DRAM, automatic testing methods are required to verify the functionality of memory chips during the design, testing, and usage phases. For example, verification of write, read, refresh, Command Bus Training, and Wck2ck Leveling read / write clock balancing functions is required.

[0039] In addition to performing the aforementioned functional verifications during the LPDDR5 design process, the Wck2ck Leveling functionality of the memory chips needs to be functionally tested during LPDDR5 testing to screen out chips that are functioning correctly. Furthermore, during the use of LPDDR5, it is necessary to automatically detect whether the Wck2ck Leveling of the memory chips is working properly to prevent system read / write errors.

[0040] Based on this, the exemplary embodiments of this disclosure provide a method for testing a memory chip to test the read / write clock equalization (Wck2ckLeveling) function of the memory chip. (Refer to...) Figure 1 The memory chip testing method includes:

[0041] Step S110: Send a mode register write command to the memory chip to control the memory chip to enter the read / write clock equalization test mode.

[0042] Step S120: Set a first preset time, wait for the first preset time, and then send a read / write clock signal to the memory chip.

[0043] Step S130: Determine the predicted value of read / write clock balance based on the first preset time and the system clock cycle;

[0044] Step S140: After sending the read / write clock, wait for the second preset time, check the test data output port of the memory chip, and obtain the test value;

[0045] Step S150: Compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.

[0046] In the memory chip testing method provided by the exemplary embodiments of this disclosure, the memory chip can be controlled to enter the read / write clock balancing test mode by sending a mode register write command to the memory chip; after entering the read / write clock balancing test mode, wait for a first preset time, and then send the read / write clock to the memory chip; then, the predicted value of read / write clock balancing can be determined according to the set first preset time and the system clock cycle; using the predicted value and the test value at the test data output port of the memory chip, it is possible to determine whether there is an abnormality in the memory chip, thereby realizing the test of the read / write clock balancing function of the memory chip.

[0047] The memory chip testing method provided by the exemplary embodiments of this disclosure will be described in detail below with reference to the following examples:

[0048] In step S110, a mode register write command is sent to the memory chip to control the memory chip to enter the read / write clock equalization test mode.

[0049] In the exemplary embodiments of this disclosure, the Mode Register Write Command (MRW Command) is used to write data to the DRAM's mode register. The Mode Register Write Command is executed through the coordination of the Clock Enable (CKE) signal, the Chip Select (CS) signal, and command / address signals, such as CA[5:0] (a set of CA signals can be labeled CA[5:0]). Both the address and data of the mode register are conveyed through CA[5:0]. The cycle time of the Mode Register Write Command is controlled by the tMRW parameter.

[0050] In practical applications, sending mode register write commands to memory chips is executed by the memory chip controller. For example, the LPDDR5 DRAM Controller sends mode register write commands to LPDDR5 DRAM.

[0051] In an exemplary embodiment of this disclosure, by sending a mode register write command to the memory chip via the memory chip controller, the memory chip can be controlled to enter the read / write clock balancing test mode, i.e., the Wck2ck Leveling mode. The Wck2ck Leveling mode is used to test the memory chip's Wck2ck Leveling function, i.e., its read / write clock balancing function.

[0052] Specifically, the read / write clock balancing function is mainly used to detect the phase relationship between the system clock CK and the read / write clock WCK. By detecting the phase relationship between the system clock CK and the read / write clock WCK, it can be determined whether the timing of the memory chip is running normally.

[0053] In the exemplary embodiments of this disclosure, after the memory chip enters the read / write clock balancing test mode, the read / write clock balancing test function of the memory chip can be tested to determine whether there is any abnormality in the memory chip.

[0054] In step S120, a first preset time is set, and after waiting for the first preset time, a read / write clock signal is sent to the memory chip.

[0055] In the exemplary embodiments of this disclosure, the first preset time needs to be set in advance to ensure that the predicted value of the read / write clock balance determined according to the first preset time and the system clock cycle is a fixed value, so as to facilitate the comparison between the fixed predicted value and the test value.

[0056] Reference Figure 2As shown in the timing diagram of the read / write clock equalization function, after the memory chip controller sends the mode register write command MRW-1 to the memory chip, and then waits for time tWLMRD until time T3 of the system clock CK, the memory chip controller begins to send the read / write clock signal WCK to the memory chip. Therefore, the first preset time is the sum of the time period from sending the mode register write command MRW-1 to time T3 of the system clock CK and the time tWLMRD.

[0057] In this exemplary embodiment of the present disclosure, the length tWCKIS of the first preset time can be set to satisfy tWCKIS = N*tCK + tis, where tCK is the system clock cycle, N is a positive integer, tis is the remaining time, and the cutoff point of the remaining time is located in the non-rising edge and non-falling edge interval of tCK. Since the cutoff point of the remaining time is neither at the rising edge nor the falling edge of the system clock cycle tCK, the system clock cycle tCK corresponding to the cutoff point of the remaining time is a definite 0 or a definite 1, and there is no transition from 0 to 1 or from 1 to 0.

[0058] In practical applications, the frequency of the transmitted read / write clock signal WCK is twice the frequency of the system clock CK. Each transmitted read / write clock signal WCK contains 7.5 cycles of read / write clock signals. The read / write clock signal WCK is used during both read and write operations.

[0059] In step S130, the predicted value of read / write clock balance is determined based on the first preset time and the system clock cycle.

[0060] In an exemplary embodiment of this disclosure, the memory chip enters the read / write clock equalization test mode as soon as it receives the mode register write command. After waiting for a first preset time to send the read / write clock signal, the time interval tWCKIS from receiving the mode register write command to receiving the first rising edge of the read / write clock signal is the first preset time. The predicted value of read / write clock equalization can be calculated based on the first preset time.

[0061] In practical applications, after receiving a write command to the mode register, the memory chip typically receives multiple read / write clock signals from the memory chip controller. For example, refer to... Figure 3 As shown in the timing diagram for sending multiple read / write clocks, after receiving the mode register write command, the memory chip also receives three read / write clock signals in succession: the first read / write clock signal, the second read / write clock signal, and the third read / write clock signal.

[0062] The first preset time from receiving a mode register write command to receiving the first rising edge of the first read / write clock signal can be denoted as tWCKIS1. The first preset time from receiving a mode register write command to receiving the first rising edge of the second read / write clock signal can be denoted as tWCKIS2. The first preset time from receiving a mode register write command to receiving the first rising edge of the third read / write clock signal can be denoted as tWCKIS3. These three first preset times have the same starting point but different ending points. The third first preset time tWCKIS3 is greater than the second first preset time tWCKIS2, and the second first preset time tWCKIS2 is greater than the first first preset time tWCKIS1.

[0063] In this exemplary embodiment, according to the pre-set first preset time tWCKIS, it is known that it is the sum of N times the system clock cycle tCK and the remaining time tis. That is, after subtracting N times the system clock cycle tCK from the first preset time tWCKIS, there is still a remaining time tis. In this embodiment, the value of tCK corresponding to the cutoff time of the remaining time is used as the predicted value for read / write clock balancing. That is, the value of the system clock cycle tCK corresponding to the cutoff time of the remaining time tis is determined as the predicted value. This predicted value is either 0 or 1.

[0064] The following provides a detailed explanation of how to determine the specific values ​​for the predicted values:

[0065] In the exemplary embodiment of this disclosure, during the process of determining the predicted value, the remaining time tis can be determined first based on the first preset time tWCKIS and the system clock cycle tCK. Then, based on the range of the remaining time tis, the specific value of the predicted value of the read / write clock equalization can be determined. The range of the remaining time tis can be determined by the system clock cycle tCK. The position of the rising edge of the read / write clock signal WCK can represent the value of the read / write clock equalization tWCK2CK. By mapping tWCK2CK to the remaining time tis, the specific position of the rising edge of the read / write clock signal WCK can be determined using the remaining time tis.

[0066] In an exemplary embodiment of this disclosure, during the process of determining the remaining time tis based on the first preset time tWCKIS and the system clock cycle tCK, the quotient of the first preset time tWCKIS and the system clock cycle tCK can be rounded down to [tWCKIS / tCK], and [tWCKIS / tCK] is determined as N as described above. That is, N is the quotient of the first preset time and the system clock cycle rounded down.

[0067] Therefore, the remaining time tis = tWCKIS - [tWCKIS / tCK] * tCK.

[0068] After the remaining time tis is determined, the prediction value can be determined according to the range where the remaining time tis falls. In the exemplary embodiments of the present disclosure, with reference to Figure 4 , the prediction value DQ determined according to the range where the remaining time tis falls is as follows:

[0069] when tis>tCK*5 / 8 and tis<tCK*7 / 8, the prediction value DQ is determined to be 0;

[0070] when tis>tCK / 8 and tis<tCK*3 / 8, the prediction value DQ is determined to be 1;

[0071] when 0<tis<tCK / 8, or 3 / 8*tCK<tis<tCK*5 / 8, or 7 / 8*tCK<tis<tCK, the prediction value DQ is determined to be 0 or 1.

[0072] Wherein, a prediction value of 0 indicates that the values of the rising edge of the read-write clock signal WCK are all 0 within the interval where the rising edge is located, a prediction value of 1 indicates that the values of the rising edge of the read-write clock signal WCK are all 1 within the interval where the rising edge is located, and a prediction value of 0 / 1 indicates that the prediction value DQ flips from 0 to 1 or from 1 to 0 at a certain point within the interval where the rising edge of the read-write clock signal WCK is located. According to the standard specification, if the flip point falls between -1 / 8tCK and 1 / 8tCK, the design of the memory chip meets the requirements.

[0073] It should be noted that, the foregoing statement that the prediction value for read-write clock equalization is a fixed value by setting a first preset time means that the prediction value DQ is a definite 0 or a definite 1 by setting the first preset time, that is, the range where the remaining time tis falls satisfies tis>tCK*5 / 8 and tis<tCK*7 / 8, or satisfies tis>tCK / 8 and tis<tCK*3 / 8. Therefore, the magnitude of the set first preset time can be determined according to the range of the remaining time tis.

[0074] As in Figure 3When multiple read / write clocks are sent, the predicted value of read / write clock balance for each read / write clock can be calculated. Specifically, the remaining time *tis* is first determined, and the first preset time *tWCKIS* in the formula for the remaining time *tis* is replaced with the first preset time *tWCKIS1* for the first read / write clock, the second preset time *tWCKIS2* for the second read / write clock, and the third preset time *tWCKIS3* for the third read / write clock. Different read / write clock signals will yield different remaining times *tis1*, *tis2*, *tis3*, etc. Based on the range of these different remaining times, the predicted value of read / write clock balance is determined. Each read / write clock signal corresponds to a predicted value of read / write clock balance. The predicted values ​​of read / write clock balance for the multiple read / write clock signals can all be used to predict whether there are any anomalies in the memory chip.

[0075] In step S140, after sending the read / write clock signal, wait for a second preset time, detect the test data output port of the memory chip, and obtain the test value.

[0076] like Figure 2 As shown, after sending the read / write clock signal WCK, that is, after sending 7.5 0-1 toggle cycles, and then waiting for the second preset time tWLO, the test value can be obtained by detecting the data port of the memory chip.

[0077] In the exemplary embodiments of this disclosure, experimental results are typically obtained and maintained before the second preset time tWLO. However, in practical applications, the timing of the experimental results from the memory chip is uncertain, occurring either earlier or later. Therefore, a latest time is specified for tWLO, meaning that the results must be available no later than tWLO, and the values ​​of the previous results are maintained after tWLO.

[0078] In practical applications, the second preset time tWLO is not a fixed value; it is usually specified with a maximum value of 20ns. Therefore, in the exemplary embodiments of this disclosure, the second preset time tWLO is less than or equal to 20ns. For example, after waiting 20ns after sending the read / write clock, the test value can be obtained by detecting the data port of the memory chip.

[0079] Step S150: Compare the test value and the predicted value to determine whether there is an abnormality in the memory chip.

[0080] In the exemplary embodiments of this disclosure, after obtaining the test value through the test data output port of the memory chip, the presence of anomalies in the memory chip can be determined by combining it with the previously determined predicted value of read / write clock balance.

[0081] Specifically, if the test value obtained from the test data output port of the memory chip is inconsistent with the predicted value, it can be determined that the memory chip is abnormal. If the inconsistency between the test value and the predicted value is determined using the memory chip testing method provided by the exemplary embodiments of this disclosure during the verification process, it is necessary to find the cause and change the circuit design of the memory chip. If the inconsistency between the test value and the predicted value is determined using the memory chip testing method provided by the exemplary embodiments of this disclosure during the testing process, it is necessary to screen out the memory chips that are working properly to ensure product quality. If the inconsistency is determined during system use, the pre-check of whether the memory chip is working properly provided by the exemplary embodiments of this disclosure can be used to anticipate risks and prevent data loss due to read / write errors.

[0082] For example Figure 3 In the case of multiple read / write clocks, after each read / write clock cycle is completed, and after waiting for a second preset time tWLO, a test value can be obtained by detecting the test data output port of the memory chip. Each test value corresponds to a predicted value. If any pair of test values ​​and predicted values ​​is inconsistent, it can be determined that the memory chip is malfunctioning and requires appropriate handling.

[0083] In summary, the memory chip testing method provided by the exemplary embodiments of this disclosure can control the memory chip to enter a read / write clock balancing test mode by sending a write command to the mode register of the memory chip. After entering the read / write clock balancing test mode, wait for a set first preset time, and then send a read / write clock signal to the memory chip. Then, the predicted value of read / write clock balancing can be determined based on the first preset time and the system clock cycle. Using the predicted value and the test value at the test data output port of the memory chip, the presence of abnormalities in the memory chip can be tested, thereby realizing the test of the read / write clock balancing function of the memory chip. In addition, by sending multiple read / write clock signals, multiple pairs of test values ​​and predicted values ​​can be determined, which can improve the accuracy of the read / write clock balancing function test.

[0084] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0085] Furthermore, in this example embodiment, a memory chip testing apparatus is also provided. (Refer to...) Figure 5, the memory chip testing apparatus 500 may include: a signal transmitting module 510, a predicted value determining module 520, a test value determining module 530 and a determining module 540, wherein:

[0086] the signal transmitting module 510 may be configured to send a mode register write command to a memory chip, and control the memory chip to enter a read / write clock deskew test mode; set a first preset time, and after waiting for the first preset time, send a read / write clock signal to the memory chip;

[0087] the predicted value determining module 520 may be configured to determine a predicted value of read / write clock deskew according to the first preset time and a system clock cycle;

[0088] the test value determining module 530 may be configured to wait for a second preset time after sending the read / write clock signal, detect a test data output port of the memory chip, and obtain a test value;

[0089] the determining module 540 may be configured to compare the test value with the predicted value, and determine whether the memory chip has an abnormality.

[0090] In an exemplary embodiment of the present disclosure, the signal transmitting module 510 may be configured to set a length tWCKIS of the first preset time to satisfy tWCKIS=N*tCK+tis, wherein tCK is the system clock cycle, N is a positive integer, tis is a remaining time, and a cut-off time point of the remaining time is in an interval of tCK that is neither a rising edge nor a falling edge.

[0091] In an exemplary embodiment of the present disclosure, the predicted value determining module 520 may be configured to use a value of tCK corresponding to the cut-off time point of the remaining time as the predicted value.

[0092] In an exemplary embodiment of the present disclosure, N is obtained by rounding down the quotient of the first preset time divided by the system clock cycle.

[0093] In an exemplary embodiment of the present disclosure, the predicted value determining module 530 may be configured to determine that the predicted value is 0 when tis>tCK*5 / 8 and tis<tCK*7 / 8; and determine that the predicted value is 1 when tis>tCK / 8 and tis<tCK*3 / 8.

[0094] In an exemplary embodiment of the present disclosure, the determining module 540 may be configured to determine that the memory chip has an abnormality if the test value is inconsistent with the predicted value.

[0095] In an exemplary embodiment of the present disclosure, the read / write clock signal is a read / write clock signal with a length of 7.5 cycles.

[0096] In one exemplary embodiment of this disclosure, the second preset time is less than or equal to 20 ns.

[0097] The specific details of the virtual modules of each memory chip testing device mentioned above have been described in detail in the corresponding memory testing methods, so they will not be repeated here.

[0098] It should be noted that although several modules or units of the memory testing apparatus have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0099] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0100] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0101] The following reference Figure 6 To describe an electronic device 600 according to this embodiment of the present invention. Figure 6 The electronic device 600 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0102] like Figure 6 As shown, the electronic device 600 is presented in the form of a general-purpose computing device. The components of the electronic device 600 may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different system components (including storage unit 620 and processing unit 610), and a display unit 640.

[0103] The storage unit 620 stores program code that can be executed by the processing unit 610, causing the processing unit 610 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 610 can perform actions such as... Figure 1In step S110, a mode register write command is sent to the memory chip to control the memory chip to enter the read / write clock balancing test mode; in step S120, a first preset time is set, and after waiting for the first preset time, a read / write clock signal is sent to the memory chip; in step S130, the predicted value of read / write clock balancing is determined according to the first preset time and the system clock cycle; in step S140, after sending the read / write clock, a second preset time is waited, and the test data output port of the memory chip is detected to obtain the test value; in step S150, the test value and the predicted value are compared to determine whether there is an abnormality in the memory chip.

[0104] Storage unit 620 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 6201 and / or cache memory 6202, and may further include a read-only memory (ROM) 6203.

[0105] Storage unit 620 may also include a program / utility 6204 having a set (at least one) program module 6206, such program module 6205 including but not limited to: operating system, one or more application programs, other program modules and program data, each of these examples or some combination of these may include an implementation of a network environment.

[0106] Bus 630 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0107] Electronic device 600 can also communicate with one or more external devices 670 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 600, and / or with any device that enables electronic device 600 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 650. Furthermore, electronic device 600 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 660. As shown, network adapter 660 communicates with other modules of electronic device 600 via bus 630. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0108] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0109] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.

[0110] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0111] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0112] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0113] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0114] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0115] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0116] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0117] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A method for testing memory chips, characterized in that, Said method comprises: sending a mode register write command to a memory chip, and controlling said memory chip to enter a read / write clock equalization test mode; setting a first preset time, after waiting for said first preset time, sending a read / write clock signal to said memory chip; determining a predicted value of read / write clock equalization according to said first preset time and a system clock cycle; after sending said read / write clock signal, waiting for a second preset time, detecting a test data output port of said memory chip, and obtaining a test value; comparing said test value with said predicted value, and determining whether said memory chip has an abnormality.

2. The method according to claim 1, characterized in that, said setting of the first preset time comprises: setting the length tWCKIS of said first preset time to satisfy tWCKIS=N*tCK+tis, wherein tCK is said system clock cycle, N is a positive integer, tis is residual time, and the cut-off time point of said residual time is in a non-rising edge and non-falling edge interval of tCK.

3. The method according to claim 2, characterized in that, said determining of the predicted value of read / write clock equalization according to the first preset time and the system clock cycle comprises: taking a value of tCK corresponding to the cut-off time point of said residual time as said predicted value.

4. The method according to claim 2 or 3, characterized in that, said method further comprises: when tis>tCK*5 / 8 and tis<tCK*7 / 8, determining said predicted value as 0; when tis>tCK / 8 and tis<tCK*3 / 8, determining said predicted value as 1.

5. The method according to claim 1, characterized in that, said comparing of the test value and the predicted value and determining whether the memory chip has an abnormality comprises: if said test value is inconsistent with said predicted value, determining that said memory chip has an abnormality.

6. The method according to claim 1, characterized in that, said read / write clock signal is a read / write clock signal with a length of 7.5 cycles.

7. The method according to claim 1, characterized in that, said second preset time is less than or equal to 20ns.

8. A memory chip testing device, characterized in that, said apparatus comprises: a signal sending module, configured to send a mode register write command to a memory chip, control said memory chip to enter a read / write clock equalization test mode; set a first preset time, after waiting for said first preset time, send a read / write clock signal to said memory chip; a predicted value determining module, configured to determine a predicted value of read / write clock equalization according to said first preset time and a system clock cycle; a test value determining module, configured to after sending said read / write clock signal, wait for a second preset time, detect a test data output port of said memory chip, and obtain a test value; a determination module, configured to compare said test value with said predicted value, and determine whether said memory chip has an abnormality.

9. The apparatus according to claim 8, characterized in that, said signal sending module is configured to set the length tWCKIS of said first preset time to satisfy tWCKIS=N*tCK+tis, wherein tCK is said system clock cycle, N is a positive integer, tis is residual time, and the cut-off time point of said residual time is in a non-rising edge and non-falling edge interval of tCK.

10. The apparatus according to claim 9, characterized in that, said predicted value determining module is configured to take a value of tCK corresponding to the cut-off time point of said residual time as said predicted value.

11. The apparatus according to claim 9 or 10, characterized in that, The predicted value determining module is configured to determine the predicted value as 0 when tis>tCK*5 / 8 and tis<tCK*7 / 8, and determine the predicted value as 1 when tis>tCK / 8 and tis<tCK*3 / 8.

12. The apparatus according to claim 8, characterized in that, The determination module is configured to determine that the memory chip is abnormal if the test value is inconsistent with the predicted value.

13. The apparatus according to claim 8, characterized in that, The read-write clock signal is a read-write clock signal with a period length of 7.5 cycles.

14. The apparatus according to claim 8, characterized in that, The second preset time is less than or equal to 20ns.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the memory chip testing method according to any one of claims 1-7 is implemented.

16. An electronic device, characterized in that, Comprising: a processor; and a memory, configured to store executable instructions of the processor; wherein the processor is configured to execute the memory chip testing method according to any one of claims 1-7 by executing the executable instructions.

Images