Semiconductor chip with crack stop ring structure

Abstract

The application discloses a semiconductor chip, comprising: a silicon substrate; a transistor region on the silicon substrate; and a crack stop ring structure on the silicon substrate, which is arranged around the transistor region, wherein the crack stop ring structure comprises a perimeter crack stop structure which surrounds the transistor region along the side edges of the semiconductor chip, and a corner crack stop structure which is arranged only at the corners of the semiconductor chip, wherein each of the corresponding opposite corners of the perimeter crack stop structure and the corner crack stop structure is a right angle, and the corner crack stop structure and the perimeter crack stop structure are connected in a non-perpendicular manner to form a closed area at the corner, wherein there is a stack dielectric layer on the silicon substrate, comprising an intermediate dielectric layer, a metal interlayer dielectric layer and an upper insulating layer, and the perimeter crack stop structure and the corner crack stop structure are formed by a metal layer formed in the stack dielectric layer.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor chips having a crack-stopping ring structure. Background Technology

[0002] As is known in the art, after the integrated circuit is fabricated on a wafer, a chip dicing process is performed to cut the wafer along the scribe lines. However, wafer dicing can damage the integrated circuit, which may originate from the propagation of cracks above and below the surface of the silicon substrate, resulting in serious chip damage or failure.

[0003] To prevent crack propagation, existing technologies often employ dual-track or multi-track crack arrestor ring structures. These rings are typically placed around the perimeter and corners of the transistor area. However, these existing structures occupy a significant portion of the chip area. Therefore, a more reliable and cost-effective crack arrestor ring structure is needed to reduce or eliminate crack propagation damage during wafer dicing. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor chip with a crack-stopping ring structure to overcome the shortcomings or defects of the prior art.

[0005] This invention provides a semiconductor chip, comprising: a silicon substrate; a transistor region located on the silicon substrate; and a crack-stopping ring structure located on the silicon substrate, the crack-stopping ring structure being disposed around the transistor region, wherein the crack-stopping ring structure includes a peripheral crack-stopping structure that surrounds the transistor region along the side of the semiconductor chip, and a corner crack-stopping structure disposed only at the corners of the semiconductor chip, wherein the corresponding diagonals of the corner crack-stopping structure and the peripheral crack-stopping structure are right angles and are connected in a non-perpendicular manner, forming a closed region at the corner, wherein a stacked dielectric layer is further disposed on the silicon substrate, including an intermediate dielectric layer, an inter-metal dielectric layer and an upper insulating layer, and the peripheral crack-stopping structure and the corner crack-stopping structure are composed of metal layers formed in the stacked dielectric layer.

[0006] According to an embodiment of the present invention, the enclosed region is an L-shaped enclosed region.

[0007] According to an embodiment of the present invention, the peripheral crack-stopping structure is located at a first predetermined distance inward from the side, the first predetermined distance being between 10 and 200 micrometers.

[0008] According to an embodiment of the present invention, a second predetermined distance is maintained between the peripheral crack-stopping structure and the corner crack-stopping structure, the second predetermined distance being between 0.5 and 5 micrometers.

[0009] According to an embodiment of the present invention, the width of the peripheral crack-stopping structure is between 2 and 20 micrometers, and the width of the corner crack-stopping structure is between 2 and 20 micrometers.

[0010] According to an embodiment of the present invention, the metal layer includes metal wires and metal vias, and the peripheral crack arrest structure includes a first side metal wall formed by continuous metal wires and metal vias.

[0011] According to an embodiment of the present invention, the corner crack prevention structure has a second side metal wall at both ends, which is composed of continuous metal wires and metal through holes, and the metal wires or metal through holes between the second side metal walls at both ends of the corner crack prevention structure are discontinuous structures.

[0012] According to an embodiment of the present invention, the discontinuous structure includes the metal wires of the individual metal vias or segments.

[0013] According to an embodiment of the present invention, at least one continuous metal wire in the width direction is included between the second side metal walls at both ends of the corner crack prevention structure.

[0014] The dual-track or multi-track crack-stopping ring structure of the present invention is only set at the corner position of the chip. Therefore, it occupies less chip area, is more reliable and more cost-effective, and can effectively eliminate crack propagation damage to the chip during wafer dicing. Attached Figure Description

[0015] Figure 1 A top view schematic diagram illustrating a semiconductor chip according to an embodiment of the present invention.

[0016] Figure 2 and Figure 3 respectively along Figure 1 A schematic diagram of the cross section shown by the tangents I-I' and II-II'.

[0017] Figure 4 A top view schematic diagram illustrating another embodiment of the semiconductor chip of the present invention.

[0018] Figure 5 For along Figure 4 A schematic diagram of the cross section shown by the tangent line III-III'.

[0019] Figure 6 As illustrated in another embodiment of the present invention, along Figure 4 A schematic diagram of the cross section shown by the tangent line III-III'.

[0020] Figures 7 to 10 This is a top view schematic diagram illustrating various semiconductor chips according to other embodiments of the present invention.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 1, 2, 3, 4, 5, 6 Semiconductor chips

[0023] 10 transistor regions

[0024] 100 silicon substrate

[0025] 110 Intermediate Dielectric Layer

[0026] 120 Interlayer Dielectric Layer

[0027] 130 Upper Insulation Layer

[0028] A1 and A2 corresponding diagonals

[0029] C1-C4 corner

[0030] CA L-shaped enclosed area

[0031] COM-1 and COM-2 side metal walls

[0032] CS Crack Arresting Ring Structure

[0033] CS1 peripheral crack arrest structure

[0034] CS2 and CS3 corner crack arresting structures

[0035] d1-d4 Pre-determined distance

[0036] DS stack dielectric layer

[0037] E1-E4 side

[0038] M1-M5 metal layers

[0039] SR protection ring structure

[0040] V0 Tungsten Plug

[0041] V1-V4 Through Holes

[0042] Widths w1, w2, and w3

[0043] θ angle Detailed Implementation

[0044] The advantages and features of the embodiments can be more readily understood by referring to the following detailed description and accompanying drawings of preferred embodiments. However, embodiments may be embodied in many different forms and should not be construed as limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations of the embodiments to those skilled in the art; therefore, the embodiments will be defined only by the appended claims. Throughout the specification, the same reference numerals refer to the same elements.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0046] It should be understood that when a component or layer is referred to as "on," "connected to," or "coupled to" another component or layer, it may be directly on, connected to, or coupled to another component or layer, or there may be intermediate elements or layers. Conversely, when a component is referred to as "directly on," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Please see Figures 1 to 3 ,in, Figure 1 A top view schematic diagram illustrating a semiconductor chip according to an embodiment of the present invention. Figure 2 and Figure 3 respectively along Figure 1 A schematic diagram of the cross-section shown by the tangents I-I' and II-II'. (See diagram below.) Figure 1 As shown, semiconductor chip 1 has four corners C1-C4 and four sides E1-E4. Side E1 is located between corners C1 and C2, side E2 is located between corners C2 and C3, side E3 is located between corners C3 and C4, and side E4 is located between corners C4 and C1. According to an embodiment of the present invention, sides E1 and E3 are of equal length, and sides E2 and E4 are of equal length, forming a rectangular outline.

[0048] According to an embodiment of the present invention, a crack-stopping ring structure CS is disposed around the semiconductor chip 1, including a peripheral crack-stopping structure CS1, which continuously surrounds the central transistor region 10 along four sides E1-E4. According to an embodiment of the present invention, the peripheral crack-stopping structure CS1 is disposed at a predetermined distance d1 inward from the four sides E1-E4. For example, the predetermined distance d1 may be between 10 and 200 micrometers, but is not limited thereto.

[0049] According to an embodiment of the present invention, the crack arresting ring structure CS further includes four corner crack arresting structures CS2, which are respectively disposed on the inner side of the peripheral crack arresting structure CS1 near the four corners C1-C4. The corresponding diagonals A1 and A2 of the corner crack arresting structures CS2 and the peripheral crack arresting structures CS1 are right angles, and the corner crack arresting structures CS2 and the peripheral crack arresting structures CS1 are connected in a non-perpendicular manner, for example, Figure 1 The enlarged area shows that the angle θ between the corner crack-stopping structure CS2 and the surrounding crack-stopping structure CS1 is less than 90 degrees. In other embodiments, the angle θ between the corner crack-stopping structure CS2 and the surrounding crack-stopping structure CS1 can be greater than 90 degrees. According to an embodiment of the present invention, the four corner crack-stopping structures CS2 are not connected to each other.

[0050] Compared to the four sides E1-E4, the corners C1-C4 are more susceptible to delamination and cracking. Even if the peripheral crack arrest structure CS1 fails to prevent crack propagation, the corner crack arrest structure CS2 can still effectively prevent crack propagation at the corners C1-C4. Since the risk of crack propagation is relatively low on the four adjacent sides E1-E4, only the peripheral crack arrest structure CS1 is used, thus increasing the effective usable area of ​​the transistor region 10.

[0051] According to an embodiment of the present invention, a predetermined distance d2 is maintained between the peripheral crack arresting structure CS1 and the corner crack arresting structure CS2 adjacent to the four corners C1-C4. For example, the predetermined distance d2 can be between 0.5 and 5 micrometers, or for example, 2 micrometers, but is not limited thereto. According to an embodiment of the present invention, the shape of the corner crack arresting structure CS2 can be zigzag or arc-shaped, but is not limited thereto. According to an embodiment of the present invention, the two ends of the corner crack arresting structure CS2 are respectively connected to the peripheral crack arresting structure CS1, forming an L-shaped closed area CA, thus forming a double-track crack arresting structure at the corners C1-C4, while a single-track crack arresting structure is formed on the side.

[0052] like Figure 2 and Figure 3 As shown, a peripheral crack arresting structure CS1 and a corner crack arresting structure CS2 are formed on a silicon substrate 100. According to an embodiment of the present invention, the width w1 of the peripheral crack arresting structure CS1 can be between 2 and 20 micrometers, for example, 8 micrometers. According to an embodiment of the present invention, the width w2 of the corner crack arresting structure CS2 can be between 2 and 20 micrometers, for example, 8 micrometers. According to an embodiment of the present invention, the width w1 of the peripheral crack arresting structure CS1 and the width w2 of the corner crack arresting structure CS2 can be the same. According to an embodiment of the present invention, the width w1 of the peripheral crack arresting structure CS1 and the width w2 of the corner crack arresting structure CS2 can be different.

[0053] According to an embodiment of the present invention, a stacked dielectric layer DS is formed on a silicon substrate 100, including but not limited to an intermediate dielectric layer 110, an inter-metal dielectric layer 120, and an upper insulating layer 130. According to an embodiment of the present invention, the intermediate dielectric layer 110 may include, but is not limited to, a silicon oxide layer or a silicon nitride layer. According to an embodiment of the present invention, the inter-metal dielectric layer 120 may include, but is not limited to, a low dielectric constant material layer or an ultra-low dielectric constant material layer. According to an embodiment of the present invention, the upper insulating layer 130 may include, but is not limited to, a tetraethyl orthosilicate (TEOS) silicon oxide layer or a passivation material.

[0054] According to an embodiment of the present invention, the peripheral crack arresting structure CS1 and the corner crack arresting structure CS2 are composed of metal layers formed in the stacked dielectric layer DS on the silicon substrate 100, such as plugs V0 (e.g., tungsten plugs) formed in the intermediate dielectric layer 110, metal wires M1-M3 and metal vias V1-V2 formed in the inter-metal dielectric layer 120, and metal wires M4-M5 and metal vias V3-V4 formed in the upper insulating layer 130.

[0055] According to embodiments of the present invention, the peripheral crack-stopping structure CS1 comprises a plug V0, metal wires M1-M5, and metal vias V1-V4 forming at least one closed and continuous metal wall surrounding and protecting the transistor region 10. For example, the peripheral crack-stopping structure CS1 includes two side metal walls COM-1, formed by continuous metal wires M1-M5 perpendicular to the plane of the paper, plug V0, and metal vias V1-V4. According to embodiments of the present invention, the corner crack-stopping structure CS2 can be a continuous or discontinuous metal wall structure formed by plug V0, metal wires M1-M5, and metal vias V1-V4. According to embodiments of the present invention, the peripheral crack-stopping structure CS1 and the corner crack-stopping structure CS2 can have the same or different metal wall structures.

[0056] Please see Figures 4 to 5 ,in, Figure 4 A top view schematic diagram illustrating another embodiment of the semiconductor chip of the present invention is shown. Figure 5 For along Figure 4 A schematic diagram of the cross-section shown by the tangent line III-III'. The same symbols are used to represent the same areas, layers, or materials. For example... Figure 4 and Figure 5 As shown, semiconductor chip 2 also has four corners C1-C4 and four sides E1-E4. Side E1 is located between corners C1 and C2, side E2 is located between corners C2 and C3, side E3 is located between corners C3 and C4, and side E4 is located between corners C4 and C1.

[0057] According to an embodiment of the present invention, a crack-stopping ring structure CS is disposed around the semiconductor chip 2, including a peripheral crack-stopping structure CS1, which continuously surrounds the central transistor region 10 along four sides E1-E4. According to an embodiment of the present invention, the peripheral crack-stopping structure CS1 is disposed at a predetermined distance d1 inward from the four sides E1-E4; for example, the predetermined distance d1 can be between 10 and 200 micrometers, but is not limited thereto. According to an embodiment of the present invention, the crack-stopping ring structure CS further includes four corner crack-stopping structures CS2, which are respectively disposed on the inner side of the peripheral crack-stopping structure CS1 near the four corners C1-C4, wherein the corner crack-stopping structures CS2 and the corresponding diagonals A1 and A2 of the peripheral crack-stopping structure CS1 are right angles, and the corner crack-stopping structures CS2 and the peripheral crack-stopping structure CS1 are connected in a non-perpendicular manner. According to an embodiment of the present invention, the four corner crack-stopping structures CS2 are not connected to each other.

[0058] According to an embodiment of the present invention, the semiconductor chip 2 further includes a guard ring structure SR, located between the transistor region 10 and the crack-stopping ring structure CS. For example... Figure 5 As shown, according to an embodiment of the present invention, the peripheral crack arrest structure CS1, the corner crack arrest structure CS2, and the guard ring structure SR are all composed of metal layers formed in the stacked dielectric layer DS on the silicon substrate 100. For example, plugs V0 formed in the intermediate dielectric layer 110, metal wires M1-M3 and metal vias V1-V2 formed in the inter-metal dielectric layer 120, and metal wires M4-M5 and metal vias V3-V4 formed in the upper insulating layer 130. According to an embodiment of the present invention, the width w3 of the guard ring structure SR can be smaller than the width w1 of the peripheral crack arrest structure CS1. According to an embodiment of the present invention, the guard ring structure SR can be grounded. According to an embodiment of the present invention, the corner crack arrest structure CS2 has two side metal walls COM-2.

[0059] Please see Figure 6 The corner crack prevention structure CS2 has two side metal walls COM-2, which are composed of continuous metal wires M1-M5 perpendicular to the paper plane, plugs V0 and metal through holes V1-V4. Figure 6 and Figure 5 The difference lies in the fact that the metal wires M1-M5 or metal through holes V1-V4 between the two side metal walls COM-2 can be discontinuous structures, including, but not limited to, individual metal through holes or segments of metal wires. According to an embodiment of the present invention, the corner crack prevention structure CS2 may include at least one transversely continuous metal wire, for example, metal wire M4, between the two side metal walls COM-2.

[0060] Please see Figures 7 to 10This is a top view schematic diagram illustrating various semiconductor chips according to other embodiments of the present invention. The same regions, layers, or materials are still represented by the same symbols.

[0061] like Figure 7 As shown, a crack-stopping ring structure CS is disposed around the semiconductor chip 3, including a peripheral crack-stopping structure CS1, which continuously surrounds the central transistor region 10 along the four sides E1-E4. According to an embodiment of the present invention, the peripheral crack-stopping structure CS1 is disposed at a predetermined distance d1 inward from the four sides E1-E4. For example, the predetermined distance d1 can be between 10 and 200 micrometers, but is not limited thereto. According to an embodiment of the present invention, the crack-stopping ring structure CS further includes four corner crack-stopping structures CS2, which are respectively disposed on the inner side of the peripheral crack-stopping structure CS1 near the four corners C1-C4. The corner crack-stopping structures CS2 and the corresponding diagonals A1 and A2 of the peripheral crack-stopping structure CS1 are both right angles, and the corner crack-stopping structures CS2 and the peripheral crack-stopping structure CS1 are connected in a non-perpendicular manner. According to an embodiment of the present invention, the four corner crack-stopping structures CS2 are not connected to each other.

[0062] According to an embodiment of the present invention, a predetermined distance d2 is maintained between the peripheral crack-stopping structure CS1 and the corner crack-stopping structure CS2. For example, the predetermined distance d2 can be between 0.5 and 5 micrometers, or for example, 2 micrometers, but is not limited thereto. According to an embodiment of the present invention, the shape of the corner crack-stopping structure CS2 can be serrated or arc-shaped, but is not limited thereto. According to an embodiment of the present invention, both ends of the corner crack-stopping structure CS2 are respectively connected to the peripheral crack-stopping structure CS1, forming a closed region CA. According to an embodiment of the present invention, the width w2 of the corner crack-stopping structure CS2 can be smaller than the width w1 of the peripheral crack-stopping structure CS1.

[0063] like Figure 8As shown, a crack-stopping ring structure CS is disposed around the semiconductor chip 4, including a peripheral crack-stopping structure CS1, which continuously surrounds the central transistor region 10 along the four sides E1-E4. According to an embodiment of the present invention, the crack-stopping ring structure CS further includes four corner crack-stopping structures CS2 and CS3, which are respectively disposed on the inner side of the peripheral crack-stopping structure CS1 near the four corners C1-C4. The corner crack-stopping structures CS2 and CS3 are perpendicular to the corresponding diagonals A1 and A2 of the peripheral crack-stopping structure CS1, and the corner crack-stopping structure CS2 is connected to the peripheral crack-stopping structure CS1 in a non-perpendicular manner. A predetermined distance d2 is maintained between the corner crack-stopping structure CS2 and the peripheral crack-stopping structure CS1. For example, the predetermined distance d2 can be between 0.5 and 5 micrometers, or for example, it can be 1 micrometer, but is not limited thereto. The corner crack arresting structure CS3 and the surrounding crack arresting structure CS1 maintain a predetermined distance d3. For example, the predetermined distance d3 can be between 2 and 8 micrometers, or the predetermined distance d2 can be 3 micrometers, but is not limited to this.

[0064] like Figure 9 As shown, a crack-stopping ring structure CS is disposed around the semiconductor chip 5, including a peripheral crack-stopping structure CS1, which is disposed on four sides E1-E4 surrounding the central transistor region 10. According to an embodiment of the present invention, the peripheral crack-stopping structure CS1 is disposed at a predetermined distance d1 inward from the four sides E1-E4. For example, the predetermined distance d1 can be between 10 and 200 micrometers, but is not limited thereto. According to an embodiment of the present invention, the crack-stopping ring structure CS further includes four L-shaped corner crack-stopping structures CS2, which are respectively disposed on the inner side of the peripheral crack-stopping structure CS1 near the four corners C1-C4, wherein the L-shaped corner crack-stopping structures CS2 are connected to the peripheral crack-stopping structure CS1. According to an embodiment of the present invention, the L-shaped corner crack-stopping structures CS2 themselves form a closed region CA. According to an embodiment of the present invention, the L-shaped corner crack-stopping structures CS2 are disposed at a predetermined distance d4 inward from the four sides E1-E4. For example, the predetermined distance d4 can be between 10 and 200 micrometers, but is not limited thereto. According to an embodiment of the present invention, the predetermined distance d4 can be less than the predetermined distance d1.

[0065] like Figure 10As shown, a crack-stopping ring structure CS is disposed around the semiconductor chip 6, including a peripheral crack-stopping structure CS1, which is disposed on four sides E1-E4 surrounding the central transistor region 10. According to an embodiment of the present invention, the peripheral crack-stopping structure CS1 is disposed at a predetermined distance d1 inward from the four sides E1-E4. For example, the predetermined distance d1 can be between 10 and 200 micrometers, but is not limited thereto. According to an embodiment of the present invention, the crack-stopping ring structure CS further includes four corner crack-stopping structures CS2, which are respectively disposed on the outer side of the peripheral crack-stopping structure CS1 near the four corners C1-C4, wherein the L-shaped corner crack-stopping structure CS2 is connected to the peripheral crack-stopping structure CS1. According to an embodiment of the present invention, the corner crack-stopping structure CS2 and the peripheral crack-stopping structure CS1 surround a closed region CA. According to an embodiment of the present invention, the L-shaped corner crack-stopping structure CS2 is disposed at a predetermined distance d4 inward from the four sides E1-E4. For example, the predetermined distance d4 can be between 10 and 200 micrometers, but is not limited thereto. According to an embodiment of the present invention, the predetermined distance d4 can be less than the predetermined distance d1.

[0066] The dual-track or multi-track crack-stopping ring structure of the present invention is only set at the corner position of the chip. Therefore, it occupies less chip area, is more reliable and more cost-effective, and can effectively eliminate crack propagation damage to the chip during wafer dicing.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor chip, characterized in that, include: silicon substrate; The transistor region is located on the silicon substrate; as well as A crack-stopping ring structure is located on the silicon substrate and disposed around the transistor region. The crack-stopping ring structure includes a peripheral crack-stopping structure and a corner crack-stopping structure. The peripheral crack-stopping structure surrounds the transistor region along the side of the semiconductor chip. The corner crack-stopping structure is disposed only at the corner of the semiconductor chip. The corresponding diagonals of the corner crack-stopping structure and the peripheral crack-stopping structure are right angles and are connected in a non-perpendicular manner to form a closed region at the corner. A stacked dielectric layer is also disposed on the silicon substrate, including an intermediate dielectric layer, an inter-metal dielectric layer, and an upper insulating layer. The peripheral crack-stopping structure and the corner crack-stopping structure are composed of metal layers formed in the stacked dielectric layer.

2. The semiconductor chip according to claim 1, characterized in that, The enclosed area is an L-shaped enclosed area.

3. The semiconductor chip according to claim 1, characterized in that, The peripheral crack-stopping structure is located at a first predetermined distance inward from the side, the first predetermined distance being between 10 and 200 micrometers.

4. The semiconductor chip according to claim 1, characterized in that, A second predetermined distance is maintained between the peripheral crack-stopping structure and the corner crack-stopping structure, the second predetermined distance being between 0.5 and 5 micrometers.

5. The semiconductor chip according to claim 1, characterized in that, The width of the peripheral crack-stopping structure is between 2 and 20 micrometers, and the width of the corner crack-stopping structure is between 2 and 20 micrometers.

6. The semiconductor chip according to claim 1, characterized in that, The metal layer includes metal wires and metal vias, and the peripheral crack-stopping structure includes a first side metal wall, which is composed of continuous metal wires and metal vias.

7. The semiconductor chip according to claim 6, characterized in that, The corner crack-stopping structure has second side metal walls at both ends, the second side metal walls being composed of continuous metal wires and metal through holes, and the metal wires or metal through holes between the second side metal walls at both ends of the corner crack-stopping structure being a discontinuous structure.

8. The semiconductor chip according to claim 7, characterized in that, The discontinuous structure includes the metal wires of individual metal vias or segments.

9. The semiconductor chip according to claim 7, characterized in that, The corner crack-stopping structure includes at least one continuous metal wire in the width direction between the second side metal walls at both ends.

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