Semiconductor structure, method of manufacturing the same, memory chip, electronic device

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure, a manufacturing method thereof, a memory chip and an electronic device, the semiconductor structure comprises: a substrate, the substrate has a stack structure, the stack structure comprises a plurality of memory cell groups arranged in a first direction, and each memory cell group comprises a plurality of memory cells arranged in a second direction; and a plurality of lead pillars, wherein at least two lead pillars are connected with the memory cells of different layers in different memory cell groups respectively. The embodiment of the present disclosure can at least improve the integration of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, specifically relating to semiconductor structures and their manufacturing methods, memory chips, and electronic devices. Background Technology

[0002] Semiconductor structures consist of multiple memory cells, which need to be connected to external circuits to perform storage functions. The higher the integration level of a semiconductor structure, the more memory cells it can accommodate, and the better its performance. However, current semiconductor structures suffer from significant space wastage; furthermore, due to physical limitations, the size of memory cells has reached its scaling limit; and due to process limitations, the number of stacked layers of memory cells is also difficult to increase.

[0003] Therefore, there is an urgent need for a new semiconductor architecture to improve the integration of semiconductor structures. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its manufacturing method, a memory chip, and an electronic device, which at least helps to improve the integration of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a stacked structure, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including multilayer memory cells arranged in a second direction; a plurality of lead posts, wherein at least two of the lead posts are respectively connected to memory cells of different layers in different memory cell groups.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including multilayer memory cells arranged in a second direction; and forming a plurality of lead posts, wherein at least two of the lead posts are respectively connected to memory cells in different layers of different memory cell groups.

[0007] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a stacked structure, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including multilayer memory cells arranged in a second direction; a plurality of lead posts, wherein at least two of the lead posts are connected to different memory cells in the same memory cell group.

[0008] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory chip, which includes the semiconductor structure as described above.

[0009] According to some embodiments of this disclosure, another aspect of this disclosure also provides an electronic device, which includes the memory chip as described above.

[0010] The technical solutions provided in this disclosure have at least the following advantages:

[0011] In the semiconductor structure provided in this disclosure, at least two lead posts are connected to memory cells in different layers of the memory cell group. That is, at least two lead posts are directly connected to the memory cells, which helps to reduce the number of steps or eliminates the need for separate step regions, thereby improving the integration density of the semiconductor structure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0013] Figure 1 A top view of a semiconductor structure is shown;

[0014] Figure 2 It shows Figure 1 A magnified view of a portion of the image;

[0015] Figure 3 It shows Figure 2 Cross-sectional view along the A-A1 direction;

[0016] Figure 4 A schematic diagram of the stacking structure provided in an embodiment of this disclosure is shown;

[0017] Figures 5-11 Partial top views of seven different semiconductor structures provided in embodiments of this disclosure are shown respectively;

[0018] Figure 12 A schematic diagram of a storage unit group provided in an embodiment of this disclosure is shown;

[0019] Figure 13 A partial side view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure is shown;

[0020] Figure 14 A schematic diagram of another storage unit group provided in an embodiment of this disclosure is shown;

[0021] Figure 15 A partial side view schematic diagram of another semiconductor structure provided in an embodiment of this disclosure is shown;

[0022] Figure 16 A schematic diagram of yet another storage unit group provided in an embodiment of this disclosure is shown;

[0023] Figure 17 A partial side view schematic diagram of another semiconductor structure provided in an embodiment of this disclosure is shown;

[0024] Figures 18-21 Schematic diagrams of four different memory cell groups provided in embodiments of this disclosure are shown respectively;

[0025] Figure 22 A schematic diagram of the structural modules provided in an embodiment of this disclosure is shown;

[0026] Figures 23-31 The diagram shows a schematic representation of each step in a method for manufacturing a semiconductor structure according to an embodiment of this disclosure.

[0027] Figures 32-35 This invention discloses a schematic diagram showing the structural steps corresponding to each step in another method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0028] Figure 36 A schematic diagram of another storage unit group provided in an embodiment of the present disclosure is shown;

[0029] Figures 37-38 Partial top views of two different semiconductor structures provided in embodiments of this disclosure are shown respectively. Detailed Implementation

[0030] As the background technology shows, the integration level of semiconductor structures needs to be further improved. This will be explained in detail below. Figure 1 This is a top view of a semiconductor structure. Figure 2 for Figure 1 Enlarged view of the step within the dashed circle. Figure 3 for Figure 2 Cross-sectional view along the A-A1 direction. (Reference) Figures 1-3The semiconductor structure includes a memory cell region 100 and a step region 200. The memory cell region 100 contains multiple layers of memory cells. The step region 200 contains multiple steps, each corresponding to a specific memory cell layer. Connecting layers (not shown) can be disposed within the steps, and lead posts 300 can be disposed on the steps. The lead posts 300 are electrically connected to the memory cells through the connecting layers within the steps, thereby leading out the memory cells for connection to external circuits. However, as the number of stacked memory cell layers increases, the area occupied by the step region 200 becomes increasingly larger. For example, if there are 64 memory cell layers, 64 steps are required, with the area of ​​the bottom steps becoming larger. If the area of ​​the top step is 0.25 μm... 2 Therefore, the area of ​​the bottommost step is 64 * 0.25 = 16 μm. 2 . refer to Figure 3 The connecting layers below each step only serve as supports and electrical connections, resulting in a waste of space at the bottom. Therefore, the integration density of semiconductor structures needs to be further improved.

[0031] One embodiment of this disclosure provides a semiconductor structure in which at least two of a plurality of lead pillars are connected to memory cells in different layers of different memory cell groups. That is, by directly connecting at least two lead pillars to the memory cells, the number of steps can be reduced or separate step areas can be eliminated, thereby improving space utilization and ultimately increasing the integration density of the semiconductor structure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] like Figures 4-22 As shown, one embodiment of this disclosure provides a semiconductor structure, the semiconductor structure including: a substrate 11 (reference) Figure 23 The substrate 11 has a stacked structure, which includes a plurality of memory cell groups TC0 arranged in a first direction X, and the memory cell groups TC0 include multi-layer memory cells TC arranged in a second direction Z; a plurality of lead posts 5, wherein at least two lead posts 5 are respectively connected to memory cells TC of different layers in different memory cell groups TC0.

[0034] That is, by utilizing the multi-layer stacking arrangement of memory cells TC, at least two lead posts 5 can be directly connected to the memory cells TC, reducing the number of steps. If all lead posts 5 are directly connected to the memory cells TC, there is no need to separately set up step areas. In other words, the orthographic projection of the lead posts 5 connected to the memory cells TC on the surface of the substrate 11 lies within the orthographic projection of the stacked structure on the surface of the substrate 11, thereby improving the utilization of the substrate 11 surface and thus improving the integration density of the semiconductor structure. Furthermore, if at least two lead posts 5 are connected to memory cells TC of different layers in different memory cell groups TC0, it means that at least two lead posts 5 can utilize the spatial positions of different memory cell groups TC0.

[0035] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0036] In some embodiments, reference Figures 4-5 , Figures 8-22 Each memory cell TC in the same memory cell group TC0 is connected to at most one lead post 5. That is, only one connection point between the lead post 5 and the memory cell TC is required in each memory cell group TC0. Because there are fewer connection points within the same memory cell group TC0, the connection methods in different memory cell groups TC0 are relatively uniform, which helps to standardize the connection process between different lead posts 5 and memory cells TC, thereby reducing production costs. It should be noted that, to connect the lead post 5 to memory cells TC in different layers, a portion of the structure within the memory cell TC can be removed so that at least some of the lead posts 5 penetrate at least one memory cell TC, or the lead post 5 can be placed on the sidewall of the memory cell TC without penetrating it.

[0037] In other embodiments, reference is made to Figures 6-7 At least two memory cells TC connected by lead posts 5 are located in the same memory cell group TC0. That is, multiple connection points between lead posts 5 and memory cells TC can be set in each memory cell group TC0. It should be noted that in order to connect the lead posts 5 to the memory cells TC, it is usually necessary to remove part of the structure within the memory cell TC to provide the space required for the lead posts 5. After the part of the structure within the memory cell TC is removed, the memory cell TC can no longer perform the storage function. If multiple lead posts 5 are located in the same memory cell group TC0, it is beneficial to reduce the number of failed memory cells TC, thereby improving the space utilization within the semiconductor structure and thus improving the integration density.

[0038] Specifically, at least two lead posts 5 connected to memory cells TC are located in the same memory cell group TC0, which can include the following two cases: at least two lead posts 5 located in the same memory cell group TC0 are connected to memory cells TC in the same layer; or, at least two lead posts 5 located in the same memory cell group TC0 are connected to memory cells TC in different layers.

[0039] refer to Figure 6 At least two lead posts 5 located in the same memory cell group TC0 can be arranged along the first direction X; Reference Figure 7 At least two lead posts 5 located in the same memory cell group TC0 can be arranged along the third direction Y.

[0040] In some embodiments, reference Figure 4 The number of lead posts 5 is equal to or greater than the number of memory cell layers TC, and each layer includes at least one memory cell TC connected to a lead post 5. That is, each layer of memory cell TC can be directly connected to a lead post 5 without the need for a separate step area. Furthermore, each layer of memory cell TC can be led out through one or more lead posts 5. Leading out each layer of memory cell TC through a single lead post 5 simplifies the manufacturing process; leading out each layer of memory cell TC through multiple lead posts 5 increases the contact area, thereby reducing contact resistance.

[0041] It should be noted that the memory cell group TC0 has various different structures. Therefore, if the number of lead posts 5 connected to the same memory cell group TC0 is too large, the space required for the lead posts 5 will be larger. Different lead posts 5 may be connected to different structures within the memory cell group TC0, and different connection processes are usually required for different structures. In some embodiments, the number of lead posts 5 connected to the same memory cell group TC0 is less than the number of layers of memory cells TC in the memory cell group TC0. By controlling the number of lead posts 5 connected to the same memory cell group TC0, this number is kept within a reasonable range to simplify the connection process between the lead posts 5 and the memory cells TC.

[0042] In some embodiments, reference Figure 6 , Figures 8-9 The lead posts 5 are arranged in a row along the first direction X. That is, the multiple lead posts 5 are roughly aligned in the first direction X, which facilitates the connection of multiple lead posts 5 to the same structure in the memory cell TC, thereby helping to standardize the connection process between the lead posts 5 and the memory cell TC and reduce production costs.

[0043] For example, refer to Figure 8 The lead posts 5 are arranged in a straight line along the first direction X. In other words, the lead posts 5 are arranged in a straight line, and the ends of multiple lead posts 5 are aligned in the first direction X, which helps to simplify the process and improve the uniformity of the semiconductor structure. Furthermore, refer to... Figure 9 The lead posts 5 can also be slightly offset, that is, the two ends of multiple lead posts 5 are not aligned in the first direction X, thereby reducing the facing area of ​​the lead posts 5 and reducing the parasitic capacitance between adjacent lead posts 5.

[0044] refer to Figure 4 , Figures 12-22 At least one lead post 5 extends in the second direction Z and penetrates at least one memory cell TC in the memory cell group TC0. In this case, the orthographic projection of at least one lead post 5 onto the surface of the substrate 11 lies within the orthographic projection of a memory cell TC onto the surface of the substrate 11. This will be described in detail below. For ease of understanding, the lead post 5 is divided into a contact portion 51 and an extension portion 52 arranged in a stack. The contact portion 51 is connected to the memory cell TC, and the memory cell TC connected to the contact portion 51 is referred to as the memory cell TC of the corresponding layer.

[0045] Specifically, if at least two lead posts 5 are connected to memory cells TC of different layers in different memory cell groups TC0, then at least one lead post 5 is connected to a non-top-layer memory cell TC. For a lead post 5 connected to a non-top-layer memory cell TC, in addition to utilizing the space of the corresponding layer's memory cell TC, it also needs to occupy the space of the memory cell TC above that layer. For example, refer to... Figure 12 , Figure 14 and Figure 16 Since the second-to-top layer is the corresponding layer, the contact portion 51 of the lead post 5 is connected to the memory cell TC of the second-to-top layer. Therefore, the extension portion 52 of the lead post 5 needs to penetrate the memory cell TC of the top layer. The penetrated memory cell TC and the memory cell TC connected to the lead post no longer have storage function. In other words, part of the structure of the memory cell TC above the corresponding layer can be directly removed, thereby providing space for the extension portion 52 of the lead post 5, which helps to simplify the manufacturing process.

[0046] It should be noted that, in some other embodiments, the extension 52 of the lead post 5 may not occupy the space of the memory cell TC above the corresponding layer, but may occupy the space between adjacent memory cells TC. Specifically, refer to... Figure 10 The contact portion 51 of the lead post 5 protrudes from the position of the memory cell TC of the corresponding layer to the space between adjacent memory cells TC, so that the extension portion 52 of the lead post 5 can be led upward from the gap between adjacent memory cells TC without penetrating the memory cell TC above the corresponding layer, thereby reducing the number of failed memory cells TC. Alternatively, refer to... Figure 11 The contact portion 51 and the extension portion 52 of the lead post 5 are provided in the space between adjacent memory cells TC, and the contact portion 51 contacts the side wall of the memory cell TC of the corresponding layer, so that the extension portion 52 of the lead post 5 can be led upward from the gap between adjacent memory cells TC without penetrating the memory cell TC above the corresponding layer, thereby reducing the number of failed memory cells TC.

[0047] refer to Figure 4For the lead post 5 connected to the top layer storage cell TC, this lead post 5 only needs to utilize the space of the corresponding layer storage cell TC, without occupying the space of other storage cells TC. Therefore, it does not need to penetrate storage cells TC outside the corresponding layer.

[0048] It should be noted that in some embodiments, references Figure 4 , Figures 12-13 The lead post 5 can also penetrate the memory cell TC of the corresponding layer, that is, remove part of the structure of the memory cell TC of the corresponding layer, thereby providing space for the contact portion 51 of the lead post 5; at this time, at least part of the side of the lead post 5 is connected to the memory cell TC.

[0049] In other embodiments, the lead post 5 may not penetrate the memory cell TC of the corresponding layer. For example, refer to... Figures 14-15 The lead post 5 is embedded in the corresponding layer's memory cell TC. At this time, the bottom surface and part of the side surface of the lead post 5 are connected to the memory cell TC. Furthermore, refer to... Figures 16-17 The bottom surface of lead post 5 is connected to the top surface of the corresponding layer's memory cell TC.

[0050] refer to Figure 4 , Figure 13 , Figure 15 and Figure 17 At least two lead posts 5 penetrate different numbers of memory cells TC. That is, at least two lead posts 5 are connected to memory cells TC of different layers, thereby leading out memory cells TC of different layers. In this way, at least two steps can be reduced to reduce the size of the semiconductor structure.

[0051] refer to Figure 12 , Figure 14 , Figure 16 , Figures 18-21 The semiconductor structure also includes a dielectric layer 6 located between the lead post 5 and the penetrated memory cell TC. The dielectric layer 6 isolates the lead post 5 from the memory cell TC above the corresponding layer. It should be noted that if the lead post 5 also penetrates the memory cell TC of the corresponding layer, the dielectric layer 6 is located between the lead post 5 and the memory cell TC above the corresponding layer, exposing the sidewall of the lead post 5 within the memory cell TC of the corresponding layer, so that the lead post 5 is connected to the memory cell TC of the corresponding layer through the sidewall.

[0052] refer to Figure 4 There must be at least one memory cell group TC0 between any two adjacent lead posts 5. That is, two adjacent lead posts 5 are not connected to adjacent memory cell groups TC0. This helps to increase the spacing between adjacent lead posts 5, thereby reducing parasitic capacitance.

[0053] Specifically, in some examples, the number of memory cell groups TC0 between two adjacent lead posts 5 is the same, i.e., the spacing between adjacent lead posts 5 is balanced, thereby improving the uniformity of the semiconductor structure. In other examples, the facing area between two adjacent lead posts 5 is proportional to the number of memory cell groups TC0 between them. It is understood that the parasitic capacitance between adjacent lead posts 5 is also related to the facing area between them. If the facing area between them is larger, the number of memory cell groups TC0 between them can be increased accordingly to increase the spacing between them, thereby reducing the parasitic capacitance. For example, two lead posts 5 connected to the bottom and second-bottom layer memory cells TC are arranged adjacently, and there are five memory cell groups TC0 between the two lead posts 5; two lead posts 5 connected to the top and second-top layer memory cells TC are arranged adjacently, and there is one memory cell group TC0 between the two lead posts 5.

[0054] In other embodiments, reference is made to Figures 8-9 Two adjacent lead posts 5 can also be located in adjacent memory cell groups TC0, and there is no memory cell group TC0 between them.

[0055] The stacking structure will be explained in detail below.

[0056] refer to Figure 4 The semiconductor structure has a first direction X, a second direction Z, and a third direction Y. The first direction X is parallel to the surface of the substrate 11, the second direction Z is perpendicular to the surface of the substrate 11, and the third direction Y is parallel to the surface of the substrate 11. The third direction Y is different from the first direction X. For example, the third direction Y may be perpendicular to the first direction X.

[0057] Continue to refer to Figure 4 The stacked structure also includes multiple parallel signal lines 3 and multiple vertical signal lines 4; the multiple parallel signal lines 3 are arranged in the second direction Z and extend along the first direction X, and the parallel signal lines 3 are connected to a layer of memory cells TC; the vertical signal lines 4 extend along the second direction Z and are connected to the multilayer memory cells TC of the same memory cell group TC0. The lead post 5 is electrically connected to the parallel signal lines 3.

[0058] In other words, the parallel signal lines 3, which are stacked on the substrate 11, need to be led out through the lead posts 5 to facilitate subsequent electrical connection between the parallel signal lines 3 and the peripheral circuits. The vertical signal lines 4, however, are arranged perpendicular to the substrate 11 and therefore do not need to be led out through the lead posts 5. In some embodiments, the lead posts 5 can be directly connected to the parallel signal lines 3 to achieve electrical connection between the lead posts 5 and the parallel signal lines 3; in other embodiments, the lead posts 5 can be electrically connected to the parallel signal lines 3 through conductive structures within the memory cell TC. This will be explained in detail later.

[0059] refer to Figures 4-22In some embodiments, the memory cell TC may include transistors T and capacitor C arranged in a third-direction Y-shape, with parallel signal lines 3 and vertical signal lines 4 connected to transistors T. For example, in Dynamic Random Access Memory (DRAM), the memory cell TC includes one transistor T and one capacitor C. In other embodiments, the memory cell TC may also include only transistors T; for example, in Static Random-Access Memory (SRAM), the memory cell TC consists of six transistors T, or in Capacitorless Double Gate Quantum Well Single Transistor DRAM (1TDRAM), the memory cell TC consists of one dual-gate transistor T.

[0060] Transistor T includes a channel region 22 and source / drain doped regions 21 arranged in a third-direction Y-axis, with the source / drain doped regions 21 located on both sides of the channel region 22. One of the parallel signal line 3 and the vertical signal line 4 is a bit line BL, and the other is a word line WL. The bit line BL is connected to the source / drain doped regions 21, and the word line WL is connected to the channel region 22. For example, the source / drain doped regions 21 include a first source / drain doped region 211 and a second source / drain doped region 212. The first source / drain doped region 211 is located between the bit line BL and the channel region 22, and the second source / drain doped region 212 is located on the side of the channel region 22 away from the first source / drain doped region 211. The first source / drain doped region 211 and the second source / drain doped region 212 can serve as the source and drain of transistor T, respectively. Furthermore, the second source / drain doped region 21 may also include a lightly doped drain structure located between the channel region and the drain.

[0061] The following will provide a detailed explanation of the specific positional relationship between lead post 5, memory cell TC, and parallel signal line 3.

[0062] When parallel signal line 3 is the bit line BL and vertical signal line 4 is the word line WL, the specific positional relationship between lead post 5, memory cell TC, and parallel signal line 3 is as follows:

[0063] Example 1, for reference Figure 4 , Figures 12-17 At least one lead post 5 has its bottom surface located within the source / drain doped region 21. That is, the orthographic projection of the lead post 5 onto the surface of the substrate 11 overlaps with the orthographic projection of the source / drain doped region 21 onto the surface of the substrate 11, allowing the lead post 5 to achieve electrical connection with the bit line BL using the spatial location of the source / drain doped region 21. It should be noted that... Figure 13 , Figure 15 and Figure 17These are all schematic diagrams showing partial side views, and the channel area, vertical signal lines, and capacitors are not shown.

[0064] Specifically, at least one lead post 5 is connected to the first source / drain doped region 211 of the corresponding layer. Since the first source / drain doped region 211 is closer to the bit line BL than the second source / drain region 212, using the spatial position of the first source / drain doped region 211 to achieve the electrical connection between the lead post 5 and the bit line BL can reduce the spacing between the lead post 5 and the bit line BL, thereby reducing resistance and simplifying the manufacturing process. If the lead post 5 utilizes the spatial position of the second source / drain doped region 212 to achieve the electrical connection between the lead post 5 and the bit line BL, then the channel region 22 and the first source / drain doped region 211 can be conductively treated to reduce their resistance.

[0065] In some embodiments, reference Figure 4 , Figures 12-13 At least one lead post 5 penetrates at least one source / drain doped region 21 in a memory cell TC. The orthographic projection of the lead post 5 onto the substrate surface at least partially overlaps with the orthographic projection of the memory cell TC, such as the first source / drain doped region 211, onto the substrate surface. Specifically, at least one lead post 5 penetrates the source / drain doped region 21 of the corresponding layer; for example, the lead post 5 may penetrate the first source / drain doped region 211 of the memory cell TC of the corresponding layer. In this case, the lead post 5 can be directly connected to the bit line BL through its sidewall.

[0066] In other embodiments, reference is made to Figures 14-15 The bottom surface of the lead post 5 is embedded within the source / drain doped region 21. That is, the bottom end of the lead post 5 is located within the source / drain doped region 21, but does not completely penetrate the source / drain doped region 21. In this case, the lead post 5 can be directly connected to the bit line BL, or indirectly electrically connected to the bit line BL through the source / drain doped region 21.

[0067] In some other embodiments, reference is made to Figures 16-17 The bottom surface of the lead post 5 is located on the top surface of the source / drain doped region 21, for example, the bottom surface of the lead post 5 is located on the top surface of the first source / drain doped region 211. In this case, the lead post 5 is not directly connected to the bit line BL, but is electrically connected to the bit line BL through the source / drain doped region 21. To reduce the resistance of the source / drain doped region 21, the source / drain doped region 21 can be made conductive, for example, by using a metal silicide process to form metal silicide in the source / drain doped region 21; or, the source / drain doped region 21 can be heavily doped.

[0068] It should be noted that for memory cells TC connected to non-top layers, lead posts 5 can also penetrate the source / drain doped regions 21 above the corresponding layer. For lead posts 5 connected to memory cells TC on the top layer, lead posts 5 do not need to penetrate other source / drain doped regions 21 outside the corresponding layer.

[0069] Example 2, see reference Figure 18 The memory cell TC also includes a bit line contact region 23, which connects the bit line BL and the source / drain doped regions 21. The bit line contact region 23 can reduce the contact resistance between the bit line BL and the source / drain doped regions 21. For example, the bit line contact region 23 can be heavily doped polysilicon or metal silicide.

[0070] At least one lead post 5 has its bottom surface located in the bit line contact area 23. That is, the lead post 5 can also be electrically connected to the bit line BL using the spatial location of the bit line contact area 23. For example, at least one lead post 5 passes through the bit line contact area 23 in a memory cell TC. Alternatively, at least one lead post 5 is embedded in the bit line contact area 23 of the corresponding layer; or, the bottom surface of at least one lead post 5 is connected to the top surface of the bit line contact area 23 of the corresponding layer.

[0071] With parallel signal line 3 being the word line WL and vertical signal line 4 being the bit line BL, the specific positional relationship between lead post 5, memory cell TC, and parallel signal line 3 is as follows:

[0072] Example 1, for reference Figure 19 At least one lead post 5 has its bottom surface located in the channel region 22. That is, the orthographic projection of the lead post 5 on the surface of the substrate 11 overlaps with the orthographic projection of the channel region 22 on the surface of the substrate 11, and the lead post 5 can be electrically connected to the word line WL by utilizing the spatial position of the channel region 22.

[0073] It should be noted that the word line WL and the channel area 22 have various positional relationships. For example, the word line WL can cover the entire channel area 22, or the word line WL can be connected to the top and / or bottom surface of the channel area 22.

[0074] The following example illustrates the positional relationship between the lead post 5 and the lead line WL, with the lead line WL covering at least the top surface of the channel area 22.

[0075] refer to Figure 19 If lead post 5 is connected to a non-top-layer memory cell TC, then lead post 5 is electrically connected to the word line WL on the corresponding layer's memory cell TC and passes through the channel region 22 located above the corresponding layer and the word line WL. The orthographic projection of lead post 5 onto the substrate surface at least partially overlaps with the orthographic projection of the channel region 22 in the memory cell TC onto the substrate surface. It is worth noting that although lead post 5 passes through the word line WL, it does not completely sever the word line WL. For example, lead post 5 passes through the center of the word line WL. A dielectric layer 6 is also present between lead post 5 and the word line WL above the corresponding layer to prevent electrical connection between lead post 5 and the word line WL above the corresponding layer.

[0076] If the lead post 5 is connected to the top layer memory cell TC, then the lead post 5 can be electrically connected to the top layer word line WL without penetrating any word line WL and channel region 22.

[0077] Since the semiconductor structure includes at least two lead posts 5 connected to memory cells TC of different layers, at least one lead post 5 is connected to a non-top-layer memory cell TC. Therefore, at least one lead post 5 penetrates the channel region 22 in at least one memory cell TC.

[0078] It should be noted that if the word line WL does not cover the top surface of the channel area 22, but covers the bottom surface of the channel area 22, then the lead post 5 connected to the top layer memory cell TC must also penetrate at least one channel area 22 to connect with the word line WL on the bottom surface of the channel area 22.

[0079] Example 2, see reference Figures 20-21 At least one lead post 5 has its bottom surface located in the source / drain doped region 21, and a portion of the side surface of the lead post 5 is connected to the word line WL of the corresponding layer. Furthermore, the word line WL also penetrates the source / drain doped region 21 located above the corresponding layer. In other words, the lead post 5 can also achieve electrical connection with the word line WL by utilizing the location of the source / drain doped region 21. Specifically, refer to... Figure 20 At least one lead post 5 has its bottom surface located in the first source / drain doped region 211, and a portion of the side surface of the lead post 5 is connected to the word line WL of the corresponding layer. The orthographic projection of the lead post 5 onto the substrate surface at least partially overlaps with the orthographic projection of the first source / drain doped region 211 in the memory cell TC onto the substrate surface; Reference Figure 21 At least one lead post 5 has its bottom surface located in the second source / drain doped region 212, and a portion of the side surface of the lead post 5 is connected to the word line WL of the corresponding layer. The orthographic projection of the lead post 5 on the substrate surface at least partially overlaps with the orthographic projection of the second source / drain doped region 212 in the memory cell TC on the substrate surface.

[0080] It should be noted that the bottom surface of the lead post 5 is located in the source / drain doped region 21, but is electrically isolated from the source / drain doped region 21. For example, an isolation layer (not shown in the figure) can be formed on the bottom surface of the lead post 5, or the surface of the source / drain doped region 21 of the corresponding layer can be passivated before the lead post 5 is formed.

[0081] The structural modules will be described in detail below.

[0082] refer to Figure 22 The stacked structure consists of multiple parallel signal lines 3 of the same stacked structure, including the first to Nth parallel signal lines arranged sequentially in the second direction Z, where N is a positive integer greater than 1.

[0083] Two stacked structures constitute a structural module. The structural module also includes multiple wires 7, which connect two lead posts 5 that connect different stacked structures. In other words, two lead posts 5 located in different stacked structures are connected to a wire 7, and the sum of the serial numbers of the two parallel signal lines 3 electrically connected to the two lead posts 5 is N+1.

[0084] That is, two parallel signal lines 3 whose sum of serial numbers is N+1 can be electrically connected through lead post 5 and wire 7. The two electrically connected parallel signal lines 3 can form a parallel signal line group. Since they have the same potential, the two parallel signal lines 3 in the parallel signal line group can also be regarded as one parallel signal line 3.

[0085] For example, parallel signal line 3 includes 1 to 5 parallel signal lines, where the 1st parallel signal line of one stacked structure is interconnected with the 5th parallel signal line of another stacked structure; the 2nd parallel signal line of one stacked structure is interconnected with the 4th parallel signal line of another stacked structure; and the 3rd parallel signal line of one stacked structure is interconnected with the 3rd parallel signal line of another stacked structure. The 1st parallel signal line is located at the top layer, and the 5th parallel signal line is located at the bottom layer.

[0086] It should be noted that since lead post 5 penetrates the memory cell TC, the penetrated memory cell TC no longer performs its storage function. Because lead post 5 connects to memory cells TC in different layers, the number of usable memory cells TC varies in different layers within the semiconductor structure. For example, in a five-layer memory cell TC structure, layer 1 (top layer) lacks five memory cells TC; layer 2 lacks four; layer 3 lacks three; layer 4 lacks two; and layer 5 (bottom layer) lacks one. Under the influence of wire 7, the number of memory cells TC connected to different parallel signal line groups is the same.

[0087] Furthermore, since the lead posts 5 connected to the memory cells TC in different layers have different lengths, different resistances are generated. Based on the RC delay effect, the delay times of different memory cells TC are different. Under the action of the wire 7, the lead posts 5 are grouped in pairs, and the total length of each group of lead posts 5 is approximately the same. Therefore, it is beneficial to unify the delay time, thereby improving the performance of the semiconductor structure.

[0088] Furthermore, the contact area between the memory cell TC and the guide post 5 in different layers can be kept consistent, thereby achieving a uniform contact resistance and avoiding different delay times. For example, the contact area between the memory cell TC and the guide post 5 in different layers is 0.036–0.054 μm. 2 .

[0089] In some embodiments, the two lead posts 5 connected by the wire 7 are positioned opposite each other, and the extension direction of the wire 7 is perpendicular to the first direction X. This facilitates shortening the distance between the two lead posts 5, thereby reducing the length of the wire. A shorter wire length results in lower resistance, lower power consumption, and a shorter delay time. In other embodiments, refer to... Figure 22 The two lead posts 5 connected by wire 7 can also be staggered.

[0090] In the same structural module, transistors T in one stacked structure are positioned facing each other. That is, capacitor C in one stacked structure has two opposite sides arranged in a third-direction Y-shape, with the side facing the other stacked structure being the inner side and the side facing away from the other stacked structure being the outer side. The opposing transistors T indicate that both transistors T are located inside their respective stacked structures. This helps to reduce the spacing between the two transistors T, thereby reducing the spacing between the two lead posts 5, and consequently reducing the length of the wire 7.

[0091] like Figure 22 As shown, in some other embodiments, within the same structural module, transistors T in one stacked structure and transistors T in another stacked structure are arranged in the same direction. Alternatively, within the same structural module, transistors T in one stacked structure and transistors T in another stacked structure are arranged in opposite directions. When transistors T are arranged in the same direction, it means that transistor T in one stacked structure is located inside capacitor C, and transistor T in the other stacked structure is located outside capacitor C. When transistors T are arranged in opposite directions, it means that both transistors T in the two stacked structures are located outside capacitor C.

[0092] In summary, the embodiments of this disclosure integrate at least two lead posts 5 from the stepped region into the area where the memory cell TC is located, thereby improving the utilization rate of the surface area of ​​the substrate 11. If all lead posts 5 are located in the area where the memory cell TC is located, there is no need to separately separate the stepped region, thereby improving the integration of the semiconductor structure and facilitating an increase in the number of memory cells TC.

[0093] like Figures 23-35 As shown, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure. This manufacturing method can be used to manufacture the semiconductor structure provided in the foregoing embodiments. For a detailed description of the semiconductor structure, please refer to the foregoing embodiments. It should be noted that, for ease of description and to clearly illustrate the steps of the semiconductor structure fabrication method, Figures 23 to 35 These are all partial structural diagrams of semiconductor structures, in which... Figure 23 , Figure 25 , Figure 26 , Figures 28-30 This is a partial side view schematic diagram, and the channel area, vertical signal lines, and capacitors are not shown. Figure 24 , Figure 27 and Figure 31 This is a partial top view, and the insulating layer 12 is not shown. Figure 32 , Figure 34 This is a cross-sectional view along the first direction X. Figure 33 , Figure 34 This is a partial top view, and the insulating layer 12 is not shown.

[0094] refer to Figure 23 A substrate 11 is provided; a stacked structure is formed on the substrate 11, the stacked structure including a plurality of memory cell groups TC0 (reference) arranged in a first direction X. Figure 1 The storage cell group TC0 comprises multiple layers of storage cells TC arranged in the second direction Z. Multiple storage cells TC of the same storage cell group TC0 include storage cells numbered 1 to N, arranged sequentially. The 1st storage cell is located at the top layer, and the Nth storage cell is located at the bottom layer.

[0095] For example, a storage cell TC may include a transistor T and a capacitor C.

[0096] Specifically, the steps for forming transistor T may include: forming multiple spaced active layers, each active layer including multiple active structures; doping the active structures to form source / drain doped regions 21 and channel regions 22; and forming a gate dielectric layer on the surface of the channel regions 22. That is, the memory cell TC includes a channel region 22 and source / drain doped regions 21 arranged in the third direction Y, with the source / drain doped regions 21 located on both sides of the channel regions 22; the third direction Y is parallel to the surface of the substrate 11.

[0097] In addition, an insulating layer 12 needs to be formed between the transistors T in adjacent layers to isolate the adjacent transistors T.

[0098] The steps for forming capacitor C may include: forming a capacitor support layer and a capacitor aperture located within the capacitor support layer; forming a lower electrode on the inner wall of the capacitor aperture; forming a capacitor dielectric layer on the surface of the lower electrode; and forming an upper electrode on the surface of the capacitor dielectric layer. The lower electrode, the capacitor dielectric layer, and the upper electrode constitute capacitor C.

[0099] The manufacturing method also includes: forming multiple parallel signal lines 3 and multiple perpendicular signal lines 4 (see reference). Figure 4 Multiple parallel signal lines 3 are arranged in the second direction Z and extend along the first direction X. Each parallel signal line 3 connects to a layer of memory cell TC. Vertical signal lines 4 extend along the second direction Z and connect to the multilayer memory cell TC of the same memory cell group TC0. The first direction X is parallel to the surface of the substrate 11, and the second direction Z is perpendicular to the surface of the substrate 11.

[0100] One of the vertical signal line 4 and the parallel signal line 3 is the bit line BL, and the other is the word line WL. The bit line BL is connected to the source / drain doped region 21, and the word line WL is connected to the channel region 22 as the gate.

[0101] The method of forming the vertical signal line 4 may include: forming an isolation structure, etching the isolation structure to form a filling hole within the isolation structure, the filling hole extending in the second direction Z; and depositing conductive material within the filling hole to form the vertical signal line 4.

[0102] The steps for forming parallel signal lines 3 may include: depositing a conductive material on the surface of an active structure to coat the active structure with the conductive material. Subsequently, an isolation structure is formed between adjacent parallel signal lines 3.

[0103] refer to Figures 23-35 Multiple lead posts 5 are formed, wherein at least two lead posts 5 are respectively connected to memory cells TC of different layers in different memory cell groups TC0.

[0104] The following will describe in detail the steps involved in forming the lead post 5.

[0105] When the parallel signal line 3 is the bit line BL and the vertical signal line 4 is the word line WL, the specific steps for forming the lead post 5 are as follows:

[0106] First, it should be noted that the multiple source / drain doped regions 21 of the same memory cell group TC0 include source / drain doped regions arranged sequentially from the first layer to the Nth layer, where N is a positive integer. The first layer of source / drain doped regions is located at the top layer, and the Nth layer of source / drain doped regions is located at the bottom layer.

[0107] refer to Figures 23-24 A mask layer 71 is formed, having N openings 72, where N is a positive integer. The openings 72 are located above the source / drain doped regions 21, such as above the first source / drain doped region 211. For example, the mask layer 71 can be a photoresist layer, and photolithography is performed on the photoresist layer to form the openings 72. Alternatively, the mask layer 71 can also be a stacked hard mask layer and a photoresist layer, where photolithography is performed on the photoresist layer followed by etching of the hard mask layer to form the openings 72.

[0108] refer to Figure 25 The first memory cell is etched along the opening 72 to form a plurality of first sub-vias 811, one of which serves as the first via 81. Specifically, the source / drain doped regions 21 are etched along the opening 72. In addition, before etching the first memory cell, the insulating layer 12 located above the first memory cell also needs to be etched.

[0109] refer to Figures 26-27A sacrificial layer 73 is formed to fill the first sub-via 8. For example, a low dielectric constant material such as silicon oxide is deposited in the first sub-via 8 as the sacrificial layer 73.

[0110] Continue to refer to Figures 26-27 The mask layer 71 is patterned so that it has N-1 openings 72. Specifically, a photoresist layer can be spin-coated again and photolithographically formed on the photoresist layer to form the openings 72.

[0111] refer to Figure 28 The sacrificial layer 73 and the second memory cell are etched along the opening 72 to form the (N-1)th second sub-via 821, one of which serves as the second via 82. After etching the sacrificial layer 73, the insulating layer 72 located on the second memory cell also needs to be etched.

[0112] refer to Figure 29 The steps of forming the sacrificial layer 73, the patterned mask layer 71, and etching are repeated until the Nth memory cell is penetrated, that is, the Nth source / drain doped region is penetrated. In other embodiments, the steps of forming the sacrificial layer, the patterned mask layer 71, and etching are repeated until the (N-1)th memory cell is penetrated and the Nth memory cell is exposed; or, until the (N-1)th memory cell is penetrated and a portion of the thickness of the Nth memory cell is removed.

[0113] At this point, based on Figures 23-29 This can form a through hole 8, which includes through holes 1 to N. For example, refer to... Figure 29 A first via 81, a second via 82, a third via 83, a fourth via 84, and a fifth via 85 can be formed. In some embodiments, the first via 81 can penetrate the first layer of source / drain doped regions, and the Nth via can penetrate from the first layer of source / drain doped regions to the Nth layer of source / drain doped regions 21. In other embodiments, the first via 8 exposes the first layer of source / drain doped regions 21, and the Nth via penetrates from the first layer of source / drain doped regions to the (N-1)th layer of source / drain doped regions and exposes the Nth layer of source / drain doped regions 21. In still other embodiments, the bottom of the first via 8 is embedded in the first layer of source / drain doped regions 21, the Nth via penetrates from the first layer of source / drain doped regions to the (N-1)th layer of source / drain doped regions, and the bottom of the Nth via is embedded in the Nth layer of source / drain doped regions. It should be noted that, in the first direction X, the depths of the first through hole 81, the second through hole 82, the third through hole 83, the fourth through hole 84, and the fifth through hole 85 arranged sequentially increase in that direction. In other embodiments, the depths of the first through hole 81, the second through hole 82, the third through hole 83, the fourth through hole 84, and the fifth through hole 85 arranged sequentially in the first direction X may not increase or decrease, but may alternate between shallow and deep holes, thereby avoiding excessive parasitic capacitance between the deeper lead posts 5 formed subsequently.

[0114] refer to Figures 30-31A dielectric layer 6 is formed to cover the sidewalls of the via 8; a lead post 5 is formed to fill the via 8, and the lead post 5 is in contact with the corresponding source / drain doped region 21.

[0115] Specifically, when the Nth via penetrates the Nth source / drain doped region 21, or when the Nth via penetrates the (N-1)th source / drain doped region 21 and its bottom is embedded in the Nth source / drain doped region 21, the steps of forming the dielectric layer 6 and the lead post 5 may include:

[0116] A contact portion 51 is formed at the bottom of the via 8, and the contact portion 51 is connected to the memory cell TC of the corresponding layer. After forming the contact portion 51, a dielectric layer 6 is formed on the sidewall of the via 8. For example, an initial dielectric layer is formed on the sidewall of the via 8 and the surface of the contact portion 51 by a chemical vapor deposition process; the initial dielectric layer located on the surface of the contact portion 51 is removed, and the initial dielectric layer located on the sidewall of the via 8 serves as the dielectric layer 6. After forming the dielectric layer 6, an extension portion 52 is formed to fill the via 8. The extension portion 52 and the contact portion 51 constitute a lead post 5.

[0117] When the Nth via 8 penetrates the (N-1)th source / drain doped region and exposes the Nth source / drain doped region, the steps of forming the dielectric layer 6 and the lead post 5 may include: forming the dielectric layer 6 on the inner wall of the via 8, and then forming the lead post 5 to fill the via 8 after forming the dielectric layer 6. In this case, a metal silicide process can be used to form metal silicide in the source / drain doped region 21 of the corresponding layer to reduce contact resistance. Specifically, a metal layer is deposited on the inner wall of the via 8 and heat-treated to react the metal layer with the source / drain doped region 21; thereafter, the unreacted metal layer, which is mainly located on the sidewall of the via 8, is removed; then, the dielectric layer 6 and the lead post 5 are formed.

[0118] When the parallel signal line 3 is the word line WL and the vertical signal line 4 is the bit line BL, the specific steps for forming the lead post 5 are as follows:

[0119] First, it should be noted that the multiple channel regions 22 of the same memory cell group TC0 include channel regions 1 to N arranged sequentially, where N is a positive integer. The first channel region is located at the top layer, and the Nth channel region is located at the bottom layer.

[0120] refer to Figures 32-33 A through-hole 8 is formed, comprising a first through-hole 81 to an Nth through-hole. The first through-hole 8 exposes the word line WL connected to the first channel region, and the Nth through-hole 8 penetrates from the first channel region 22 to the (N-1)th channel region and exposes the word line WL connected to the Nth channel region. The steps for forming the through-hole 8 can be found in the detailed description described above.

[0121] refer to Figures 34-35A dielectric layer 6 is formed covering the sidewall of the through hole 8. Specifically, an initial dielectric layer is formed on the inner wall of the through hole 8, and the initial dielectric layer located on the bottom wall of the through hole 8 is removed to expose the corresponding letter line WL. The initial dielectric layer located on the sidewall of the through hole 8 serves as the dielectric layer 6.

[0122] Continue to refer to Figures 34-35 This forms lead posts 5 that fill the through-hole 8, and the lead posts 5 also contact the corresponding word lines WL. For example, metals such as copper, aluminum, titanium, or tungsten are deposited in the through-hole 8 to serve as lead posts 5.

[0123] It should be noted that the above method for forming the lead post 5 is only an example and is not limited thereto. The method for forming the lead post 5 can be adjusted according to the specific structure of the lead post 5.

[0124] In summary, in this embodiment, the memory cell TC is etched to form a via 8, and a dielectric layer and lead post 5 are formed to fill the via 8. Thus, the lead post 5 can utilize the spatial location of the memory cell TC to directly achieve electrical connection with the memory cell TC, thereby reducing the number of steps or eliminating the formation of separate step regions, which is beneficial for improving the integration density of the semiconductor structure.

[0125] refer to Figures 36-38 Another embodiment of this disclosure provides a semiconductor structure that is substantially the same as the semiconductor structure in the foregoing embodiments, the main difference being that at least two lead posts 5 of this semiconductor structure are connected to different memory cells TC in the same memory cell group TC0. For the parts of this semiconductor structure that are the same as or similar to the semiconductor structures in the foregoing embodiments, please refer to the detailed descriptions in the foregoing embodiments, which will not be repeated here.

[0126] The semiconductor structure includes: substrate 11 (reference) Figure 34 The substrate 11 has a stacked structure, which includes multiple memory cell groups TC0 arranged in a first direction X, and the memory cell groups TC0 include multilayer memory cells TC arranged in a second direction Z; multiple lead posts 5, wherein at least two lead posts 5 are connected to different memory cells TC in the same memory cell group TC0.

[0127] Compared to different lead posts 5 being located in different memory cell groups TC0, at least two lead posts 5 can utilize the space within the same memory cell group TC0, thereby improving space utilization within the same memory cell group TC0 and increasing the number of available memory cells TC. For example, if two lead posts 5 are connected to the top-level and second-to-top-level memory cells TC respectively, three failed memory cells TC will be generated when they are located in different memory cell groups TC0; and two failed memory cells TC will be generated when they are located in the same memory cell group TC0.

[0128] It should be noted that the above two schemes can also be combined in the same semiconductor structure. For example, the semiconductor structure includes at least four lead posts 5, wherein at least two lead posts 5 are respectively connected to memory cells TC of different layers in different memory cell groups TC0, and at least two lead posts 5 are respectively connected to memory cells TC of different layers in the same memory cell group TC0.

[0129] Continue to refer to Figures 36-38 At least two lead posts 5 connecting different memory cells TC in the same memory cell group TC0 are arranged along the first direction X. This facilitates the unification of the connection positions between the lead posts 5 and the memory cells TC, thereby simplifying the connection process.

[0130] In some embodiments, the stacked structure further includes multiple parallel signal lines 3 and multiple vertical signal lines 4; the multiple parallel signal lines 3 are arranged in a second direction Z and extend along a first direction X, and the parallel signal lines 3 are connected to a layer of memory cells TC; the vertical signal lines 4 extend along the second direction Z and are connected to the multilayer memory cells TC of the same memory cell group TC0. The lead post 5 is electrically connected to the parallel signal lines 3.

[0131] In some embodiments, the lead posts 5 connecting different memory cells TC in the same memory cell group TC0 are arranged in a row along a first direction X. That is, the lead posts 5 are approximately aligned in the first direction X. In this way, the spacing between the multiple lead posts 5 and the parallel signal lines 3 is approximately the same, which helps to balance the contact resistance between the multiple lead posts 5 and the parallel signal lines 3. Furthermore, it also helps to simplify the process and improve the uniformity of the semiconductor structure. For example, referring to… Figure 37 Multiple lead posts 5 are aligned at both ends in the first direction X, which simplifies the manufacturing process. (Reference) Figure 38 The two ends of the multiple lead posts 5 in the first direction X are slightly offset, thereby reducing the facing area and reducing parasitic capacitance.

[0132] In summary, in this embodiment, at least two lead posts 5 are fused from the stepped region into the area where the memory cell TC is located, thereby improving the utilization rate of the surface area of ​​the substrate 11. Furthermore, since at least two lead posts 5 are connected to memory cells TC of different layers within the same memory cell group TC0, it indicates that at least two lead posts 5 can utilize the spatial location of the same memory cell group TC0, which helps to reduce the number of failed memory cells TC and thus improves the integration density of the semiconductor structure.

[0133] This disclosure also provides a memory chip, including the semiconductor structure provided in the foregoing embodiments.

[0134] Memory chips are memory components used to store programs and various data information. For example, memory chips can be random access memory (RAM) chips or read-only memory (ROM) chips. Specifically, RAM chips can include dynamic random access memory (DRAM) or static random access memory (SRAM). The high integration density of the aforementioned semiconductor structures facilitates the miniaturization of memory chips.

[0135] This disclosure also provides an electronic device, including the memory chip provided in the foregoing embodiments.

[0136] For example, the electronic device can be a television, computer, mobile phone, or tablet. The electronic device may include a circuit board and a package structure, with the memory chip soldered onto the circuit board and protected by the package structure. Furthermore, the electronic device may include a power supply for providing operating voltage to the memory chip.

[0137] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0138] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a stacked structure, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including multi-layer memory cells arranged in a second direction; Multiple lead posts, wherein at least two of the lead posts are respectively connected to memory cells in different layers of different memory cell groups, and the number of memory cells penetrated by the at least two lead posts is different, the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

2. The semiconductor structure according to claim 1, characterized in that, The lead posts are arranged in a row along the first direction.

3. The semiconductor structure according to claim 2, characterized in that, The lead posts are arranged in a straight line along the first direction.

4. The semiconductor structure according to claim 1, characterized in that, All of the memory cells in the same group of memory cells are connected to at most one of the lead posts.

5. The semiconductor structure according to claim 1, characterized in that, The number of lead posts is equal to or greater than the number of layers of the memory cell, and each layer includes at least one memory cell connected to the lead post.

6. The semiconductor structure according to claim 1, characterized in that, The number of lead posts connected to the same group of storage cells is less than the number of layers of the storage cells in the group of storage cells.

7. The semiconductor structure according to claim 1, characterized in that, The stacked structure further includes multiple parallel signal lines and multiple vertical signal lines; the multiple parallel signal lines are arranged in a second direction and extend along the first direction, and the parallel signal lines connect to one layer of the memory cell; the vertical signal lines extend along the second direction and connect to multiple layers of the memory cell group. The lead post is electrically connected to the parallel signal line.

8. The semiconductor structure according to claim 7, characterized in that, The memory cell includes a channel region and source / drain doped regions arranged in a third direction, with the source / drain doped regions located on both sides of the channel region; the third direction is parallel to the substrate surface.

9. The semiconductor structure according to claim 8, characterized in that, The parallel signal lines are bit lines, and the vertical signal lines are word lines; The bit line is connected to the source / drain doped region, and the word line is connected to the channel region; At least one of the lead posts penetrates the source / drain doped regions in at least one of the memory cells.

10. The semiconductor structure according to claim 9, characterized in that, The source / drain doped region includes a first source / drain doped region and a second source / drain doped region. The first source / drain doped region is located between the bit line and the channel region, and the second source / drain doped region is located on the side of the channel region away from the first source / drain doped region. The lead post penetrates the first source / drain doped region.

11. The semiconductor structure according to claim 8, characterized in that, The parallel signal lines are word lines, and the vertical signal lines are bit lines; The bit line is connected to the source / drain doped region, and the word line is connected to the channel region; At least one of the lead posts penetrates the channel region in at least one of the memory cells.

12. The semiconductor structure according to claim 8, characterized in that, The storage cell further includes a bit line contact region, which connects the bit line and the source / drain doped regions.

13. The semiconductor structure according to claim 12, characterized in that, At least one of the lead posts extends through the bit line contact area in one of the memory cells.

14. The semiconductor structure according to claim 1, characterized in that, There is at least one group of memory cells between any two adjacent lead posts.

15. The semiconductor structure according to claim 14, characterized in that, The number of memory cell groups between two adjacent lead posts is the same.

16. The semiconductor structure according to claim 15, characterized in that, The area of ​​two adjacent lead posts facing each other is proportional to the number of memory cell groups between the two adjacent lead posts.

17. The semiconductor structure according to claim 7, characterized in that, The stacked structure is multiple, and the multiple parallel signal lines of the same stacked structure include the 1st to Nth parallel signal lines arranged sequentially in the second direction, where N is a positive integer greater than 1; The two stacked structures constitute a structural module, and the structural module further includes multiple wires. The wires connect two lead posts that connect different stacked structures, and the sum of the sequence numbers of the two parallel signal lines electrically connected to the two lead posts is N+1.

18. The semiconductor structure according to claim 17, characterized in that, The two lead posts connected by the wire are positioned opposite each other, and the extension direction of the wire is perpendicular to the first direction.

19. The semiconductor structure according to claim 17, characterized in that, The storage unit includes transistors and capacitors arranged in a third direction; In the same structural module, the transistors of one stacked structure are arranged facing each other with the transistors of another stacked structure; or In the same structural module, the transistors of one stacked structure are arranged in the same direction as the transistors of another stacked structure; or In the same structural module, the transistors of one stacked structure are arranged in reverse order with the transistors of another stacked structure.

20. The semiconductor structure according to claim 1, characterized in that, At least one of the lead posts extends in a second direction and penetrates at least one memory cell in the memory cell group; The semiconductor structure further includes a dielectric layer located between the lead post and the memory cell through which it is penetrated.

21. The semiconductor structure according to claim 20, characterized in that, The bottom surface of the lead post is connected to the storage cell, or at least a portion of the side surface of the lead post is connected to the storage cell.

22. The semiconductor structure according to claim 1, characterized in that, At least two of the aforementioned lead posts are connected to the same memory cell group.

23. The semiconductor structure according to claim 1, characterized in that, At least two of the lead posts are connected to different memory cells in the same memory cell group.

24. The semiconductor structure according to claim 23, characterized in that, At least two of the lead posts connecting different memory cells in the same memory cell group are arranged along a first direction.

25. The semiconductor structure according to claim 24, characterized in that, The lead posts connecting different memory cells in the same memory cell group are arranged in a row along a first direction.

26. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a base A stacked structure is formed on the substrate, the stacked structure including a plurality of memory cell groups arranged in a first direction, the memory cell groups including multilayer memory cells arranged in a second direction; Multiple lead posts are formed, wherein at least two of the lead posts are respectively connected to memory cells in different layers of different memory cell groups, and the number of memory cells penetrated by the at least two lead posts is different. The first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface.

27. The method for manufacturing a semiconductor structure according to claim 26, characterized in that, The first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface; Multiple parallel signal lines and multiple vertical signal lines are formed; the multiple parallel signal lines are arranged in a second direction and extend along the first direction, and each of the parallel signal lines connects to one layer of the memory cell; the vertical signal lines extend along the second direction and are connected to multiple layers of memory cells in the same memory cell group.

28. The method for manufacturing a semiconductor structure according to claim 27, characterized in that, The memory cell includes a channel region and source / drain doped regions arranged in a third direction, with the source / drain doped regions located on both sides of the channel region; the third direction is parallel to the substrate surface; the multiple source / drain doped regions of the same memory cell group include a first layer of source / drain doped regions to an Nth layer of source / drain doped regions arranged sequentially, where N is a positive integer; The parallel signal lines are bit lines, and the vertical signal lines are word lines; The bit line is connected to the source / drain doped region, and the word line is connected to the channel region; The manufacturing method includes: Forming vias 1 to N, with the first via exposing the first layer of source / drain doped regions and the Nth via penetrating the first layer of source / drain doped regions to the (N-1)th layer of source / drain doped regions and exposing the Nth layer of source / drain doped regions; A dielectric layer is formed covering the sidewalls of the through-hole; A lead post is formed to fill the through-hole, and the lead post is in contact with the corresponding source / drain doped region.

29. The method for manufacturing a semiconductor structure according to claim 27, characterized in that, The memory cell includes a channel region and a source / drain doped region arranged in a third direction, with the source / drain doped regions located on both sides of the channel region; the third direction is parallel to the substrate surface; the multiple channel regions in the same memory cell group include a first channel region to an Nth channel region arranged in sequence, where N is a positive integer; the parallel signal lines are word lines, and the vertical signal lines are bit lines; The bit line is connected to the source / drain doped region, and the word line is connected to the channel region; The method includes: Forming a first through hole to a Nth through hole, the first through hole exposing the word line connected to the first channel area, and the Nth through hole penetrating the first channel area to the (N-1)th channel area and exposing the word line connected to the Nth channel area; A dielectric layer is formed covering the sidewalls of the through-hole; A lead post is formed to fill the through hole, and the lead post is also in contact with the corresponding word line.

30. The method for manufacturing a semiconductor structure according to claim 28, characterized in that, The plurality of storage cells in the same storage cell group include storage cells numbered 1 to N arranged sequentially; Before forming multiple lead posts, the process includes: A mask layer is formed, the mask layer having N openings; N is a positive integer; The first memory cell is etched along the opening to form a plurality of first sub-vias, one of which serves as the first via; A sacrificial layer is formed to fill the first sub-via; The mask layer is patterned so that it has N-1 openings; Etch the sacrificial layer and the second memory cell along the opening; The steps of forming the sacrificial layer, patterning the mask layer, and etching are repeated until the N-1th memory cell is penetrated.

31. A memory chip, characterized in that, The semiconductor structure included in any one of claims 1-25.

32. An electronic device, characterized in that, Includes the memory chip as described in claim 31.

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