P-gan active-passivated gan hemt device with etch stop layer and method of making
By inserting a graded Al composition AlGaN etch stop layer between the p-GaN active passivation layer and the AlGaN etch stop layer, self-stopping etching is achieved, solving the etching damage problem and improving the stability and high-frequency performance of gallium nitride high electron mobility transistors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-10-10
- Publication Date
- 2026-07-31
AI Technical Summary
In the prior art, etching damage in gallium nitride high electron mobility transistors is difficult to control, leading to unstable device performance. This is especially true in P-type gate enhancement devices, where etching damage affects the integrity of the AlGaN barrier layer and the high-frequency application of the device.
By inserting a graded Al composition AlGaN etch stop layer between the p-GaN active passivation layer and the AlGaN etch stop layer, self-stopping etch is achieved by utilizing its different etch selectivity ratio with p-GaN, avoiding etch damage. The p-GaN active passivation layer is retained between the gate and drain, reducing damage to the AlGaN barrier layer.
It effectively avoids etching damage, improves device consistency and stability, reduces dynamic on-resistance, and enhances the device's high-voltage application capability.
Smart Images
Figure CN117352547B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronics technology, specifically relating to a p-GaN active passivated GaNHEMT device with an etch stop layer and its fabrication method. Background Technology
[0002] With the development of new energy technologies, power electronic systems are constantly evolving towards higher efficiency and higher power, which places higher demands on power devices. To meet the needs of miniaturization and high efficiency in power electronics, it is necessary to further improve their performance. Gallium nitride (GaN) devices have become the mainstay of the next generation of power devices due to their excellent material properties. How to further improve the power performance and stability of GaN high electron mobility transistors has become a key research focus.
[0003] Currently, there are two main types of mainstream gallium nitride (GaN) power devices: cascaded and P-gate enhancement-mode (PGM). Cascaded GaN devices achieve enhancement mode by connecting a depletion-mode GaN device to an enhancement-mode silicon power transistor. While this avoids many problems introduced by etching, the cascading introduces lead inductance, which limits the high-frequency application of GaN devices to some extent. P-gate enhancement-mode devices deplete electrons in the channel through a P-type GaN cap layer above the barrier layer and below the gate. This approach requires etching away the P-type GaN cap layer in the non-gate region. Since precise etching is not possible, etching damage is inevitably introduced, affecting device performance. Therefore, achieving precise etching, reducing etching damage, and improving the performance of enhancement-mode devices are crucial issues.
[0004] Currently, there are solutions to reduce etching damage and protect the barrier layer by using interfacial acid-base treatment and retaining a certain thickness of p-GaN layer. This involves incomplete etching of p-GaN to avoid damaging the AlGaN barrier layer, followed by acid-base treatment of the etched device surface to improve interfacial properties, thereby obtaining a p-GaN enhancement-mode device with minimal etching damage and stable performance. However, in real-world scenarios, etching processes are not entirely controllable, and it is difficult to guarantee the thickness of the retained p-GaN layer during etching. Therefore, existing methods cannot effectively reduce etching damage and thus provide effective protection for the barrier layer. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a p-GaN active passivated GaN HEMT device with an etch stop layer and its fabrication method.
[0006] The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] In a first aspect, the present invention provides a p-GaN active passivated GaN HEMT device with an etch stop layer, comprising:
[0008] The substrate layer, GaN buffer layer, GaN channel layer and AlGaN barrier layer are arranged sequentially from bottom to top;
[0009] A source and a drain are disposed along the upper surface of the AlGaN barrier layer; the source and the drain are located at opposite ends of the AlGaN barrier layer;
[0010] A p-GaN active passivation layer and a graded AlGaN etch stop layer of equal width are disposed from bottom to top in the target region between the source and the drain. A p-GaN layer is disposed in a portion of the graded AlGaN etch stop layer, and a gate is disposed in a portion of the p-GaN layer. A SiN passivation layer of predetermined thickness is covered along the surface from the inner wall of the drain to the inner wall of the source, and the SiN passivation layer does not cover the gate.
[0011] Optionally, the left sidewalls of the p-GaN active passivation layer, the gradient Al composition AlGaN etch stop layer, and the p-GaN layer are aligned. The widths of the p-GaN active passivation layer and the gradient Al composition AlGaN etch stop layer are smaller than the width of the target region, the width of the p-GaN layer is smaller than the width of the gradient Al composition AlGaN etch stop layer, and the width of the gate is smaller than the width of the p-GaN layer.
[0012] Optionally, the thickness of the gradient Al composition AlGaN etch stop layer is between 3 and 5 nm; wherein the molar fraction of Al decreases sequentially from 25% to 13% or from 28% to 15% along the lower surface to the upper surface of the gradient Al composition AlGaN etch stop layer.
[0013] Optionally, the gradient Al composition AlGaN etch stop layer is p-type AlGaN.
[0014] Optionally, the thickness of the p-GaN active passivation layer is between 3 and 9 nm, the thickness of the p-GaN layer is between 50 and 80 nm, and the thickness of the GaN buffer layer is between 1 and 4 μm.
[0015] Optionally, the gradient Al composition AlGaN etch stop layer is divided into two regions, left and right, with the thickness of the left region being greater than that of the right region. The p-GaN layer is disposed on the left region, and its bottom surface completely occupies the left region.
[0016] Optionally, the substrate material is any one of sapphire, Si, and SiC.
[0017] Optionally, the AlGaN barrier layer has a thickness between 13 and 20 nm and an Al molar composition of 18%.
[0018] Optionally, the thickness of the SiN passivation layer is 100 nm.
[0019] Secondly, the present invention provides a method for fabricating a p-GaN active passivated GaN HEMT device with an etch stop layer, comprising:
[0020] GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-GaN active passivation layer, graded Al composition AlGaN etch stop layer and p-GaN layer are grown sequentially upward on the substrate.
[0021] The p-GaN layer, the gradient Al composition AlGaN etch stop layer, and the p-GaN active passivation layer are etched to make the widths of the gradient Al composition AlGaN etch stop layer and the p-GaN active passivation layer equal, and the width of the p-GaN layer is smaller than the width of the gradient Al composition AlGaN etch stop layer, thus forming a first current sample.
[0022] A source and a drain are grown upwards at both ends of the AlGaN barrier layer of the first current sample to form a second current sample;
[0023] A gate metal layer is deposited upward in a portion of the p-GaN layer of the second current sample to form a gate;
[0024] A SiN passivation layer of predetermined thickness is deposited along the inner wall of the drain to the inner wall of the source, wherein the SiN passivation layer does not cover the gate.
[0025] This invention provides a p-GaN active passivated GaN HEMT device with an etch stop layer and its fabrication method. The p-GaN active passivated GaN HEMT device with an etch stop layer includes: a substrate layer, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer, arranged sequentially from bottom to top; a source and a drain are disposed along the upper surface of the AlGaN barrier layer; the source and the drain are located at opposite ends of the AlGaN barrier layer; a p-GaN active passivation layer and a graded Al composition AlGaN etch stop layer of equal width are disposed from bottom to top in a target region between the source and the drain; a p-GaN layer is disposed in a portion of the graded Al composition AlGaN etch stop layer, and a gate is disposed in a portion of the p-GaN layer; a SiN passivation layer of predetermined thickness is covered along the surface from the inner wall of the drain to the inner wall of the source, and the SiN passivation layer does not cover the gate. By inserting a graded Al composition AlGaN etch stop layer between the p-GaN active passivation layer and the p-GaN layer, the different etch selectivity ratios of AlGaN and p-GaN enable the p-GaN layer to achieve self-stopping etching during the etching process. In addition, by setting a p-GaN active passivation layer and a graded Al composition AlGaN etch stop layer of the same width, the p-GaN active passivation layer retained between the gate and drain can avoid etching damage on the AlGaN barrier layer, thereby improving device uniformity.
[0026] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description
[0027] Figure 1 A schematic diagram of the structure of a p-GaN active passivated GaN HEMT device with an etch stop layer provided in an embodiment of the present invention;
[0028] Figure 2 This is a schematic diagram of the fabrication process of a p-GaN active passivated GaN HEMT device with an etch stop layer provided in an embodiment of the present invention. Detailed Implementation
[0029] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0030] To avoid etching damage and improve device consistency, this invention provides a p-GaN active passivated GaN HEMT device with an etch stop layer. Figure 1 A schematic diagram of the structure of a p-GaN active passivated GaN HEMT device with an etch stop layer provided in an embodiment of the present invention is shown below. Figure 1As shown, the p-GaN active passivated GaNHEMT device with an etch stop layer includes:
[0031] The substrate layer, GaN buffer layer, GaN channel layer and AlGaN barrier layer are arranged sequentially from bottom to top;
[0032] A source and a drain are disposed along the upper surface of the AlGaN barrier layer; the source and the drain are located at opposite ends of the AlGaN barrier layer;
[0033] A p-GaN active passivation layer and a graded AlGaN etch stop layer of equal width are disposed from bottom to top in the target region between the source and the drain. A p-GaN layer is disposed in a portion of the graded AlGaN etch stop layer, and a gate is disposed in a portion of the p-GaN layer. A SiN passivation layer of predetermined thickness is covered along the surface from the inner wall of the drain to the inner wall of the source, and the SiN passivation layer does not cover the gate.
[0034] from Figure 1 It can be seen that by setting a p-GaN active passivation layer of the same width and an AlGaN etch stop layer with a gradient Al composition, the p-GaN active passivation layer retained between the gate and drain can avoid etching damage to the interface states on the AlGaN barrier layer, thus preventing the interface states from trapping electrons and forming a virtual gate. At the same time, the holes in the p-GaN active passivation layer can shield the virtual gate, ensuring that the 2DEG concentration is not affected, and thus the dynamic on-resistance phenomenon in the device is well resolved.
[0035] This invention provides a p-GaN active passivated GaN HEMT device with an etch stop layer, comprising: a substrate layer, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer disposed sequentially from bottom to top; a source and a drain disposed along the upper surface of the AlGaN barrier layer; the source and the drain being located at opposite ends of the AlGaN barrier layer; a p-GaN active passivation layer and a graded Al composition AlGaN etch stop layer of equal width disposed from bottom to top in a target region between the source and the drain; a p-GaN layer disposed in a portion of the graded Al composition AlGaN etch stop layer, and a gate disposed in a portion of the p-GaN layer; a SiN passivation layer of predetermined thickness covering the surface traversed from the inner sidewall of the drain to the inner sidewall of the source, wherein the SiN passivation layer does not cover the gate. By inserting a graded Al composition AlGaN etch stop layer between the p-GaN active passivation layer and the p-GaN layer, the different etch selectivity ratios of AlGaN and p-GaN enable the p-GaN layer to achieve self-stopping etching during the etching process. In addition, by setting a p-GaN active passivation layer and a graded Al composition AlGaN etch stop layer of the same width, the p-GaN active passivation layer retained between the gate and drain can avoid etching damage on the AlGaN barrier layer, thereby improving device uniformity.
[0036] Optionally, the left sidewalls of the p-GaN active passivation layer, the gradient Al composition AlGaN etch stop layer, and the p-GaN layer are aligned. The widths of the p-GaN active passivation layer and the gradient Al composition AlGaN etch stop layer are smaller than the width of the target region, the width of the p-GaN layer is smaller than the width of the gradient Al composition AlGaN etch stop layer, and the width of the gate is smaller than the width of the p-GaN layer.
[0037] It is understood that the depletion capability of the p-GaN active passivation layer in the embodiments of the present invention can disperse the electric field between the gate and drain under high voltage off-state, reduce the peak electric field near the gate, and improve the device breakdown voltage.
[0038] Optionally, the thickness of the gradient Al composition AlGaN etch stop layer is between 3 and 5 nm; wherein the molar fraction of Al decreases sequentially from 25% to 13% or from 28% to 15% along the lower surface to the upper surface of the gradient Al composition AlGaN etch stop layer.
[0039] It should be noted that the higher the molar fraction of Al, the more difficult the etching becomes. By increasing the molar fraction of Al from the upper to the lower surface, the etching difficulty can be appropriately increased, thus avoiding over-etching of the p-GaN layer to some extent.
[0040] Optionally, the gradient Al composition AlGaN etch stop layer is p-type AlGaN.
[0041] It is understood that the p-type AlGaN provided in the embodiments of the present invention can increase the built-in electric field of the gate, increase the gate breakdown voltage, and improve the gate voltage swing, which is beneficial for applications in high-voltage scenarios.
[0042] Optionally, the thickness of the p-GaN active passivation layer is between 3 and 9 nm, the thickness of the p-GaN layer is between 50 and 80 nm, and the thickness of the GaN buffer layer is between 1 and 4 μm.
[0043] Optionally, the gradient Al composition AlGaN etch stop layer is divided into two regions, left and right, with the thickness of the left region being greater than that of the right region. The p-GaN layer is disposed on the left region, and its bottom surface completely occupies the left region.
[0044] It should be noted that, in this embodiment of the invention, the p-GaN active passivation layer is also divided into two regions, similar to the division method of the AlGaN etch stop layer with gradient Al composition. The depletion capability of the p-GaN active passivation layer in the right region can disperse the electric field between the gate and drain under high voltage off state, reduce the peak electric field near the gate, and improve the device breakdown voltage.
[0045] Optionally, the substrate material is any one of sapphire, Si, and SiC.
[0046] Optionally, the AlGaN barrier layer has a thickness between 13 and 20 nm and an Al molar composition of 18%.
[0047] Optionally, the thickness of the SiN passivation layer is 100 nm.
[0048] Corresponding to a p-GaN active passivated GaN HEMT device with an etch stop layer, this invention provides a method for fabricating a p-GaN active passivated GaN HEMT device with an etch stop layer, comprising:
[0049] GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-GaN active passivation layer, graded Al composition AlGaN etch stop layer and p-GaN layer are grown sequentially upward on the substrate.
[0050] The p-GaN layer, the gradient Al composition AlGaN etch stop layer, and the p-GaN active passivation layer are etched to make the widths of the gradient Al composition AlGaN etch stop layer and the p-GaN active passivation layer equal, and the width of the p-GaN layer is smaller than the width of the gradient Al composition AlGaN etch stop layer, thus forming a first current sample.
[0051] A source and a drain are grown upwards at both ends of the AlGaN barrier layer of the first current sample to form a second current sample;
[0052] A gate metal layer is deposited upward in a portion of the p-GaN layer of the second current sample to form a gate;
[0053] A SiN passivation layer of predetermined thickness is deposited along the inner wall of the drain to the inner wall of the source, wherein the SiN passivation layer does not cover the gate.
[0054] It should be noted that, in the embodiments of the present invention, the substrate material can be any one of sapphire, Si, and SiC.
[0055] Optionally, in this embodiment of the invention, an MOCVD process can be used to grow a GaN buffer layer.
[0056] To clearly illustrate the fabrication process of the p-GaN active passivated GaN HEMT device with an etch stop layer provided in the embodiments of the present invention, Figure 2 A schematic diagram of the fabrication process of a p-GaN active passivated GaN HEMT device with an etch stop layer is provided.
[0057] In this embodiment of the invention, the growth process of the first current sample may include: using a spin coater at a rotation speed of 3000 rpm to... Figure 2 In Figure (f), the p-GaN layer is spin-coated and then exposed using an NSR1755I7A lithography machine to form a p-GaN region mask pattern. The substrate with the mask is then etched using an ICP98c inductively coupled plasma etching machine. By adjusting the etching gas and electrode power, and utilizing different etching ratios for GaN and AlGaN, self-stop etching is achieved, resulting in... Figure 2 The device in Figure (g) is shown. Next, the substrate obtained from the self-stop etching process is spin-coated at 3000 rpm using a spin coater, and then exposed using an NSR1755I7A lithography machine to form a mask pattern for the p-GaN active passivation layer region. Then, the substrate with the p-GaN active passivation layer mask pattern is etched using an ICP98c inductively coupled plasma etching machine to remove the gradient Al composition AlGaN etching stop layer and the p-GaN active passivation layer in the non-active passivation region, resulting in... Figure 2 The device in the (h) diagram.
[0058] The growth process of the source and drain electrodes may include: using a spin coater at a speed of 5000 rpm... Figure 2The device in Figure (h) was subjected to photoresist stripping to obtain a photoresist mask with a thickness of 0.8 μm. Next, it was baked in a high-temperature oven at 80°C for 10 min and exposed using an NSR1755I7A lithography machine to form the source and drain region mask patterns. Then, ohmic electrodes were fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The ohmic electrode metals were sequentially selected as Ti / Al / Ni / Au, with Ti thicknesses of 20 nm, Al thicknesses of 160 nm, Ni thicknesses of 55 nm, and Au thicknesses of 45 nm. After the evaporation of the source and drain ohmic electrode metals, metal stripping was performed to obtain complete source and drain electrodes. Finally, rapid thermal annealing was performed in an RTP500 rapid thermal annealing furnace at 870°C in a N2 atmosphere for 30 s to alloy the ohmic electrode metals, completing the fabrication of the source and drain electrodes. Figure 2 The device in diagram (i) of the diagram.
[0059] The specific process of etching the mesa may include: first, using a spin coater at a speed of 3000 rpm to... Figure 2 The device in Figure (i) is spin-coated and then exposed using an NSR1755I7A lithography machine to form source and drain mesa mask patterns. The masked substrate is then etched using an ICP98c inductively coupled plasma etching machine to a depth of 200 nm, resulting in the final product. Figure 2 The device in (j) diagram.
[0060] The gate fabrication process may specifically include: using a spin coater at a speed of 5000 rpm to... Figure 2 The device in Figure (j) was spin-coated to obtain a photoresist mask with a thickness of 0.8 μm. Next, it was baked in a high-temperature oven at 80°C for 10 min, followed by exposure using an NSR1755I7A lithography machine to form the gate region mask pattern. Finally, the gate metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The gate metal was selected as Ni / Au, with Ni having a thickness of 45 nm and Au a thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete gate, forming... Figure 2 The device in the (k) diagram.
[0061] The deposition process of the SiN passivation layer may include: using a CVD deposition device to deposit a SiN passivation layer of a predetermined thickness along the surface traversed from the inner wall of the drain to the inner wall of the source, wherein the SiN passivation layer does not cover the gate, ultimately resulting in... Figure 2 The device in Figure (l) of the diagram.
[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0063] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the description of this invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0064] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A p-GaN active-passivated GaN HEMT device with an etch stop layer, characterized by, include: The substrate layer, GaN buffer layer, GaN channel layer and AlGaN barrier layer are arranged sequentially from bottom to top; A source and a drain are disposed along the upper surface of the AlGaN barrier layer; The source and the drain are located at opposite ends of the AlGaN barrier layer; A p-GaN active passivation layer and a graded AlGaN etch stop layer of equal width are disposed from bottom to top in the target region between the source and the drain. A p-GaN layer is disposed in a portion of the AlGaN etching stop layer with gradient Al composition, and a gate is disposed in a portion of the p-GaN layer; The surface along the inner wall of the drain to the inner wall of the source is covered with a SiN passivation layer of a predetermined thickness, and the SiN passivation layer does not cover the gate.
2. The p-GaN active-passivated GaN HEMT device with etch stop layer of claim 1, wherein, The p-GaN active passivation layer, the gradient Al composition AlGaN etch stop layer, and the left sidewall of the p-GaN layer are aligned. The widths of the p-GaN active passivation layer and the gradient Al composition AlGaN etch stop layer are smaller than the width of the target region. The width of the p-GaN layer is smaller than the width of the gradient Al composition AlGaN etch stop layer. The width of the gate is smaller than the width of the p-GaN layer.
3. The p-GaN active passivated GaN HEMT device with an etch stop layer according to claim 1, characterized in that, The thickness of the gradient Al composition AlGaN etch stop layer is between 3 and 5 nm; wherein, the molar fraction of Al decreases sequentially from 25% to 13% or from 28% to 15% along the lower surface to the upper surface of the gradient Al composition AlGaN etch stop layer.
4. The p-GaN active-passivated GaN HEMT device with etch stop layer of claim 1, wherein, The gradient Al composition AlGaN etch stop layer is p-type AlGaN.
5. The p-GaN active-passivated GaN HEMT device with etch stop layer of claim 1, wherein, The thickness of the p-GaN active passivation layer is between 3 and 9 nm, the thickness of the p-GaN layer is between 50 and 80 nm, and the thickness of the GaN buffer layer is between 1 and 4 μm.
6. The p-GaN active-passivated GaN HEMT device with etch stop layer of claim 1, wherein, The gradient Al composition AlGaN etch stop layer is divided into two regions, left and right. The thickness of the left region is greater than that of the right region. The p-GaN layer is disposed on the left region, and its bottom surface completely occupies the left region.
7. The p-GaN active-passivated GaN HEMT device with etch stop layer of claim 1, wherein, The substrate material is any one of sapphire, Si, and SiC.
8. The p-GaN active passivated GaN HEMT device with an etch stop layer according to claim 1, characterized in that, The AlGaN barrier layer has a thickness between 13 and 20 nm and an Al molar composition of 18%.
9. The p-GaN active passivated GaN HEMT device with an etch stop layer according to claim 1, characterized in that, The thickness of the SiN passivation layer is 100 nm.
10. A method of fabricating a p-GaN active-passivated GaN HEMT device with an etch stop layer, the method comprising: include: GaN buffer layer, GaN channel layer, AlGaN barrier layer, p-GaN active passivation layer, graded Al composition AlGaN etch stop layer and p-GaN layer are grown sequentially upward on the substrate. The p-GaN layer, the gradient Al composition AlGaN etch stop layer, and the p-GaN active passivation layer are etched to make the widths of the gradient Al composition AlGaN etch stop layer and the p-GaN active passivation layer equal, and the width of the p-GaN layer is smaller than the width of the gradient Al composition AlGaN etch stop layer, thus forming a first current sample. A source and a drain are grown upwards at both ends of the AlGaN barrier layer of the first current sample to form a second current sample; A gate metal layer is deposited upward in a portion of the p-GaN layer of the second current sample to form a gate; A SiN passivation layer of predetermined thickness is deposited along the inner wall of the drain to the inner wall of the source, wherein the SiN passivation layer does not cover the gate.