A ramp signal generating circuit and a dc-dc converter

Abstract

The application provides a ramp signal generation circuit and a DC-DC converter. A first input processing module performs delay processing and phase inversion processing on a high-side drive signal to output a pulse signal. A second input processing module performs phase inversion processing on the high-side drive signal to output an inverted signal. A voltage signal enhancement module performs drive capability enhancement processing on a ramp signal output by a ramp amplitude determination module to output a target voltage signal when the pulse signal is at a high level. The ramp amplitude determination module outputs a ramp signal with a voltage change amplitude within a preset amplitude interval when the high-side drive signal and the inverted signal are in a time period of the high-side drive signal. A maximum value of the preset amplitude interval is a target voltage value of the target voltage signal, and a minimum value of the preset amplitude interval is determined according to the target voltage value. The ramp signal generation circuit can generate a ramp signal with a constant amplitude, and ensures that the performance of the DC-DC converter is not affected by application conditions.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically, to a ramp signal generation circuit and a DC-DC converter. Background Technology

[0002] DC-to-DC converters can become unstable under certain conditions, such as unstable inductor current or inconsistent inductor current waveforms between adjacent cycles. However, adding a constant on-time (COT) ramp signal generation circuit to the DC-to-DC converter can solve these problems.

[0003] However, the voltage amplitude of the output ramp signal from a traditional ramp signal generation circuit may vary with changes in process, input voltage, and output voltage, causing the entire loop bandwidth to change accordingly. This leads to a decrease in the performance of the DC-DC converter, such as a decrease in dynamic response performance. Consequently, when the load current changes, the output voltage will also change significantly. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a ramp signal generation circuit and a DC-DC converter, which can generate a ramp signal with constant amplitude to ensure that the performance of the DC-DC converter is not affected by application conditions.

[0005] In a first aspect, embodiments of this application provide a ramp signal generation circuit, including:

[0006] The first input processing module is used to perform delay processing and phase inversion processing on the input high-side drive signal in order to output a pulse signal;

[0007] The second input processing module is used to perform phase inversion processing on the input high-side drive signal to output an inverted signal;

[0008] A voltage signal enhancement module is connected to the output terminal of the first input processing module and the output terminal of the ramp amplitude determination module, respectively. It is used to enhance the driving capability of the ramp signal output by the ramp amplitude determination module under the condition that the pulse signal is high level, so as to output a target voltage signal. The waveform of the target voltage signal remains unchanged within the time period corresponding to the high-end driving signal, and the target voltage value of the target voltage signal is the maximum voltage value of the ramp signal.

[0009] The ramp amplitude determination module is connected to the output terminal of the second input processing module and the output terminal of the voltage signal enhancement module, respectively. It is used to output a ramp signal with a voltage change amplitude within a preset amplitude range when the high-side drive signal and the inverting signal are within the time period corresponding to the high-side drive signal. The maximum value of the preset amplitude range is the target voltage value of the target voltage signal, and the minimum value of the preset amplitude range is determined based on the target voltage value.

[0010] In one optional embodiment of this application, the first input processing module includes a delay processing module and a pulse generation module, wherein the output terminal of the delay processing module is connected to the input terminal of the pulse generation module, and the output terminal of the pulse generation module is connected to the input terminal of the voltage signal enhancement module;

[0011] The delay processing module is used to receive the input high-end drive signal, perform delay processing on the high-end drive signal to obtain a delayed drive signal, and output the delayed drive signal to the pulse generation module.

[0012] The pulse generation module is used to process the delayed drive signal to obtain a pulse signal and output the pulse signal to the voltage signal enhancement module.

[0013] In one optional embodiment of this application, the pulse generation module includes a delay unit, a first inverter, and an AND gate unit. The output terminal of the delay unit is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the AND gate unit, the input terminal of the delay unit is connected to the second input terminal of the AND gate unit, and the output terminal of the AND gate unit is connected to the input terminal of the voltage signal enhancement module. The input terminal of the delay unit is used to receive the delayed drive signal.

[0014] In one optional embodiment of this application, the delay processing module includes a plurality of second inverters, wherein the number of the plurality of second inverters is an even number;

[0015] And / or, the delay unit includes a plurality of third inverters, wherein the number of the plurality of third inverters is an even number.

[0016] In one optional embodiment of this application, the second input processing module includes a fourth inverter, the input of which is used to receive the high-side drive signal and perform phase inversion processing on the high-side drive signal to output an inverted drive signal to the ramp amplitude determination module.

[0017] In one optional embodiment of this application, the voltage signal enhancement module includes a first buffer, a second buffer, a first switching unit, and a fourth capacitor unit. The output terminal of the first buffer is connected to the input terminal of the first switching unit. The output terminal of the first switching unit is connected to the input terminal of the second buffer and the upper plate of the fourth capacitor unit, respectively. The control terminal of the first switching unit is connected to the output terminal of the first input processing module for receiving the pulse signal.

[0018] The lower plate of the fourth capacitor unit is connected to the first input terminal of the ramp amplitude determination module, the input terminal of the first buffer is connected to the output terminal of the ramp amplitude determination module to receive the feedback ramp signal, and the output terminal of the second buffer is connected to the second input terminal of the ramp amplitude determination module to output the target voltage signal obtained after the drive capability enhancement processing to the ramp amplitude determination module.

[0019] In one optional embodiment of this application, the first buffer includes a first current source, a second current source, a first field-effect transistor, and a second field-effect transistor;

[0020] The output terminal of the first current source is connected to the source of the first field-effect transistor and the source of the second field-effect transistor respectively. The drain of the first field-effect transistor is grounded, and the drain of the second field-effect transistor is grounded through the second current source. The gate of the first field-effect transistor is connected to the output terminal of the ramp amplitude determination module as an input terminal, and the gate of the second field-effect transistor is connected to the input terminal of the first switching unit as an output terminal.

[0021] And / or, the second buffer includes a third current source, a fourth current source, a third field-effect transistor, and a fourth field-effect transistor;

[0022] The output terminal of the third current source is connected to the source of the third field-effect transistor and the source of the fourth field-effect transistor, respectively. The drain of the third field-effect transistor is grounded, and the drain of the fourth field-effect transistor is grounded through the fourth current source. The gate of the third field-effect transistor is connected to the output terminal of the first switching unit as an input terminal, and the gate of the fourth field-effect transistor is connected to the second input terminal of the ramp amplitude determination module as an output terminal.

[0023] In one optional embodiment of this application, the ramp amplitude determination module includes a voltage regulation unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a first capacitor unit, a second capacitor unit, a third capacitor unit, a first resistor unit, and a second resistor unit.

[0024] The control terminals of the fourth and sixth switching units are both connected to the input terminal of the second input processing module to receive the high-side drive signal. The control terminals of the second, third, and fifth switching units are all connected to the output terminal of the second input processing module to receive the inverted signal.

[0025] The output terminal of the voltage regulating unit is connected to the input terminal of the fourth switching unit. The output terminal of the fourth switching unit is connected to the upper plate of the first capacitor unit and the input terminal of the second switching unit. The output terminal of the second switching unit is grounded. The lower plate of the first capacitor unit is connected to the output terminal of the third switching unit and the input terminal of the sixth switching unit. The input terminal of the third switching unit is connected to the output terminal of the second buffer in the voltage signal enhancement module. The output terminal of the sixth switching unit is grounded through the second capacitor unit. The input terminal of the fifth switching unit is connected to the first terminal of the first resistor unit. The output terminal of the fifth switching unit is connected to the upper plate of the second capacitor unit and the first terminal of the second resistor unit. The second terminal of the second resistor unit is connected to the second terminal of the first resistor unit through the third capacitor unit. The second terminal of the first resistor unit is also connected to the lower plate of the fourth capacitor unit in the voltage signal enhancement module.

[0026] In one optional embodiment of this application, the slope amplitude determination module determines the minimum value of the preset amplitude range through the following steps:

[0027] Obtain the first voltage value corresponding to the first voltage signal output by the voltage regulation unit, the first capacitance value of the first capacitor unit, the second capacitance value of the second capacitor unit, and the target voltage value corresponding to the target voltage signal;

[0028] Using the principle of charge conservation, the minimum value of the preset amplitude range is calculated based on the first voltage value, the first capacitance value, the second capacitance value, and the target voltage value.

[0029] Secondly, embodiments of this application also provide a DC-DC converter, including a pulse width modulation circuit, a seventh switching unit, an eighth switching unit, a filter circuit, and a ramp signal generation circuit as described above;

[0030] The ramp signal output terminal of the ramp signal generation circuit is connected to the first signal input terminal of the pulse width modulation circuit. The average signal output terminal of the ramp signal generation circuit is connected to the second signal input terminal of the pulse width modulation circuit. The first output terminal of the pulse width modulation circuit is connected to the control terminal of the ramp signal generation circuit and the control terminal of the seventh switching unit. The second output terminal of the pulse width modulation circuit is connected to the control terminal of the eighth switching unit. The first terminal of the seventh switching unit is connected to the input terminal of the ramp signal generation circuit. The second terminal of the seventh switching unit is connected to the first terminal of the eighth switching unit. The second terminal of the eighth switching unit is grounded. The filter circuit is connected in parallel across the eight switches. The output terminal of the filter circuit is connected to the control terminal of the pulse width modulation circuit.

[0031] The embodiments of this application have at least the following beneficial effects:

[0032] The ramp signal generation circuit provided in this application embodiment can enhance the driving capability of the feedback ramp signal when the pulse signal is at a high level. It outputs a target voltage signal whose waveform remains constant within the time period corresponding to the high-side drive signal, and whose target voltage value is the maximum voltage value of the ramp signal. This target voltage signal is then sent to the ramp amplitude determination module. This ensures that, under the condition that the high-side drive signal and the inverting signal are within the time period corresponding to the high-side drive signal, the ramp amplitude determination module outputs a ramp signal with a voltage change amplitude within a preset amplitude range. The maximum value of the preset amplitude range is the target voltage value of the target voltage signal, and the minimum value of the preset amplitude range is determined based on the target voltage value. The ramp signal generation circuit provided in this application embodiment can generate a ramp signal with constant amplitude, thereby ensuring that the performance of the DC-DC converter is not affected by application conditions. In other words, the dynamic response performance of the DC-DC converter remains consistent after changes in application conditions such as input voltage and output voltage.

[0033] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a ramp signal generation circuit provided in an embodiment of this application;

[0036] Figure 2 This is a waveform diagram of a ramp signal generation circuit provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of another ramp signal generation circuit provided in an embodiment of this application;

[0038] Figure 4 This is a schematic diagram of the pulse generation module in a ramp signal generation circuit provided in an embodiment of this application;

[0039] Figure 5 This is a waveform diagram of a signal generated in a pulse generation module provided in an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of the structure of the first buffer in a ramp signal generation circuit provided in an embodiment of this application.

[0041] Figure 7 This is a schematic diagram of a DC-DC converter provided in an embodiment of this application.

[0042] Figure descriptions: 10-Ramp signal generation circuit; 11-First input processing module; 12-Second input processing module; 13-Voltage signal enhancement module; 14-Ramp amplitude determination module; 20-Pulse width modulation circuit; 30-Seventh switching unit; 40-Eighth switching unit; 50-Filtering circuit. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0044] The terms “a,” “an,” “the,” and “the” are used in this specification to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markings and are not a limitation on the number of objects.

[0045] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0046] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0047] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0048] A DC-to-DC converter is an electrical energy conversion circuit that can convert DC power into DC power of different voltages. Its power range can be from very small (small battery) to very large (high voltage power conversion), and it has been widely used in various fields.

[0049] DC-DC converters may exhibit instability under certain testing conditions, such as unstable inductor current or inconsistent inductor current waveforms between adjacent cycles. However, adding a constant on-time (COT) ramp signal generation circuit to the DC-DC converter can solve these problems.

[0050] However, the voltage amplitude of the output ramp signal from a traditional ramp signal generation circuit may vary with changes in process, input voltage, and output voltage, causing the entire loop bandwidth to change accordingly. This leads to a decrease in the performance of the DC-DC converter, such as a decrease in dynamic response performance. Consequently, when the load current changes, the output voltage will also change significantly.

[0051] Based on this, this application provides a ramp signal generation circuit that can generate a ramp signal with constant amplitude, thereby ensuring that the performance of the DC-DC converter is not affected by application conditions.

[0052] Please see Figure 1 , Figure 1 This is a schematic diagram of a ramp signal generation circuit provided in an embodiment of this application. Figure 1 As shown in the figure, the ramp signal generation circuit 10 provided in this application embodiment includes a first input processing module 11, a second input processing module 12, a voltage signal enhancement module 13, and a ramp amplitude determination module 14. The voltage signal enhancement module 13 is connected to the output terminal of the first input processing module 11 and the output terminal of the ramp amplitude determination module 14, respectively. The ramp amplitude determination module 14 is connected to the output terminal of the second input processing module 12 and the output terminal of the voltage signal enhancement module 13, respectively. The input terminal of the ramp amplitude determination module 14 is connected to the voltage input terminal to receive the voltage input signal VIN. The control terminals of the first input processing module 11, the second input processing module 12, and the ramp amplitude determination module 14 are all connected to the high-side drive signal terminal to receive the high-side drive signal DH.

[0053] In other words, the first input processing module 11 performs delay and phase inversion processing on the high-side drive signal DH to output a pulse signal JS, the second input processing module 12 performs phase inversion processing on the high-side drive signal DH to output an inverted signal DHB, and the voltage signal enhancement module 13 enhances the driving capability of the ramp signal VP output by the ramp amplitude determination module 14 when the pulse signal JS is at a high level to output a target voltage signal J2. The waveform of the target voltage signal J2 remains unchanged within the time period corresponding to the high-side drive signal DH, and the target voltage value of the target voltage signal J2 is the maximum voltage value VP of the ramp signal VP. max The ramp amplitude determination module 14 outputs a ramp signal VP whose voltage change amplitude is within a preset amplitude range when the high-side drive signal DH and the inverting signal DHB are within the time period of the high-side drive signal DH; wherein the maximum value of the preset amplitude range is the target voltage value VP of the target voltage signal J2. max The minimum value of the preset amplitude range is determined based on the target voltage value. Specifically, each waveform is as follows: Figure 2As shown, VN is the average voltage signal obtained after the ramp signal VP is processed by the filter, and VP min It can be based on the law of conservation of charge and the target voltage value VP max Confirmed.

[0054] In this way, the ramp signal generation circuit can generate a ramp signal with constant amplitude, thereby ensuring that the performance of the DC-DC converter is not affected by application conditions.

[0055] This embodiment divides the ramp signal generation circuit into four modules: a first input processing module 11, a second input processing module 12, a voltage signal enhancement module 13, and a ramp amplitude determination module 14. Through close cooperation between these modules, the voltage amplitude of the ramp signal is controlled to periodically change within a preset amplitude range, thereby generating a ramp signal with constant amplitude. The functional modules of the ramp signal generation circuit are described in detail below:

[0056] The first input processing module 11 is used to perform delay processing and phase inversion processing on the input high-side drive signal to output a pulse signal.

[0057] Among them, the high-side drive signal DH is output by the pulse width modulation (PWM) circuit. In addition to monitoring the output status of the power circuit, the PWM circuit also provides control signals for the power components. Therefore, it is widely used in various high-power circuits such as DC-DC converters. In addition, the pulse width modulation circuit can also output the low-side drive signal DL. In this way, the high-side drive signal DH and the low-side drive signal DL can be synchronously turned on and off the high-side switch and low-side switch driven by the external driver.

[0058] Specifically, the purpose of delay processing is to create a certain time delay in the high-side drive signal. For example, delay processing is usually implemented through a delay circuit. Common types of delay circuits include delay circuits composed of multiple inverters, RC delay circuits, 555 delay circuits, and delay relays. This application does not specifically limit the type of delay circuit. Any delay circuit that can implement the delay processing involved in this application is within the protection scope of this application.

[0059] The purpose of phase inversion processing is to reverse the phase of the delayed high-side drive signal by 180 degrees. Phase describes the periodicity and time delay of the high-side drive signal. For example, phase inversion processing can be implemented using an inverter.

[0060] Then, a high-side drive signal is input to the first input processing module. After delaying and reversing the phase of the high-side drive signal, a pulse signal is output to the voltage signal enhancement module. The pulse signal controls the voltage signal enhancement module to enhance the driving capability of the feedback ramp signal.

[0061] In one alternative embodiment, such as Figure 3 As shown, the first input processing module 11 includes a delay processing module Delay and a pulse generation module Pulse. The input terminal of the delay processing module Delay receives the high-side drive signal DH. Optionally, the input terminal of the delay processing module Delay can be connected to the first output terminal of the pulse width modulation circuit to receive the high-side drive signal DH output by the first output terminal of the pulse width modulation circuit. The output terminal of the delay processing module Delay is connected to the input terminal of the pulse generation module Pulse, and the output terminal of the pulse generation module Pulse is connected to the input terminal of the voltage signal enhancement module 13. Specifically, the output terminal of the pulse generation module Pulse is connected to the control terminal of the first switching unit S1 in the voltage signal enhancement module 13. Here, the delay processing module Delay performs delay processing to obtain the delayed drive signal J1, and the pulse generation module Pulse processes the delayed drive signal J1 to obtain the pulse signal JS.

[0062] Specifically, the delay processing module Delay is used to receive the input high-side drive signal DH, perform delay processing on the high-side drive signal DH to obtain the delayed drive signal J1, and output the delayed drive signal J1 to the pulse generation module Pulse.

[0063] For example, the delay processing module Delay provided in this application embodiment may include a plurality of second inverters, wherein the number of the plurality of second inverters is even. The desired delay time can be generated by an even number of second inverters.

[0064] Specifically, the delayed drive signal J1 generates a pulse signal JS at the rising edge of the pulse generation module Pulse, and outputs the pulse signal JS to the voltage signal enhancement module.

[0065] For example, the pulse generation module Pulse provided in the embodiments of this application can be as follows: Figure 4As shown, the pulse generation module includes a delay unit delay1, a first inverter inv1, and an AND gate unit and1. The output of the delay unit delay1 is connected to the input of the first inverter inv1. The output of the first inverter inv1 is connected to the first input of the AND gate unit and1. The input of the delay unit delay1 is connected to the second input of the AND gate unit and1. The output of the AND gate unit and1 is connected to the input of the voltage signal enhancement module 13. Specifically, the output of the AND gate unit and1 is connected to the control terminal of the first switching unit S1 in the voltage signal enhancement module 13. The input of the delay unit delay1 is used to receive the delayed drive signal J1.

[0066] Specifically, the high-side drive signal DH is delayed by the delay processing module Delay to obtain the delayed drive signal J1. The delayed drive signal J1 is then delayed by the delay unit delay1 in the pulse generation module Pulse to obtain the first delayed drive signal JA. The first delayed drive signal JA is then phase-inverted by the first inverter inv1 to obtain the second delayed drive signal JB. The second delayed drive signal JB and the delayed drive signal J1 are then ANDed by the AND gate unit and JS to obtain the pulse signal JS, with the waveform shown below. Figure 5 As shown.

[0067] The delay unit delay1 includes multiple third inverters, and the number of third inverters is always even. The more third inverters there are, the longer the delay time will be; the appropriate number can be selected based on the actual design.

[0068] Specifically, the second input processing module 12 is used to perform phase inversion processing on the input high-side drive signal to output an inverted signal.

[0069] In one alternative embodiment, such as Figure 3 As shown, the second input processing module 12 includes a fourth inverter inv4. The input terminal of the fourth inverter inv4 is used to receive the high-side drive signal DH and perform phase inversion processing on the high-side drive signal DH to output the inverted drive signal DHB to the ramp amplitude determination module 14. Specifically, the inverted drive signal DHB is output to the control terminal of the second switching unit S2 in the ramp amplitude determination module 14.

[0070] Specifically, the voltage signal enhancement module 13 is connected to the output terminal of the first input processing module 11 and the output terminal of the ramp amplitude determination module 14, respectively. It is used to enhance the driving capability of the ramp signal VP output by the ramp amplitude determination module 14 when the pulse signal JS is at a high level, so as to output a target voltage signal J2. The waveform of the target voltage signal J2 remains unchanged within the time period corresponding to the high-side drive signal DH, and the target voltage value of the target voltage signal J2 is the maximum voltage value VP of the ramp signal VP. max .

[0071] In one alternative embodiment, such as Figure 3 As shown, the voltage signal enhancement module 13 includes a first buffer Buf1, a second buffer Buf2, a first switching unit S1, and a fourth capacitor unit C4. The output terminal of the first buffer Buf1 is connected to the input terminal of the first switching unit S1. The output terminal of the first switching unit S1 is connected to the input terminal of the second buffer Buf2 and the upper plate of the fourth capacitor unit C4. The control terminal of the first switching unit S1 is connected to the output terminal of the first input processing module 11 to receive the pulse signal JS. Specifically, the control terminal of the first switching unit S1 is connected to the output terminal of the pulse generation module Pulse in the first input processing module 11. The lower plate of the fourth capacitor unit C4 is connected to the first input terminal of the ramp amplitude determination module 14. The input terminal of the first buffer Buf1 is connected to the output terminal of the ramp amplitude determination module 14 to receive the feedback ramp signal VP. The output terminal of the second buffer Buf2 is connected to the second input terminal of the ramp amplitude determination module 14 to output the target voltage signal J2 obtained after the drive capability enhancement processing to the ramp amplitude determination module 14.

[0072] Here, the ramp signal VP maintains a consistent waveform after passing through the first buffer Buf1, enhancing the signal driving capability and preventing the sampling action from affecting the ramp signal VP. When the pulse signal JS is high, the first switching unit S1 is turned on, setting the maximum voltage value VP of the ramp signal VP to... max The signal is sampled onto the fourth capacitor cell C4, and the second buffer Buf2 maintains the waveform unchanged, enhancing the signal driving capability. That is, the target voltage signal J2 is always equal to the maximum voltage value VP of the ramp signal VP. max .

[0073] Furthermore, the waveform of the target voltage signal J2 remains unchanged within the time period corresponding to the high-side drive signal DH, and the target voltage value of the target voltage signal remains unchanged, always being the maximum voltage value VP of the ramp signal VP. max The time period corresponding to the high-end drive signal DH refers to the time interval between two identical high-end drive signals DH. Within each time period, the high-end drive signal DH has a drive signal in a high-level state and a drive signal in a low-level state.

[0074] For example, such as Figure 6 As shown, the first buffer Buf1 includes a first current source I1, a second current source I2, a first field-effect transistor MP1, and a second field-effect transistor MP2. The output terminal of the first current source I1 is connected to the source of the first field-effect transistor MP1 and the source of the second field-effect transistor MP2, respectively. The drain of the first field-effect transistor MP1 is grounded, and the drain of the second field-effect transistor MP2 is grounded through the second current source I2. The gate of the first field-effect transistor MP1 is connected to the output terminal of the ramp amplitude determination module 14 as an input terminal, and the gate of the second field-effect transistor MP2 is connected to the input terminal of the first switching unit S1 as an output terminal.

[0075] In this context, the voltage value of node B is raised by |Vthp| compared to the voltage of input node A, where Vthp is the threshold voltage of the first field-effect transistor MP1. The output voltage Out of the output node is reduced by |Vthp| compared to the voltage of node B. Therefore, the output voltage Out remains basically the same as the voltage value of node A.

[0076] In a preferred embodiment, the first field-effect transistor MP1 and the second field-effect transistor MP2 are of the same type and have the same size. The layout design principle of the first field-effect transistor MP1 and the second field-effect transistor MP2 is a matched P-channel MOS transistor. The first current source I1 and the second current source I2 are current sources that generate the same current value, that is, the first current source I1 and the second current source I2 are designed to have the same current value.

[0077] Furthermore, the second buffer Buf2 can adopt the same circuit structure as the first buffer Buf1. Specifically, the second buffer Buf2 may include a third current source, a fourth current source, a third field-effect transistor (FET), and a fourth FET. The output terminal of the third current source is connected to the source of the third FET and the source of the fourth FET, respectively. The drain of the third FET is grounded, and the drain of the fourth FET is grounded through the fourth current source. The gate of the third FET serves as the input terminal and is connected to the output terminal of the first switching unit. The gate of the fourth FET serves as the output terminal and is connected to the second input terminal of the ramp amplitude determination module. For the specific circuit structure, please refer to [link to relevant documentation]. Figure 6 Among them, the third and fourth current sources are current sources that produce the same current value, and the third and fourth field-effect transistors are P-channel MOS transistors designed according to the matching principle.

[0078] Specifically, the ramp amplitude determination module 14 is connected to the output terminal of the second input processing module 12 and the output terminal of the voltage signal enhancement module 13, respectively. It is used to output a ramp signal VP with a voltage change amplitude within a preset amplitude range when the high-side drive signal DH and the inverted signal DHB are in the time period corresponding to the high-side drive signal DH. The maximum value of the preset amplitude range is the target voltage value of the target voltage signal J2, and the minimum value of the preset amplitude range is determined according to the target voltage value.

[0079] In one alternative embodiment, such as Figure 3 As shown, the ramp amplitude determination module includes a voltage regulation unit VR, a second switch unit S2, a third switch unit S3, a fourth switch unit S4, a fifth switch unit S5, a sixth switch unit S6, a first capacitor unit C1, a second capacitor unit C2, a third capacitor unit C3, a first resistor unit R1, and a second resistor unit R2.

[0080] The control terminals of the fourth switch unit C4 and the sixth switch unit S6 are both connected to the input terminal of the second input processing module 12 to receive the high-side drive signal DH. The control terminals of the second switch unit S2, the third switch unit S3 and the fifth switch unit S5 are all connected to the output terminal of the second input processing module 12 to receive the inverted signal DHB.

[0081] The output terminal of the voltage regulating unit VR is connected to the input terminal of the fourth switching unit S4. The output terminal of the fourth switching unit S4 is connected to the upper plate of the first capacitor unit C1 and the input terminal of the second switching unit S2. The output terminal of the second switching unit S2 is grounded. The lower plate of the first capacitor unit C1 is connected to the output terminal of the third switching unit S3 and the input terminal of the sixth switching unit S6. The input terminal of the third switching unit S3 is connected to the output terminal of the second buffer Buf2 in the voltage signal enhancement module 13. The output terminal of the sixth switching unit S6 is grounded through the second capacitor unit C2. The input terminal of the fifth switching unit S5 is connected to the first terminal of the first resistor unit R1. The output terminal of the fifth switching unit S5 is connected to the upper plate of the second capacitor unit C2 and the first terminal of the second resistor unit R2. The second terminal of the second resistor unit R2 is connected to the second terminal of the first resistor unit R1 through the third capacitor unit C3. The second terminal of the first resistor unit R1 is also connected to the lower plate of the fourth capacitor unit C4 in the voltage signal enhancement module 13.

[0082] based on Figure 3 The ramp signal generation circuit shown has a high-level state that has the same time period as the high-side drive signal DH, only the falling edge is different. Therefore, the working principle of the ramp amplitude determination module is as follows:

[0083] S1. When the high-side drive signal DH is low and the inverting signal DHB is high, the second switch unit S2 and the third switch unit S3 are turned on. The upper plate of the first capacitor unit C1 is grounded, and the lower plate is connected to the second buffer Buf2 in the voltage signal enhancement module 13 to receive the target voltage signal J2. This causes the voltage across the first capacitor unit C1 to be charged to a value equal to the voltage value VP of the target voltage signal J2. max .

[0084] S2. When the high-side drive signal DH goes high and the inverting signal DHB goes low, the fourth switch unit S4 and the sixth switch unit S6 are turned on, causing the first capacitor unit C1 and the second capacitor unit C2 to share charge. At this time, the upper plate of the first capacitor unit C1 is connected to the output terminal of the voltage regulating unit VR, and can be charged according to the first voltage signal VRO output by the voltage regulating unit VR. The voltage regulating unit VR generates an internally stable first voltage signal VRO, for example, the first voltage value of the first voltage signal VRO is 3.3V. In addition, the lower plate of the first capacitor unit C1 is connected to the upper plate of the second capacitor unit C2.

[0085] S3. When the high-end drive signal DH is low and the inverting signal DHB is high, the fifth switch unit S5 is turned on, and the second capacitor unit C2 discharges to ground through the first resistor unit R1.

[0086] S4. When the rising edge of the high-side drive signal DH arrives, the voltage of the second capacitor cell C2 (i.e., the voltage value of the ramp signal VP) is discharged to the minimum voltage value VP. min Among them, the minimum voltage VP min Based on the principle of charge conservation and the target voltage value VP of the target voltage signal, it can be determined that... max Sure.

[0087] Here, in order for the ramp signal generation circuit to stably output a ramp signal with a constant amplitude, it is necessary to ensure that the capacitance ratio between the first capacitor unit C1 and the second capacitor unit C2 in the ramp amplitude determination module 14 is less than 1.

[0088] Among them, the ramp amplitude determination module calculates the minimum value of the preset amplitude range based on the principle of charge conservation: it obtains the first voltage value VR corresponding to the first voltage signal VRO output by the voltage regulation unit VR. O The first capacitance value C1 of the first capacitor unit C1, the second capacitance value C2 of the second capacitor unit C2, and the target voltage value VP corresponding to the target voltage signal J2. max Using the principle of charge conservation, based on the first voltage value VR O First capacitor value C1, second capacitor value C2, target voltage value VP max Calculate the minimum value within the preset amplitude range.

[0089] For example, based on the principle of charge conservation during capacitor charge sharing, we can obtain:

[0090] VP max ×C1+VP min ×C2=VP max ×C2+(VP max -VR O )×C1;

[0091] Among them, VP max VP is the maximum voltage value of the ramp signal VP. min VR represents the minimum voltage value of the ramp signal VP, C1 represents the capacitance value of the first capacitor unit C1, C2 represents the capacitance value of the second capacitor unit C2, and VR represents the capacitance value of the second capacitor unit C2. O The first voltage value of the first voltage signal VRO output by the voltage regulator VR.

[0092] Simplifying the above formulas, we get: (VP) max -VP min )×C2=VR O ×C1;

[0093] Furthermore, we can obtain: VP max -VP min =VR O ×C1 / C2;

[0094] The voltage value of the first voltage signal VRO can be designed as an accurate voltage value based on a bandgap reference. The layout design principle for the first capacitor cell C1 and the second capacitor cell C2 is a matched design. In a preferred embodiment, the first capacitor cell C1 and the second capacitor cell C2 in the layout design are designed with their geometric centers coinciding. In this way, the ratio of C1 / C2 can be designed to be very accurate. Preferably, the value of C1 / C2 is less than 1.

[0095] The embodiments of this application, through the above-described settings, can ensure that the ramp signal generation circuit stably generates a ramp signal with a constant amplitude for use by the DC-DC converter. Here, the voltage change amplitude varies within a preset amplitude range. The endpoint values ​​of the preset amplitude range can be determined by the feedback ramp signal and the principle of charge conservation, ensuring that the circuit can stably output a ramp signal with a voltage change amplitude within the preset amplitude range.

[0096] Secondly, embodiments of this application provide a DC-DC converter, such as... Figure 7 As shown, it includes a pulse width modulation circuit 20, a seventh switching unit 30, an eighth switching unit 40, a filter circuit 50, and as shown in the figure. Figure 1 or Figure 3 The ramp signal generation circuit 10 is described above;

[0097] The ramp signal output terminal of the ramp signal generation circuit 10 is connected to the first signal input terminal of the pulse width modulation circuit 20. The average signal output terminal of the ramp signal generation circuit 10 is connected to the second signal input terminal of the pulse width modulation circuit 20. The first output terminal of the pulse width modulation circuit 20 is connected to the control terminal of the ramp signal generation circuit 10 and the control terminal of the seventh switching unit 30, respectively. The second output terminal of the pulse width modulation circuit 20 is connected to the control terminal of the eighth switching unit 40. The first terminal of the seventh switching unit 30 is connected to the input terminal of the ramp signal generation circuit 10. The second terminal of the seventh switching unit 30 is connected to the first terminal of the eighth switching unit 40. The second terminal of the eighth switching unit 40 is grounded. The filter circuit 50 is connected in parallel across the eight switches. The output terminal of the filter circuit 50 is connected to the control terminal of the pulse width modulation circuit 20.

[0098] Specifically, the filter circuit 50 includes an inductor L1 and a capacitor C0. The input terminal of the inductor L1 is connected to the second terminal of the seventh switching unit 30, the output terminal of the inductor L1 is connected to the input terminal of the capacitor C0, and the output terminal of the capacitor C0 is connected to the second terminal of the eighth switching unit 40.

[0099] exist Figure 6 In the circuit, the ramp signal generation circuit 10 receives the voltage input signal VIN, and then outputs a ramp signal VP and an average voltage signal VN to the pulse width modulation circuit 20. The ramp signal VP is a voltage signal with a constant amplitude, and the average voltage signal VN is the average signal of the ramp signal VP after passing through the filter circuit 50. The pulse width modulation circuit 20 generates a high-side drive signal DH for the seventh switching unit 30 and a low-side drive signal DL for the eighth switching unit 40 based on the voltage output signal VO. For example, the seventh switching unit 30 is a high-side switch K1, and the eighth switching unit 40 is a low-side switch K2. The filter circuit 50 filters the voltage signal SW generated by the pulse width modulation circuit 20 to obtain a DC voltage output signal VO, which can be used to supply power externally.

[0100] Here, the function of this DC-DC converter is to step down the voltage input signal VIN to a lower voltage output signal VO, so as to power other circuits. When the voltage output signal VO is too low or too high, the pulse width modulation circuit 20 can adjust the duty cycle of the high-side drive signal DH and the low-side drive signal DL to adjust the magnitude of the voltage output signal VO.

[0101] Specifically, when the voltage output signal VO is low (e.g., lower than the internal reference voltage signal, built into the pulse width modulation circuit 20), the pulse width modulation circuit 20 can increase the duty cycle of the high-side drive signal DH and decrease the duty cycle of the low-side drive signal DL, thereby increasing the duty cycle of the voltage signal SW. The voltage value of the output signal VO after filtering by the filter circuit 50 will then increase. Conversely, when the voltage output signal VO is high (e.g., higher than the internal reference voltage signal, built into the pulse width modulation circuit 20), the pulse width modulation circuit 20 can decrease the duty cycle of the high-side drive signal DH and increase the duty cycle of the low-side drive signal DL, thereby decreasing the duty cycle of the voltage signal SW. The voltage value of the output signal VO after filtering by the filter circuit 50 will then decrease. This negative feedback loop is relatively stable, thus generating a stable voltage output signal VO.

[0102] The ramp signal generation circuit provided in this application embodiment can generate a ramp signal with constant amplitude. Applying the above ramp signal generation circuit in a DC-DC converter can improve the dynamic response characteristics of the DC-DC converter. That is, when the load current suddenly changes from a light load current to a heavy load current, the output voltage jump amplitude is smaller, thereby ensuring that the performance of the DC-DC converter is not affected by the application conditions. In other words, the dynamic response performance of the DC-DC converter remains consistent after the application conditions such as input voltage and output voltage change with the application conditions before the change.

[0103] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ramp signal generation circuit, characterized in that, include: The first input processing module is used to perform delay processing and phase inversion processing on the input high-side drive signal in order to output a pulse signal; The second input processing module is used to perform phase inversion processing on the input high-side drive signal to output an inverted signal; A voltage signal enhancement module is connected to the output terminal of the first input processing module and the output terminal of the ramp amplitude determination module, respectively. It is used to enhance the driving capability of the ramp signal output by the ramp amplitude determination module under the condition that the pulse signal is high level, so as to output a target voltage signal. The waveform of the target voltage signal remains unchanged within the time period corresponding to the high-end driving signal, and the target voltage value of the target voltage signal is the maximum voltage value of the ramp signal. The ramp amplitude determination module is connected to the output terminal of the second input processing module and the output terminal of the voltage signal enhancement module, respectively. It is used to output a ramp signal with a voltage change amplitude within a preset amplitude range when the high-side drive signal and the inverting signal are in the time period corresponding to the high-side drive signal. The maximum value of the preset amplitude range is the target voltage value of the target voltage signal, and the minimum value of the preset amplitude range is determined based on the target voltage value.

2. The ramp signal generation circuit according to claim 1, characterized in that, The first input processing module includes a delay processing module and a pulse generation module. The input terminal of the delay processing module receives a high-side drive signal, the output terminal of the delay processing module is connected to the input terminal of the pulse generation module, and the output terminal of the pulse generation module is connected to the input terminal of the voltage signal enhancement module. The delay processing module is used to receive the input high-end drive signal, perform delay processing on the high-end drive signal to obtain a delayed drive signal, and output the delayed drive signal to the pulse generation module. The pulse generation module is used to process the delayed drive signal to obtain a pulse signal and output the pulse signal to the voltage signal enhancement module.

3. The ramp signal generation circuit according to claim 2, characterized in that, The pulse generation module includes a delay unit, a first inverter, and an AND gate unit. The output terminal of the delay unit is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the AND gate unit, the input terminal of the delay unit is connected to the second input terminal of the AND gate unit, and the output terminal of the AND gate unit is connected to the input terminal of the voltage signal enhancement module. The input terminal of the delay unit is used to receive the delayed drive signal.

4. The ramp signal generation circuit according to claim 3, characterized in that, The delay processing module includes a plurality of second inverters, and the number of the plurality of second inverters is an even number. And / or, the delay unit includes a plurality of third inverters, wherein the number of the plurality of third inverters is an even number.

5. The ramp signal generation circuit according to claim 1, characterized in that, The second input processing module includes a fourth inverter, the input of which is used to receive the high-side drive signal and perform phase inversion processing on the high-side drive signal to output an inverted drive signal to the ramp amplitude determination module.

6. The ramp signal generation circuit according to claim 1, characterized in that, The voltage signal enhancement module includes a first buffer, a second buffer, a first switching unit, and a fourth capacitor unit. The output terminal of the first buffer is connected to the input terminal of the first switching unit. The output terminal of the first switching unit is connected to the input terminal of the second buffer and the upper plate of the fourth capacitor unit. The control terminal of the first switching unit is connected to the output terminal of the first input processing module for receiving the pulse signal. The lower plate of the fourth capacitor unit is connected to the first input terminal of the ramp amplitude determination module, the input terminal of the first buffer is connected to the output terminal of the ramp amplitude determination module to receive the feedback ramp signal, and the output terminal of the second buffer is connected to the second input terminal of the ramp amplitude determination module to output the target voltage signal obtained after the drive capability enhancement processing to the ramp amplitude determination module.

7. The ramp signal generation circuit according to claim 6, characterized in that, The first buffer includes a first current source, a second current source, a first field-effect transistor, and a second field-effect transistor; The output terminal of the first current source is connected to the source of the first field-effect transistor and the source of the second field-effect transistor respectively. The drain of the first field-effect transistor is grounded, and the drain of the second field-effect transistor is grounded through the second current source. The gate of the first field-effect transistor is connected to the output terminal of the ramp amplitude determination module as an input terminal, and the gate of the second field-effect transistor is connected to the input terminal of the first switching unit as an output terminal. And / or, the second buffer includes a third current source, a fourth current source, a third field-effect transistor, and a fourth field-effect transistor; The output terminal of the third current source is connected to the source of the third field-effect transistor and the source of the fourth field-effect transistor, respectively. The drain of the third field-effect transistor is grounded, and the drain of the fourth field-effect transistor is grounded through the fourth current source. The gate of the third field-effect transistor is connected to the output terminal of the first switching unit as an input terminal, and the gate of the fourth field-effect transistor is connected to the second input terminal of the ramp amplitude determination module as an output terminal.

8. The ramp signal generation circuit according to claim 1, characterized in that, The ramp amplitude determination module includes a voltage regulation unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a first capacitor unit, a second capacitor unit, a third capacitor unit, a first resistor unit, and a second resistor unit. The control terminals of the fourth and sixth switching units are both connected to the input terminal of the second input processing module to receive the high-side drive signal. The control terminals of the second, third, and fifth switching units are all connected to the output terminal of the second input processing module to receive the inverted signal. The output terminal of the voltage regulating unit is connected to the input terminal of the fourth switching unit. The output terminal of the fourth switching unit is connected to the upper plate of the first capacitor unit and the input terminal of the second switching unit. The output terminal of the second switching unit is grounded. The lower plate of the first capacitor unit is connected to the output terminal of the third switching unit and the input terminal of the sixth switching unit. The input terminal of the third switching unit is connected to the output terminal of the second buffer in the voltage signal enhancement module. The output terminal of the sixth switching unit is grounded through the second capacitor unit. The input terminal of the fifth switching unit is connected to the first terminal of the first resistor unit. The output terminal of the fifth switching unit is connected to the upper plate of the second capacitor unit and the first terminal of the second resistor unit. The second terminal of the second resistor unit is connected to the second terminal of the first resistor unit through the third capacitor unit. The second terminal of the first resistor unit is also connected to the lower plate of the fourth capacitor unit in the voltage signal enhancement module.

9. The ramp signal generation circuit according to claim 8, characterized in that, The slope amplitude determination module determines the minimum value of the preset amplitude range through the following steps: Obtain the first voltage value corresponding to the first voltage signal output by the voltage regulation unit, the first capacitance value of the first capacitor unit, the second capacitance value of the second capacitor unit, and the target voltage value corresponding to the target voltage signal; Using the principle of charge conservation, the minimum value of the preset amplitude range is calculated based on the first voltage value, the first capacitance value, the second capacitance value, and the target voltage value.

10. A DC-DC converter, characterized in that, It includes a pulse width modulation circuit, a seventh switching unit, an eighth switching unit, a filter circuit, and a ramp signal generation circuit as described in any one of claims 1 to 9; The ramp signal output terminal of the ramp signal generation circuit is connected to the first signal input terminal of the pulse width modulation circuit. The average signal output terminal of the ramp signal generation circuit is connected to the second signal input terminal of the pulse width modulation circuit. The first output terminal of the pulse width modulation circuit is connected to the control terminal of the ramp signal generation circuit and the control terminal of the seventh switching unit. The second output terminal of the pulse width modulation circuit is connected to the control terminal of the eighth switching unit. The first terminal of the seventh switching unit is connected to the input terminal of the ramp signal generation circuit. The second terminal of the seventh switching unit is connected to the first terminal of the eighth switching unit. The second terminal of the eighth switching unit is grounded. The filter circuit is connected in parallel across the eight switches. The output terminal of the filter circuit is connected to the control terminal of the pulse width modulation circuit.

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