Grid voltage bootstrap switching circuit suitable for high-speed high-precision sampling

Abstract

The application provides a gate voltage self-boosting switch circuit suitable for high-speed and high-precision sampling, which comprises a two-stage inverter chain and an improved gate voltage self-boosting switch structure timing module; the two-stage inverter chain generates a delay signal through an enabling signal from an input first clock signal; the improved gate voltage self-boosting switch structure timing module changes the conduction resistance of a MOS transistor through a positive feedback mode under the delay of the delay signal, and changes the signal transmission time in the mode of reducing the parasitic capacitance of the delay signal. In the application, the gate end of two large-size switch tubes connected to an output node is removed, the parasitic capacitance of the output node is reduced, the signal transmission speed is improved, and a positive feedback path is introduced into a signal transmission loop, so that the signal transmission speed is further improved.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit design, specifically relating to a gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling. Background Technology

[0002] With the development of information technology, the application of analog-to-digital converters (ADCs) is becoming increasingly widespread. In products such as radar, ultra-wideband communication systems, and high-performance digital oscilloscopes, the speed performance of ADCs is often the bottleneck of the entire system performance. Therefore, the research on high-speed ADCs has received much attention.

[0003] Sample and hold circuits (S / H) are key modules in analog circuits such as analog-to-digital converters and signal readout circuits. Their performance characteristics directly affect the performance characteristics of the entire system. Research on high-speed and high-precision sample and hold circuits is of great significance. Gate voltage bootstrap switches are the key to realizing high-speed and high-precision sample and hold circuits. Summary of the Invention

[0004] To address the problem of excessive gate-terminal parasitic capacitance in traditional gate-voltage bootstrap switches, this invention provides a gate-voltage bootstrap switch circuit suitable for high-speed, high-precision sampling.

[0005] The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a gate voltage bootstrap switch circuit suitable for high-speed and high-precision sampling, comprising: a two-stage inverter chain and an improved gate voltage bootstrap switch structure timing module;

[0007] The two-stage inverter chain generates a delayed signal from the input first clock signal through an enable signal;

[0008] The improved gate voltage bootstrap switch timing module changes the signal transmission time by altering the on-resistance of the MOSFET and reducing the parasitic capacitance of the delay signal through positive feedback under the delay signal.

[0009] Optionally, the two-stage inverter chain includes: NMOS transistors Mn13-Mn15 and PMOS transistors Mp5-Mp7; the gate of PMOS transistor Mp5, the gate of NMOS transistor Mn13, and a first clock signal (SH) CLKBThe following connections are made: the drain of PMOS transistor Mp5, the drain of NMOS transistor Mn13, the gate of PMOS transistor Mp6, and the gate of NMOS transistor Mn14 are connected; the drain of PMOS transistor Mp6 is connected to the source of PMOS transistor Mp7; the source of PMOS transistor Mp6, the source of PMOS transistor Mp5, and the power supply voltage (AVDD) are connected; the drain of NMOS transistor Mn14, the drain of NMOS transistor Mn15, the drain of PMOS transistor Mp7, and the delay signal (SH) are connected. CLKB_DELAY The NMOS transistors Mn13, Mn14, and Mn15 are connected to ground; the gate of the NMOS transistor Mn15 is connected to the enable signal (pwrd).

[0010] Optionally, the improved gate voltage bootstrap switch structure timing module includes: NMOS transistors Mn1-Mn12, PMOS transistors Mp1-Mp4, capacitors C1-C3, and an inverter (inv0);

[0011] The first terminal of capacitor C1 is connected to the source of NMOS transistor Mn1, the gate of NMOS transistor Mn2, and the gate of NMOS transistor Mn3; the second terminal of capacitor C1 is connected to the delay signal (SH). CLKB_DELAY The first terminal of the inverter (inv0) is connected to the gate of NMOS transistor Mn1 and the source of NMOS transistor Mn2; the gate of NMOS transistor Mn2, the source of NMOS transistor Mn1, and the gate of NMOS transistor Mn3 are connected; the drain of NMOS transistor Mn1, the drain of NMOS transistor Mn2, the drain of NMOS transistor Mn3, the source of PMOS transistor Mp1, and the power supply voltage (AVDD) are connected; the second terminal of the capacitor C2 is connected to the second terminal of the inverter (inv0); The first terminal of capacitor C2 is connected to the gate of NMOS transistor Mn1 and the source of NMOS transistor Mn2; the first terminal of capacitor C3 is connected to the source of NMOS transistor Mn3, the source of PMOS transistor Mp2, and the source of PMOS transistor Mp4; the second terminal of capacitor C3 is connected to the source of NMOS transistor Mn8, the drain of NMOS transistor Mn6, and the source of NMOS transistor Mn9; the gates of NMOS transistors Mn4, Mn6, and Mn7, and the delay signal (SH) are also connected. CLKB_DELAY The following are connected: the drain of NMOS transistor Mn4, the drain of NMOS transistor Mn8, the gate of PMOS transistor Mp4, the gate of PMOS transistor Mp2, the drain of NMOS transistor Mn10; the source of NMOS transistor Mn4, and the first clock signal (SH). CLKBThe PMOS transistor Mp4 is connected to the source of PMOS transistor Mp2; the drain of PMOS transistor Mp4, the gate of NMOS transistor Mn8, the drain of NMOS transistor Mn5, and the gate of NMOS transistor Mn9 are connected; the source of NMOS transistor Mn5 is connected to the drain of NMOS transistor Mn7; the gate of NMOS transistor Mn5 is connected to the power supply voltage (AVDD); the sources of NMOS transistors Mn7, Mn6, and Mn12 are all grounded; the gates of PMOS transistor Mp1 and NMOS transistor Mn10 are connected to the second clock signal (SH). CLK The drain of PMOS transistor Mp1, the gate of PMOS transistor Mp2, and the drain of NMOS transistor Mn10 are connected together; the drain of PMOS transistor Mp2 is connected to the output signal (BST). CLK ); The drain of NMOS transistor Mn9 and the input signal (V IN ) connected; the gate of PMOS transistor Mp3, the gate of NMOS transistor Mn12, and the first clock signal (SH) CLKB The drains of PMOS transistor Mp3, the source of NMOS transistor Mn11, and the drain of NMOS transistor Mn12 are connected; the drains of NMOS transistor Mn11, the drain of PMOS transistor Mp2, and the output signal (BST) are connected. CLK The gate of the NMOS transistor Mn11 is connected to the power supply voltage (AVDD).

[0012] Optionally, the improved gate voltage bootstrap switch structure timing module has three operating modes: reset phase, hold phase, and sampling phase.

[0013] Optionally, when the improved gate voltage bootstrap switch structure timing module operates in the reset phase, the enable signal (pwrd) is high, and the output signal (BST) is high. CLK ) and second clock signal (SH) CLK The signal changes in a consistent trend, and the high-speed, high-precision sampling gate voltage bootstrap switching circuit does not work.

[0014] Optionally, when the improved gate voltage bootstrap switch structure timing module operates in the hold phase, the second clock signal (SH) CLK When the enable signal (pwrd) is low, the upper stage board of capacitor C3 is charged to the power supply voltage (AVDD), and the lower stage board of capacitor C3 is pulled low. The voltage stored in capacitor C3 is the power supply voltage (AVDD), and the output signal (BST) is released. CLK The voltage of ) is the power supply voltage (AVDD).

[0015] Optionally, when the improved gate voltage bootstrap switch structure timing module operates in the sampling phase, the second clock signal (SH) CLKWhen the input signal (pwrd) is high, the enable signal (pwrd) is low, and capacitor C3 is charged to the input signal (V). IN The voltage across the upper plate of capacitor C3 is pulled up to V. IN +AVDD, output signal (BST) CLK The voltage of ) is V IN +AVDD.

[0016] Beneficial effects:

[0017] In this embodiment, by removing the gate terminals of the two large-sized switching transistors connected to the output node, the parasitic capacitance of the output node is reduced, and the signal transmission speed is improved. At the same time, a positive feedback loop is introduced into the signal transmission loop, which further accelerates the signal transmission speed.

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a structural diagram of a traditional gate voltage bootstrap switching circuit;

[0020] Figure 2 The diagram shows a gate voltage bootstrap switch circuit structure suitable for high-speed, high-precision sampling, provided for embodiments of the present invention. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] Figure 1 This is a structural diagram of a traditional gate-voltage bootstrap switch circuit. In this circuit, the gate-voltage bootstrap switch timing includes a hold phase and a sampling phase.

[0023] Hold the stage clock signal SH CLK For a low level, first at SH CLK When the voltage is low, the lower plate of capacitor C1 is high and the lower plate of capacitor C2 is low. Assuming all capacitors have a voltage of 0 before circuit startup, due to the characteristic that capacitor voltage cannot change abruptly, the upper plate of C1 is high, Mn2 conducts, charging the upper plate of C2 to AVDD. At this time, the voltage across C1 is 0, while the voltage across C2 is AVDD. Simultaneously, Mn3 and Mn6 also conduct, the upper plate voltage of C3 is AVDD, and the lower plate voltage is 0. At this point, SH... CLKB When the signal is high, both Mn10 and Mn11 are turned on, and the output node BST is activated. CLK When the signal is low, Mn8 and Mn9 are turned off. SH CLKWhen the voltage is low, Mp4 is turned on, Mn7 is turned off, the gate of Mp1 is pulled to a high level, and Mp1 is turned off. At this time, there is no discharge path between the upper and lower plates of C3, and the voltage across C3 is maintained at AVDD.

[0024] Sampling phase SH CLK With the voltage at a high level, the lower plate of capacitor C1 is at a low level, and the lower plate of capacitor C2 is at a high level. Due to the characteristic that the voltage across a capacitor cannot change abruptly, the upper plate of C1 is at a low level, and Mn2 is turned off. The voltage across the upper plate of C2 is 2AVDD, Mn1 conducts, and the upper plate of C1 is charged to AVDD. Mn2 is turned off. At this time, the voltages across C1 and C2 are both AVDD, Mn3 and Mn6 are turned off, and the voltage across C3 remains at AVDD. SH CLKB When the signal is low, Mp2 is turned on, the source node of Mn10 is charged to AVDD, and Mn10 is turned off. In SH... CLKB When SH changes from high level to low level, CLKB_DELAY The signal is still high, Mn5 is temporarily turned on, pulling the gate of Mp1 low and turning it on, BST CLK When pulled high, Mn8 and Mn9 conduct, and the voltage on the lower plate of C3 rises to V. IN SH CLK When the voltage is high, Mp4 is off and Mn7 is on. At this time, there is no discharge path for the charge in C3, so the voltage across the upper plate of C3 is V. IN +AVDD, and this voltage will be transmitted to the output point BST. CLK This achieves the goal of fixing the final output gate-source voltage near AVDD.

[0025] And adopt Figure 1 Gate voltage bootstrap switching circuits suffer from excessively large gate-terminal parasitic capacitance. To address this issue, this invention provides a gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling. Figure 2 A gate voltage bootstrap switching circuit structure diagram suitable for high-speed, high-precision sampling is provided for embodiments of the present invention, as shown below. Figure 2 The diagram shows: a two-stage inverter chain and a timing module with an improved gate voltage bootstrap switch structure;

[0026] The two-stage inverter chain generates a delayed signal from the input first clock signal through an enable signal;

[0027] The improved gate voltage bootstrap switch timing module changes the signal transmission time by altering the on-resistance of the MOSFET and reducing the parasitic capacitance of the delayed signal through positive feedback during the delay signal delay.

[0028] The gate voltage bootstrap switching circuit for high-speed, high-precision sampling provided in this invention includes: a two-stage inverter chain and an improved gate voltage bootstrap switching structure timing module; the two-stage inverter chain generates a delayed signal from the input first clock signal via an enable signal; the improved gate voltage bootstrap switching structure timing module changes the signal transmission time by altering the on-resistance of the MOSFETs and reducing the parasitic capacitance of the delayed signal through positive feedback during the delay. In this embodiment, by removing the gate terminals of the two large-size switching transistors connected to the output node, the parasitic capacitance of the output node is reduced, improving the signal transmission speed. Simultaneously, a positive feedback path is introduced into the signal transmission loop, further accelerating the signal transmission speed.

[0029] Optionally, the two-stage inverter chain includes: NMOS transistors Mn13-Mn15, PMOS transistors Mp5-Mp7; the gate of PMOS transistor Mp5, the gate of NMOS transistor Mn13, and a first clock signal (SH). CLKB The following connections are made: the drain of PMOS transistor Mp5, the drain of NMOS transistor Mn13, the gate of PMOS transistor Mp6, and the gate of NMOS transistor Mn14 are connected; the drain of PMOS transistor Mp6 is connected to the source of PMOS transistor Mp7; the source of PMOS transistor Mp6, the source of PMOS transistor Mp5, and the power supply voltage (AVDD) are connected; the drain of NMOS transistor Mn14, the drain of NMOS transistor Mn15, the drain of PMOS transistor Mp7, and the delay signal (SH) are connected. CLKB_DELAY The NMOS transistors Mn13, Mn14, and Mn15 are connected to ground; the gate of the NMOS transistor Mn15 is connected to the enable signal (pwrd).

[0030] Optionally, the improved gate-voltage bootstrap switch timing module includes: NMOS transistors Mn1-Mn12, PMOS transistors Mp1-Mp4, capacitors C1-C3, and an inverter (inv0); the first terminal of capacitor C1 is connected to the source of NMOS transistor Mn1, the gate of NMOS transistor Mn2, and the gate of NMOS transistor Mn3; the second terminal of capacitor C1 is connected to the delay signal (SH). CLKB_DELAYThe first terminal of the inverter (inv0) is connected to the gate of NMOS transistor Mn1 and the source of NMOS transistor Mn2; the gates of NMOS transistor Mn2, Mn1, and Mn3 are connected; the drains of NMOS transistors Mn1, Mn2, and Mn3, the source of PMOS transistor Mp1, and the power supply voltage (AVDD) are connected; the second terminal of capacitor C2 is connected to the second terminal of the inverter (inv0); The first terminal of capacitor C2 is connected to the gate of NMOS transistor Mn1 and the source of NMOS transistor Mn2; the first terminal of capacitor C3 is connected to the source of NMOS transistor Mn3, the source of PMOS transistor Mp2, and the source of PMOS transistor Mp4; the second terminal of capacitor C3 is connected to the source of NMOS transistor Mn8, the drain of NMOS transistor Mn6, and the source of NMOS transistor Mn9; the gates of NMOS transistors Mn4, Mn6, and Mn7, and the delay signal (SH) are also connected. CLKB_DELAY The following are connected: the drain of NMOS transistor Mn4, the drain of NMOS transistor Mn8, the gate of PMOS transistor Mp4, the gate of PMOS transistor Mp2, the drain of NMOS transistor Mn10; the source of NMOS transistor Mn4, and the first clock signal (SH). CLKB The PMOS transistor Mp4 is connected to the source of PMOS transistor Mp2; the drain of PMOS transistor Mp4, the gate of NMOS transistor Mn8, the drain of NMOS transistor Mn5, and the gate of NMOS transistor Mn9 are connected; the source of NMOS transistor Mn5 is connected to the drain of NMOS transistor Mn7; the gate of NMOS transistor Mn5 is connected to the power supply voltage (AVDD); the sources of NMOS transistors Mn7, Mn6, and Mn12 are all grounded; the gates of PMOS transistor Mp1 and NMOS transistor Mn10 are connected to the second clock signal (SH). CLK The drain of PMOS transistor Mp1, the gate of PMOS transistor Mp2, and the drain of NMOS transistor Mn10 are connected together; the drain of PMOS transistor Mp2 is connected to the output signal (BST). CLK ); The drain of NMOS transistor Mn9 and the input signal (V IN ) connected; the gate of PMOS transistor Mp3, the gate of NMOS transistor Mn12, and the first clock signal (SH) CLKB The drains of PMOS transistor Mp3, the source of NMOS transistor Mn11, and the drain of NMOS transistor Mn12 are connected; the drains of NMOS transistor Mn11, the drain of PMOS transistor Mp2, and the output signal (BST) are connected. CLK The gate of the NMOS transistor Mn11 is connected to the power supply voltage (AVDD).

[0031] Input clock signal SHCLKB The two-stage inverter controlled by the PWRD signal generates a delayed signal SH. CLKB_DELAY This signal controls Mn4, Mn6, and Mn7 to discharge and reset the circuit nodes. Simultaneously, it controls the C1, C2, Mn1, and Mn2 loop, thereby controlling the charging and discharging of the Mn3 transistor on the upper-level board of C3. SH CLK The signals control Mp2 and Mn8 via Mp1 and Mn10, outputting the voltage of the upper-level board of C3. Mn4 controls Mn8 and Mn9 through Mp4, thereby controlling the voltage of the lower-level board of C3. SH CLKB The signal controls the switching of Mn11 via Mp3 and Mn12, thereby controlling BST. CLK Signal discharge path status.

[0032] Furthermore, the circuit structure utilizes the positive feedback structure formed by Mp4 and Mn8 to quickly turn on Mn9 and Mp2 during the sampling phase, thereby accelerating the signal transmission rate and simultaneously outputting the BST node. CLK Compared to traditional structures, it has two fewer gate capacitors for the large-size switching transistors Mn8 and Mn9, resulting in faster signal transmission to the output node.

[0033] Optionally, the timing module of the improved gate voltage bootstrap switch structure has three operating modes: reset phase, hold phase and sampling phase.

[0034] Optionally, when the improved gate voltage bootstrap switch structure timing module operates in the reset phase, the enable signal (pwrd) is high, and the output signal (BST) is high. CLK ) and second clock signal (SH) CLK The signal changes in a consistent trend, and the high-speed, high-precision sampling gate voltage bootstrap switching circuit does not work.

[0035] It should be noted that during the reset phase, pwrd is high, the second stage inverter in the two-stage inverter chain stops working, and SH... CLKB_DELAY When the signal is pulled low, Mn4, Mn6, and Mn7 are turned off. Since there is no discharge path, the gate voltage of Mp2 remains high, and Mp2 is turned off. In SH CLKB When the signal is high, Mn12 is on, Mp3 is off, the source of Mn11 is pulled low, Mn11 is on, and the output BST is on. CLK Pulled low to a low level; in SH CLKB When the signal is low, Mp3 is on, Mn12 is off, and the source of Mn11 is pulled from low to high. During this period, the output BST... CLK It will also be pulled high. During the reset phase, the output signal BST... CLK and SH CLK The signal changes in the same trend.

[0036] Optionally, when the operating mode of the improved gate voltage bootstrap switch structure timing module is the hold phase, the second clock signal (SH) CLK When the enable signal (pwrd) is low, the upper stage board of capacitor C3 is charged to the power supply voltage (AVDD), and the lower stage board of capacitor C3 is pulled low. The voltage stored in capacitor C3 is the power supply voltage (AVDD), and the output signal (BST) is released. CLK The voltage of ) is the power supply voltage (AVDD).

[0037] It should be noted that, in the embodiments of the present invention, the holding phase SH CLK The pwrd signal is low, and the SH signal is low. CLK When the voltage is low, the lower plate of capacitor C1 is high, and the lower plate of capacitor C2 is low. Assuming all capacitors have a voltage of 0 before circuit startup, due to the characteristic that capacitor voltage cannot change abruptly, the upper plate of C1 is high, Mn2 conducts, charging the upper plate of C2 to VDD. At this time, the voltage across C1 is 0, while the voltage across C2 is AVDD. Simultaneously, Mn3 and Mn6 also conduct, the upper plate of C3 has a voltage of AVDD, and the lower plate voltage is 0. The voltage across C3 is AVDD. Because SH CLKB When the gate is high, Mn7 conducts, which in turn turns on Mn5. The gates of Mn9 and Mn8 are pulled low, and both Mn9 and Mn8 are turned off. SH CLK When the voltage is low, Mp1 is turned on, and the gate voltages of Mp2 and Mp4 are both pulled high. When Mp2 and Mp4 are turned off, there is no discharge path for the charge on C3, and the voltage across it remains at AVDD. CLKB When the signal is high, both Mn11 and Mn12 are turned on, and the output node BST is activated. CLK It is a low level.

[0038] Optionally, when the improved gate voltage bootstrap switch structure timing module operates in the sampling phase, the second clock signal (SH) CLK When the input signal (pwrd) is high, the enable signal (pwrd) is low, and capacitor C3 is charged to the input signal (V). IN The voltage across the upper plate of capacitor C3 is pulled up to V. IN +AVDD, output signal (BST) CLK The voltage of ) is V IN +AVDD.

[0039] Specifically, during the sampling phase SH CLKWhen the signal is high, the PWRD signal is low, the lower plate of capacitor C1 is low, and the lower plate of capacitor C2 is high. Due to the characteristic that the voltage across a capacitor cannot change abruptly, the upper plate of C1 is low, and Mn2 is off. The voltage across the upper plate of C2 is 2AVDD, Mn1 is on, and the upper plate of C1 is charged to AVDD. Mn2 is off. At this time, the voltages across C1 and C2 are both AVDD, Mn3, Mn6, and Mn7 are off, and the voltage across C3 remains at AVDD. SH CLKB When Mp3 is low, Mn11 is turned on, the source node of Mn11 is charged to AVDD, and Mn11 is turned off. Mn4 is at SH... CLKB When the voltage changes from low to high, the gate voltage remains high temporarily, Mn4 is turned on, pulling down the gate voltages of Mp2 and Mp4 and turning them on, BST CLK When the gate of Mn9 is pulled high, Mn8 and Mn9 conduct. Mn8 further pulls down the gate voltages of Mp2 and Mp4, forming positive feedback, which increases the signal transmission speed. At the same time, the voltage of the lower plate of C3 rises to V. IN Since there is no discharge path for the charge on C3, the voltage across the upper plate of C3 is V. IN +AVDD, and this voltage will be transmitted to the output point BST. CLK This achieves the goal of fixing the final output gate-source voltage near AVDD.

[0040] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0041] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0042] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the description of this invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0043] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling, characterized in that, include: A two-stage inverter chain and an improved gate voltage bootstrap switch structure timing module; The two-stage inverter chain generates a delayed signal from the input first clock signal through an enable signal; The improved gate voltage bootstrap switch timing module changes the signal transmission time by changing the on-resistance of the MOSFET and reducing the parasitic capacitance of the delay signal through positive feedback under the delay signal delay. The improved gate voltage bootstrap switch structure timing module includes: NMOS transistors Mn1-Mn12, PMOS transistors Mp1-Mp4, capacitors C1-C3, and an inverter (inv0). The first terminal of capacitor C1 is connected to the source of NMOS transistor Mn1, the gate of NMOS transistor Mn2, and the gate of NMOS transistor Mn3; the second terminal of capacitor C1 is connected to the delay signal ( The first terminal of the inverter (inv0) is connected to the gate of NMOS transistor Mn1 and the source of NMOS transistor Mn2; the gate of NMOS transistor Mn2, the source of NMOS transistor Mn1, and the gate of NMOS transistor Mn3 are connected; the drain of NMOS transistor Mn1, the drain of NMOS transistor Mn2, the drain of NMOS transistor Mn3, the source of PMOS transistor Mp1, and the power supply voltage ( The capacitor C2 is connected to the inverter (inv0); the second terminal of the capacitor C2 is connected to the gate of NMOS transistor Mn1 and the source of NMOS transistor Mn2; the first terminal of the capacitor C3 is connected to the source of NMOS transistor Mn3, the source of PMOS transistor Mp2, and the source of PMOS transistor Mp4; the second terminal of the capacitor C3 is connected to the source of NMOS transistor Mn8, the drain of NMOS transistor Mn6, and the source of NMOS transistor Mn9; the gates of NMOS transistors Mn4, Mn6, and Mn7, and the delay signal ( The following are connected: the drain of NMOS transistor Mn4, the drain of NMOS transistor Mn8, the gate of PMOS transistor Mp4, the gate of PMOS transistor Mp2, the drain of NMOS transistor Mn10; the source of NMOS transistor Mn4, and the first clock signal ( The PMOS transistor Mp4 is connected to the source of the PMOS transistor Mp2; the drain of the PMOS transistor Mp4, the gate of the NMOS transistor Mn8, the drain of the NMOS transistor Mn5, and the gate of the NMOS transistor Mn9 are connected; the source of the NMOS transistor Mn5 is connected to the drain of the NMOS transistor Mn7; the gate of the NMOS transistor Mn5 is connected to the power supply voltage (…). The sources of NMOS transistors Mn7, Mn6, and Mn12 are all grounded; the gates of PMOS transistor Mp1 and Mn10 are connected to the second clock signal ( The drain of PMOS transistor Mp1, the gate of PMOS transistor Mp2, and the drain of NMOS transistor Mn10 are connected together; the drain of PMOS transistor Mp2 is connected to the output signal ( The drain of NMOS transistor Mn9 and the input signal ( ) connected; the gate of PMOS transistor Mp3, the gate of NMOS transistor Mn12, and the first clock signal ( The drain of PMOS transistor Mp3, the source of NMOS transistor Mn11, and the drain of NMOS transistor Mn12 are connected; the drain of NMOS transistor Mn11, the drain of PMOS transistor Mp2, and the output signal ( ) connected; the gate of NMOS transistor Mn11 is connected to the power supply voltage ( ).

2. The gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling according to claim 1, characterized in that, The two-stage inverter chain includes: NMOS transistors Mn13-Mn15, PMOS transistors Mp5-Mp7; the gate of PMOS transistor Mp5, the gate of NMOS transistor Mn13, and a first clock signal ( The drain of PMOS transistor Mp5, the drain of NMOS transistor Mn13, the gate of PMOS transistor Mp6, and the gate of NMOS transistor Mn14 are connected; the drain of PMOS transistor Mp6 is connected to the source of PMOS transistor Mp7; the source of PMOS transistor Mp6, the source of PMOS transistor Mp5, and the power supply voltage ( ) connected; the drain of NMOS transistor Mn14, the drain of NMOS transistor Mn15, the drain of PMOS transistor Mp7, and the delay signal ( The NMOS transistors Mn13, Mn14, and Mn15 are connected to ground; the gate of Mn15 is connected to the enable signal. ).

3. The gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling according to claim 1, characterized in that, The improved gate voltage bootstrap switch structure timing module has three working modes: reset phase, hold phase and sampling phase.

4. The gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling according to claim 3, characterized in that, When the operating mode of the improved gate voltage bootstrap switch structure timing module is the reset phase, the enable signal ( When ) is high, the output signal ( ) and second clock signal ( The signal changes in a consistent trend, and the high-speed, high-precision sampling gate voltage bootstrap switching circuit does not work.

5. The gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling according to claim 3, characterized in that, When the improved gate voltage bootstrap switch structure timing module operates in the hold phase, the second clock signal ( The enable signal is low. When the voltage is low, capacitor C3 is charged to the power supply voltage. The lower-level board is pulled low to a low level when capacitor C3 is applied, and the voltage stored in capacitor C3 is the power supply voltage. ), output signal ( The voltage of ) is the power supply voltage ( ).

6. The gate voltage bootstrap switching circuit suitable for high-speed, high-precision sampling according to claim 3, characterized in that, When the improved gate voltage bootstrap switch structure timing module operates in the sampling phase, the second clock signal ( ) is high level, enable signal ( When the signal is low, capacitor C3 is charged to the input signal level on the lower stage board. The voltage on the upper plate of capacitor C3 is pulled up to... Output signal ( The voltage of ) is .

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