Delay adaptive calibration method and apparatus, calibration circuit

Abstract

This invention relates to a delay adaptive calibration method, apparatus, and calibration circuit, within the field of integrated circuit technology. To address the technical problems of existing delay calibration techniques, such as complex calibration algorithms, high resource consumption, and applicability only to delay calibration of a single asynchronous ADC, this invention provides a delay adaptive calibration method. The method includes: dividing the acquired sampling clock signal to generate a divided signal; generating a multi-phase clock; performing an AND operation between each multi-phase clock and its corresponding original sampling clock signal to obtain an output signal, which serves as a coarse calibration enable and a fine calibration enable; gradually reducing the signal delay through switch control when the coarse or fine calibration enable is detected; latching the current switch control signal when the voltage of the signal to be detected reaches a preset high-level threshold; and completing the calibration of other clock signals in step six. This method is applied to the delay adaptive calibration of column-level asynchronous ADCs.

Description

Technical Field

[0001] This relates to the field of integrated circuit technology, specifically asynchronous logic analog-to-digital converters. Background Technology

[0002] Currently, asynchronous logic analog-to-digital converters (ADCs) can achieve high accuracy and speed while maintaining low power consumption and a small area. These characteristics make asynchronous logic ADCs suitable for a wide range of applications and have attracted much attention in the field of analog-to-digital converters.

[0003] ADCs can be categorized into synchronous logic ADCs and asynchronous logic ADCs based on the clock they use. Asynchronous logic ADCs use an internally generated asynchronous multi-phase clock as the clock for the comparators and logic. This clock is affected by the internal comparison speed. However, at medium speeds, asynchronous ADCs require an additional delay module to control the conversion time and reduce the setup requirements of the reference buffer. Therefore, asynchronous ADCs have certain requirements regarding the delay time of the entire delay module.

[0004] In asynchronous ADCs, the response time of each bit conversion stage can vary due to PVT (process, voltage, and temperature) variations. Specifically, several aspects need to be considered: First, process-related issues, where changes in process parameters can alter the comparator speed and delay unit latency; second, fluctuations in power supply voltage can cause instability in the current and voltage of each bit stage, thus affecting conversion time fluctuations; furthermore, changes in ambient temperature during chip operation also impact performance, for example, increased temperature can shorten comparator response time and reduce delay module latency. These variations also place higher demands on DAC setup and impose greater driving pressure on the reference voltage buffer. Due to the asynchronous delay differences caused by PVT, the accuracy and performance of asynchronous ADCs may be affected. To address this issue, the following measures are typically employed: temperature and power supply fluctuations are detected using temperature sensors and power monitoring modules, and the ADC is adjusted to compensate for the asynchronous delay caused by PVT variations; calibration and adaptive algorithms are used to dynamically adjust the parameters of each module in each bit conversion stage to adapt to PVT changes and reduce the impact of asynchronous delay; environmental stability is optimized during design and testing, including improving the stability of the supply voltage and temperature control. This usually requires complex on-chip power module design and temperature regulation.

[0005] Meanwhile, the difficulties and problems encountered in performing delay calibration on a large number of ADC modules in a column-level ADC are more challenging and complex. Delay calibration on a large number of asynchronous ADC modules requires processing a large amount of data and signals, thus significantly increasing the complexity of the calibration algorithm; resource overhead is high: in order to perform delay calibration, a large number of ports need to be added during design, and a large amount of data needs to be processed and controlled during testing for calibration; calibration accuracy is difficult to guarantee: the delay of asynchronous ADCs usually has a large range of variation, and there may even be significant delay differences between ADC modules in the array, so it is difficult to ensure that each ADC achieves high accuracy requirements during calibration; simultaneous calibration is difficult: simultaneous timing synchronization and data processing calibration introduces great uncertainty, and a large number of parasitic parameters in the array can easily lead to unreliable calibration results.

[0006] Currently, common delay calibration techniques generally employ off-chip configuration of an internally adjustable delay chain and an internally designed adaptive delay adjustment module to control the delay magnitude. Invention patent (CN 115412099 A) configures the adjustable delay unit for each conversion cycle via external SPI, achieving full utilization of the conversion stage time. Reference (Baek S, Jang I, Choi M, et al. 10.5A 12b 600MS / s Pipelined SAR and 2x-Interleaved IncrementalDelta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nmFinFET[C]. 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2021, 64: 172-174.) uses a background delay calibration algorithm to increase or decrease the delay by detecting the number of clock generator cycles until a determined number of cycles is obtained, at which point the calibration ends.

[0007] The aforementioned techniques all achieve delay calibration, but their application in asynchronous ADCs suffers from the following problems, significantly limiting their development: First, the calibration algorithms are complex and require processing large amounts of data; second, a large number of ports are needed for signal detection or configuration, resulting in significant resource overhead; furthermore, existing technologies are only suitable for delay calibration of a single asynchronous ADC and cannot achieve delay calibration of a column-level asynchronous ADC. These problems collectively constrain the application of asynchronous ADCs. Summary of the Invention

[0008] To address the limitations of existing delay calibration technologies, such as complex calibration algorithms requiring large amounts of data processing and numerous ports for signal detection or configuration leading to high resource overhead, and the fact that existing technologies are only applicable to delay calibration of single asynchronous ADCs and cannot achieve delay calibration of column-level asynchronous ADCs, thus restricting the application of asynchronous ADCs, the present invention provides the following technical solution:

[0009] Delay adaptive calibration method, the method comprising:

[0010] Step one: Divide the acquired sampling clock signal to generate a frequency-divided signal;

[0011] The frequency division signal is registered and a multiphase clock is generated. Each phase of the multiphase clock corresponds to step two of the ADC calibration process.

[0012] Step three involves performing an AND operation between each of the multiphase clocks and its corresponding original sampling clock signal to obtain the output signal.

[0013] The output signal is used as: coarse calibration enable and fine calibration enable of the multiphase clock within one clock cycle;

[0014] Step four involves gradually reducing the signal delay by controlling a switch when the coarse calibration enable or fine calibration enable is detected.

[0015] Step five: When the voltage of the signal to be detected reaches the preset high-level threshold, latch the current switch control signal.

[0016] Repeat steps four and five to complete step six, which involves calibrating the other clock signals.

[0017] Furthermore, a preferred embodiment is provided in which the sampling clock signal is divided by N to generate a frequency-divided signal with a duty cycle of 50%.

[0018] Furthermore, in a preferred embodiment, the initialization signal of the method is controlled by a global reset signal RST_N.

[0019] Furthermore, a preferred embodiment is provided in which the multiphase clock is generated via an XOR gate.

[0020] Furthermore, a preferred embodiment is provided, wherein the phase change step and latching step are specifically as follows: each time the coarse calibration or fine calibration enable arrives, the switch control signal changes, the delay gradually decreases, the phase of the signal to be detected changes, and when the voltage of the detected signal reaches a preset high-level threshold, the switch control signal is latched, and the calibration is completed.

[0021] Based on the same inventive concept, the present invention also provides a delay adaptive calibration device, the device comprising:

[0022] Module 1: Divide the acquired sampling clock signal to generate the divided signal;

[0023] The frequency division signal is registered and a multi-phase clock is generated. Each phase of the multi-phase clock corresponds to a module two of the ADC calibration process.

[0024] Module three outputs the signal by performing an AND operation between each of the multiphase clocks and its corresponding original sampling clock signal.

[0025] The output signal is used as: coarse calibration enable and fine calibration enable of the multiphase clock within one clock cycle;

[0026] When the coarse calibration enable or fine calibration enable is detected, module four gradually reduces the signal delay by controlling the switch.

[0027] Module 5 latches the current switch control signal when the voltage of the signal to be detected reaches the preset high-level threshold.

[0028] Module 6 repeats the functions of Modules 4 and 5 to complete the calibration of the other clock signals.

[0029] Based on the same inventive concept, the present invention also provides a delay adaptive calibration circuit, which is used to implement the aforementioned delay adaptive calibration method, and the circuit includes:

[0030] A global calibration logic circuit for calibrating column-level asynchronous ADCs one by one;

[0031] A configurable delay chain used to change the delay time, thereby changing the phase of the signal to be detected;

[0032] The circuit is used to detect the output signal of the inserted redundant trigger to generate a calibration completion signal and to perform calibration detection and storage of the latching of the switch control signal.

[0033] Furthermore, a preferred embodiment is provided, wherein the global calibration logic circuit includes: a frequency divider for reducing the frequency of the output signal to an integer multiple of the frequency of the input signal;

[0034] An asynchronous clock generation module for generating multiphase clocks;

[0035] A calibration enable module used to provide a calibration enable signal.

[0036] Based on the same inventive concept, the present invention also provides a computer storage medium for storing a computer program, wherein when the computer program is read by a computer, the computer executes the aforementioned delay adaptive calibration method.

[0037] Based on the same inventive concept, the present invention also provides a computer, including a processor and a storage medium, wherein when the processor reads a computer program stored in the storage medium, the computer executes the aforementioned delay adaptive calibration method.

[0038] The delay adaptive calibration method provided by this invention solves the problem of calibrating all ADCs simultaneously through the design of global logic circuits and local calibration circuits, and reduces the reduction in calibration accuracy caused by clock synchronization, thereby realizing array-type delay calibration of asynchronous ADCs.

[0039] The delay adaptive calibration method provided by this invention requires no additional port overhead; only a single reset port providing a reset signal is needed to complete the on-chip calibration process. This makes it suitable for large-scale array designs, while reducing the complexity of asynchronous ADC delay calibration and avoiding the chip complexity caused by a large number of configuration ports.

[0040] The delay-adaptive calibration method provided by this invention achieves column-level delay-adaptive calibration of asynchronous ADCs through ingenious design of global logic circuits and local calibration circuits. It reduces complexity and improves calibration accuracy in large-scale array applications while minimizing the need for additional ports. This is an innovation with potential commercial and technological value.

[0041] The delay adaptive calibration method provided by this invention is applied to the delay adaptive calibration of column-level asynchronous ADCs. Attached Figure Description

[0042] Figure 1 This is an overall block diagram of the column-level asynchronous ADC delay adaptive calibration circuit mentioned in Embodiment Eleven of the present invention.

[0043] Figure 2 This is a circuit block diagram of the global calibration switching module mentioned in Embodiment Eleven of the present invention.

[0044] Figure 3 This is a circuit diagram of the configurable delay chain mentioned in Embodiment Eleven of the present invention.

[0045] Figure 4 The circuit diagram for generating the internal asynchronous logic clock of the ADC mentioned in Embodiment Eleven of this invention.

[0046] Figure 5 This is a schematic diagram of the delay adaptive calibration process of the asynchronous ADC mentioned in Embodiment Eleven of the present invention.

[0047] Figure 6 This is a schematic diagram of the asynchronous SAR ADC delay adaptive calibration result mentioned in Embodiment 11 of the present invention. Detailed Implementation

[0048] To make the advantages and benefits of the technical solution provided by the present invention clearer, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings. Specifically:

[0049] Implementation Method 1: This implementation method provides a delay adaptive calibration method, the method comprising:

[0050] Step one: Divide the acquired sampling clock signal to generate a frequency-divided signal;

[0051] The frequency division signal is registered and a multiphase clock is generated. Each phase of the multiphase clock corresponds to step two of the ADC calibration process.

[0052] Step three involves performing an AND operation between each of the multiphase clocks and its corresponding original sampling clock signal to obtain the output signal.

[0053] The output signal is used as: coarse calibration enable and fine calibration enable of the multiphase clock within one clock cycle;

[0054] Step four involves gradually reducing the signal delay by controlling a switch when the coarse calibration enable or fine calibration enable is detected.

[0055] Step five: When the voltage of the signal to be detected reaches the preset high-level threshold, latch the current switch control signal.

[0056] Repeat steps four and five to complete step six, which involves calibrating the other clock signals.

[0057] Specifically,

[0058] During initialization, the reset signal is controlled by the global reset signal RST_N.

[0059] Step 1: The frequency divider divides the input sampling clock signal by N to generate a frequency-divided signal with a duty cycle of 50%.

[0060] Step 2: The asynchronous clock generation circuit registers the frequency division signal and generates a multi-phase clock through an XOR gate. Each corresponding phase of the multi-phase clock corresponds to a calibration process of an ADC.

[0061] Step 3: The calibration enable module performs an AND operation between the clock of the corresponding phase and the original signal, and registers the output signal. The output signal serves as the coarse calibration enable and fine calibration enable for the corresponding ADC.

[0062] Step 4: Each time the coarse or fine calibration is enabled, the switch control signal changes, the delay gradually decreases, the phase of the signal to be detected changes, and generally the detection signal is detected to a high level. The switch control signal is then latched, and the ADC completes the calibration.

[0063] Step 5: Perform delay adaptive calibration for the next ADC in the array.

[0064] Implementation Method 2: This implementation method further defines the delay adaptive calibration method provided in Implementation Method 1. The sampling clock signal is divided by N to generate a frequency-divided signal with a duty cycle of 50%.

[0065] Implementation Method 3: This implementation method further defines the delay adaptive calibration method provided in Implementation Method 1. The initialization signal of the method is controlled by the global reset signal RST_N.

[0066] Implementation Method 4: This implementation method further defines the delay adaptive calibration method provided in Implementation Method 1, wherein the multiphase clock is generated through an XOR gate.

[0067] Implementation Method 5: This implementation method further defines the delay adaptive calibration method provided in Implementation Method 1. The phase change step and latching step are as follows: each time the coarse calibration or fine calibration enable arrives, the switch control signal changes, the delay gradually decreases, the phase of the signal to be detected changes, and when the voltage of the detected signal reaches a preset high-level threshold, the switch control signal is latched, and the calibration is completed.

[0068] Implementation Method Six: This implementation method provides a delay adaptive calibration device, the device comprising:

[0069] Module 1: Divide the acquired sampling clock signal to generate the divided signal;

[0070] The frequency division signal is registered and a multi-phase clock is generated. Each phase of the multi-phase clock corresponds to a module two of the ADC calibration process.

[0071] Module three outputs the signal by performing an AND operation between each of the multiphase clocks and its corresponding original sampling clock signal.

[0072] The output signal is used as: coarse calibration enable and fine calibration enable of the multiphase clock within one clock cycle;

[0073] When the coarse calibration enable or fine calibration enable is detected, module four gradually reduces the signal delay by controlling the switch.

[0074] Module 5 latches the current switch control signal when the voltage of the signal to be detected reaches the preset high-level threshold.

[0075] Module 6 repeats the functions of Modules 4 and 5 to complete the calibration of the other clock signals.

[0076] Implementation Method Seven: This implementation method provides a delay adaptive calibration circuit, which is used to implement the method provided in Implementation Method One, and is used to solve the problem of unreliable delay of asynchronous ADC in large-scale arrays;

[0077] The circuit includes:

[0078] A global calibration logic circuit for calibrating column-level asynchronous ADCs one by one;

[0079] A configurable delay chain used to change the delay time, thereby changing the phase of the signal to be detected;

[0080] The circuit is used to detect the output signal of the inserted redundant trigger to generate a calibration completion signal and to perform calibration detection and storage of the latching of the switch control signal.

[0081] Specifically,

[0082] The circuitry includes: global calibration logic, a configurable delay chain, and calibration detection and storage circuitry.

[0083] The global calibration logic circuit processes the sampling clock signal FS to obtain the calibration enable of each ADC, thus completing the calibration of each column-level asynchronous ADC.

[0084] The configurable delay chain is used to change the delay time and thus change the phase of the signal to be detected;

[0085] The calibration detection and storage circuit is used to detect the output signal of the inserted redundant trigger to generate a calibration completion signal, and to latch the switch control signal to end the calibration process of each ADC.

[0086] The calibration parameters include: the length of the delay chain and the delay time.

[0087] Optionally, the global calibration logic circuit includes: a frequency divider, an asynchronous clock generation module, and a calibration enable module.

[0088] The frequency divider typically consists of flip-flops, inverters, etc., and is used to reduce the frequency of the output signal to an integer multiple of the input signal frequency. The asynchronous clock generation module includes pull-up units, flip-flops, XOR gates, and inverters. It generates multiple clock cycles using the rising edge of the divided clock signal to produce a multi-phase clock, each corresponding to an ADC to be calibrated in the array. The calibration enable module includes flip-flops, AND gates, and pull-up units. It provides calibration enable signals to each asynchronous ADC during the coarse calibration and fine calibration stages through periodic resets of the multi-phase clock.

[0089] Optionally, the calibration detection and storage circuit includes calibration detection logic circuitry and registers;

[0090] The calibration detection circuit includes a multiplexer, an inverter, and a flip-flop. It generates a calibration completion enable signal by detecting the output signal of the inserted redundant flip-flop and controls the register to latch the switch control signal.

[0091] Optionally, the configurable delay chain includes a fixed delay unit, a switch, a capacitor, and an inverter;

[0092] The fixed delay unit consists of an inverter chain. The switch, capacitor, and inverter form a configurable delay branch. The delay is adjusted by switch control. In order to achieve high-precision delay control, the configurable delay chain provides two adjustment steps: coarse and fine.

[0093] Implementation Method 8: This implementation method is a further limitation of the delay adaptive calibration circuit provided in Implementation Method 7. The global calibration logic circuit includes: a frequency divider for reducing the frequency of the output signal to an integer multiple of the frequency of the input signal.

[0094] An asynchronous clock generation module for generating multiphase clocks;

[0095] A calibration enable module used to provide a calibration enable signal.

[0096] Implementation Method Nine: This implementation method provides a computer storage medium for storing a computer program. When the computer program is read by the computer, the computer executes the method provided in Implementation Method One.

[0097] Implementation Method 10: This implementation method provides a computer, including a processor and a storage medium. When the processor reads a computer program stored in the storage medium, the computer executes the method provided in Implementation Method 1.

[0098] Implementation Method Eleven: Combination Figure 1-6This embodiment describes several specific examples of the delay adaptive calibration circuit provided in Embodiment Seven, demonstrating the advantages and benefits of the technical solution provided in Embodiment Seven. Specifically:

[0099] Example 1:

[0100] This embodiment provides a delay adaptive calibration circuit applied to a column-level asynchronous ADC, referencing... Figure 1 It includes: global calibration logic circuitry, configurable delay chain, calibration detection and storage circuitry.

[0101] The global calibration logic module includes a frequency divider, an asynchronous logic generation module, and a calibration enable module. The frequency divider divides the calibration process into a coarse calibration stage and a fine calibration stage. The asynchronous logic generation module generates multi-phase clocks corresponding to the calibration of multiple ADCs, including the coarse and fine calibration stages. The calibration enable module generates calibration enable signals for each asynchronous ADC in both the coarse and fine calibration stages.

[0102] The configurable delay chain adjusts the phase of the signal to be detected by controlling the switch signal, thereby changing the phase of the output signal of the redundant trigger.

[0103] The calibration detection and storage circuit consists of a storage module, a redundant trigger module, and calibration logic. The storage module locks the delay by registering the switch control signal of a configurable delay chain. A redundancy transition stage is obtained by inserting an additional redundant trigger module, providing the test signal to the calibration logic. The calibration logic generates a calibration completion signal by detecting the level of the test signal and sends it to the storage module, thus latching the switch control signal.

[0104] The global calibration logic circuit is as follows Figure 2 As shown; this module forms a 2-frequency divider circuit by cascading J frequency divider circuits. J Frequency dividers, each divided by two consists of a single D flip-flop. The following only uses 2... J Taking a frequency divider as an example, the input signal FS is connected to the clock port CK of the first flip-flop, while the negative output port QB of the frequency divider is fed back to the input port D. The clock port of the subsequent frequency divider circuit is connected to the positive output port Q of the previous stage, and the rest is the same as the first stage.

[0105] The workflow of the global calibration logic circuit includes:

[0106] Step 1: Set the reset signal RST_N to 1. The frequency divider starts generating the FS frequency division signal. Divide the FS signal by 2J to obtain FS_DIV. By switching the input signal of the flip-flop in each clock cycle, a frequency division signal with a 50% duty cycle is achieved.

[0107] Step 2: The frequency-divided signal FS_DIV generates an asynchronous logic calibration enable signal EN through a chain of flip-flops (containing N+1 flip-flops). Two adjacent clock signals EN... <i-1>and EN (where i = 1, 1:...:N) A multiphase clock FCLK with relative inertia FS_DIV is generated through an XOR gate. Each clock phase corresponds to one ADC;

[0108] Step 3: Divide the calibration process of a single asynchronous ADC into coarse calibration and fine calibration stages using NAND gates. Specifically, a high level of FS_DIV corresponds to the coarse calibration stage, and a low level corresponds to the fine calibration stage. Each coarse and fine calibration stage contains at least 2... J -1 rising edge of the FS signal. Therefore, the delay of a single asynchronous ADC can support up to 2 J -1 coarse calibration and 2 J -1 fine calibration.

[0109] Similarly, the calibration enable module also uses an asynchronous logic generation module to generate an asynchronous clock. The CK terminal is connected to FS, and the reset terminal is connected to FS_DIV to obtain the calibration signal for the coarse calibration stage. Likewise, connecting the reset terminal to the inverted signal of FS_DIV yields the calibration signal for the fine calibration stage. Calibration enable is achieved through FCLK. AND to obtain ADC The corresponding calibration enable signal.

[0110] Furthermore, in order to achieve low-overhead calibration and digital control, this invention does not use a voltage-controlled delay line to configure the delay. Figure 3 This is a schematic diagram of the configurable delay chain circuit. Coarse calibration is performed using K groups of switches SC<1:K> and capacitor C. c The calibration consists of K sets of switches SF<1:K> and capacitors Cc, each with identical parameters. These K calibration branches are connected in parallel to form a coarse-tuning delay unit. Similarly, fine-tuning calibration is performed using K sets of switches SF<1:K> and capacitors Cc. f <1:K> consists of a switch SF and a capacitor C. f With identical parameters, K calibration branches are connected in parallel to form a fine-tuning delay unit. In each calibration phase, each switch toggles once, thereby reducing the delay, with each delay change being approximately the same.

[0111] During the coarse calibration phase of a single ADC, when SC<1:K> are all 1, i.e., all switches are on, the propagation delay of a single inverter link with variable load, i.e., the propagation time from input A to output AC, can be approximated as:

[0112] t p =(t phl +t plh ) / 2=0.69((R eqp +R eqn ) / 2)(C m +KC c )+3t inv ;

[0113] In the formula t phl and t plh R represents the propagation delay of the signal from low to high and from high to low, respectively; eqp and R eqn C represents the equivalent on-resistance during the propagation time. m C represents the intrinsic capacitance of the MOSFET (assuming that the intrinsic capacitances of PMOS and NMOS are the same). c To coarsely calibrate the load capacitance C of the branch, t inv The propagation delay for a single inverter.

[0114] Similarly, when SC<1:K> are all 0, meaning all switches are off, the propagation time from AC to YC can be approximated as:

[0115] t p =(t phl +t plh ) / 2=0.69((R eqp +R eqn ) / 2)C m +3t inv ;

[0116] During the fine calibration phase of a single ADC, when all SF<1:K> are 1, i.e. all switches are on, the propagation delay of a single variable inverter link, i.e., the propagation delay from the input terminal AF to the output terminal YF, can be approximated as:

[0117] t p =(t phl +t plh ) / 2=0.69((R eqp +R eqn ) / 2)(C m +KC f )+3t inv ;

[0118] In the formula C f k1 represents the capacitance value of the load capacitor C of the coarse calibration branch, and k2 represents the number of coarse calibration branches in the access link.

[0119] Similarly, when SF<1:K> are all 0, meaning all switches are off, the propagation delay from AC to Y can be approximated as:

[0120] t p =(t phl +t plh ) / 2=0.69((R eqp +R eqn ) / 2)C m +3t inv ;

[0121] Therefore, the propagation delay of the configurable delay chain, i.e., the propagation delay t from A to Y, is... d_all The configuration range is represented as follows:

[0122] 0.69((R eqp +R eqn ) / 2)C m +6t inv ≤t d_all ≤0.69((R eqp +R eqn ) / 2)(C m +KC c +KC f )+6t inv ;

[0123] Figure 4 This example shows the internal asynchronous logic clock generation circuit of the ADC, including comparators, pull-up units, L flip-flop delay units, and logic gates. Two redundant flip-flops are inserted at the end of the original L-2 flip-flop chain. The outputs of these redundant flip-flops, INS_C and INS_F, serve as the signals to be detected during the coarse and fine calibration stages, respectively. The FS signal is delayed and then ANDed with itself to obtain the signal RST_DFF. RST_DFF and FS are ANDed to obtain the signal CK. The redundant signals INS_C and INS_F are detected when the rising edge of CK arrives. The signal RST_DFF serves as the reset signal for the ADC's internal asynchronous clock flip-flop chain, ensuring that a valid redundant signal is detected on the rising edge of CK.

[0124] Furthermore, the delay calibration process for a single ADC is as follows: Figure 5 As shown. When the calibration enable signal arrives, the adjustable delay link is in the maximum propagation delay state by default. First, a coarse calibration phase is performed. At the end of each conversion phase, it is checked whether INS_C is high. If it is high, the coarse calibration ends; otherwise, after each complete conversion phase, the propagation delay of the coarse adjustment delay unit is reduced until INS_C is detected as high, at which point the coarse calibration ends. Next, the fine calibration phase begins. Similarly, at the end of each conversion phase, it is checked whether INS_F is high. If it is high, the calibration ends; otherwise, after each complete conversion phase, the propagation delay of the fine adjustment delay unit is reduced until INS_F is detected as high or the entire conversion is completed, at which point the calibration ends.

[0125] Example 2:

[0126] This embodiment provides a delay adaptive calibration method for a column-level asynchronous ADC. The method is implemented based on the aforementioned delay adaptive calibration circuit and includes:

[0127] Step 1: The frequency divider divides the input sampling clock signal by N to generate a frequency-divided signal with a duty cycle of 50%.

[0128] Step 2: The asynchronous clock generation circuit registers the frequency division signal, and the reset signal is controlled by the global reset signal RST_N. It generates a multi-phase clock through an XOR gate, and each corresponding phase of the multi-phase clock corresponds to a calibration process of an ADC.

[0129] Step 3: The calibration enable module performs an AND operation between the clock of the corresponding phase and the original signal, and registers the output signal. The output signal serves as the coarse calibration enable and fine calibration enable for the corresponding ADC.

[0130] Step 4: Each time the coarse or fine calibration is enabled, the switch control signal changes, the delay gradually decreases, the phase of the signal to be detected changes, and generally the detection signal is detected to a high level. The switch control signal is then latched, and the ADC completes the calibration.

[0131] Step 5: Perform delay adaptive calibration for the next ADC in the array.

[0132] Example 3:

[0133] This embodiment provides a delay-adaptive calibration method for a column-level 10-bit asynchronous SAR ADC, implemented based on the aforementioned delay-adaptive calibration circuit. The global calibration logic circuit provides calibration enable signals for coarse and fine calibration stages to the 16 asynchronous ADCs; the configurable delay chain includes 6 coarse calibration branches and 6 fine calibration branches; the calibration detection and storage circuit detects the output signals of redundant triggers and latches the switching control signals.

[0134] Optionally, the asynchronous SARADC has a sampling frequency of 20 MSPS, with 25 ns allocated to each of the sampling and conversion phases. A total of 12 comparisons are required within the conversion period, corresponding to the 10-bit code value output and the 2-bit redundancy phase.

[0135] A verification platform was built based on CMOS 55nm process and simulations were performed. Figure 6 This is a simulation result of the delay calibration of the first ADC in the delay adaptive calibration circuit of the column-level 10-bit SAR ADC provided in this embodiment of the invention. The horizontal axis corresponds to the simulation time axis, and the vertical axis represents the voltage values ​​of each signal under a 1.2V power supply, with units of seconds and volts, respectively. In the figure, FS is the sampling signal, and the ADC performs conversion during the low-level phase; END_C and END_F are the end signals output by the calibration detection circuit, respectively; INS_C and INS_F are the signals to be detected output by the redundant triggers during the conversion phase; CK is the detection signal fully correlated with FS; CLK_C<0:5> and CLK_F<0:5> are the coarse calibration enable and fine calibration enable provided to the ADC by the global calibration logic circuit, respectively.

[0136] Based on the simulation results, the calibration process is described as follows:

[0137] 1) The reset signal RST_N is set to 1. The frequency divider divides the FS signal by 16 to obtain FS_DIV. The first pulse of FS_DIV corresponds to the first ADC performing adaptive calibration. The asynchronous logic generation module and the calibration enable module generate... Figure 6 The CLK_C<0:5> and CLK_F<0:5> signals are used as the coarse calibration enable and fine calibration enable for this ADC calibration.

[0138] 2) In CLK_C <0> Before the arrival, all switch enable signals SC<1:K> and SF<1:K> are connected to logic level 1, so that both the coarse calibration branch and the fine calibration branch are connected to the delay chain. At this time, the propagation delay of the delay chain reaches its maximum, and the signals to be detected INS_C and INS_F are always 0.

[0139] 3) After CLK_C arrives, the corresponding SC switch control signal changes from 1 to 0, the switch is turned off, and the delay of the delay chain is reduced accordingly with a larger step size. When CLK_C arrives... <5> When the coarse calibration branch is reached, all coarse calibration branches are turned off. At this time, INS_C is detected to be 1 and END_C is output as 0. The switch control signal of the coarse calibration branch is latched.

[0140] 4) Similarly, after CLK_F arrives, the corresponding SF switch control signal changes from 1 to 0, the switch closes, and the delay chain's delay decreases accordingly with a smaller step size. Figure 6 CLK_F <1> When CLK_F arrives, the INS_F signal has already appeared, but the rising edge of CK corresponds to INS_F still being 0, so the output END_F is 1. <2> When it arrives, the delay of the delay chain in the previous stage is reduced by a small step size. INS_F is detected to be 1, and the output result END_F is 0. The switch control signal of the fine calibration branch is latched.

[0141] 5) End the delay adaptive calibration of the ADC, wait for the next ADC pulse in the array to arrive, and execute the delay adaptive calibration process.

[0142] This embodiment retains a 2-bit redundant stage time in each delay adaptive calibration of the column-level ADC, ensuring that the delay still meets the output requirements of all code values ​​even under different temperature or voltage fluctuations. Meanwhile, the entire calibration method requires no additional port overhead, only a single reset port to provide the reset signal, making it suitable for large-scale array designs.

[0143] The above description of several specific embodiments further details the technical solution provided by the present invention in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the above-described specific embodiments are not intended to limit the present invention. Any reasonable modifications and improvements to the present invention, combinations of embodiments, and equivalent substitutions based on the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0144] In the description of this specification, only preferred embodiments of the present invention are described, and should not be construed as limiting the scope of the invention. Furthermore, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or N embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Additionally, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified. Any process or method described in the flowcharts or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logical functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain. The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or N wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM).Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory. It should be understood that various parts of the invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0145] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments. Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

Claims

1. A delay adaptive calibration method, characterized in that, The method includes: Step one: Divide the acquired sampling clock signal to generate a frequency-divided signal; The frequency division signal is registered and a multiphase clock is generated. Each phase of the multiphase clock corresponds to step two of the ADC calibration process. Step three involves performing an AND operation between each of the multiphase clocks and its corresponding original sampling clock signal to obtain the output signal. The output signal is used as: coarse calibration enable and fine calibration enable of the multiphase clock within one clock cycle; Step four involves gradually reducing the signal delay by controlling a switch when the coarse calibration enable or fine calibration enable is detected. Step five: When the voltage of the signal to be detected reaches the preset high-level threshold, latch the current switch control signal. Repeat steps four and five to complete step six, which involves calibrating the other clock signals. The initialization signal of the method is controlled by the global reset signal RST_N; The multiphase clock is generated via an XOR gate; Steps four and five are specifically as follows: each time the coarse or fine calibration is enabled, the switch control signal changes, the delay gradually decreases, the phase of the signal to be detected changes, and when the voltage of the detected signal reaches the preset high-level threshold, the switch control signal is latched, and the calibration is completed.

2. The delay adaptive calibration method according to claim 1, characterized in that, The sampling clock signal, after being divided by N, generates a frequency-divided signal with a duty cycle of 50%.

3. A delay adaptive calibration device, characterized in that, The device includes: Module 1: Divide the acquired sampling clock signal to generate the divided signal; The frequency division signal is registered and a multi-phase clock is generated. Each phase of the multi-phase clock corresponds to a module two of the ADC calibration process. Module three outputs the signal by performing an AND operation between each of the multiphase clocks and its corresponding original sampling clock signal. The output signal is used as: coarse calibration enable and fine calibration enable of the multiphase clock within one clock cycle; When the coarse calibration enable or fine calibration enable is detected, module four gradually reduces the signal delay by controlling the switch. Module 5 latches the current switch control signal when the voltage of the signal to be detected reaches the preset high-level threshold. Module 6 repeats the functions of modules four and five to complete the calibration of the other clock signals; The initialization signal of the device is controlled by the global reset signal RST_N; The multiphase clock is generated via an XOR gate; Modules four and five are specifically defined as follows: each time coarse or fine calibration is enabled, the switch control signal changes, the delay gradually decreases, the phase of the signal to be detected changes, and when the voltage of the detected signal reaches a preset high-level threshold, the switch control signal is latched, and the calibration is completed.

4. A delay adaptive calibration circuit, characterized in that, The circuit is used to implement the method of claim 1, and the circuit includes: A global calibration logic circuit for calibrating column-level asynchronous ADCs one by one; A configurable delay chain used to change the delay time, thereby changing the phase of the signal to be detected; The circuit is used to detect the output signal of the inserted redundant trigger to generate a calibration completion signal and to perform calibration detection and storage of the latching of the switch control signal.

5. The delay adaptive calibration circuit according to claim 4, characterized in that, The global calibration logic circuit includes: a frequency divider for reducing the frequency of the output signal to an integer multiple of the frequency of the input signal; An asynchronous clock generation module for generating multiphase clocks; A calibration enable module used to provide a calibration enable signal.

6. A computer storage medium for storing computer programs, characterized in that, When the computer program is read by the computer, the computer executes the method of claim 1.

7. A computer, comprising a processor and a storage medium, characterized in that, When the processor reads the computer program stored in the storage medium, the computer executes the method of claim 1.

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