A multi-stage high-precision comparator based on bandwidth adjustment technology

Abstract

The application discloses a kind of multistage high-precision comparators based on bandwidth adjustment technology, it is related to CMOS analog integrated circuit technical field, including: multistage amplifier, multistage offset calibration module, multistage bandwidth adjustment module and latch, the input end of first stage amplifier is connected with signal input end, output end is connected with first stage offset calibration module, the input end of nth stage amplifier is connected with the output end of last stage offset calibration module, the output end of nth stage amplifier is connected to nth stage offset calibration module by nth-1 stage bandwidth adjustment module, the input end of last stage amplifier is connected with the output end of last stage offset calibration module, the output end of last stage amplifier is sequentially connected with last stage bandwidth adjustment module and latch, and latch is used to lock the analog potential output by last stage amplifier as digital potential 1 or 0.The comparator provided in the application effectively reduces the equivalent offset and equivalent noise of input end.

Description

Technical Field

[0001] This invention belongs to the field of CMOS analog integrated circuit technology, specifically relating to a multi-stage high-precision comparator based on bandwidth adjustment technology. Background Technology

[0002] As the feature size of CMOS (Complementary Metal Oxide Semiconductor) technology continues to shrink, analog circuits are constantly evolving towards higher integration and stronger performance. Successive approximation analog-to-digital converters (SAR ADCs) have also received widespread attention due to their better compatibility with digital circuits.

[0003] As a key module in SAR ADCs, the comparator's accuracy, noise, and offset significantly impact the ADC's dynamic performance. While existing dynamic comparators offer high speed, they struggle to address inherent comparator offset issues, and conventional dynamic comparators suffer from significant noise, making them unsuitable for high-precision applications such as those exceeding 18 bits.

[0004] Therefore, those skilled in the art urgently need to design a comparator with higher accuracy and lower offset, which is also of great significance for the design of high-precision SAR ADCs. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a multi-stage high-precision comparator based on bandwidth adjustment technology. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a multi-stage high-precision comparator based on bandwidth adjustment technology, comprising: a multi-stage amplifier, a multi-stage offset calibration module, a multi-stage bandwidth adjustment module, and a latch;

[0007] The input terminal of the first-stage amplifier is connected to the signal input terminal, and the output terminal is connected to the first-stage offset calibration module. The input terminal of the nth-stage amplifier is connected to the output terminal of the previous-stage offset calibration module. The output terminal of the nth-stage amplifier is connected to the nth-stage offset calibration module via the (n-1)th-stage bandwidth adjustment module. The input terminal of the last-stage amplifier is connected to the output terminal of the previous-stage offset calibration module. The output terminal of the last-stage amplifier is sequentially connected to the last-stage bandwidth adjustment module and a latch. The latch is used to latch the analog potential output by the last-stage amplifier as a digital potential 1 or 0. Where n = 2, 3, ..., N-1, and N represents the number of stages of the multi-stage amplifier.

[0008] In one embodiment of the invention, a bias circuit is further included, which is used to provide bias current for each stage of the amplifier and bias voltage for each stage of the offset calibration module.

[0009] In one embodiment of the present invention, a voltage source VDD is further included. The signal input terminal includes a positive input terminal IP and a negative input terminal IN. The first stage amplifier includes a current source I_A, input transistors M1_A and M2_A, self-biased common gate transistors M3_A and M4_A, and load resistors R1_A, R2_A, R3_A, and R4_A. The input terminal of the first stage amplifier includes a positive input terminal VIP1 and a negative input terminal VIN1, and the output terminal includes a positive output terminal VOP1 and a negative output terminal VON1. The positive input terminal VIP1 and the negative input terminal VIN1 of the first stage amplifier are respectively connected to the positive input terminal IP and the negative input terminal IN.

[0010] In this configuration, the positive terminal of current source I_A is connected to voltage source VDD, and its negative terminal is connected to the source terminals of M1_A and M2_A, respectively. The gate terminal of M1_A is connected to the positive input terminal VIP1, and its drain terminal is connected to the source terminal of M3_A. The gate terminal of M2_A is connected to the negative input terminal VIN1, and its drain terminal is connected to the source terminal of M4_A. The gate terminal of M3_A is connected to the negative terminal of load resistor R1_A and the positive terminal of R3_A, and its drain terminal is connected to the positive output terminal VOP1 and the positive terminal of load resistor R1_A. The gate terminal of M4_A is connected to the negative terminal of load resistor R2_A and the positive terminal of load resistor R4_A, and its drain terminal is connected to the negative output terminal VON1 and the positive terminal of load resistor R2_A. The negative terminals of load resistors R3_A and R4_A are both grounded.

[0011] In one embodiment of the present invention, the input transistors M1_A and M2_A, as well as the self-biased common gate transistors M3_A and M4_A, are PMOS transistors.

[0012] In one embodiment of the present invention, the nth stage amplifier has the same structure as the last stage amplifier. The nth stage amplifier includes a current source I_n, input transistors M1_n and M2_n, self-biased common gate transistors M3_n and M4_n, and load resistors R1_n, R2_n, R3_n, and R4_n. The input terminals of the nth stage amplifier include a positive input terminal VIPn and a negative input terminal VINn, and the output terminals include a positive output terminal VOPn and a negative output terminal VONn. The positive input terminal VIPn and the negative input terminal VINn of the nth stage amplifier are respectively connected to the positive output terminal and the negative output terminal of the (n-1)th stage offset calibration module.

[0013] The positive terminals of R3_n and R4_n are connected to the voltage source VDD. The negative terminal of R3_n is connected to the positive terminal of R1_n and the gate terminal of M3_n. The negative terminal of R4_n is connected to the positive terminal of R2_n and the gate terminal of M4_n. The negative terminal of R1_n is connected to the positive output terminal VOPn and the drain terminal of M3_n. The negative terminal of R2_n is connected to the negative output terminal VONn and the drain terminal of M4_n. The source terminal of M3_n is connected to the drain terminal of M1_n. The source terminal of M4_n is connected to the drain terminal of M2_n. The gate terminal of M1_n is connected to the positive input terminal VIPn. The gate terminal of M2_n is connected to the negative input terminal VINn. The source terminals of M1_n and M2_n are connected together and connected to the positive terminal of the current source I_n. The negative terminal of I_n is grounded.

[0014] The input transistors M1_n and M2_n, as well as the self-biased common gate transistors M3_n and M4_n, are NMOS transistors.

[0015] In one embodiment of the present invention, the offset calibration modules at each stage include offset calibration capacitors: CC1, CC2 and offset calibration transistors: MC1, MC2, MC3; wherein,

[0016] The first plates of offset calibration capacitors CC1 and CC2 are connected to the positive and negative input terminals of the offset calibration module, respectively. The second plate of offset calibration capacitor CC1 is connected to the positive output terminal of the offset calibration module, the source terminal of offset calibration transistor MC1, and the source terminal of offset calibration transistor MC3. The second plate of offset calibration capacitor CC2...

[0017] The electrode plate is connected to the negative output terminal of the offset calibration module, the source terminal of offset calibration transistor MC2, and the drain terminal of offset calibration transistor MC3. The gate terminal of offset calibration transistor MC1 is connected to the gate terminal of offset calibration transistor MC2 and connected to the control signal CTRL1. The drain terminal of offset calibration transistor MC1 is connected to the drain terminal of offset calibration transistor MC2 and connected to the bias voltage Vcm. The gate terminal of offset calibration transistor MC3 is connected to the control signal CTRL2. Offset calibration transistors MC1, MC2, and MC3 are all NMOS transistors.

[0018] In one embodiment of the present invention, the operation of the comparator includes an offset calibration stage and a comparator quantization stage; wherein, the nth stage offset calibration module is in the working state during the offset calibration stage and is used to store the offset voltage of the nth stage amplifier, and the nth stage offset calibration module is in the holding state during the comparator quantization stage and is used to eliminate the offset of the amplifier using the stored offset voltage.

[0019] In one embodiment of the present invention, each level of the bandwidth adjustment module includes a bandwidth adjustment capacitor CW and switching transistors: MW1, MW2, MW3, and MW4; wherein,

[0020] The positive input ports of each bandwidth adjustment module are connected to their own positive output ports and then to the source of switch MW1. The negative input ports of each bandwidth adjustment module are connected to their own negative output ports and then to the source of switch MW2. The gate terminals of switches MW1 and MW2 are connected to the control signal CTRL3. The drain terminal of switch MW1 is connected to the positive terminal of the bandwidth adjustment point capacitor CW and the drain terminal of MW3. The drain terminal of switch MW2 is connected to the negative terminal of the bandwidth adjustment capacitor CW and the drain terminal of switch MW4. The gate terminals of switches MW3 and MW4 are connected and then connected to the control signal CTRL2b. The source terminals of switches MW3 and MW4 are connected and then connected to VDD.

[0021] In one embodiment of the present invention, the switching transistors MW1, MW2, MW3 and MW4 are all PMOS transistors.

[0022] In one embodiment of the present invention, the latch is connected to a clock signal CLKL, which is used to control the reset mode and latching mode of the latch.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] This invention provides a high-precision comparator based on bandwidth adjustment technology, comprising: a multi-stage amplifier, a multi-stage offset calibration module, a multi-stage bandwidth adjustment module, and a latch. The comparator reduces the equivalent offset and noise at the comparator input through the multi-stage amplifier, eliminates amplifier offset through the multi-stage offset calibration module, and adjusts the noise bandwidth of each amplifier stage through the multi-stage bandwidth adjustment module, thereby reducing the comparator's noise. Because the comparator utilizes timing control of each switching transistor in the bandwidth adjustment module, the influence of the bandwidth adjustment capacitor on the offset calibration process is avoided. Therefore, the high-precision comparator based on bandwidth adjustment technology provided by this invention can be applied to high-precision analog-to-digital converters, effectively reducing the equivalent offset and equivalent noise at the input.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a multi-stage high-precision comparator based on bandwidth adjustment technology provided in an embodiment of the present invention;

[0027] Figure 2 This is another schematic diagram of a multi-stage high-precision comparator based on bandwidth adjustment technology provided in an embodiment of the present invention;

[0028] Figure 3 This is a circuit diagram of the first-stage amplifier provided in an embodiment of the present invention;

[0029] Figure 4This is a circuit diagram of the nth stage amplifier provided in an embodiment of the present invention;

[0030] Figure 5 This is a circuit diagram of the various levels of offset calibration modules provided in the embodiments of the present invention;

[0031] Figure 6 This is a circuit diagram of the bandwidth adjustment modules at each level provided in an embodiment of the present invention;

[0032] Figure 7 This is a timing diagram of a high-precision comparator based on bandwidth adjustment technology provided in an embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0034] Figure 1 This is a schematic diagram of a multi-stage high-precision comparator based on bandwidth adjustment technology provided in an embodiment of the present invention. Figure 1 As shown, this embodiment of the invention provides a multi-stage high-precision comparator based on bandwidth adjustment technology, including: a multi-stage amplifier, a multi-stage offset calibration module, a multi-stage bandwidth adjustment module, and a latch;

[0035] The input terminal of the first-stage amplifier is connected to the signal input terminal, and the output terminal is connected to the first-stage offset calibration module. The input terminal of the nth-stage amplifier is connected to the output terminal of the previous-stage offset calibration module. The output terminal of the nth-stage amplifier is connected to the nth-stage offset calibration module via the (n-1)th-stage bandwidth adjustment module. The input terminal of the last-stage amplifier is connected to the output terminal of the previous-stage offset calibration module. The output terminal of the last-stage amplifier is sequentially connected to the last-stage bandwidth adjustment module and a latch. The latch is used to latch the analog potential output by the last-stage amplifier as a digital potential 1 or 0. Here, n = 2, 3, ..., N-1, and N represents the number of stages in the multi-stage amplifier.

[0036] In this embodiment, the multi-stage high-precision comparator based on bandwidth adjustment technology includes: a multi-stage amplifier, a multi-stage offset calibration module, a multi-stage bandwidth adjustment module, and a latch. Specifically, the first-stage amplifier is a high-bandwidth, low-noise differential amplifier, and the remaining stages are low-bandwidth differential amplifiers. The multi-stage amplifier structure can effectively reduce the noise of the subsequent stages and the offset of the latch at the input. Each stage offset calibration module stores the amplifier offset in its own offset calibration capacitor under timing coordination, thereby reducing the equivalent offset at the comparator input. Each stage bandwidth adjustment module is used to adjust the noise bandwidth of its respective amplifier stage and filter out noise. Finally, the latch latches the analog potential output by the N-stage amplifier as a digital potential of 1 or 0.

[0037] Figure 2This is another schematic diagram of a multi-stage high-precision comparator based on bandwidth adjustment technology provided in an embodiment of the present invention. When N=4, the multi-stage high-precision comparator based on bandwidth adjustment technology is as follows: Figure 2 As shown.

[0038] Optionally, please continue to see Figure 2 The aforementioned multi-stage high-precision comparator based on bandwidth adjustment technology also includes a bias circuit. This bias circuit provides bias current for each stage of the amplifier and bias voltage for each stage of the offset calibration module. It should be noted that the input current of the bias circuit is a variable current I_var, and in analog-to-digital converter applications, the current magnitude can be adjusted according to the capacitance of the bandwidth adjustment module.

[0039] Figure 3 This is a circuit diagram of the first-stage amplifier provided in an embodiment of the present invention. Figure 3 As shown, the multi-stage high-precision comparator based on bandwidth adjustment technology also includes a voltage source VDD, signal input terminals including a positive input terminal IP and a negative input terminal IN, and a first-stage amplifier including a current source I_A, input transistors M1_A and M2_A, self-biased common-gate transistors M3_A and M4_A, and load resistors R1_A, R2_A, R3_A, and R4_A. The first-stage amplifier has positive input terminals VIP1 and negative input terminals VIN1, and output terminals including positive output terminals VOP1 and negative output terminals VON1. The positive input terminals VIP1 and VIN1 of the first-stage amplifier are connected to the positive input terminal IP and the negative input terminal IN, respectively.

[0040] The positive terminal of current source I_A is connected to voltage source VDD, and its negative terminal is connected to the source terminals of M1_A and M2_A respectively. The gate terminal of M1_A is connected to the positive input terminal VIP1, and its drain terminal is connected to the source terminal of M3_A. The gate terminal of M2_A is connected to the negative input terminal VIN1, and its drain terminal is connected to the source terminal of M4_A. The gate terminal of M3_A is connected to the negative terminal of load resistor R1_A and the positive terminal of R3_A, and its drain terminal is connected to the positive output terminal VOP1 and the positive terminal of load resistor R1_A. The gate terminal of M4_A is connected to the negative terminal of load resistor R2_A and the positive terminal of load resistor R4_A, and its drain terminal is connected to the negative output terminal VON1 and the positive terminal of load resistor R2_A. The negative terminals of load resistors R3_A and R4_A are both grounded.

[0041] It should be noted that the input transistors M1_A and M2_A, as well as the self-biased common gate transistors M3_A and M4_A, are PMOS transistors.

[0042] Figure 4 This is a circuit diagram of the nth stage amplifier provided in an embodiment of the present invention. In this embodiment, the nth stage amplifier has the same structure as the last stage amplifier, as shown below. Figure 4Taking the nth stage amplifier as an example, the nth stage amplifier includes a current source I_n, input transistors: M1_n and M2_n, self-biased common gate transistors: M3_n and M4_n, and load resistors: R1_n, R2_n, R3_n and R4_n. The input terminals of the nth stage amplifier include a positive input terminal VIPn and a negative input terminal VINn, and the output terminals include a positive output terminal VOPn and a negative output terminal VONn. The positive input terminal VIPn and the negative input terminal VINn of the nth stage amplifier are respectively connected to the positive output terminal and the negative output terminal of the (n-1)th stage offset calibration module.

[0043] The positive terminals of R3_n and R4_n are connected to the voltage source VDD. The negative terminal of R3_n is connected to the positive terminal of R1_n and the gate terminal of M3_n. The negative terminal of R4_n is connected to the positive terminal of R2_n and the gate terminal of M4_n. The negative terminal of R1_n is connected to the positive output terminal VOPn and the drain terminal of M3_n. The negative terminal of R2_n is connected to the negative output terminal VONn and the drain terminal of M4_n. The source terminal of M3_n is connected to the drain terminal of M1_n. The source terminal of M4_n is connected to the drain terminal of M2_n. The gate terminal of M1_n is connected to the positive input terminal VIPn. The gate terminal of M2_n is connected to the negative input terminal VINn. The source terminals of M1_n and M2_n are connected together and connected to the positive terminal of the current source I_n. The negative terminal of I_n is grounded.

[0044] Among them, the input transistors M1_n and M2_n, as well as the self-biased common gate transistors M3_n and M4_n, are NMOS transistors.

[0045] Figure 5 This is a circuit diagram of the various levels of offset calibration modules provided in an embodiment of the present invention. Please refer to... Figure 5 The offset calibration modules at each level include offset calibration capacitors: CC1, CC2 and offset calibration transistors: MC1, MC2, MC3; among which,

[0046] The first plates of offset calibration capacitors CC1 and CC2 are connected to the positive and negative input terminals of the offset calibration module, respectively. The second plate of offset calibration capacitor CC1 is connected to the positive output terminal of the offset calibration module, the source terminal of offset calibration transistor MC1, and the source terminal of offset calibration transistor MC3. The second plate of offset calibration capacitor CC2...

[0047] The electrode plate is connected to the negative output terminal of the offset calibration module, the source terminal of offset calibration transistor MC2, and the drain terminal of offset calibration transistor MC3. The gate terminal of offset calibration transistor MC1 is connected to the gate terminal of offset calibration transistor MC2 and connected to the control signal CTRL1. The drain terminal of offset calibration transistor MC1 is connected to the drain terminal of offset calibration transistor MC2 and connected to the bias voltage Vcm. The gate terminal of offset calibration transistor MC3 is connected to the control signal CTRL2. Offset calibration transistors MC1, MC2, and MC3 are all NMOS transistors.

[0048] It should be understood that the working process of the comparator includes: offset calibration stage and comparator quantization stage; wherein, the nth stage offset calibration module is in working state during the offset calibration stage, and is used to store the offset voltage of the nth stage amplifier; the nth stage offset calibration module is in holding state during the comparator quantization stage, and is used to cancel the amplifier offset with the stored offset voltage.

[0049] Figure 6 This is a circuit diagram of the bandwidth adjustment modules at each level provided in an embodiment of the present invention. Further, please refer to... Figure 6 Each level of the bandwidth adjustment module includes a bandwidth adjustment capacitor CW and switching transistors: MW1, MW2, MW3, and MW4; among which,

[0050] The positive input ports of each bandwidth adjustment module are connected to their own positive output ports and then to the source of switch MW1. The negative input ports of each bandwidth adjustment module are connected to their own negative output ports and then to the source of switch MW2. The gate terminals of switches MW1 and MW2 are connected to the control signal CTRL3. The drain terminal of switch MW1 is connected to the positive terminal of the bandwidth adjustment point capacitor CW and the drain terminal of MW3. The drain terminal of switch MW2 is connected to the negative terminal of the bandwidth adjustment capacitor CW and the drain terminal of switch MW4. The gate terminals of switches MW3 and MW4 are connected and then connected to the control signal CTRL2b. The source terminals of switches MW3 and MW4 are connected and then connected to VDD.

[0051] Among them, the switching transistors MW1, MW2, MW3 and MW4 are all PMOS transistors.

[0052] Furthermore, the latch is connected to a clock signal CLKL, which is used to control the latch's reset mode and latching mode.

[0053] The working principle of the high-precision comparator based on bandwidth adjustment technology provided by this invention will be explained below.

[0054] Figure 7 This is a timing diagram of a high-precision comparator based on bandwidth adjustment technology provided in an embodiment of the present invention. In this embodiment, the signal input terminals include a positive input terminal IP and a negative input terminal IN, the output signal terminals include a positive output terminal OutP and a negative output terminal OutN, the offset calibration signals are CTRL1 and CTRL2, the control signals are CTRL3 and CTRL2b, the clock signal is CLKL, and the input current is I_var.

[0055] The comparator's operation is divided into an offset calibration stage and a comparator quantization stage. Specifically, as follows: Figure 7As shown, when the comparator is in the offset calibration stage, the clock signal CLKL is always high. First, CTRL1, CTRL2, and CTRL3 are high, and CTRL2b is low. The offset calibration module is in operation, MC1, MC2, and MC3 are turned on, and the offset calibration capacitors CC1 and CC2 store the offset voltage of the preamplifier. The bandwidth adjustment module is in a reset state, MW1 and MW2 are turned off, and MW3 and MW4 are turned on, thereby disconnecting the bandwidth adjustment capacitor CW from the offset calibration module and discharging the bandwidth adjustment capacitor CW until the top and bottom plates are at the same potential. Afterward, CTRL2 and CTRL3 are high, and CTRL1 and CTRL2b are low. MC1 and MC2 in the offset calibration module are turned off, and M When C3 is turned on, the offset voltage between MC1 and MC2 is eliminated by MC3, and the bandwidth adjustment module remains in the reset state. When the offset calibration stage ends, CTRL1 and CTRL2 are low, and CTRL3 and CTRL2b are high. The offset calibration module is in the hold state, MC1, MC2, and MC3 are turned off, and the offset voltage difference between offset calibration capacitors CC1 and CC2 is maintained. MW3 and MW4 in the bandwidth adjustment module are turned off. Then, the comparator quantization stage begins. CTRL1, CTRL2, and CTRL3 are low, and CTRL2b is high. The offset calibration module remains in the off state, and MW1 and MW2 in the bandwidth adjustment module are turned on. The bandwidth adjustment capacitor MW is connected to the output of the preamplifier to reduce the noise bandwidth and lower the noise.

[0056] When the comparator is in the quantization phase, CTRL1, CTRL2, and CTRL3 are always low, and CTRL2b is always high. CLKL is high, and the input signal is amplified by a five-stage amplifier before reaching the latch input. When CLKL toggles to low, the latch outputs the high / low levels of OutP and OutN based on the output voltage of the last stage amplifier.

[0057] As can be seen from the above embodiments, the beneficial effects of the present invention are as follows:

[0058] This invention provides a high-precision comparator based on bandwidth adjustment technology, comprising: a multi-stage amplifier, a multi-stage offset calibration module, a multi-stage bandwidth adjustment module, and a latch. The comparator reduces the equivalent offset and noise at the comparator input through the multi-stage amplifier, eliminates amplifier offset through the multi-stage offset calibration module, and adjusts the noise bandwidth of each amplifier stage through the multi-stage bandwidth adjustment module, thereby reducing the comparator's noise. Because the comparator utilizes timing control of each switching transistor in the bandwidth adjustment module, the influence of the bandwidth adjustment capacitor on the offset calibration process is avoided. Therefore, the high-precision comparator based on bandwidth adjustment technology provided by this invention can be applied to high-precision analog-to-digital converters, effectively reducing the equivalent offset and equivalent noise at the input.

[0059] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0060] The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0061] Although this application has been described herein in conjunction with various embodiments, other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in carrying out the claimed application by reviewing the accompanying drawings, the disclosure, and the appended claims.

[0062] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A multi-stage high-precision comparator based on bandwidth adjustment technology, characterized in that, include: Multistage amplifier, multistage offset calibration module, multistage bandwidth adjustment module and latch; The input terminal of the first-stage amplifier is connected to the signal input terminal, and the output terminal is connected to the first-stage offset calibration module. The input terminal of the nth-stage amplifier is connected to the output terminal of the previous-stage offset calibration module. The output terminal of the nth-stage amplifier is connected to the nth-stage offset calibration module via the (n-1)th-stage bandwidth adjustment module. The input terminal of the last-stage amplifier is connected to the output terminal of the previous-stage offset calibration module. The output terminal of the last-stage amplifier is sequentially connected to the last-stage bandwidth adjustment module and a latch. The latch is used to latch the analog potential output by the last-stage amplifier as a digital potential 1 or 0. Where n = 2, 3, ..., N-1, and N represents the number of stages of the multi-stage amplifier.

2. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 1, characterized in that, It also includes a bias circuit, which provides bias current for each stage of the amplifier and bias voltage for each stage of the offset calibration module.

3. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 2, characterized in that, It also includes a voltage source VDD. The signal input terminal includes a positive input terminal IP and a negative input terminal IN. The first stage amplifier includes a current source I_A, input transistors M1_A and M2_A, self-biased common gate transistors M3_A and M4_A, and load resistors R1_A, R2_A, R3_A, and R4_A. The input terminal of the first stage amplifier includes a positive input terminal VIP1 and a negative input terminal VIN1, and the output terminal includes a positive output terminal VOP1 and a negative output terminal VON1. The positive input terminal VIP1 and the negative input terminal VIN1 of the first stage amplifier are respectively connected to the positive input terminal IP and the negative input terminal IN. In this configuration, the positive terminal of current source I_A is connected to voltage source VDD, and its negative terminal is connected to the source terminals of M1_A and M2_A, respectively. The gate terminal of M1_A is connected to the positive input terminal VIP1, and its drain terminal is connected to the source terminal of M3_A. The gate terminal of M2_A is connected to the negative input terminal VIN1, and its drain terminal is connected to the source terminal of M4_A. The gate terminal of M3_A is connected to the negative terminal of load resistor R1_A and the positive terminal of R3_A, and its drain terminal is connected to the positive output terminal VOP1 and the positive terminal of load resistor R1_A. The gate terminal of M4_A is connected to the negative terminal of load resistor R2_A and the positive terminal of load resistor R4_A, and its drain terminal is connected to the negative output terminal VON1 and the positive terminal of load resistor R2_A. The negative terminals of load resistors R3_A and R4_A are both grounded.

4. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 3, characterized in that, The input transistors M1_A and M2_A, as well as the self-biased common gate transistors M3_A and M4_A, are PMOS transistors.

5. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 3, characterized in that, The nth stage amplifier has the same structure as the last stage amplifier. The nth stage amplifier includes a current source I_n, input transistors M1_n and M2_n, self-biased common gate transistors M3_n and M4_n, and load resistors R1_n, R2_n, R3_n, and R4_n. The input terminals of the nth stage amplifier include a positive input terminal VIPn and a negative input terminal VINn, and the output terminals include a positive output terminal VOPn and a negative output terminal VONn. The positive input terminal VIPn and the negative input terminal VINn of the nth stage amplifier are respectively connected to the positive output terminal and the negative output terminal of the (n-1)th stage offset calibration module. The positive terminals of R3_n and R4_n are connected to the voltage source VDD. The negative terminal of R3_n is connected to the positive terminal of R1_n and the gate terminal of M3_n. The negative terminal of R4_n is connected to the positive terminal of R2_n and the gate terminal of M4_n. The negative terminal of R1_n is connected to the positive output terminal VOPn and the drain terminal of M3_n. The negative terminal of R2_n is connected to the negative output terminal VONn and the drain terminal of M4_n. The source terminal of M3_n is connected to the drain terminal of M1_n. The source terminal of M4_n is connected to the drain terminal of M2_n. The gate terminal of M1_n is connected to the positive input terminal VIPn. The gate terminal of M2_n is connected to the negative input terminal VINn. The source terminals of M1_n and M2_n are connected together and connected to the positive terminal of the current source I_n. The negative terminal of I_n is grounded. The input transistors M1_n and M2_n, as well as the self-biased common gate transistors M3_n and M4_n, are NMOS transistors.

6. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 5, characterized in that, Each offset calibration module includes offset calibration capacitors: CC1, CC2 and offset calibration transistors: MC1, MC2, MC3; among which, The first plates of offset calibration capacitors CC1 and CC2 are connected to the positive and negative input terminals of the offset calibration module, respectively. The second plate of offset calibration capacitor CC1 is connected to the positive output terminal of the offset calibration module, the source terminal of offset calibration transistor MC1, and the source terminal of offset calibration transistor MC3. The second plate of offset calibration capacitor CC2 is connected to the negative output terminal of the offset calibration module, the source terminal of offset calibration transistor MC2, and the drain terminal of offset calibration transistor MC3. The gate terminal of offset calibration transistor MC1 is connected to the gate terminal of offset calibration transistor MC2 and connected to the control signal CTRL1. The drain terminal of offset calibration transistor MC1 is connected to the drain terminal of offset calibration transistor MC2 and connected to the bias voltage Vcm. The gate terminal of offset calibration transistor MC3 is connected to the control signal CTRL2. Offset calibration transistors MC1, MC2, and MC3 are all NMOS transistors.

7. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 6, characterized in that, The comparator's operation includes an offset calibration stage and a comparator quantization stage; wherein, the nth-stage offset calibration module is in the working state during the offset calibration stage to store the offset voltage of the nth-stage amplifier, and the nth-stage offset calibration module is in the holding state during the comparator quantization stage to eliminate the amplifier's offset using the stored offset voltage.

8. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 3, characterized in that, Each level of the bandwidth adjustment module includes a bandwidth adjustment capacitor CW and switching transistors: MW1, MW2, MW3, and MW4; among which, The positive input ports of each bandwidth adjustment module are connected to their own positive output ports and then to the source of switch MW1. The negative input ports of each bandwidth adjustment module are connected to their own negative output ports and then to the source of switch MW2. The gate terminals of switches MW1 and MW2 are connected to the control signal CTRL3. The drain terminal of switch MW1 is connected to the positive terminal of the bandwidth adjustment point capacitor CW and the drain terminal of MW3. The drain terminal of switch MW2 is connected to the negative terminal of the bandwidth adjustment capacitor CW and the drain terminal of switch MW4. The gate terminals of switches MW3 and MW4 are connected and then connected to the control signal CTRL2b. The source terminals of switches MW3 and MW4 are connected and then connected to VDD.

9. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 8, characterized in that, The switching transistors MW1, MW2, MW3, and MW4 are all PMOS transistors.

10. The multi-stage high-precision comparator based on bandwidth adjustment technology according to claim 1, characterized in that, The latch is connected to a clock signal CLKL, which is used to control the latch's reset mode and latching mode.

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