A port state detection method, device, apparatus and storage medium

Abstract

The application relates to the communication field and discloses a port state detection method, a device, equipment and a storage medium. The method comprises the following steps: in a first scanning period, reading a first port state of a physical layer chip to be a connection state, then reading first state information and a first interrupt state register, and clearing an interrupt flag of the first interrupt state register; in a second scanning period, reading a second port state of the physical layer chip to be a connection state, then reading a second interrupt state register, if it is determined that the second interrupt state register is set, then reading second state information, and if the second state information is inconsistent with the first state information, then generating configuration information of a data link layer chip according to the second state information. According to the application, the port state and the state information of the physical layer chip are read in two scanning periods, so that a missed port event in a scanning process is screened out, and link abnormal working is avoided.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a method, apparatus, device, and storage medium for detecting port status. Background Technology

[0002] In network products such as switches and routers, the MAC controller is configured by reading the status information of the physical layer chip (PHY chip) to ensure the normal operation of the link. The methods for reading the PHY chip's status information include interrupts and polling. The interrupt method requires connecting the PHY chip's interrupt pin to the CPU's I / O port; therefore, polling is generally used to read the status information. The polling method involves scanning the PHY chip's ports at specified intervals to read the PHY chip's status register, thereby determining the current status of the PHY chip. When a change in the PHY chip's connection status is detected, the MAC controller is configured accordingly based on the current PHY chip status.

[0003] However, when there are many PHY chips or the port scanning interval is unreasonable, polling mode may miss port events. Therefore, to avoid the above problems, the polling interval is generally reduced. However, when there are many ports and the CPU is busy, it is difficult to guarantee that port events will not be missed. Summary of the Invention

[0004] In view of this, in order to solve the problems existing in the prior art, this application provides a port status detection method, apparatus, device and storage medium.

[0005] Firstly, this application provides a port status detection method, including:

[0006] Within a preset first scan cycle, the first port status of the physical layer chip is read. If the first port status is connected, the current first status information of the physical layer chip and the first interrupt status register corresponding to the physical layer chip are read, and the interrupt flag of the first interrupt status register is cleared.

[0007] The second port status of the physical layer chip is read within the preset second scan cycle. If the second port status is connected, the second interrupt status register corresponding to the physical layer chip is read, and it is determined whether the second interrupt status register is set.

[0008] If the second interrupt status register is set, the current second status information of the physical layer chip is read, and the second status information is compared with the first status information. If the comparison is inconsistent, the configuration information of the data link layer chip is generated based on the second status information.

[0009] In an optional implementation, the first port status of the physical layer chip is read within a preset first scan cycle. If the first port status is in an open state, the third interrupt status register corresponding to the physical layer chip is read, and the interrupt flag of the third interrupt status register is cleared.

[0010] In an optional implementation, the second port status of the physical layer chip is read within a preset second scan cycle. If the second port status is disconnected, the fourth interrupt status register corresponding to the physical layer chip is read, and the interrupt flag of the fourth interrupt status register is cleared.

[0011] In an optional implementation, if it is determined that the second interrupt status register is not set, the subsequent processing flow is not executed.

[0012] In an optional implementation, if the second status information matches the first status information, then no subsequent processing procedure is executed.

[0013] In an optional implementation, the first state information or the second state information includes the connection status, port rate, port duplex, and port flow control information of the physical layer chip.

[0014] In an optional implementation, comparing the second state information with the first state information includes:

[0015] The first interrupt status register corresponding to the first status information is compared with the second interrupt status register corresponding to the second status information.

[0016] Secondly, this application provides a port status detection device, comprising:

[0017] The first scanning module is used to read the first port status of the physical layer chip within a preset first scanning cycle. If the first port status is a connected state, the module reads the current first status information of the physical layer chip and the first interrupt status register corresponding to the physical layer chip, and clears the interrupt flag.

[0018] The second scanning module is used to read the second port status of the physical layer chip within a preset second scanning cycle. If the second port status is a connected state, it reads the second interrupt status register corresponding to the physical layer chip and determines whether the second interrupt status register is set.

[0019] The comparison module is used to read the current second status information of the physical layer chip if it is determined that the second interrupt status register is set, compare the second status information with the first status information, and generate configuration information of the data link layer chip based on the second status information if the comparison is inconsistent.

[0020] Thirdly, this application provides a computer device, the computer device including a memory and at least one processor, the memory storing a computer program, and the processor executing the computer program to implement the aforementioned port status detection method.

[0021] Fourthly, this application provides a computer storage medium storing a computer program, which, when executed, implements the aforementioned port status detection method.

[0022] The embodiments of this application have the following beneficial effects:

[0023] This application provides a port status detection method, which includes: reading the first port status of a physical layer chip within a preset first scan cycle; if the first port status is connected, reading the current first status information of the physical layer chip and the corresponding first interrupt status register of the physical layer chip, and clearing the interrupt flag of the first interrupt status register; reading the second port status of the physical layer chip within a preset second scan cycle; if the second port status is connected, reading the corresponding second interrupt status register of the physical layer chip, and determining whether the second interrupt status register is set; if the second interrupt status register is determined to be set, reading the current second status information of the physical layer chip, comparing the second status information with the first status information; if the comparison is inconsistent, generating configuration information of the data link layer chip based on the second status information. This application, by reading the port status of the physical layer chip and obtaining status information within two scan cycles, filters out port events missed during the scanning process, facilitating timely subsequent processing, avoiding link malfunctions, and improving the security and reliability of link operation. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. In the various drawings, similar components are numbered similarly.

[0025] Figure 1 A schematic diagram of the first embodiment of the port status detection method in this application is shown;

[0026] Figure 2A schematic diagram of a second embodiment of the port status detection method in this application is shown;

[0027] Figure 3 A schematic diagram of a third embodiment of the port status detection method in this application is shown;

[0028] Figure 4 A schematic diagram of a port status detection device in an embodiment of this application is shown. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0030] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0032] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0033] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0034] Currently, network interface cards (NICs) operate at the last two layers of the Open Systems Interconnection (OSI) model: the physical layer and the data link layer. The physical layer defines the electrical and optical signals, line states, clock references, data encoding, and circuitry required for data transmission and reception, and provides a standard interface to data link layer devices. The chip at the physical layer is called the PHY chip. The data link layer provides functions such as addressing mechanisms, data frame construction, data error checking, transmission control, and providing a standard data interface to the network layer. The chip at the data link layer in an Ethernet NIC is called the MAC controller.

[0035] Furthermore, the MAC controller and PHY chip are connected via the IEEE-defined standard MII / GigaMII (Media Independent Interface). This interface is defined by IEEE, and the MII interface is responsible for sending and receiving data between the MAC controller and the PHY chip. The management and control of the PHY chip is achieved using the SMI (Serial Management Interface), which reads and writes the PHY chip's internal registers to read the PHY chip's status and manage and control it.

[0036] In network products such as switches and routers, the configuration of the MAC controller is completed by reading the status information of the PHY chip to ensure the normal operation of the link. This status information specifically includes LINK status, speed, duplex, flow control and other information.

[0037] Furthermore, the methods for reading the PHY chip's status information include interrupts and polling. The interrupt method requires connecting the PHY chip's interrupt pin to the CPU's I / O port; therefore, polling is generally used to read the status information. The polling method involves scanning the PHY chip's ports at specified intervals to read the PHY chip's status register, thereby determining the PHY chip's current status. When a change in the PHY chip's connection status is detected, the MAC controller is configured accordingly based on the current PHY chip status.

[0038] However, when there are many PHY chips or the port scan interval is unreasonable, polling mode may miss port events. Specifically, in one scan cycle, the total time consumed is the sum of the scan time and the scan interval. Suppose that during a scan interval, port A was originally in a connected state, suddenly disconnected and immediately returned to a connected state. Then, the port scan will miss the port disconnection event. If the current connected state information of the PHY chip corresponding to port A is completely consistent with the previous connected state information, then the link can work normally. If the current connected state information is inconsistent with the previous connected state information, for example, the speed changes from 1000M to 100M, but the MAC controller is still working at 1000M speed, it will lead to the link being down or receiving a large number of error messages.

[0039] Therefore, in order to avoid the above problems, the polling interval is generally reduced. However, when there are many ports and the CPU is busy, it is difficult to ensure that port events are not missed.

[0040] Based on this, this application provides a port status detection method. By reading the port status of the physical layer chip and obtaining status information in two scanning cycles, the method can determine the status changes of the physical layer chip, filter out port events missed during the scanning process, facilitate timely subsequent processing, avoid link malfunctions, and improve the security and reliability of link operation.

[0041] Please refer to Figure 1 The method will now be explained in detail.

[0042] S10: Read the first port status of the physical layer chip within the preset first scan cycle. If the first port status is connected, read the current first status information of the physical layer chip and the first interrupt status register corresponding to the physical layer chip, and clear the interrupt flag of the first interrupt status register.

[0043] As an example, the current state of the first port of the physical layer chip (i.e., the PHY chip) is scanned within a preset first scan cycle, which means reading the register value of the PHY chip's status register to determine the current state of the PHY chip. The specific time range of this first scan cycle can be set according to actual needs and is not limited here.

[0044] It is important to note that the PHY chip contains multiple registers. The port status of the PHY chip is used to indicate whether communication with the device connected to the PHY chip is possible through that port. This port status can be reflected by the register value of the PHY chip's status register.

[0045] Specifically, the changes in the PHY chip port state correspond to the UP / DOWN events (i.e., port events) of the PHY chip port. UP (i.e., link up state) means that the device connected to the PHY chip can communicate through the port; DOWN (i.e., link down state) means that the device connected to the PHY chip cannot communicate through the port.

[0046] The PHY chip port status changes can be scanned by using an integrated chip in the switch that carries the SMI protocol. This integrated chip can be a chip from Broadcom, such as the BCM56340.

[0047] Furthermore, if the scan reveals that the first port status is in a connected state (i.e., link-up state), then the current first state information of the PHY chip and the interrupt status register of the PHY chip are read, and this interrupt status register is recorded as the first interrupt status register. The first state information includes the physical layer chip's connection status, port speed, port duplex, port flow control information, etc.; this first interrupt status register is the register that records changes in the PHY chip's state. Then, all interrupt flags in the first interrupt status register are cleared; subsequently, the register value of the first interrupt status register is 0, thus achieving register clearing.

[0048] In one embodiment, the first port state of the physical layer chip is read within a preset first scan cycle. If the first port state is disconnected, the corresponding interrupt status register of the physical layer chip is read and used as the third interrupt status register. The interrupt flag of the third interrupt status register is then cleared, i.e., the register is read. Subsequently, it is further determined whether the state of the PHY chip has changed. Further, if the second port state of the physical layer chip read in the second scan cycle is disconnected and the corresponding read interrupt status register is set, it indicates that the port state of the physical layer chip has changed, i.e., there is a port event omission. Conversely, if the second port state of the physical layer chip read in the second scan cycle is connected and the corresponding read interrupt status register is set, the port event will be recorded in time when the port state changes, and no port event omission occurs in this case.

[0049] S20: Read the second port status of the physical layer chip within the preset second scan cycle. If the second port status is connected, read the second interrupt status register corresponding to the physical layer chip and determine whether the second interrupt status register is set.

[0050] Then, within the preset second scan cycle, the status of the second port of the PHY chip is read. If the second port status is connected at this time, the current interrupt status register of the PHY chip is read and used as the second interrupt status register. Then, it is determined whether the second interrupt status register is set, that is, whether the register value of the second interrupt status register is 1.

[0051] As can be understood, setting a bit is a way to map the input to the output by forcibly changing the input from an external source. Setting a bit variable means setting it to "1". Therefore, setting a bit refers to the process of changing a switch or flag bit in a circuit or system from 0 to 1, that is, changing the value of the corresponding bit to a valid value.

[0052] S30: If it is determined that the second interrupt status register is set, the current second status information of the physical layer chip is read, and the second status information is compared with the first status information. If the comparison is inconsistent, the configuration information of the data link layer chip is generated according to the second status information.

[0053] If the second interrupt status register is set, it indicates that the PHY chip obtained in the current scan has changed compared to the PHY chip obtained in the previous scan, meaning that a port event was missed. In other words, after clearing the register during the first scan cycle, the value of this interrupt status register is set during the second scan cycle, indicating that the state of the scanned PHY chip has changed during the scanning process of both the first and second scan cycles.

[0054] Then, the current second state information of the PHY chip is read, and then the recorded second state information is compared with the first state information. Based on the comparison result, it is determined whether to configure the MAC controller accordingly.

[0055] Furthermore, the second status information is compared with the first status information; that is, the first interrupt status register corresponding to the first status information is compared with the second interrupt status register corresponding to the second status information. This can be understood as determining whether the first interrupt status register and the second interrupt status register are consistent.

[0056] If the first state information does not match the second state information, the configuration information of the data link layer chip is generated based on the second state information. That is, the MAC controller is configured accordingly based on the current state information of the PHY chip.

[0057] S40: If it is determined that the second interrupt status register is not set, the subsequent processing flow will not be executed.

[0058] Furthermore, if it is determined that the second interrupt status register is not set, it means that the port status scanned and read by the PHY chip in the first scan cycle and the second scan cycle has not changed, which means that there is no port event omission, and therefore, the subsequent processing flow is not executed.

[0059] In one implementation, such as Figure 2 As shown, the embodiments of this application also include the following steps:

[0060] S50: Read the second port status of the physical layer chip within the preset second scan cycle. If the second port status is disconnected, read the fourth interrupt status register corresponding to the physical layer chip and clear the interrupt flag of the fourth interrupt status register.

[0061] That is, the current port status of the PHY chip is read within a preset second scan cycle to determine the current connection status of the PHY chip. Further, if the second port status is disconnected, it means that the port status of the PHY chip has changed (in this case, the port event can be detected in time and there is no port event omission), and then the interrupt status register of the PHY chip is read and used as the fourth interrupt status register, and the interrupt flag of the fourth interrupt status register is cleared.

[0062] In one implementation, such as Figure 3 As shown, the embodiments of this application also include the following steps:

[0063] S60, if it is determined that the second interrupt status register is set, then read the current second status information of the physical layer chip, compare the second status information with the first status information, and if the second status information matches the first status information, then do not execute the subsequent processing flow.

[0064] It is understandable that if the second status information matches the first status information when it is determined that a port event is missing, then there is no need to execute the subsequent processing procedure.

[0065] In other words, if the PHY chip status information detected in two scan cycles is inconsistent when a port event is found to be missing, the MAC controller needs to be configured according to the current status information of the PHY chip; otherwise, if the status information corresponding to the two scan cycles is consistent, the MAC controller does not need to be configured.

[0066] This application embodiment determines whether the port status of the physical layer chip has changed by comparing the port status and status information of the physical layer chip scanned in two scanning cycles, and then determines whether there is any port event omission. Thus, without increasing the scanning frequency, port event omission can be accurately screened out, avoiding link malfunctions and ensuring the idle rate of the communication system.

[0067] Please see Figure 4 This application provides a port status detection device, which includes:

[0068] The first scanning module 110 is used to read the first port status of the physical layer chip within a preset first scanning cycle. If the first port status is a connected state, it reads the current first status information of the physical layer chip and the first interrupt status register corresponding to the physical layer chip, and clears the interrupt flag.

[0069] The second scanning module 120 is used to read the second port status of the physical layer chip within a preset second scanning cycle. If the second port status is a connected state, it reads the second interrupt status register corresponding to the physical layer chip and determines whether the second interrupt status register is set.

[0070] The comparison module 130 is used to read the current second status information of the physical layer chip if it is determined that the second interrupt status register is set, compare the second status information with the first status information, and generate configuration information of the data link layer chip based on the second status information if the comparison is inconsistent.

[0071] It is understood that the port status detection device in this embodiment corresponds to the port status detection method in the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0072] This application also provides a computer device, which may be, but is not limited to, a desktop computer, a laptop, a smartphone, a tablet, etc. Its form is not limited, mainly depending on whether it needs to support the interface display function of a browser webpage, etc. Exemplarily, the computer device includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to cause the computer device to perform the port status detection method of this application. The method includes: reading the first port status of a physical layer chip within a preset first scan cycle; if the first port status is connected, reading the current first status information of the physical layer chip and the corresponding first interrupt status register of the physical layer chip, and clearing the interrupt flag of the first interrupt status register; reading the second port status of the physical layer chip within a preset second scan cycle; if the second port status is connected, checking the corresponding second interrupt status register of the physical layer chip and determining whether the second interrupt status register is set; if the second interrupt status register is set, reading the current second status information of the physical layer chip, comparing the second status information with the first status information; if the comparison is inconsistent, generating configuration information of the data link layer chip based on the second status information; thereby, by reading the port status of the physical layer chip and obtaining status information within two scan cycles, port events missed during the scanning process are filtered out, facilitating timely subsequent processing, avoiding link malfunctions, and improving the security and reliability of link operation.

[0073] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0074] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory stores computer programs, and the processor, upon receiving execution instructions, can execute the computer programs accordingly.

[0075] Furthermore, this application also provides a computer storage medium for storing the computer program used in the aforementioned computer device. When the computer program is executed on a processor, it implements the port status detection method of the above embodiments. This method includes: reading the first port status of a physical layer chip within a preset first scan cycle; if the first port status is connected, reading the current first status information of the physical layer chip and the corresponding first interrupt status register of the physical layer chip, and clearing the interrupt flag of the first interrupt status register; reading the second port status of the physical layer chip within a preset second scan cycle; if the second port status is connected, checking the corresponding second interrupt status register of the physical layer chip and determining whether the second interrupt status register is set; if the second interrupt status register is set, reading the current second status information of the physical layer chip, comparing the second status information with the first status information, and if the comparison is inconsistent, generating configuration information for the data link layer chip based on the second status information.

[0076] It is understood that the optional methods in the port status detection method of the above embodiments are also applicable to this embodiment, so they will not be described again here.

[0077] The aforementioned computer storage medium can be a non-volatile storage medium or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0078] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0079] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0080] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0081] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A port status detection method, characterized in that, include: Within a preset first scan cycle, the first port status of the physical layer chip is read. If the first port status is connected, the current first status information of the physical layer chip and the interrupt status register corresponding to the physical layer chip are read. The interrupt status register is recorded as the first interrupt status register, and the interrupt flag of the first interrupt status register is cleared. The second port status of the physical layer chip is read within the preset second scan cycle. If the second port status is connected, the interrupt status register corresponding to the physical layer chip is read, the interrupt status register is used as the second interrupt status register, and it is determined whether the second interrupt status register is set. The first and second status information include the connection status, port rate, port duplex, and port flow control information of the physical layer chip. If the second interrupt status register is set, the current second status information of the physical layer chip is read, and the second status information is compared with the first status information. If the comparison is inconsistent, the configuration information of the data link layer chip is generated based on the second status information.

2. The port status detection method according to claim 1, characterized in that, Within a preset first scan cycle, the first port status of the physical layer chip is read. If the first port status is disconnected, the interrupt status register corresponding to the physical layer chip is read, the interrupt status register is used as the third interrupt status register, and the interrupt flag of the third interrupt status register is cleared.

3. The port status detection method according to claim 1, characterized in that, The second port status of the physical layer chip is read within the preset second scan cycle. If the second port status is disconnected, the interrupt status register corresponding to the physical layer chip is read, the interrupt status register is used as the fourth interrupt status register, and the interrupt flag of the fourth interrupt status register is cleared.

4. The port status detection method according to claim 1, characterized in that, If it is determined that the second interrupt status register is not set, the subsequent processing flow will not be executed.

5. The port status detection method according to claim 1, characterized in that, If the second status information matches the first status information, then the subsequent processing procedure will not be executed.

6. The port status detection method according to claim 1, characterized in that, The step of comparing the second state information with the first state information includes: The first interrupt status register corresponding to the first status information is compared with the second interrupt status register corresponding to the second status information.

7. A port status detection device, characterized in that, include: The first scanning module is used to read the first port status of the physical layer chip within a preset first scanning cycle. If the first port status is a connected state, the module reads the current first status information of the physical layer chip and the interrupt status register corresponding to the physical layer chip, records the interrupt status register as the first interrupt status register, and clears the interrupt flag. The second scanning module is used to read the second port status of the physical layer chip within a preset second scanning cycle. If the second port status is a connected state, the module reads the interrupt status register corresponding to the physical layer chip, uses the interrupt status register as the second interrupt status register, and determines whether the second interrupt status register is set. The first and second status information include the connection status, port rate, port duplex, and port flow control information of the physical layer chip. The comparison module is used to read the current second status information of the physical layer chip if it is determined that the second interrupt status register is set, compare the second status information with the first status information, and generate configuration information of the data link layer chip based on the second status information if the comparison is inconsistent.

8. A computer device, characterized in that, The computer device includes a memory and at least one processor, the memory storing a computer program, and the processor executing the computer program to implement the port status detection method according to any one of claims 1-6.

9. A computer storage medium, characterized in that, It stores a computer program, which, when executed, implements the port status detection method according to any one of claims 1-6.

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