Electronic device and method of transmitting video data and audio data

Abstract

Various embodiments of the present invention relate to an electronic device and a method of transmitting video data and audio data. The electronic device includes a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives audio data and first video data. The signal processing unit generates second video data and a pixel clock signal for playing the second video data according to the first video data. The transmitting unit outputs the second video data, the audio data, the pixel clock signal, and a period timestamp to a receiving end. The audio timing unit includes a reference signal generator and a controller. The reference signal generator generates an internal reference signal. The controller adjusts a frequency of the internal reference signal according to a speed of the audio data, and generates the period timestamp according to the internal reference signal and the pixel clock signal so that the receiving end generates an audio clock signal for playing the audio data according to the pixel clock signal and the period timestamp.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device for transmitting video and audio data. Background Technology

[0002] High Definition Multimedia Interface (HDMI) is a common display interface today. According to the HDMI specification, each frame of video data is transmitted sequentially, with specific gaps between each frame and each line. These gaps, not used for video data transmission, are used to transmit audio data. Because the transmitting end of the HDMI interface only sends the pixel clock signal used for video data playback to the receiving end, the receiving end must manually regenerate the audio clock signal needed for playing the audio data based on the pixel clock signal.

[0003] According to the recommendations of the High Definition Multimedia Interface (HDMI) specification, the receiver can use frequency dividers and frequency multipliers to adjust the frequency of the pixel signals to generate an audio clock signal. However, in this case, the circuitry of the frequency divider and frequency multiplier is more complex, thus increasing the circuit area of ​​the receiver. Furthermore, if errors occur during the reconstruction of the audio clock signal, popping sounds may occur at the receiver. Therefore, how to effectively reconstruct the audio clock signal and avoid the continuous accumulation of errors in the audio clock signal to ensure the quality of audio-visual presentation has become a problem to be solved in this field. Summary of the Invention

[0004] One embodiment of this disclosure provides an electronic device comprising a receiving unit, a signal processing unit, a transmitting unit, and an audio timing unit. The receiving unit receives multiple audio data and multiple first video data. The signal processing unit generates multiple second video data based on the first video data and generates a pixel clock signal for playing the second video data. The transmitting unit outputs the second video data, the audio data, the pixel clock signal, and a cycle time stamp (CTS) to a receiving end. The value obtained by dividing the frequency of the pixel clock signal by the cycle time stamp is equal to the value obtained by dividing the frequency of an audio reference clock signal used by the receiving end for playing the audio data by a preset multiple. The audio timing unit includes a reference signal generator and a controller. The reference signal generator generates an internal reference signal. The controller adjusts the frequency of the internal reference signal according to the speed at which the audio data is transmitted, and generates the cycle time stamp according to the preset multiple, the internal reference signal, and the pixel clock signal.

[0005] Another embodiment of this disclosure provides a method for transmitting video data and audio data. The method includes receiving multiple audio data and multiple first video data; generating multiple second video data and a pixel clock signal for playing the second video data based on the first video data; generating an internal reference signal; adjusting the frequency of the internal reference signal according to the speed at which the audio data is transmitted; generating a periodic timestamp based on a preset multiple, the internal reference signal, and the pixel clock signal; and outputting the second video data, the audio data, the pixel clock signal, and the periodic timestamp to a receiving end. The value obtained by dividing the frequency of the pixel clock signal by the periodic timestamp is equal to the value obtained by dividing the frequency of the audio reference clock signal used by the receiving end for playing the audio data by the preset multiple.

[0006] The electronic device and method for transmitting video and audio data provided in the embodiments of this disclosure can generate an internal reference signal with the same frequency as the audio clock signal used to play the audio data based on the reception status of the audio data, and can generate a periodic timestamp corresponding to the pixel clock signal of the output video data based on the internal reference signal. Therefore, when the receiving end receives the video data output by the electronic device, it can accurately regenerate the audio clock signal based on the periodic timestamp and the pixel clock signal of the video data. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of an embodiment of the data transmission system disclosed herein.

[0008] Figure 2 This is a schematic diagram of another embodiment of the data transmission system disclosed herein.

[0009] Figure 3 This is a schematic diagram of an embodiment of the electronic device disclosed herein.

[0010] Figure 4 This is a flowchart illustrating an embodiment of the method for transmitting video and audio data disclosed herein.

[0011] Figure 5 This is a schematic diagram of another embodiment of the electronic device disclosed herein.

[0012] Figure 6 This is a public document Figure 5 A schematic diagram of a reference signal generator producing an internal reference signal. Detailed Implementation

[0013] Figure 1This is a schematic diagram of an embodiment of the data transmission system 10 disclosed herein. The data transmission system 10 includes a transmitting end TX and a receiving end RX, and the transmitting end TX can be coupled to the receiving end RX via a High Definition Multimedia Interface (HDMI). Figure 1 As shown, the transmitting end TX can transmit multiple video data VD1 and multiple audio data AD1 to the receiving end RX so that the receiving end RX can play the audio and video content of the video data VD1 and audio data AD1.

[0014] When transmitting data via HDMI, the transmitting end (TX) sends not only video data VD1 to the receiving end (RX), but also the pixel clock signal CLK_TMDS1 used to play video data VD1, enabling the receiving end (RX) to correctly play video data VD1. However, during HDMI transmission, the transmitting end (TX) does not separately send the audio clock signal used to play audio data AD1 to the receiving end (RX). The receiving end (RX) typically reconstructs the audio clock signal CLK_AUDIO for playing audio data AD1 from the pixel clock signal CLK_TMDS1. To enable the receiving end (RX) to reconstruct the audio clock signal CLK_AUDIO, the transmitting end (TX) separately sends a cycle time stamp (CTS1) associated with the pixel clock signal CLK_TMDS1 and the audio clock signal CLK_AUDIO, along with a preset multiplier N, to the receiving end (RX). According to the HDMI specification, the frequency f of the audio clock signal CLK_AUDIO is... CLK_A The frequency f of the pixel clock signal CLK_TMDS1 CLKT The relationship is shown in equation (1).

[0015]

[0016] In this way, according to equation (1), the receiving end RX can perform frequency division and frequency multiplication on the pixel clock signal CLK_TMDS1 after receiving the pixel clock signal CLK_TMDS1, using the value of the period timestamp CTS1 and the multiplier N, thereby generating the audio clock signal CLK_AUDIO for playing the audio data AD1.

[0017] However, frequency division and multiplication operations require more complex frequency dividers and multipliers, thus increasing the circuit area required at the receiver RX. Furthermore, in some applications, other electronic devices for buffering or signal processing may be placed between the transmitter TX and transmitter RX. In this case, if the pixel clock signal generated by the electronic device has a slight frequency error compared to the pixel clock signal CLK_TMDS1 generated by the transmitter TX, the accumulated error may cause a popping sound at the receiver RX.

[0018] Figure 2 This is a schematic diagram of an embodiment of the data transmission system 20 disclosed herein. In this embodiment, the data transmission system 20 may include a transmitting end TX, an electronic device 200, and a receiving end RX, and the electronic device 200 may be coupled to the transmitting end TX and the receiving end RX via a high-definition multimedia interface. The electronic device 200 may receive multiple video data VD1 and multiple audio data AD1 transmitted from the transmitting end TX, and may process or buffer the video data VD1, and then transmit the audio data AD1 and the processed or buffered video data VD2 to the receiving end RX. For example, the transmitting end TX may be a computer, a set-top box, a game console, or other audio-visual device used to provide audio and video data, the receiving end RX may be a television or monitor used to display images and play audio, and the electronic device 200 may be an expansion port (docking) providing buffering function or a processor that can improve image quality or clarity.

[0019] In this embodiment, the transmitting end TX can send video data VD1 and a pixel clock signal CLK_TMDS1 for playing video data VD1 to the electronic device 200. After processing or buffering the video data VD1, the electronic device 200 can generate video data VD2, and when sending the video data VD2 to the receiving end RX, it also sends the pixel clock signal CLK_TMDS2 for playing video data VD2 to the receiving end RX.

[0020] In addition, as mentioned above, during the transmission using HDMI, in order for the circuit receiving video data VD1 and audio data AD1 to regenerate the audio clock signal CLK_AUDIO based on the pixel clock signal CLK_TMDS1, the transmitting end TX also transmits a cycle time stamp CTS1 and a preset multiple N1 to the electronic device 200.

[0021] In some applications, the pixel clock signal CLK_TMDS2 generated by the electronic device 200 has substantially the same frequency as the pixel clock signal CLK_TMDS1 generated by the transmitting end TX. Therefore, the electronic device 200 can directly transmit the periodic timestamp CTS1 and the preset multiplier N1 transmitted by the transmitting end TX to the receiving end RX. In this way, according to the above formula (1), after receiving the pixel clock signal CLK_TMDS2, the receiving end RX can use the value of the periodic timestamp CTS1 and the preset multiplier N1 to perform frequency division and frequency multiplication operations on the pixel clock signal CLK_TMDS2, thereby generating the audio clock signal CLK_AUDIO for playing the audio data AD1. However, if the error of the electronic components in the electronic device 200 causes the actual frequency of the pixel clock signal CLK_TMDS2 to be not exactly the same as the frequency of the pixel clock signal CLK_TMDS1, then when the receiving end RX regenerates the audio clock signal CLK_AUDIO according to the pixel clock signal CLK_TMDS2, a popping sound may occur after the error accumulates for a period of time.

[0022] To solve this problem, the electronic device 200 of this disclosure can first generate an internal reference signal SIG with the same frequency as the audio clock signal CLK_AUDIO. AR It allows users to set a preset multiplier N2, and then, based on the preset multiplier N2 and the internal reference signal SIG, it will generate a value. AR The periodic timestamp CTS2 is calculated based on the multiple relationship between the pixel clock signal CLK_TMDS2 and the pixel clock signal CLK_TMDS2. When the electronic device 200 sends video data VD2 and audio data AD1 to the receiving end RX, the electronic device 200 can also transmit the pixel clock signal CLK_TMDS2, the periodic timestamp CTS2, and the preset multiple N2 to the receiving end RX at the same time. Since the relationship between the audio clock signal CLK_AUDIO and the pixel clock signal CLK_TMDS2, the periodic timestamp CTS2, and the preset multiple N2 is still as shown in equation (1), the receiving end RX can reconstruct the audio clock signal CLK_AUDIO based on the periodic timestamp CTS2 and the preset multiple N2 when it receives the pixel clock signal CLK_TMDS2. In some embodiments, the preset multiple N2 of the electronic device 200 can be the same as the preset multiple N1 of the transmitting end TX, but it can also be different.

[0023] Furthermore, in some embodiments, the electronic device 200 can perform image processing on the video data VD1 to generate video data VD2 with higher clarity. In this case, the frequency of the pixel clock signal CLK_TMDS2 used to play the video data VD2 may be higher than the frequency of the pixel clock signal CLK_TMDS1 used to play the video data VD1 received by the transmitting end TX. However, since the electronic device 200 can regenerate the corresponding periodic timestamp CTS2 based on the pixel clock signal CLK_TMDS2, even if the frequency of the pixel clock signal CLK_TMDS2 is different from the frequency of the pixel clock signal CLK_TMDS1, the receiving end RX can still reconstruct the correct audio clock signal CLK_AUDIO based on the pixel clock signal CLK_TMDS2 and periodic timestamp CTS2 transmitted by the electronic device 200.

[0024] Figure 3 This is a schematic diagram of an embodiment of the electronic device 200 disclosed herein. For example... Figure 3 As shown, the electronic device 200 may include a receiving unit 210, a signal processing unit 220, a transmitting unit 230, and an audio timing unit 240. Figure 4 This is a flowchart illustrating an embodiment of the method 300 for transmitting video and audio data disclosed herein. In this embodiment, method 300 may include steps S310 to S360, and method 300 may be executed by electronic device 200.

[0025] In step S310, the receiving unit 210 receives multiple audio data AD1 and multiple video data VD1. Next, in step S320, the signal processing unit 220 generates multiple second video data VD2 and a pixel clock signal CLK_TMDS2 for playing the second video data VD2 based on the multiple video data VD1. In steps S330 to S350, the audio timing unit 240 generates a periodic timestamp CTS2 corresponding to the pixel clock signal CLK_TMDS2, enabling the receiving end RX to regenerate the audio clock signal CLK_AUDIO based on the pixel clock signal CLK_TMDS2 and the periodic timestamp CTS2.

[0026] like Figure 3 As shown, the audio timing unit 240 may include a reference signal generator 242 and a controller 244. In step S330, the reference signal generator 242 may generate an internal reference signal SIG. AR In this embodiment, the internal reference signal SIG ARThe frequency is the frequency of the audio clock signal CLK_AUDIO estimated by the electronic device 200. Generally, although the frequency of the audio clock signal CLK_AUDIO used to play audio data AD1 may vary slightly over time, it will mainly revolve around a specific frequency and increase or decrease around that center frequency. Therefore, in some embodiments, the reference signal generator 242 may set the internal reference signal SIG in step S330 according to the possible center frequency of the audio clock signal CLK_AUDIO. AR The frequency. For example, if the center frequency of the audio clock signal CLK_AUDIO is estimated to be 4.096MHz, the controller 244 can cause the reference signal generator 242 to generate an internal reference signal SIG with a frequency of 4.096MHz. AR In some embodiments, the reference signal generator 242 may include a phase-locked loop (PLL) and may utilize the PLL to generate an internal reference signal SIG with the desired frequency. AR .

[0027] After generating the internal reference signal SIG AR Subsequently, the controller 244 can further adjust the internal reference signal SIG in step S340 based on the received audio data AD1. AR The frequency of the internal reference signal SIG AR The frequency can be closer to the appropriate frequency of the audio clock signal CLK_AUDIO. Regarding how to adjust the internal reference signal SIG in step S340... AR The method for determining the frequency will be explained in detail in later paragraphs.

[0028] In this embodiment, the transmitting end TX generates multiple audio data AD1s based on a fixed sampling rate, and the appropriate frequency of the audio clock signal CLK_AUDIO is the product of this sampling frequency and a sampling multiple K, where K is a positive integer. In this case, the receiving end RX plays a corresponding segment of audio data AD1 every K cycles of the audio clock signal CLK_AUDIO. For example, the value of K can be 128, meaning the frequency of the audio clock signal CLK_AUDIO can be, for example, but not limited to, 128 times the sampling frequency of the audio data AD1. In this case, the receiving end RX plays a segment of audio data AD1 every K cycles (e.g., 128 cycles) of the audio clock signal CLK_AUDIO (in a two-channel application, since there is an audio data segment for each channel simultaneously, the receiving end RX plays two segments of audio data AD1 every 128 cycles of the audio clock signal CLK_AUDIO, i.e., one segment for each channel).

[0029] Although the transmitting end TX generates audio data AD1 based on a fixed sampling rate, since the transmitting end TX can only transmit audio data AD1 during periods when video data VD1 is not being transmitted, the actual frequency at which the transmitting end TX transmits audio data AD1 may vary over time. This means that the electronic device 200 cannot directly regard the frequency of the transmitted audio data AD1 as its sampling frequency. However, over a relatively long period, the average frequency at which the transmitting end TX transmits audio data AD1 will still be quite close to the sampling rate of audio data AD1.

[0030] In this embodiment, the electronic device 200 can temporarily store the audio data AD1 transmitted from the transmitter TX in the memory 246 in a first-in-first-out (FIFO) manner. After a period of time, when the audio data AD1 has occupied a predetermined capacity of the memory 246, it begins to process the data every time the internal reference signal SIG passes. AR At K cycles (e.g., 128 cycles), an audio data segment is retrieved from memory 246. In this case, if the internal reference signal SIG... AR If the frequency is accurate enough, then on average, the frequency at which audio data AD1 is stored in memory 246 will be very close to the frequency at which audio data AD1 is retrieved from memory 246. That is, both should be very close to the sampling rate of audio data AD1. Therefore, the amount of audio data AD1 temporarily stored in memory 246 will also remain within a certain range and will not increase or decrease continuously in the long term.

[0031] However, if the internal reference signal SIG AR If the frequency is inaccurate, the amount of memory occupied by the audio data AD1 in memory 246 may gradually increase or decrease over time. For example, if the amount of memory occupied by the audio data AD1 in memory 246 gradually increases, it may indicate that the internal reference signal SIG is malfunctioning. AR The frequency of the audio data AD1 is lower than the appropriate frequency of the audio clock signal CLK_AUDIO, causing the controller 244 to fetch audio data AD1 from memory 246 at a slower speed than it can store newly received audio data AD1 into memory 246. In this case, when the audio data AD1 occupies more than a predetermined upper limit of memory 246, the controller 244 can increase the internal reference signal SIG. AR The frequency. Conversely, if the amount of memory 246 occupied by audio data AD1 gradually decreases, it may indicate that the internal reference signal SIG is decreasing. ARThe frequency of the audio data AD1 is higher than the appropriate frequency of the audio clock signal CLK_AUDIO, causing the controller 244 to fetch the audio data AD1 from the memory 246 much faster than it can store the newly received audio data AD1 into the memory 246. In this case, when the amount of audio data AD1 occupying the memory 246 is less than a predetermined lower limit, the controller 244 can reduce the internal reference signal SIG. AR The frequency.

[0032] For example, if the memory 246 can store 200 segments of audio data AD1, then the controller 244 can start storing 100 segments of audio data AD1 after each pass of the internal reference signal SIG. AR At 128 cycles, one audio data segment is retrieved from memory 246 (or two audio data segments in a two-channel application). Controller 244 continuously monitors the capacity of memory 246, and when more than 120 audio data segments are stored in memory 246, controller 244 determines that the capacity of memory 246 has exceeded the upper limit (i.e., the predetermined upper limit capacity value is 120), and accordingly increases the internal reference signal SIG. AR The frequency. Conversely, when the memory 246 stores less than 80 segments of audio data, the controller 244 can determine that the capacity of the memory 246 has fallen below the lower limit (i.e., the predetermined lower limit value is 80), and correspondingly lower the internal reference signal SIG. AR The frequency of the received audio data AD1. In this way, the controller 244 can dynamically adjust the internal reference signal SIG according to the speed of the received audio data AD1. AR The frequency, thereby ensuring the internal reference signal SIG AR The frequency can approach the appropriate frequency of the audio clock signal CLK_AUDIO.

[0033] Generate an internal reference signal SIG with an appropriate frequency. AR Then, in step S350, the controller 244 can further determine the parameters based on the preset multiple N2 and the internal reference signal SIG. AR The periodic timestamp CTS2 is generated based on the ratio of the pixel clock signal CLK_TMDS2, and the transmitting unit 230 can output the periodic timestamp CTS2 together with the video data VD2, the audio data AD1 and the pixel clock signal CLK_TSMD2 to the receiving end RX in step S360.

[0034] In this embodiment, the memory 246 can be, for example, Dynamic Random Access Memory (DRAM). In this case, the audio timing unit 240 can place the memory 246 externally and select an appropriate size of DRAM as needed, thus offering greater design flexibility. However, in some other embodiments, the memory 246 can also be Static Random Access Memory (SRAM) located inside the audio timing unit 240. In this case, the controller 244 can access the memory 246 more quickly; however, designers generally need to determine the capacity of the memory 246 in advance when designing the audio timing unit 240, and it is difficult to expand the capacity of the memory 246 afterward.

[0035] In the aforementioned embodiments, the audio timing unit 240 uses the memory 246 to temporarily store the audio data AD1, and determines the internal reference signal SIG based on the change in the capacity of the memory 246. AR The relationship between the frequency and the sampling rate of the audio data AD1 is used to adjust the internal reference signal SIG in step S340. AR The frequency of the internal reference signal SIG. However, this disclosure is not limited thereto. In some embodiments, the audio timing unit 240 may also use other methods to determine the internal reference signal SIG. AR The relationship between the frequency and the sampling rate of the audio data AD1, and the internal reference signal SIG. AR When the frequency is less than the product of the sampling rate of the audio data AD1 and a sampling factor (e.g., 128), the internal reference signal SIG is increased. AR The frequency; and the internal reference signal SIG. AR When the frequency is greater than the product of the sampling rate of the audio data AD1 and that sampling multiple, the internal reference signal SIG is reduced. AR The frequency. For example, the audio timing unit 240 can determine the internal reference signal SIG by counting instead of using memory. AR The relationship between the frequency and the sampling rate of the audio data AD1.

[0036] Figure 5 This is a schematic diagram of an embodiment of the electronic device 400 disclosed herein. The electronic device 400 includes a receiving unit 210, a signal processing unit 220, a transmitting unit 230, and an audio timing unit 440. The electronic device 400 has a similar structure to the electronic device 200 and can also be used to execute the method 300. However, the difference between the electronic device 400 and the electronic device 200 is that the audio timing unit 440 in the electronic device 400 may include a counter 446 but not a memory.

[0037] like Figure 5 As shown, the audio timing unit 440 may include a reference signal generator 442, a counter 446, and a controller 444. In this embodiment, the audio timing unit 440 does not need to temporarily store the received audio data in memory, but can use the counter 446 to simulate the occupancy status of a virtual memory, so that the controller 444 can adjust the internal reference signal SIG accordingly. AR The frequency.

[0038] For example, when the audio timing unit 440 executes step S340, the audio timing unit 440 increments the value of the counter 446 by one each time the receiving unit 210 receives each segment of audio data AD1. After the value of the counter 446 reaches a predetermined value, the internal reference signal SIG is incremented every time it passes. AR During K cycles (K could be, for example, 128), controller 444 can decrement the value of counter 446 by one. In other words, the value of counter 446 can be considered as the capacity of a virtual memory. When the value of counter 446 increases by one, it means that a segment of audio data is stored in the virtual memory, and when the value of counter 446 decreases by one, it means that a segment of audio data is retrieved from the virtual memory. In this case, when the internal reference signal SIG... AR When the frequency is comparable to the appropriate frequency of the audio clock signal CLK_AUDIO, the virtual memory capacity occupied by the audio data should remain within a certain range, without continuously increasing or decreasing.

[0039] When the value of counter 446 exceeds the predetermined upper limit, it indicates that the speed at which audio data AD1 is stored in the virtual memory is greater than the speed at which audio data AD1 is retrieved from the virtual memory. At this time, the internal reference signal SIG... AR The frequency may be lower than the appropriate frequency of the audio clock signal CLK_AUDIO, therefore the controller 444 can correspondingly increase the internal reference signal SIG. AR The frequency. Conversely, when the value of counter 446 is less than a predetermined lower limit, it means that the speed at which audio data AD1 is stored in the virtual memory is less than the speed at which audio data AD1 is retrieved from the virtual memory. At this time, the internal reference signal SIG... AR The frequency may be higher than the appropriate frequency of the audio clock signal CLK_AUDIO, therefore the controller 444 can correspondingly reduce the internal reference signal SIG. AR The frequency. In some embodiments, the predetermined upper limit value may be greater than the predetermined value, and the predetermined value may be greater than the predetermined lower limit value. For example, the predetermined value may be 100, the predetermined upper limit value may be 120, and the predetermined lower limit value may be 80.

[0040] Furthermore, in some embodiments, the controller 444 adjusts the internal reference signal SIG. AR After a certain frequency, the value of counter 446 may take some time to gradually return to the range between the predetermined lower limit and the predetermined upper limit. In this case, if controller 444 continuously increases or decreases the internal reference signal SIG before the value of counter 446 returns to this range... AR The frequency of this could cause the internal reference signal SIG to... AR The frequency swing is too large to approach the appropriate frequency of the audio clock signal CLK_AUDIO. To solve this problem, in this embodiment, the controller 444 can increase the internal reference signal SIG. AR After determining the frequency, it checks if the counter value has decreased, and then decides whether to increase the internal reference signal SIG. AR The frequency.

[0041] For example, controller 444 increases the internal reference signal SIG. AR After the frequency is reached, if the counter value still does not decrease, the controller 444 can raise the internal reference signal SIG again. AR The frequency. Conversely, the internal reference signal SIG is increased in controller 444. AR After the frequency is reached, if the value of counter 446 has decreased, then even if the value of counter 446 is still greater than the predetermined upper limit, controller 444 will not immediately raise the internal reference signal SIG. AR The frequency of the internal reference signal SIG. Conversely, controller 444 can reduce the frequency of the internal reference signal SIG. AR After the frequency is adjusted, if the counter value still does not increase, the internal reference signal SIG is decreased again. AR The frequency. Conversely, the controller 444 lowers the internal reference signal SIG. AR After the frequency is reached, if the value of counter 446 has increased, then even if the value of counter 446 is still less than the predetermined lower limit, controller 444 will not immediately decrease the internal reference signal SIG. AR The frequency. In this way, the controller 444 can avoid over-adjusting the internal reference signal SIG. AR The frequency causes the internal reference signal SIG to be affected. AR The frequency cannot approach the appropriate frequency of the audio clock signal CLK_AUDIO.

[0042] Furthermore, in some embodiments, due to the internal reference signal SIG AR This is not the actual clock signal used to play the audio data AD1, therefore the waveform requirements are lower. In other words, as long as the audio timing unit 440 can make the internal reference signal SIG... ARThe frequency should be close to the appropriate frequency of the audio clock signal CLK_AUDIO. As for the internal reference signal SIG... AR Whether each cycle is exactly the same will not affect the calculation of the subsequent cycle timestamp CTS2. In this case, the reference signal generator 442 can also be implemented using logic circuits instead of a phase-locked loop. Since the circuit of a phase-locked loop is relatively complex and requires a large circuit area, implementing the reference signal generator 442 using logic circuits can also reduce the circuit area required by the electronic device 400.

[0043] For example, in order to enable its internal digital circuitry to operate, electronic device 400 itself generates the necessary internal clock signal CLK_INN (indicated by...). Figure 6 (in the middle). In this case, if the controller 444 knows the frequency of the internal clock signal CLK_INN and the internal reference signal SIG... AR The ratio of the frequency can be used to generate the internal reference signal SIG based on the internal clock signal CLK_INN. AR .

[0044] In this embodiment, the controller 444 can use the internal clock signal CLK_INN to estimate a detection time and calculate the number of audio data AD1 received by the receiving unit 210 within the detection time. For example, if 250 cycles of the internal clock signal CLK_INN is exactly one microsecond, the controller 444 can, for example, set the detection time to 250 times 2. 17 The period of the internal clock signal CLK_INN is 131.072 milliseconds. If the receiving unit 210 receives 4194 audio data AD1s within this 131.072 millisecond detection time, it means that the corresponding audio clock signal CLK_AUDIO should have undergone (4194 × K) cycles during this period. With K = 128, the relationship between the internal clock signal CLK_INN and the internal reference signal SIG can be deduced. AR The frequency ratio is (250×2) 10 ):4194.

[0045] Obtain the internal clock signal CLK_INN and the internal reference signal SIG AR After determining the frequency ratio, the reference signal generator 442 can generate the internal reference signal SIG based on the ratio and the internal clock signal CLK_INN. AR For example, if the internal clock signal CLK_INN and the internal reference signal SIG... ARIf the frequency ratio is A:B, then the reference signal generator 442 can set a level discrimination value, starting from 0, and incrementing it by B each time the internal clock signal CLK_INN completes one cycle. When the accumulated result causes the level discrimination value to be greater than A, the reference signal generator 442 can subtract A from the accumulated result. After each level discrimination value update, the reference signal generator 442 can further compare the level discrimination value with... The magnitude of the level is determined when the level discrimination value is greater than or equal to... At that time, the internal reference signal SIG will be... AR Set to logic high level, and when the level discrimination value is less than At that time, the internal reference signal SIG will be set. AR Set to logic low. This will cause the internal reference signal SIG to... AR It will periodically switch between logic high and logic low levels, and on average over a period of time, the internal clock signal CLK_INN and the internal reference signal SIG... AR The frequency ratio is A:B.

[0046] Figure 6 The reference signal generator 442 disclosed herein generates the internal reference signal SIG. AR A schematic diagram. In Figure 6 In this embodiment, the internal clock signal CLK_INN and the internal reference signal SIG AR The frequency ratio is 5:2. In this case, the reference signal generator 442 increments the level discrimination value B_ACC by 2 every cycle of the internal clock signal CLK_INN. Therefore, B_ACC will accumulate sequentially from 0 to 2 and then 4. When the accumulated value of the level discrimination value B_ACC is greater than 5, the reference signal generator 442 can subtract 5 from the accumulated value. Therefore, if... Figure 6 As shown, the level discrimination value B_ACC will be updated sequentially to 0, 2, 4, 1, 3, 5, 2...

[0047] After each update of the level discrimination value B_ACC, the reference signal generator 442 can further compare the level discrimination value B_ACC with... (In this embodiment, it is 2.5). When the level discrimination value B_ACC is greater than or equal to 2.5, the internal reference signal SIG... AR This will be set to a logic high level, and when the level discrimination value B_ACC is less than 2.5, the internal reference signal SIG will be... AR It will then be set to a logic low level. In this way, such as... Figure 6 As shown, during the period P1 when the internal clock signal CLK_INN has undergone 5 cycles, the internal reference signal SIGAR This involves two cycles, namely the internal clock signal CLK_INN and the internal reference signal SIG. AR The frequency ratio is 5:2. Furthermore, when controller 444 wants to adjust the internal reference signal SIG... AR When the frequency is adjusted, it is equivalent to adjusting the internal clock signal CLK_INN and the internal reference signal SIG. AR The frequency ratio is such that simply increasing or decreasing the value of B can increase or decrease the internal reference signal SIG. AR The effect of frequency.

[0048] Since the reference signal generator 442 can use logic circuits to generate an internal reference signal SIG with the required frequency. AR Therefore, compared to using a phase-locked loop to generate the internal reference signal SIG, AR The audio timing unit 240 and the audio timing unit 440 require a smaller circuit area.

[0049] In summary, the electronic device and method for transmitting video and audio data provided in this disclosure can generate an internal reference signal with the same frequency as the audio clock signal used to play the audio data based on the reception status of the audio data, and can generate a periodic timestamp corresponding to the pixel clock signal of the output video data based on the internal reference signal. Therefore, when the receiving end receives the video data output by the electronic device, it can accurately regenerate the audio clock signal based on the periodic timestamp and the pixel clock signal of the video data, thereby reducing the popping sound phenomenon generated by the receiving end when playing the audio data.

[0050] [Symbol Explanation]

[0051] 10, 20: Data transmission system

[0052] 200, 400: Electronic devices

[0053] 210: Receiving Unit

[0054] 220: Signal Processing Unit

[0055] 230: Transmitting Unit

[0056] 240, 440: Audio timing unit

[0057] 242, 442: Reference signal generator

[0058] 244, 444: Controller

[0059] 246: Memory

[0060] 300: Method

[0061] 446: Counter

[0062] AD1: Audio Data

[0063] B_ACC: Level discrimination value

[0064] CLK_AUDIO: Audio clock signal

[0065] CLK_INN: Internal clock signal

[0066] CLK_TMDS1, CLK_TMDS2: Pixel clock signals

[0067] CTS1, CTS2: Periodic Timestamps

[0068] N, N1, N2: Preset multipliers

[0069] RX: Receiver

[0070] S310 to S360: Steps

[0071] SIG AR Internal reference signal

[0072] TX: Sender

[0073] VD1, VD2: Video data

Claims

1. An electronic device comprising: A receiving unit is used to receive multiple audio data and multiple first video data; A signal processing unit is configured to generate multiple second video data based on the multiple first video data and to generate a pixel clock signal for playing the multiple second video data; A transmitting unit is configured to output the plurality of second video data, the plurality of audio data, the pixel clock signal, and a periodic timestamp to a receiving end, wherein the value obtained by dividing the frequency of the pixel clock signal by the periodic timestamp is equal to the value obtained by dividing the frequency of an audio reference clock signal used by the receiving end to play the plurality of audio data by a preset multiple; and An audio timing unit, comprising: A reference signal generator for generating an internal reference signal; and A controller is configured to adjust the frequency of the internal reference signal according to the speed at which the multiple audio data are transmitted, and to generate the periodic timestamp according to the preset multiple, the internal reference signal, and the pixel clock signal.

2. The electronic device as claimed in claim 1, wherein: When the frequency of the internal reference signal is less than the product of a sampling rate and a sampling multiple of the plurality of audio data, the controller controls the reference signal generator to increase the frequency of the internal reference signal; as well as When the frequency of the internal reference signal is greater than the product of the sampling rate and the sampling multiple of the plurality of audio data, the controller controls the reference signal generator to reduce the frequency of the internal reference signal.

3. The electronic device of claim 1, wherein the audio timing unit further comprises: A memory is provided for temporarily storing the plurality of audio data; in: When the plurality of audio data have occupied a predetermined capacity of the memory, the controller retrieves one audio data from the memory every K cycles of the internal reference signal, where K is a positive integer; When the plurality of audio data occupies a memory capacity exceeding a predetermined upper limit, the controller increases the frequency of the internal reference signal; and when the plurality of audio data occupies a memory capacity less than a predetermined lower limit, the controller decreases the frequency of the internal reference signal. The predetermined upper limit capacity is greater than the predetermined capacity, and the predetermined capacity is greater than the predetermined lower limit capacity.

4. The electronic device of claim 1, wherein the audio timing unit further comprises a counter, and the controller is configured to: Each time the receiving unit receives one audio data from the plurality of audio data, the value of a counter is incremented by one; After the value of the counter reaches a predetermined value, the value of the counter is decremented by one every K cycles of the internal reference signal, where K is a positive integer. When the value of the counter is greater than a predetermined upper limit, the frequency of the internal reference signal is increased; as well as When the value of the counter is less than a predetermined lower limit, the frequency of the internal reference signal is reduced. The predetermined upper limit value is greater than the predetermined value, and the predetermined value is greater than the predetermined lower limit value.

5. The electronic device of claim 4, wherein the controller is further configured to: After increasing the frequency of the internal reference signal, if the value of the counter does not decrease, the frequency of the internal reference signal is increased again. After reducing the frequency of the internal reference signal, if the value of the counter does not increase, the frequency of the internal reference signal is reduced again. After increasing the frequency of the internal reference signal, when the value of the counter has decreased, the frequency of the internal reference signal is maintained; and After reducing the frequency of the internal reference signal, the frequency of the internal reference signal is maintained when the value of the counter has increased.

6. A method for transmitting video data and audio data, the method comprising: Receive multiple audio data and multiple first video data; Generate multiple second video data and a one-pixel clock signal for playing the multiple second video data based on the multiple first video data; Generate an internal reference signal; The frequency of the internal reference signal is adjusted according to the speed at which the multiple audio data are transmitted. A time stamp is generated based on a preset multiple, the internal reference signal, and the pixel clock signal; as well as The plurality of second video data, the plurality of audio data, a pixel clock signal, and a periodic timestamp are output to a receiving end, wherein the value obtained by dividing the frequency of the pixel clock signal by the periodic timestamp is equal to the value obtained by dividing the frequency of an audio reference clock signal used by the receiving end to play the plurality of audio data by the preset multiple.

7. The method of claim 6, wherein the step of adjusting the frequency of the internal reference signal according to the speed at which the plurality of audio data are transmitted comprises: When the frequency of the internal reference signal is less than the product of a sampling rate and a sampling factor of the plurality of audio data, the controller controls the reference signal generator to increase the frequency of the internal reference signal; and When the frequency of the internal reference signal is greater than the product of the sampling rate and the sampling multiple of the plurality of audio data, the controller controls the reference signal generator to reduce the frequency of the internal reference signal.

8. The method of claim 6, wherein the step of adjusting the frequency of the internal reference signal according to the speed at which the plurality of audio data are transmitted comprises: The multiple audio data are stored in a memory; Once the plurality of audio data has occupied a predetermined capacity of the memory, one audio data is retrieved from the memory every K cycles of the internal reference signal, where K is a positive integer; When the multiple audio data occupy more than a predetermined upper limit of the memory capacity, the frequency of the internal reference signal is increased; as well as When the memory capacity occupied by the multiple audio data is less than a predetermined lower limit, the frequency of the internal reference signal is reduced; The predetermined upper limit capacity is greater than the predetermined capacity, and the predetermined capacity is greater than the predetermined lower limit capacity.

9. The method of claim 6, wherein the step of adjusting the frequency of the internal reference signal according to the speed at which the plurality of audio data are transmitted comprises: Each time the receiving unit receives one of the multiple audio data, the value of a counter is incremented by one. After the value of the counter reaches a predetermined value, the value of the counter is decremented by one every K cycles of the internal reference signal, where K is a positive integer. When the value of the counter exceeds a predetermined upper limit, the frequency of the internal reference signal is increased; and When the value of the counter is less than a predetermined lower limit, the frequency of the internal reference signal is reduced. The predetermined upper limit value is greater than the predetermined value, and the predetermined value is greater than the predetermined lower limit value.

10. The method of claim 9, wherein the step of adjusting the frequency of the internal reference signal according to the speed at which the plurality of audio data are transmitted further comprises: After increasing the frequency of the internal reference signal, if the value of the counter does not decrease, the frequency of the internal reference signal is increased again. After reducing the frequency of the internal reference signal, if the value of the counter does not increase, the frequency of the internal reference signal is reduced again. After increasing the frequency of the internal reference signal, when the value of the counter has decreased, the frequency of the internal reference signal is maintained; and After reducing the frequency of the internal reference signal, the frequency of the internal reference signal is maintained when the value of the counter has increased.

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