Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes: a doped semiconductor layer including an upper surface facing a first direction; a multifunctional stack including a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked on top of the doped semiconductor layer in the first direction, the multifunctional stack including a groove; an inner insulating layer located on a bottom surface of the groove; an inner semiconductor layer located on the inner insulating layer; and a first electrode and a second electrode spaced apart from each other in the groove and extending from the inner semiconductor layer in the first direction.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to semiconductor memory devices and methods of manufacturing such semiconductor memory devices, and more specifically, to three-dimensional semiconductor memory devices and methods of manufacturing such three-dimensional semiconductor memory devices. Background Technology

[0002] Test patterns can be formed to measure the electrical characteristics of semiconductor memory devices. In three-dimensional semiconductor memory devices proposed for increasing integration density, test patterns can be formed through a process independent of the process for forming the cell array structure. As a result, the reliability of data obtained through test patterns is not high. Summary of the Invention

[0003] According to an embodiment, a semiconductor memory device may include: a first doped semiconductor layer and a second doped semiconductor layer, each having an upper surface facing a first direction, the first doped semiconductor layer and the second doped semiconductor layer being spaced apart from each other; a multifunctional stack including a plurality of first interlayer insulating layers and a plurality of first conductive layers alternately stacked on top of the first doped semiconductor layer in a first direction, the multifunctional stack including a recess; an inner insulating layer located on the bottom surface of the recess; an inner semiconductor layer located on the inner insulating layer; a first electrode and a second electrode spaced apart from each other in the recess and extending from the inner semiconductor layer in a first direction; a gate stack including a plurality of second interlayer insulating layers and a plurality of second conductive layers alternately stacked on the second doped semiconductor layer in a first direction, the gate stack including a vertical via; a memory layer located on the side of the vertical via; and a vertical semiconductor layer disposed on the memory layer.

[0004] According to an embodiment, a semiconductor memory device may include: a doped semiconductor layer including an upper surface facing a first direction; a multifunctional stack including a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked on top of the doped semiconductor layer in the first direction, the multifunctional stack including a groove; an inner insulating layer located on the bottom surface of the groove; an inner semiconductor layer located on the inner insulating layer; and a first electrode and a second electrode spaced apart from each other in the groove and extending from the inner semiconductor layer in the first direction, wherein at least one of the plurality of conductive layers is located between the inner insulating layer and the doped semiconductor layer.

[0005] According to an embodiment, a semiconductor memory device may include: a first doped semiconductor layer and a second doped semiconductor layer, each including an upper surface facing a first direction, the first doped semiconductor layer and the second doped semiconductor layer being spaced apart from each other; a test array overlapping the first doped semiconductor layer; and a three-dimensional memory cell array structure overlapping the second doped semiconductor layer. The test array may include: a plurality of multifunctional stacks including a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked on top of the first doped semiconductor layer in a first direction, the plurality of multifunctional stacks including a plurality of grooves; a plurality of inner insulating layers respectively disposed on a plurality of bottom surfaces corresponding to the plurality of grooves; a plurality of inner semiconductor layers respectively disposed on the plurality of inner insulating layers; a plurality of filling insulating layers disposed in the plurality of grooves; and a plurality of electrode pairs passing through the plurality of filling insulating layers and connected to the plurality of inner semiconductor layers.

[0006] According to an embodiment, a method of manufacturing a semiconductor memory device may include: forming a multifunctional stack including a groove and a gate stack including a vertical hole; forming a memory layer on the side of the vertical hole; forming an inner insulating layer on the surface of the groove while forming the memory layer; forming a vertical semiconductor layer on the memory layer; forming an inner semiconductor layer on the inner insulating layer while forming the vertical semiconductor layer; and forming a first electrode and a second electrode in the groove that are connected to the inner semiconductor layer and spaced apart from each other. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a substrate according to an embodiment of the present disclosure;

[0008] Figure 2 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figure 3A and Figure 3B They are Figure 2 Enlarged plan views of regions A and B;

[0010] Figure 4A and Figure 4B This is an enlarged plan view of the test pattern and unit plug according to an embodiment of the present disclosure;

[0011] Figure 5A and Figure 5B This is a cross-sectional view illustrating the test area and memory cell array area of ​​a semiconductor memory device according to an embodiment of the present disclosure;

[0012] Figure 6 This is a plan view illustrating a test group according to an embodiment of the present disclosure;

[0013] Figure 7This is a plan view illustrating a test pattern array in a transistor region according to an embodiment of the present disclosure;

[0014] Figure 8A and Figure 8B This is a plan view illustrating a first test pattern and a second test pattern in a transistor region according to an embodiment of the present disclosure;

[0015] Figure 9 This is a plan view illustrating a test pattern array in a capacitor region according to an embodiment of the present disclosure;

[0016] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0017] Figure 18 This is a block diagram illustrating the configuration of a memory system according to embodiments of the present disclosure; and

[0018] Figure 19 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural and functional descriptions disclosed herein are merely illustrative examples for the purpose of describing embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure can be modified in various ways and replaced with other equivalent embodiments. Therefore, this disclosure should not be construed as limited to the embodiments set forth herein.

[0020] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and the order or number of components is not limited by these terms. Furthermore, when an element or layer is referred to as being “on,” “connected to,” or “linked to” another element or layer, it may be directly on, directly connected to, or directly linked to the other element or layer, or an intermediary element or layer may be present. Conversely, when an element or layer is referred to as being “directly” “on,” “directly connected to,” or “directly linked to” another element or layer, no intermediary element or layer is present. Similar reference numerals always refer to similar elements.

[0021] Various embodiments relate to semiconductor memory devices that improve the reliability of data obtained through test patterns and methods for manufacturing such semiconductor memory devices.

[0022] Figure 1 This is a schematic diagram illustrating a substrate 101 according to an embodiment of the present disclosure.

[0023] Reference Figure 1 The substrate 101 may include multiple chip regions CR and scribing regions SR between the multiple chip regions CR. The multiple chip regions CR can be divided by the scribing regions SR. Each chip region CR can be surrounded by the scribing regions SR.

[0024] According to one embodiment, the three-dimensional memory cell array structure includes a plurality of memory cells arranged in three dimensions in each chip region CR. Test patterns representing the electrical characteristics of the memory cells in the three-dimensional memory cell array structure can be provided in a test area of ​​the substrate 101. The test area can be provided in each chip region CR or in a scribing area SR. The operation of the memory cells can be controlled by peripheral logic circuitry. The peripheral logic circuitry may include row decoders, column decoders, page buffers, control circuitry, etc. According to one embodiment, a peripheral circuit structure for the peripheral logic circuitry can be formed in each chip region CR. The chip region CR may include a memory cell array region and a peripheral circuit region. A memory cell array region can be provided for the three-dimensional memory cell array structure. The peripheral circuit structure can be formed in the peripheral circuit region of the chip region CR, or it can overlap with the three-dimensional memory cell array structure. According to another embodiment, the peripheral circuit structure can be formed on a separate substrate. The peripheral circuit structure and the three-dimensional memory cell array structure can be interconnected by bonding pads connected to the three-dimensional memory cell array structure and bonding pads connected to the peripheral circuit structure.

[0025] A three-dimensional memory cell array structure may include a gate stack, a vertical semiconductor layer in the gate stack, and a memory layer between the vertical semiconductor layer and the gate stack. A test pattern according to embodiments of the present disclosure may include a multifunctional stack, an inner semiconductor layer in the multifunctional stack, and an inner insulating layer between the inner semiconductor layer and the multifunctional stack.

[0026] Figure 2 This is a plan view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0027] Reference Figure 2 The semiconductor memory device may include a first doped semiconductor layer 110A, a second doped semiconductor layer 110B, a test group 120, and a three-dimensional memory cell array structure 130. The first doped semiconductor layer 110A and the test group 120 may be formed in a test region, which is positioned such that... Figure 1 The substrate 101 shown contains at least one of the chip region CR and the scribing region SR. The second doped semiconductor layer 110B and the three-dimensional memory cell array structure 130 can be arranged as follows: Figure 1 In the chip region CR of the substrate 101 shown.

[0028] The first doped semiconductor layer 110A and the second doped semiconductor layer 110B can be arranged as follows: Figure 1 Above the substrate 101 shown. The top surfaces of the first doped semiconductor layer 110A and the second doped semiconductor layer 110B may face the first direction DR1. The first doped semiconductor layer 110A and the second doped semiconductor layer 110B may be spaced apart from each other in the direction in which their top surfaces extend. According to an embodiment, the first doped semiconductor layer 110A and the second doped semiconductor layer 110B may be spaced apart from each other in the second direction DR2. The first doped semiconductor layer 110A and the second doped semiconductor layer 110B may extend adjacent to each other. According to an embodiment, the first doped semiconductor layer 110A and the second doped semiconductor layer 110B may extend in the third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 may be defined as directions extending along axes that intersect each other. According to an embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 may be defined as the Z-axis direction, the X-axis direction, and the Y-axis direction, respectively. The first doped semiconductor layer 110A and the second doped semiconductor layer 110B may be spaced apart from each other in the XY plane. In this embodiment, the first doped semiconductor layer 110A and the second doped semiconductor layer 110B can be spaced apart from each other and do not overlap in the first direction DR1, for example, as shown in the example. Figure 2 As shown.

[0029] Test group 120 may be arranged to overlap with the first doped semiconductor layer 110A. Test group 120 may include multiple test patterns to test the electrical characteristics of the three-dimensional memory cell array structure 130. According to an embodiment, test group 120 may include at least one of a capacitor and a transistor.

[0030] The three-dimensional memory cell array structure 130 can be arranged to overlap with the second doped semiconductor layer 110B. The three-dimensional memory cell array structure 130 can include a non-volatile memory cell array, such as a NAND flash memory cell array, a ferroelectric memory cell array, and a phase-change memory cell array. The second doped semiconductor layer 110B can be configured as a source layer connected to the NAND flash memory cell array, or as a lower structure of the ferroelectric memory cell array, or as a lower structure of the phase-change memory cell array. The structure of the second doped semiconductor layer 110B configured as a lower structure of the ferroelectric memory cell array or the phase-change memory cell array is not limited to... Figure 2 The structure shown can be divided into multiple line patterns.

[0031] Figure 3A and Figure 3B They are Figure 2 Enlarged plan views of regions A and B.

[0032] Reference Figure 2 and Figure 3A Test group 120 may include a multifunctional stack (MST). The MST may include multiple layers stacked on the first doped semiconductor layer 110A. The MST may include a test pattern array region (TAR) and an electrode contact region (CTR_E).

[0033] Multiple layers of the multifunctional laminate MST can form a stepped structure in the electrode contact region CTR_E. At least one contact plug 187A can overlap with the electrode contact region CTR_E of the multifunctional laminate MST. According to an embodiment, the multiple contact plugs 187A can be spaced apart from each other along at least one step of the multiple steps constituting the stepped structure of the electrode contact region CTR_E. However, the embodiments of this disclosure are not limited thereto. According to another embodiment, the contact plug corresponding to at least one step of the stepped structure of the electrode contact region CTR_E can extend continuously in a strip shape along a step.

[0034] The multifunctional laminate (MST) may include multiple grooves (GVs). The multiple grooves (GVs) may be spaced apart from each other in the second direction (DR2) and the third direction (DR3). Multiple test patterns (TPs) may be arranged in the multiple grooves (GVs). The multiple grooves (GVs) and the multiple test patterns (TPs) may be arranged in a test pattern array region (TAR).

[0035] Reference Figure 2 and Figure 3B The three-dimensional memory cell array structure 130 may include a plurality of gate stacks GSTs. Adjacent gate stacks GSTs may be separated from each other by slits SI. Although not shown, a vertical structure may be disposed in the slits SI. According to one embodiment, the vertical structure may include an insulating material filling the space between adjacent gate stacks GSTs. According to another embodiment, the vertical structure may include a sidewall insulating layer on the sidewalls of the gate stacks GSTs and a vertical conductor. The vertical conductor may be separated from the gate stacks GSTs while the sidewall insulating layer is inserted between the vertical conductor and the gate stacks GSTs, and may be connected to the second doped semiconductor layer 110B.

[0036] The gate stack (GST) may include multiple layers stacked above the second doped semiconductor layer 110B. The gate stack (GST) may include a cell array region (CAR) and a gate contact region (CTR_G).

[0037] Multiple layers of the gate stack GST can form a stepped structure in the gate contact region CTR_G. Multiple gate contact plugs 187B can overlap with multiple steps defining the stepped structure in the gate contact region CTR_G.

[0038] Each gate stack (GST) may include multiple vertical vias (H). The multiple vertical vias (H) may be spaced apart from each other on the second direction (DR2) and the third direction (DR3). Multiple cell plugs (CP) may be arranged in the multiple vertical vias (H). The multiple vertical vias (H) and the multiple cell plugs (CP) may be formed in the cell array region (CAR) of the gate stack (GST).

[0039] Reference Figure 3A and Figure 3B In the plan view, the groove GV can have a larger area than the vertical hole H. The test pattern TP and the unit plug CP can extend in the first direction DR1.

[0040] Figure 4A and Figure 4B This is an enlarged plan view of the test pattern and unit plug according to an embodiment of the present disclosure.

[0041] Reference Figure 4AThe test pattern TP may include an inner insulating layer 161A, an inner semiconductor layer 163A, a first electrode 171E, and a second electrode 171E2. The inner semiconductor layer 163A can be insulated from the first electrode 171E1 and the second electrode 171E2 by a filling insulating layer 165A. When the filling insulating layer 165A surrounds the first electrode 171E1 and the second electrode 171E2, the filling insulating layer 165A can insulate the first electrode 171E1 and the second electrode 171E2 from each other. The inner semiconductor layer 163A can surround the filling insulating layer 165A. The inner insulating layer 161A can be inserted into, for example,... Figure 3A The multifunctional stack shown is between the MST and the inner semiconductor layer 163A.

[0042] Reference Figure 4B The cell plug CP may include a memory layer 161B, a vertical semiconductor layer 163B, and a conductive overlay pattern 167. The vertical semiconductor layer 163B may surround the conductive overlay pattern 167. The memory layer 161B may surround the vertical semiconductor layer 163B.

[0043] Reference Figure 4A and Figure 4B The inner insulating layer 161A of the test pattern TP can have the same material as the memory layer 161B to represent the characteristics of the memory layer 161B.

[0044] Memory layer 161B can be used as a data storage layer for various memory cells, such as a data storage layer for NAND flash memory cells, a data storage layer for ferroelectric memory cells, or a data storage layer for phase-change memory cells. According to one embodiment, when memory layer 161B is configured as a data storage layer for a phase-change memory cell, each of memory layer 161B and inner insulating layer 161A may include a phase-change layer. According to another embodiment, when memory layer 161B is configured as a data storage layer for a ferroelectric memory cell, each of memory layer 161B and inner insulating layer 161A may include a ferroelectric layer. According to another embodiment, when memory layer 161B is configured as a data storage layer for a NAND flash memory cell, each of memory layer 161B and inner insulating layer 161A may include a floating gate layer, an insulating layer including conductive nanodots, or a charge trapping layer (CTL). Hereinafter, embodiments of the present disclosure will be described based on an example where memory layer 161B includes a charge trapping layer (CTL). However, the present disclosure is not limited thereto.

[0045] Each of the inner insulating layer 161A and the memory layer 161B may further include a tunnel insulating layer TI and a barrier insulating layer BI, which are separated from each other by a charge trapping layer CTL interposed therebetween. The charge trapping layer CTL may include a silicon nitride layer. The barrier insulating layer BI may be interposed between the inner semiconductor layer 163A or the vertical semiconductor layer 163B corresponding to the inner semiconductor layer and the charge trapping layer CTL. The barrier insulating layer BI may include an insulating material that blocks charge movement. According to an embodiment, the barrier insulating layer BI may include a silicon oxide layer, a high-k dielectric oxide layer such as an aluminum oxide layer or a hafnium oxide layer, or a combination of a silicon oxide layer and a high-k dielectric oxide layer. The tunnel insulating layer TI may include an insulating material capable of tunneling. According to an embodiment, the tunnel insulating layer TI may include a silicon oxide layer.

[0046] The inner semiconductor layer 163A of the test pattern TP may include the same semiconductor material as the vertical semiconductor layer 163B to represent the characteristics of the vertical semiconductor layer 163B of the cell plug CP.

[0047] The vertical semiconductor layer 163B can be configured as a channel layer or a vertical electrode. The NAND flash memory cell array can include multiple memory cell strings. Each memory cell string can include multiple memory cells connected in series via a channel layer. According to one embodiment, the vertical semiconductor layer 163B can be configured as a channel layer. According to another embodiment, the vertical semiconductor layer 163B can be configured as a vertical electrode for controlling ferroelectric memory cells or a vertical electrode for controlling phase-change memory cells. Hereinafter, embodiments of the present disclosure will be described based on an example where the vertical semiconductor layer 163B is configured as a channel layer of a memory cell string. However, the embodiments are not limited thereto.

[0048] Each of the inner semiconductor layer 163A and the vertical semiconductor layer 163B may include a semiconductor material, including silicon, germanium, or a combination thereof. Each of the inner semiconductor layer 163A and the vertical semiconductor layer 163B may be a doped semiconductor layer, an undoped semiconductor, or a semiconductor partially doped with impurities.

[0049] The first electrode 171E1 and the second electrode 171E2 of the test pattern TP may include semiconductor materials doped with impurities.

[0050] The conductive overlay pattern 167 of the unit plug CP may include a conductive material formed from a semiconductor material doped with impurities, a metal, or a combination thereof.

[0051] Figure 5A and Figure 5BThis is a cross-sectional view illustrating the test area and memory cell array area of ​​a semiconductor memory device according to an embodiment of the present disclosure. Figure 5A It is along Figure 3A The cross-sectional view of the test area intercepted by line II′ is shown. Figure 5B It is along Figure 3B The cross-sectional view of the memory cell array region intercepted by line II-II′ is shown.

[0052] Reference Figure 5A and Figure 5B The first doped semiconductor layer 110A and the second doped semiconductor layer 110B can be arranged at substantially the same height and can respectively include upper surfaces TS1 and TS2. The first doped semiconductor layer 110A and the second doped semiconductor layer 110B can be separated by a lower insulating layer 115. In the following cross-sectional views, components arranged below the first doped semiconductor layer 110A and the second doped semiconductor layer 110B are omitted. However, as Figure 1 The substrate 101 shown can be arranged below the first doped semiconductor layer 110A and the second doped semiconductor layer 110B.

[0053] The first doped semiconductor layer 110A and the second doped semiconductor layer 110B may comprise a semiconductor material doped with at least one of n-type impurities and p-type impurities. According to an embodiment, each of the first doped semiconductor layer 110A and the second doped semiconductor layer 110B may comprise an n-type doped semiconductor layer, the n-type doped semiconductor layer comprising an n-type impurity as a majority carrier.

[0054] The multifunctional stack MST and the gate stack GST can be arranged at substantially the same height and separated from each other by etching multiple layers stacked on the first direction DR1. The multiple layers of the multifunctional stack MST may include multiple first interlayer insulating layers 141A and multiple first conductive layers 143A alternately stacked on the first direction DR1 above the first doped semiconductor layer 110A. The multiple layers of the gate stack GST may include multiple second interlayer insulating layers 141B and multiple second conductive layers 143B alternately stacked on the first direction DR1 above the second doped semiconductor layer 110B.

[0055] The plurality of first interlayer insulating layers 141A of the multifunctional stack MST can be disposed at substantially the same height as the plurality of second interlayer insulating layers 141B of the gate stack GST. The plurality of first interlayer insulating layers 141A and the plurality of second interlayer insulating layers 141B can have the same insulating material. According to an embodiment, each of the plurality of first interlayer insulating layers 141A and the plurality of second interlayer insulating layers 141B may include a silicon oxide layer. The plurality of first conductive layers 143A of the multifunctional stack MST can be disposed at substantially the same height as the plurality of second conductive layers 143B of the gate stack GST. The plurality of first conductive layers 143A and the plurality of second conductive layers 143B can have the same conductive material. The plurality of first conductive layers 143A and the plurality of second conductive layers 143B can include a single layer or a multilayer such as a double layer. The plurality of first conductive layers 143A and the plurality of second conductive layers 143B can include at least one selected from a doped semiconductor layer, a metal, a conductive metal nitride layer, and a transition metal.

[0056] A first insulating layer 151 can be formed on the multifunctional stack MST and the gate stack GST. The first insulating layer 151 can cover the stepped structure formed in the electrode contact region CTR_E of the multifunctional stack MST and the stepped structure formed in the gate contact region CTR_G of the gate stack GST. A plurality of insulating layers having predetermined etch selectivity can be arranged on the first insulating layer 151. According to an embodiment, a second insulating layer 153, a third insulating layer 181, a fourth insulating layer 183, a fifth insulating layer 185, and a sixth insulating layer 193 can be stacked on the first insulating layer 151 in a first direction DR1. The second insulating layer 153 and the fourth insulating layer 183 can include insulating materials having etch selectivity relative to the first insulating layer 151, the third insulating layer 181, the fifth insulating layer 185, and the sixth insulating layer 193. According to embodiments, the first insulating layer 151, the third insulating layer 181, the fifth insulating layer 185, and the sixth insulating layer 193 may comprise silicon oxide layers, while the second insulating layer 153 and the fourth insulating layer 183 may comprise silicon nitride layers. The stacked structure of the insulating layers on the first insulating layer 151 may not be limited to the figures and may have various designs. As used herein with respect to parameters, the term "predetermined" (such as predetermined etch selectivity or predetermined distance) means that the value of the parameter is determined before its use in the process or algorithm. In some embodiments, the value of the parameter is determined before the start of the process or algorithm. In other embodiments, the value of the parameter is determined during the process or algorithm but before its use in the process or algorithm.

[0057] Reference Figure 5AThe first conductive layer 143A of the multifunctional laminate MST can extend from the test pattern array region TAR to the electrode contact region CTR_E, and can be stacked to form a stepped structure in the electrode contact region CTR_E. The ends of multiple first conductive layers 143A can form a stepped structure in the electrode contact region CTR_E.

[0058] An inner insulating layer 161A, an inner semiconductor layer 163A, a filling insulating layer 165A, a first electrode 171E1, and a second electrode 171E2 can be arranged in a groove GV of a multifunctional laminate MST. In the multifunctional laminate MST, the bottom surface GV_B of the groove GV can have different depths, such that the bottom surface GV_B can be defined by one of a plurality of first conductive layers 143A. According to an embodiment, the lowermost first conductive layer among the plurality of first conductive layers 143A can define the bottom surface GV_B of the groove GV. The first conductive layer defining the bottom surface GV_B of the groove GV can be used as the third electrode conductive layer EL of the test pattern TP.

[0059] The inner insulating layer 161A can be disposed on the bottom surface GV_B of the groove GV and can extend along the side GV_S of the groove GV. The inner semiconductor layer 163A can be disposed on the inner insulating layer 161A and can extend along the bottom surface GV_B and the side GV_S of the groove GV, and the inner insulating layer 161A is inserted between the inner semiconductor layer and the bottom surface and the side.

[0060] The filling insulating layer 165A can be disposed in the groove GV on the inner semiconductor layer 163A. The first electrode 171E1 and the second electrode 171E2 can extend from the inner semiconductor layer 163A in a first direction DR1 to pass through the filling insulating layer 165A. The first electrode 171E1 and the second electrode 171E2 can be separated from each other.

[0061] The inner insulating layer 161A, the inner semiconductor layer 163A, the filling insulating layer 165A, the first electrode 171E1, and the second electrode 171E2 may protrude further than the multifunctional laminate MST in the first direction DR1. According to an embodiment, the inner insulating layer 161A, the inner semiconductor layer 163A, the filling insulating layer 165A, the first electrode 171E1, and the second electrode 171E2 may extend in the first direction DR1 to pass through the first insulating layer 151 and the second insulating layer 153.

[0062] According to embodiments of this disclosure, at least one of the plurality of first conductive layers 143A may not be penetrated by the groove GV and may extend between the inner insulating layer 161A and the first doped semiconductor layer 110A. The first conductive layer extending between the inner insulating layer 161A and the first doped semiconductor layer 110A and contacting the inner insulating layer 161A may be configured as the aforementioned third electrode conductive layer EL. The contact plug 187A may extend from the end of the third electrode conductive layer EL in a first direction DR1 to pass through the first insulating layer 151, the second insulating layer 153, the third insulating layer 181, the fourth insulating layer 183, and the fifth insulating layer 185. The contact plug 187A may include a single conductive layer or multiple layers comprising two or more layers stacked in the first direction DR1.

[0063] The first electrode 171E1 and the second electrode 171E2 can be connected to the first upper contact plug 189A and the second upper contact plug 189B, respectively. The first upper contact plug 189A and the second upper contact plug 189B can extend from the first electrode 171E1 and the second electrode 171E2 to pass through the third insulating layer 181, the fourth insulating layer 183, and the fifth insulating layer 185. The first upper contact plug 189A and the second upper contact plug 189B may include metal.

[0064] A transistor or capacitor can be defined by a test pattern TP and a third electrode conductive layer EL. According to one embodiment, the first electrode 171E1 and the second electrode 171E2 of the test pattern TP can be used as the source electrode and the drain electrode, respectively, and the third electrode conductive layer EL can be used as the gate electrode. In this embodiment, the inner semiconductor layer 163A of the test pattern TP can be used as the channel layer of the transistor, and the inner insulating layer 161A can be used as the gate insulating layer of the transistor. According to another embodiment, the inner semiconductor layer 163A of the test pattern TP can be used as the upper electrode of the capacitor, and the first electrode 171E1 and the second electrode 171E2 can be used as contact electrodes connected to the upper electrode. The third electrode conductive layer EL can be used as the lower electrode of the capacitor, and the inner insulating layer 161A can be used as the insulator of the capacitor.

[0065] Reference Figure 5BThe second conductive layer 143B of the gate stack GST can extend from the cell array region CAR to the gate contact region CTR_G, and can be stacked to form a stepped structure in the electrode contact region CTR_E. Multiple ends of the plurality of second conductive layers 143B can form a stepped structure in the gate contact region CTR_G. A gate contact plug 187B can extend from the end of the second conductive layer 143B corresponding to the gate contact plug along a first direction DR1 to pass through a first insulating layer 151, a second insulating layer 153, a third insulating layer 181, a fourth insulating layer 183, and a fifth insulating layer 185. The gate contact plug 187B can include a single conductive layer, or multiple conductive layers comprising two or more layers stacked along the first direction DR1.

[0066] The memory layer 161B, vertical semiconductor layer 163B, core insulating layer 165B, and conductive overlay pattern 167 of the cell plug CP can be disposed in the vertical via H of the gate stack GST. The vertical via H, memory layer 161B, and vertical semiconductor layer 163B can pass through multiple second conductive layers 143B from the top to the bottom of the gate stack GST. In an embodiment, the vertical via H, memory layer 161B, and vertical semiconductor layer 163B can pass through multiple second conductive layers 143B from the uppermost to the lowermost second conductive layer, for example, as... Figure 5B As shown. In this embodiment, the vertical via H, the memory layer 161B, and the vertical semiconductor layer 163B can pass through multiple second conductive layers 143B in the first direction DR1, for example, as Figure 5B As shown. The bottom surface H_B of the vertical hole H can be defined by a second doped semiconductor layer 110B. The vertical hole H can completely penetrate the multiple second interlayer insulating layers 141B and multiple second conductive layers 143B of the gate stack GST.

[0067] The memory layer 161B can be disposed on the side H_S of the vertical via H. The vertical semiconductor layer 163B can be connected to the second doped semiconductor layer 110B through the bottom surface H_B of the vertical via H, and can extend from the second doped semiconductor layer 110B along the memory layer 161B in the first direction DR1. In an embodiment, the vertical semiconductor layer 163B can be directly connected to the second doped semiconductor layer 110B through the bottom surface H_B of the vertical via H. The memory layer 161B can be interposed between the vertical semiconductor layer 163B and the gate stack GST. The core insulating layer 165B and the conductive overlay pattern 167 can be disposed in the central region of the vertical via H. The conductive overlay pattern 167 can overlap with the core insulating layer 165B.

[0068] The cell plug CP may protrude further than the gate stack GST in the first direction DR1. According to an embodiment, the cell plug CP may extend in the first direction DR1 to pass through the first insulating layer 151 and the second insulating layer 153.

[0069] The plurality of second conductive layers 143B can be divided into at least one second lower conductive layer adjacent to the second doped semiconductor layer 110B, a plurality of second intermediate conductive layers located above the second lower conductive layer, and at least one second upper conductive layer located above the plurality of second intermediate conductive layers. When the plurality of second conductive layers 143B are configured as gate electrodes of a NAND flash memory cell array structure, the second lower conductive layer can be used as a source select line connected to the gate electrode of a source select transistor, the plurality of second intermediate conductive layers can be used as multiple word lines connected to the gate electrodes of a plurality of memory cells, and the second upper conductive layer can be used as a drain select line connected to the gate electrode of a drain select transistor.

[0070] The conductive overlay pattern 167 may be connected to the third upper contact plug 191. The third upper contact plug 191 may extend through the third insulating layer 181, the fourth insulating layer 183, and the fifth insulating layer 185. The third upper contact plug 191 may include metal.

[0071] Reference Figure 5A and Figure 5B The sixth insulating layer 193 can be penetrated by the first wiring 195E1, the second wiring 195E2, the third wiring 195A, the fourth wiring 195B and the fifth wiring 195BL.

[0072] The first wiring 195E1 can be connected to the first electrode 171E via the first upper contact plug 189A. The second wiring 195E2 can be connected to the second electrode 171E2 via the second upper contact plug 189B. The first wiring 195E1 and the second wiring 195E2 can be configured as source wiring and drain wiring for transmitting electrical signals to the transistor, or as capacitor wiring for transmitting electrical signals to the upper electrode of a capacitor.

[0073] The third wiring 195A can be connected to the third electrode conductive layer EL via contact plug 187A. The third wiring 195A can be configured as a gate wiring for transmitting electrical signals to the gate electrode of a transistor, or as wiring for transmitting electrical signals to a capacitor at the lower electrode.

[0074] The fourth wiring 195B can be connected to the corresponding second conductive layer 143B via the gate contact plug 187B. The fifth wiring 195BL can be connected to the conductive overlay pattern 167 via the third upper contact plug 191. When the vertical semiconductor layer 163B of the cell plug CP is configured as the channel layer of the memory cell string included in the NAND flash memory cell array structure, the fifth wiring 195BL can be used as a bit line.

[0075] According to an embodiment of this disclosure, the bottom surface GV_B of the groove GV can be located at a higher height than the bottom surface H_B of the vertical hole H in the first direction DR1.

[0076] Figure 6 This is a plan view illustrating a test group according to an embodiment of the present disclosure.

[0077] Reference Figure 6 The first doped semiconductor layer 110A disposed in the test region may include a transistor region AR_T and a capacitor region AR_C. The test group may include a plurality of multifunctional stacks MST_T disposed to overlap with the transistor region AR_T and a plurality of multifunctional stacks MST_CA, MST_CB and MST_CC disposed to overlap with the capacitor region AR_C.

[0078] The multiple multifunctional stacks MST_T above the transistor region AR_T and the multiple multifunctional stacks MST_CA, MST_CB, and MST_CC above the capacitor region AR_C can be separated from each other and can have the same or different dimensions. According to an embodiment, the multiple multifunctional stacks MST_T above the transistor region AR_T can have the same size, and the multiple multifunctional stacks MST_CA, MST_CB, and MST_CC above the capacitor region AR_C can be divided into a first group of MST_CA, a second group of MST_CB, and a third group of MST_CC. The first group of MST_CA, the second group of MST_CB, and the third group of MST_CC can have different dimensions. However, embodiments of this disclosure are not limited thereto. The multiple multifunctional stacks MST_T above the transistor region AR_T and the multiple multifunctional stacks MST_CA, MST_CB, and MST_CC above the capacitor region AR_C can be designed to have various dimensions. Each of the multiple multifunctional stacks MST_T above the transistor region AR_T and the multiple multifunctional stacks MST_CA, MST_CB, and MST_CC above the capacitor region AR_C may include padding as referenced above. Figure 5A Multiple grooves of the described multiple test patterns.

[0079] Figure 7This is a plan view illustrating a test pattern array in a transistor region according to an embodiment of the present disclosure.

[0080] Reference Figure 7 The first multifunctional stack MST_T1 and the second multifunctional stack MST_T2 can be arranged to overlap with the transistor region AR_T of the first doped semiconductor layer 110A. The first multifunctional stack MST_T1 and the second multifunctional stack MST_T2 can be adjacent to each other at a predetermined distance. Each of the first multifunctional stack MST_T1 and the second multifunctional stack MST_T2 can have, for example, […]. Figure 5A The multifunctional laminates MST shown have the same cross-sectional structure. For example, each of the first multifunctional laminate MST_T1 and the second multifunctional laminate MST_T2 may include the structure described above. Figure 5A The plurality of first conductive layers 143A are described. One of the first conductive layers 143A in the first multifunctional stack MST_T1 may be configured as a first gate electrode conductive layer GE1. One of the plurality of first conductive layers 143A in the second multifunctional stack MST_T2 may be configured as a second gate electrode conductive layer GE2. In the following text, terms related to... Figure 5A The components shown are similar to the components described above.

[0081] The first multifunctional laminate MST_T1 may include multiple first grooves GV1. The second multifunctional laminate MST_T2 may include multiple second grooves GV2. The first grooves GV1 and the second grooves GV2 may have the same or different areas in a planar view. Similar to... Figure 5A The third electrode conductive layer EL, as shown, and the first gate electrode conductive layer GE1 can extend between the first groove GV1 and the first doped semiconductor layer 110A. Similar to... Figure 5A The third electrode conductive layer EL and the second gate electrode conductive layer GE2 shown can extend between the second groove GV2 and the first doped semiconductor layer 110A. The first gate electrode conductive layer GE1 and the second gate electrode conductive layer GE2 can be connected to the first gate wiring 195A1 and the second gate wiring 195A2 respectively through the first contact plug 187A1 and the second contact plug 187A2.

[0082] Multiple first test patterns TP1 can be arranged in multiple first recesses GV1. Multiple second test patterns TP2 can be arranged in multiple second recesses GV2. The multiple first test patterns TP1 can include multiple first electrode pairs. The multiple first electrode pairs can include multiple first source electrodes 171E11 and multiple first drain electrodes 171E21. The multiple first source electrodes 171E11 can each be connected to multiple first source wirings 195E11. The multiple first drain electrodes 171E21 can each be connected to multiple first drain wirings 195E21. Similar to the multiple first test patterns TP1, the multiple second test patterns TP2 can include multiple second electrode pairs, and the multiple second electrode pairs include multiple second source electrodes 171E12 and multiple second drain electrodes 171E22. Similar to multiple first source electrodes 171E11 and multiple first drain electrodes 171E21, multiple second source electrodes 171E12 and multiple second drain electrodes 171E22 can each be connected to multiple second source wirings 195E12 and multiple second drain wirings 195E22.

[0083] Figure 8A and Figure 8B This is a plan view illustrating a first test pattern TP1 and a second test pattern TP2 above a transistor region according to an embodiment of the present disclosure.

[0084] like Figure 8A The first test pattern TP1 shown can correspond to, for example: Figure 7 The first test pattern TP1 is shown.

[0085] Reference Figure 8A The first test pattern TP1 may include a pair of first source electrodes 171E11 and first drain electrodes 171E21, a first filling insulating layer 165A1 corresponding to the first test pattern, a first inner semiconductor layer 163A1 corresponding to the first test pattern, and a first inner insulating layer 161A1 corresponding to the first test pattern. Similarly, as Figure 5A The first electrode 171E1 and the second electrode 171E2 shown, the paired first source electrode 171E11 and first drain electrode 171E21 can extend from the first inner semiconductor layer 163A1 in a first direction. Similarly, as Figure 5A The inner semiconductor layer 163A and the inner insulating layer 161A shown herein, the first inner semiconductor layer 163A1 and the first inner insulating layer 161A1 can be arranged along the path of the inner semiconductor layer 163A1 and the first inner insulating layer 161A1 as shown herein. Figure 7 The bottom surface of the first groove defined by the first gate electrode conductive layer GE1 extends.

[0086] like Figure 8B The second test pattern TP2 shown can correspond to Figure 7 The second test pattern TP2 is shown in the figure.

[0087] Reference Figure 8B The second test pattern TP2 may include a pair of second source electrodes 171E12 and second drain electrodes 171E22, a second filling insulating layer 165A2 corresponding to the second test pattern, a second inner semiconductor layer 163A2 corresponding to the second test pattern, and a second inner insulating layer 161A2 corresponding to the second test pattern. Similarly, as Figure 5A The first electrode 171E1 and the second electrode 171E2 shown, and the paired second source electrode 171E12 and second drain electrode 171E22, can extend from the second inner semiconductor layer 163A2 in a first direction. Similarly, as Figure 5A The inner semiconductor layer 163A and the inner insulating layer 161A shown, the second inner semiconductor layer 163A2 and the second inner insulating layer 161A2 can be along the direction of the inner semiconductor layer 163A2 and the inner insulating layer 161A2 as shown. Figure 7 The bottom surface of the second groove, defined by the second gate electrode conductive layer GE2, extends.

[0088] Reference Figure 8A and Figure 8B The length L1 of each of the first source electrode 171E11 and the first drain electrode 171E21, the length L2 of each of the second source electrode 171E12 and the second drain electrode 171E22, the distance D1 between the first source electrode 171E11 and the first drain electrode 171E21, and the distance D2 between the second source electrode 171E12 and the second drain electrode 171E22 can be designed to have various values. According to an embodiment, the length L1 of each of the first source electrode 171E11 and the first drain electrode 171E21 can be the same as or different from the length L2 of each of the second source electrode 171E12 and the second drain electrode 171E22. According to an embodiment, the distance D1 between the first source electrode 171E11 and the first drain electrode 171E21 can be the same as or different from the distance D2 between the second source electrode 171E12 and the second drain electrode 171E22. The length L1 of each of the first source electrode 171E11 and the first drain electrode 171E21 can define the channel width of the first transistor corresponding to the first test pattern TP1. The distance D1 between the first source electrode 171E11 and the first drain electrode 171E21 can define the channel length of the first transistor. The length L2 of each of the second source electrode 171E12 and the second drain electrode 171E22 can define the channel width of the second transistor corresponding to the second test pattern TP2. The distance D2 between the second source electrode 171E12 and the second drain electrode 171E22 can define the channel length of the second transistor.

[0089] Transistors with various structures can be derived from the above reference. Figure 7 , Figure 8A and Figure 8B The first test pattern TP1, the second test pattern TP2, the first gate electrode conductive layer GE1, and the second gate electrode conductive layer GE2 are formed. Each of the first inner semiconductor layer 163A1 and the second inner semiconductor layer 163A2 can be configured as the channel layer of the corresponding transistor. According to embodiments of this disclosure, transistors with various channel lengths and channel widths can be provided by changing the design conditions of the first test pattern TP1 and the second test pattern TP2. Therefore, in various embodiments, data about memory cells under various design conditions can be obtained through the first test pattern TP1 and the second test pattern TP2.

[0090] Figure 9 This is a plan view illustrating a test pattern array above a capacitor region AR_C according to an embodiment of the present disclosure.

[0091] Reference Figure 9 The first multifunctional stack MST_C1 and the second multifunctional stack MST_C2 can be arranged to overlap with the capacitor region AR_C of the first doped semiconductor layer 110A. The first multifunctional stack MST_C1 and the second multifunctional stack MST_C2 can be adjacent to each other at a predetermined distance. Each of the first multifunctional stack MST_C1 and the second multifunctional stack MST_C2 can have, for example, […]. Figure 5A The multifunctional laminates MST shown have the same cross-sectional structure. For example, each of the first multifunctional laminate MST_C1 and the second multifunctional laminate MST_C2 may include the structure described above. Figure 5A The plurality of first conductive layers 143A are described. One of the first conductive layers 143A in the first multifunctional stack MST_C1 can be configured as a first lower electrode conductive layer BE1. One of the plurality of first conductive layers 143A in the second multifunctional stack MST_C2 can be configured as a second lower electrode conductive layer BE2. In the following text, terms related to... Figure 5A The components shown are similar to the components described above.

[0092] As referenced above Figure 7 The first multifunctional stack MST_C1 may include a plurality of first grooves GV1' filled with a plurality of first test patterns TP1', and the second multifunctional stack MST_C2 may include a plurality of second grooves GV2' filled with a plurality of second test patterns TP2'. Similar to... Figure 5A The third electrode conductive layer EL shown can extend between the first groove GV1′ and the first doped semiconductor layer 110A. Similar to... Figure 5AThe third electrode conductive layer EL and the second lower electrode conductive layer BE2 shown can extend between the second groove GV2′ and the first doped semiconductor layer 110A.

[0093] The first lower electrode conductive layer BE1 and the second lower electrode conductive layer BE2 can be connected to the first capacitor wiring 195Aa together with their corresponding first contact plugs 187A1′ and second contact plugs 187A2′.

[0094] Each of the plurality of first test patterns TP1′ and the plurality of second test patterns TP2′ can have the same as Figure 5A The test pattern TP shown has the same cross-sectional structure. Although in Figure 9 Not shown, but each of the plurality of first test patterns TP1′ and second test patterns TP2′ may include a corresponding inner insulating layer, an inner semiconductor layer and a filling insulating layer, as referenced above. Figure 5A As described.

[0095] Multiple first test patterns TP1′ may include multiple first electrodes 171E11′ and multiple second electrodes 171E21′ of multiple first electrode pairs. Multiple second test patterns TP2′ may include multiple first electrodes 171E12′ and multiple second electrodes 171E22′ of multiple second electrode pairs. (Refer to the above.) Figure 5A As described above, in each of the first electrode pairs, the first electrode 171E11′ and the second electrode 171E21′ can extend from their corresponding inner semiconductor layer in a first direction to pass through their corresponding filling insulating layer. (Referring to the above...) Figure 5A The first electrode 171E12′ and the second electrode 171E22′ of each of the second electrode pairs can extend from their corresponding inner liner semiconductor layer in a first direction to pass through their corresponding filling insulating layer.

[0096] The plurality of first electrodes 171E11′ and the plurality of second electrodes 171E21′ of the first electrode pair can be commonly connected to the second capacitor wiring 195L. Additionally, the plurality of first electrodes 171E12′ and the plurality of second electrodes 171E22′ of the plurality of second electrode pairs can be commonly connected to the second capacitor wiring 195L. According to an embodiment, the second capacitor wiring 195L may include a first line pattern portion 195E1_P1, a second line pattern portion 195E2_P2, and a connecting pattern portion 195C connecting the first line pattern portion 195E1_P1 and the second line pattern portion 195E2_P2. The first line pattern portion 195E1_P1 can be connected to the first electrodes 171E11′ and 171E12′ of the first electrode pair arranged adjacent to each other. The second line pattern portion 195E2_P2 can be connected to the second electrodes 171E21′ and 171E22′ of the first electrode pair arranged adjacent to each other.

[0097] The first capacitor wiring is 195Aa and the second capacitor wiring is 195L, not limited to... Figure 9 As shown in the diagram. For example, the first capacitor wiring connected to the first lower electrode conductive layer BE1 and the first capacitor wiring connected to the second lower electrode conductive layer BE2 can be separated from each other. The second capacitor wiring connected to the plurality of first electrodes 171E11′ and the plurality of second electrodes 171E21′ of the first electrode pair and the second capacitor wiring connected to the plurality of first electrodes 171E12′ and the plurality of second electrodes 171E22′ of the second electrode pair can be separated from each other. The first capacitor wiring 195Aa and the second capacitor wiring 195L can have various designs to provide various capacitances.

[0098] According to reference Figure 9 The described implementation can provide various capacitors.

[0099] Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14 , Figure 15 , Figure 16A , Figure 16B , Figure 17A and Figure 17B This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 15 , Figure 16A and Figure 17A This illustrates the formation in, for example Figure 1 The diagram shows a cross-sectional view of a structure on a portion of the scribing region SR or a portion of the chip region CR of the substrate 101, which is set as a test area. Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14 , Figure 16B and Figure 17B This illustrates the formation in, for example Figure 1 A cross-sectional view of the structure on another part of the chip region CR of the substrate 101 shown.

[0100] Reference Figure 10A and Figure 10B This can form the following structure. The lower structure can be separated by a lower insulating layer 215 and can include a first doped semiconductor layer 210A and a second doped semiconductor layer 210B spaced apart from each other. The first doped semiconductor layer 210A and the second doped semiconductor layer 210B can include, as referenced above... Figure 2 The first doped semiconductor layer 110A and the second doped semiconductor layer 110B are made of the same material.

[0101] Subsequently, a preliminary stacked structure 240 can be formed by alternately stacking multiple interlayer insulating layers 241 and multiple conductive layers 243 on the lower structure. The multiple interlayer insulating layers 241 may include silicon oxide layers. The multiple conductive layers 243 may include at least one of a doped semiconductor layer, a metal, a conductive metal nitride layer, and a transition metal.

[0102] Reference Figure 11A and Figure 11B Through etching, such as Figure 10A and 10B The preliminary stacked structure 240 shown can be separated into a multifunctional stack 240A and a gate stack 240B. More specifically, as Figure 10A and Figure 10B The multiple interlayer insulating layers 241 shown can be separated into multiple first interlayer insulating layers 241A of a multifunctional stack 240A and multiple second interlayer insulating layers 241B of a gate stack 240B. For example... Figure 10A and Figure 10B The plurality of conductive layers 243 shown can be separated into a plurality of first conductive layers 243A of a multifunctional stack 240A and a plurality of second conductive layers 243B of a gate stack 240B.

[0103] According to an embodiment, a plurality of second conductive layers 243B can be configured as gate electrodes of a NAND flash memory cell array. The lowest second conductive layer among the plurality of second conductive layers 243B can be used as a source select line 243SL. The upper second conductive layer above the source select line 243SL can be used as a word line and a drain select line.

[0104] One of the first conductive layers 243A can be used as an electrode layer 243EL. According to an embodiment, the lowest first conductive layer among the plurality of first conductive layers 243A can be configured as an electrode layer 243EL. However, embodiments of this disclosure are not limited thereto. At least one of the upper first conductive layers above the lowest first conductive layer can be configured as an electrode layer.

[0105] The multifunctional stack 240A can overlap with the first doped semiconductor layer 210A. The first doped semiconductor layer 210A can overlap with the multifunctional stack 240A, which is separated into multiple structures. The structure and size of the multifunctional stack 240A after separation can vary. Additionally, as described above... Figure 6 The discrete structure formed by the multifunctional stack 240A can be arranged to overlap with the capacitor region and the transistor region. The gate stack 240B can overlap with the second doped semiconductor layer 210B.

[0106] A stepped structure can be formed on each of the multifunctional stack 240A and the gate stack 240B. The process of forming the stepped structure on each of the multifunctional stack 240A and the gate stack 240B may include forming a mask pattern (not shown) on each of the multifunctional stack 240A and the gate stack 240B, and repeatedly performing a trimming cycle on the electrode contact region of the multifunctional stack 240A and the gate contact region of the gate stack 240B. Each trimming cycle may include etching multiple interlayer insulating layers 241 and multiple conductive layers 243 by using the mask pattern as an etch stop, and reducing the size of the mask pattern.

[0107] After forming the stepped structure, the mask pattern can be removed, and a first insulating layer 251 can be formed. The first insulating layer 251 can cover the stepped structure of the multifunctional stack 240A and the stepped structure of the gate stack 240B. The surface of the first insulating layer 251 can be planarized. A second insulating layer 253 can be formed on the first insulating layer 251. The second insulating layer 253 may include a material that has etch selectivity relative to the first insulating layer 251. According to an embodiment, the first insulating layer 251 may include a silicon oxide layer, while the second insulating layer 253 may include a silicon nitride layer.

[0108] A recess 255 can be formed in the multifunctional stack 240A. The recess 255 can be deep enough not to penetrate the electrode layer 243EL. The bottom surface 255B of the recess 255 can extend along the electrode layer 243EL. The recess 255 can be formed simultaneously with the formation of the first vertical via 257A in the gate stack 240B. In other words, the recess 255 and the first vertical via 257A can be formed concurrently.

[0109] The process of forming the recess 255 and the first vertical hole 257A may include forming a first mask layer (not shown) including an opening defining the recess 255 and the first vertical hole 257A, and using the first mask layer as an etch stop to etch the second insulating layer 253, the first insulating layer 251, the multifunctional stack 240A, and the gate stack 240B. An etching process may be performed to expose the electrode layer 243EL of the multifunctional stack 240A. The bottom surface of the first vertical hole 257A may be defined by a second conductive layer 243B disposed at the same height as the electrode layer 243EL. According to an embodiment, the bottom surface of the first vertical hole 257A may be defined by the upper surface of the source select line 243SL.

[0110] Reference Figure 12A and Figure 12B This can form a filling groove 255 and make it as Figure 11B The first vertical aperture 257A shown exposes a second mask layer 259. The second mask layer 259 can be formed on the first mask layer, or it can be formed after the first mask layer is removed. Subsequently, a portion of the gate stack 240B can be etched using an etching process that uses the second mask layer 259 as an etch barrier. The portion of the gate stack etched by the etching process can refer to the portion etched by, for example... Figure 11B The portion of the bottom surface of the first vertical hole 257A shown is exposed.

[0111] The etching process described above forms a second vertical hole 257B with a greater depth than the recess 255. Multiple second interlayer insulating layers 241B and multiple second conductive layers 243B of the gate stack 240B can be penetrated by the second vertical hole 257B, and the second doped semiconductor layer 210B can be exposed through the second vertical hole 257B. Subsequently, the second mask layer 259 can be removed.

[0112] Reference Figure 13A and Figure 13B A preliminary test pattern 260A can be formed in the groove 255. The preliminary test pattern 260A can be provided by a process of forming a preliminary unit plug 260B in the second vertical hole 257B.

[0113] According to an embodiment, the process of forming the preliminary test pattern 260A and the preliminary cell plug 260B may include: forming a preliminary memory layer 261 on the surface of the recess 255 and the surface of the second vertical hole 257B; removing a portion of the preliminary memory layer 261 from the bottom surface 257B_B of the second vertical hole 257B to expose the second doped semiconductor layer 210B, and forming a semiconductor layer 263 on the preliminary memory layer 261; filling the central region of the recess 255 and the central region of the second vertical hole 257B exposed by the semiconductor layer 263 with an insulating layer 265; and performing a planarization process to expose the second insulating layer 253.

[0114] The initial memory layer 261 may include a data storage layer, such as a floating gate layer, an insulating layer comprising conductive nanodots, a charge trapping layer, a ferroelectric layer, or a phase transition layer. According to an embodiment, the initial memory layer 261 may include, for example... Figure 4A and Figure 4B The barrier insulating layer BI, charge trapping layer CTL, and tunnel insulating layer TI are shown. Semiconductor layer 263 may include semiconductor materials such as silicon, germanium, or combinations thereof.

[0115] Before removing a portion of the initial memory layer 261, a mask layer (not shown) may be formed to protect the side portion 257B_S of the second vertical via 257B and a portion of the initial memory layer 261 on the surface of the recess 255. The mask layer may be removed before forming the semiconductor layer 263. The semiconductor layer 263 may be formed after exposing the second doped semiconductor layer 210B. Therefore, the semiconductor layer 263 may be connected to the second doped semiconductor layer 210B.

[0116] Through a planarization process, the initial memory layer 261 can be separated into an inner insulating layer 261A on the surface of the recess 255 and a memory layer 261B on the side 257B_S of the second vertical hole 257B. The semiconductor layer 263 can be separated into an inner semiconductor layer 263A on the inner insulating layer 261A and a vertical semiconductor layer 263B on the memory layer 261B. The insulating layer 265 can be divided into a filling insulating layer 265A in the recess 255 and a core insulating layer 265B in the second vertical hole 257B.

[0117] Reference Figure 14 A portion of the core insulating layer 265B can be etched and the area where the core insulating layer 265B has been removed can be filled with a conductive overlay pattern 267. The conductive overlay pattern 267 may include semiconductor material doped with impurities. The impurities in the conductive overlay pattern 267 may be dispersed into the vertical semiconductor layer 263B adjacent to the conductive overlay pattern 267.

[0118] Reference Figure 15A first electrode 271E1 and a second electrode 271E2 can be formed in the groove 255. The first electrode 271E1 and the second electrode 271E2 can pass through the filling insulating layer 265A and be connected to the inner liner semiconductor layer 263A. The first electrode 271E1 and the second electrode 271E2 may include doped semiconductor material.

[0119] Reference Figure 16A and Figure 16B At least one insulating layer may be formed on the second insulating layer 253. According to an embodiment, a third insulating layer 281, a fourth insulating layer 283, and a fifth insulating layer 285 may be formed on the second insulating layer 253. The fourth insulating layer 283 may include a material having etch selectivity relative to the third insulating layer 281 and the fifth insulating layer 285. According to an embodiment, the third insulating layer 281 and the fifth insulating layer 285 may include silicon oxide layers, while the fourth insulating layer 283 may include a silicon nitride layer.

[0120] Subsequently, contact groups 287A, 289A, 289B, 287B, and 291 can be formed. Contact groups 287A, 289A, 289B, 287B, and 291 may include a contact plug 287A connected to electrode layer 243EL, a gate contact plug 287B connected to conductive layer 243B, a first upper contact plug 289A and a second upper contact plug 289B connected to first electrode 271E1 and second electrode 271E2, and a third upper contact plug 291 connected to conductive overlay pattern 267.

[0121] According to one embodiment, the process of forming contact groups 287A, 289A, 289B, 287B, and 291 may include an etching process that uses an etching process to form contact holes of different depths by using an etching process that opens the regions where contact groups 287A, 289A, 289B, 287B, and 291 are formed as etching barriers, and a process of filling the contact holes with a conductive material. According to another embodiment, the process of forming contact groups 287A, 289A, 289B, 287B, and 291 may include a process of forming contact plugs 287A and gate contact plugs 287B, and a process of forming a first upper contact plug 289A, a second upper contact plug 289B, and a third upper contact plug 291.

[0122] In addition to the above-described embodiments, the processes for forming the third insulating layer 281, the fourth insulating layer 283, and the fifth insulating layer 285, as well as the processes for forming contact groups 287A, 289A, 289B, 287B, and 291, can be divided into unit processes according to various schemes.

[0123] Reference Figure 17A and Figure 17BA sixth insulating layer 293 may be formed on the fifth insulating layer 285 to cover contact groups 287A, 289A, 289B, 287B and 291. Wiring groups 295A, 295E1, 295E2, 295B and 295BL may be formed to pass through the sixth insulating layer 293.

[0124] Cabling groups 295A, 295E1, 295E2, 295B, and 295BL can be connected to contact groups 287A, 289A, 289B, 287B, and 291. The layout of cabling groups 295A, 295E1, 295E2, 295B, and 295BL can be referenced as described above. Figure 7 and Figure 9 The changes described.

[0125] Based on the preliminary stacked structure 240, including as follows Figure 10A and Figure 10B The example shown, illustrating a plurality of interlayer insulating layers 241 and a plurality of conductive layers 243 stacked alternately, describes the above-described manufacturing method. However, embodiments of this disclosure are not limited thereto. According to another embodiment, the initial stacked structure may include a plurality of interlayer insulating layers and a plurality of sacrificial layers stacked alternately. The plurality of sacrificial layers may include a material having etch selectivity relative to the plurality of interlayer insulating layers. For example, the plurality of interlayer insulating layers may include silicon oxide layers and the plurality of sacrificial layers may include silicon nitride layers. The plurality of sacrificial layers may be replaced by a plurality of conductive layers by a replacement process. The process described above can be performed... Figure 14 and Figure 15 The replacement process is then performed using a slit for replacement.

[0126] Figure 18 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0127] Reference Figure 18 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0128] The memory controller 1110 may include a three-dimensional cell array structure and a test pattern in a multifunctional stack. The multifunctional stack and the test pattern may have a structure similar to the three-dimensional memory cell array structure. More specifically, the multifunctional stack may include multiple interlayer insulating layers and multiple conductive layers alternately stacked over a doped semiconductor layer, and may include a recess. Since the multifunctional stack is similar to a gate stack with vertical holes in a three-dimensional cell array structure, the multifunctional stack can be formed simultaneously with the gate stack. The test pattern may include an inner insulating layer on the bottom surface of the recess, an inner semiconductor layer on the inner insulating layer, and a first electrode and a second electrode spaced apart from each other in the recess. The test pattern may be formed in the vertical holes by a process of forming cell plugs.

[0129] The memory device 1120 may be a multi-chip package including multiple flash memory chips.

[0130] Memory controller 1110 can be configured to control memory device 1120 and may include static random access memory (SRAM) 1111, central processing unit (CPU) 1112, host interface 1113, error correction block 1114, and memory interface 1115. SRAM 1111 can serve as operating memory for CPU 1112, which performs overall control operations for data exchange with memory controller 1110. Host interface 1113 may include a data exchange protocol for a host connected to memory system 1100. Error correction block 1114 can detect and correct errors in data read from memory device 1120, and memory interface 1115 can perform interface connections with memory device 1120. Additionally, memory controller 1110 may include read-only memory (ROM) storing code data for connection to the host interface.

[0131] Figure 19 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0132] Reference Figure 19 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0133] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 and the memory controller 1211 may be compatible with those described above. Figure 18 The memory device 1120 and memory controller 1110 described are configured in the same manner.

[0134] According to embodiments of the present disclosure, a test pattern including an inner insulating layer and an inner semiconductor layer can be formed in a multifunctional laminate by using a process for forming a three-dimensional memory cell array structure. Therefore, in various embodiments, the reliability of data obtained using the test pattern according to the present disclosure can be improved.

[0135] Cross-reference to related applications

[0136] This application claims priority to Korean Patent Application No. 10-2022-0082182, filed with the Korean Intellectual Property Office on July 5, 2022, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first doped semiconductor layer and a second doped semiconductor layer, each of the first doped semiconductor layer and the second doped semiconductor layer including an upper surface facing a first direction, the first doped semiconductor layer and the second doped semiconductor layer being spaced apart from each other; A multifunctional stack comprising a plurality of first interlayer insulating layers and a plurality of first conductive layers alternately stacked on top of a first doped semiconductor layer in a first direction, the multifunctional stack including grooves; An inner insulating layer is located on the bottom surface of the groove; An inner semiconductor layer is located on the inner insulating layer; A first electrode, which is located in the groove and extends from the inner semiconductor layer in the first direction; A second electrode is located in the groove and extends from the inner semiconductor layer in the first direction, wherein the first electrode and the second electrode are spaced apart from each other; A gate stack comprising a plurality of second interlayer insulating layers and a plurality of second conductive layers alternately stacked on a second doped semiconductor layer in a first direction, the gate stack comprising a vertical via; A memory layer located on the side of the vertical aperture; and A vertical semiconductor layer is disposed on the memory layer.

2. The semiconductor memory device according to claim 1, in, At least one of the plurality of first conductive layers is located between the inner insulating layer and the first doped semiconductor layer, and Each of the vertical aperture, the memory layer, and the vertical semiconductor layer extends through the plurality of second conductive layers from the uppermost second conductive layer to the lowermost second conductive layer.

3. The semiconductor memory device according to claim 1, wherein, The bottom surface of the groove is at a higher height in the first direction than the bottom surface of the vertical hole.

4. The semiconductor memory device according to claim 1, in, The multifunctional stack is arranged at the same height as the gate stack. Wherein, the plurality of first interlayer insulating layers comprise the same insulating material as the plurality of second interlayer insulating layers, and The plurality of first conductive layers comprises the same conductive material as the plurality of second conductive layers.

5. The semiconductor memory device according to claim 1, wherein, The inner insulating layer comprises the same material layer as the memory layer.

6. The semiconductor memory device according to claim 1, wherein, Each of the inner insulating layer and the memory layer includes a floating gate layer, an insulating layer including conductive nanodots, a charge trapping layer, a ferroelectric layer, or a phase change layer.

7. The semiconductor memory device according to claim 1, wherein, The inner semiconductor layer comprises the same semiconductor material as the vertical semiconductor layer.

8. The semiconductor memory device according to claim 1, wherein, Each of the inner insulating layer and the inner semiconductor layer extends along the side of the groove.

9. The semiconductor memory device of claim 1, further comprising: A source wiring is provided, which is connected to the first electrode; as well as Drain wiring, which is connected to the second electrode.

10. The semiconductor memory device of claim 1, further comprising capacitor wiring connected to the first electrode and the second electrode.

11. The semiconductor memory device according to claim 1, in, The plurality of first conductive layers include a third electrode conductive layer, and The third electrode conductive layer defines the bottom surface of the groove.

12. The semiconductor memory device of claim 11, further comprising: A contact plug that extends from the third electrode conductive layer in the first direction; as well as Wiring is provided that connects to the contact plug and transmits signals to the third electrode conductive layer.

13. A semiconductor memory device, the semiconductor memory device comprising: A doped semiconductor layer, the doped semiconductor layer including an upper surface facing a first direction; A multifunctional stack comprising a plurality of interlayer insulating layers and a plurality of conductive layers alternately stacked on top of the doped semiconductor layer in the first direction, the multifunctional stack including grooves; An inner insulating layer is located on the bottom surface of the groove; An inner semiconductor layer is located on the inner insulating layer; as well as A first electrode, which is located in the groove and extends from the inner semiconductor layer in the first direction; as well as A second electrode, located within the groove and extending from the inner semiconductor layer in the first direction, wherein the first electrode and the second electrode are spaced apart from each other. At least one of the plurality of conductive layers is located between the inner insulating layer and the doped semiconductor layer.

14. The semiconductor memory device according to claim 13, wherein, Each of the inner insulating layer and the inner semiconductor layer extends along the side of the groove.

15. The semiconductor memory device of claim 13, further comprising: A source wiring is provided, which is connected to the first electrode; as well as Drain wiring, which is connected to the second electrode.

16. The semiconductor memory device of claim 13, further comprising capacitor wiring connected to the first electrode and the second electrode.

17. The semiconductor memory device according to claim 13, in, The plurality of conductive layers include a third electrode conductive layer, and The third electrode conductive layer defines the bottom surface of the groove.

18. The semiconductor memory device of claim 17, further comprising: A contact plug that extends from the third electrode conductive layer in the first direction; as well as Wiring is provided that connects to the contact plug and transmits signals to the third electrode conductive layer.

19. The semiconductor memory device according to claim 18, in, The plurality of conductive layers are stacked to define a stepped structure, and The contact plug is connected to the end of the third electrode conductive layer corresponding to the stepped structure.

20. A semiconductor memory device, the semiconductor memory device comprising: A first doped semiconductor layer and a second doped semiconductor layer, each including an upper surface facing a first direction, are spaced apart from each other. The test group overlaps with the first doped semiconductor layer; as well as A three-dimensional memory cell array structure, which overlaps with the second doped semiconductor layer. The test group includes: Multiple multifunctional stacks include multiple interlayer insulating layers and multiple conductive layers alternately stacked on top of a first doped semiconductor layer in a first direction, and the multiple multifunctional stacks include multiple grooves; Multiple inner insulating layers are respectively arranged on multiple bottom surfaces corresponding to the multiple grooves; Multiple inner semiconductor layers, wherein the multiple inner semiconductor layers are respectively disposed on the multiple inner insulating layers; Multiple insulating layers are filled and arranged in the multiple grooves; and Multiple electrode pairs, which pass through the multiple filled insulating layers and are connected to the multiple inner liner semiconductor layers.

21. The semiconductor memory device of claim 20, wherein, Each of the plurality of inner insulating layers and the plurality of inner semiconductor layers extends along the side of the corresponding groove in the plurality of grooves.

22. The semiconductor memory device of claim 20, wherein, The first doped semiconductor layer includes a transistor region and a capacitor region.

23. The semiconductor memory device according to claim 22, in, The plurality of multifunctional stacks include a first multifunctional stack above the transistor region. The plurality of grooves includes a plurality of first grooves in the first multifunctional laminate. The first multifunctional stack includes a gate electrode conductive layer located between the first doped semiconductor layer and the plurality of first grooves. The plurality of inner semiconductor layers include a plurality of first inner semiconductor layers corresponding to the plurality of first grooves. The plurality of electrode pairs includes a plurality of first electrode pairs corresponding to the plurality of inner semiconductor layers, and The plurality of first electrode pairs include a plurality of first source electrodes corresponding to the plurality of inner semiconductor layers and a plurality of first drain electrodes corresponding to the plurality of first inner semiconductor layers.

24. The semiconductor memory device of claim 23, further comprising: A gate wiring connection connected to the gate electrode conductive layer; Multiple source wirings are provided, each of which is connected to one of the multiple first source electrodes. as well as Multiple drain wires are connected to the multiple first drain electrodes respectively.

25. The semiconductor memory device according to claim 22, in, The plurality of multifunctional stacks include a first multifunctional stack and a second multifunctional stack above the transistor region. The plurality of grooves includes a first groove in the first multifunctional laminate and a second groove in the second multifunctional laminate. The first multifunctional stack includes a first gate electrode conductive layer located between the first doped semiconductor layer and the first groove. The second multifunctional stack includes a second gate electrode conductive layer located between the first doped semiconductor layer and the second trench. The plurality of inner semiconductor layers include a first inner semiconductor layer in the first groove and a second inner semiconductor layer in the second groove, and The plurality of electrode pairs include a first electrode pair and a second electrode pair. The first electrode pair includes a first source electrode and a first drain electrode extending from the first inner semiconductor layer in the first direction. The second electrode pair includes a second source electrode and a second drain electrode extending from the second inner semiconductor layer in the first direction.

26. The semiconductor memory device of claim 25, further comprising: A first gate wiring is connected to the first gate electrode conductive layer; A second gate wiring is connected to the second gate electrode conductive layer; A first source wiring is connected to the first source electrode; The second source wiring is connected to the second source electrode; A first drain wiring is connected to the first drain electrode; as well as The second drain wiring is connected to the second drain electrode.

27. The semiconductor memory device according to claim 25, wherein, The distance between the first source electrode and the first drain electrode is different from the distance between the second source electrode and the second drain electrode.

28. The semiconductor memory device according to claim 22, in, The plurality of multifunctional stacks include a first multifunctional stack that overlaps with the capacitor region. The plurality of grooves includes a plurality of first grooves passing through the first multifunctional laminate. The first multifunctional stack includes a lower electrode conductive layer located between the first doped semiconductor layer and the plurality of first grooves. Wherein, the plurality of inner semiconductor layers include a plurality of first inner semiconductor layers corresponding to the plurality of first grooves, and The plurality of electrode pairs include a plurality of first electrode pairs corresponding to the plurality of first inner semiconductor layers.

29. The semiconductor memory device of claim 28, further comprising: A first capacitor wiring is connected to the lower electrode conductive layer; as well as A second capacitor wiring is connected to the plurality of first electrode pairs.

30. The semiconductor memory device according to claim 22, in, The plurality of multifunctional stacks include a first multifunctional stack and a second multifunctional stack that overlap with the capacitor region. The plurality of grooves include a first groove in the first multifunctional laminate and a second groove in the second multifunctional laminate. The first multifunctional laminate includes a first lower electrode conductive layer located between the first doped semiconductor layer and the first groove. The second multifunctional stack includes a second lower electrode conductive layer located between the first doped semiconductor layer and the second groove. Wherein, the plurality of inner semiconductor layers include a first inner semiconductor layer in the first groove and a second inner semiconductor layer in the second groove, and The plurality of electrode pairs include a first electrode pair extending from the first inner semiconductor layer in the first direction and a second electrode pair extending from the second inner semiconductor layer in the first direction.

31. The semiconductor memory device of claim 30, further comprising: A first contact plug extends from the first lower electrode conductive layer in the first direction; A second contact plug extends in the first direction from the second lower electrode conductive layer; A first capacitor wiring is connected to the first contact plug and the second contact plug; as well as A second capacitor wiring is connected to the first electrode pair and the second electrode pair.

32. A method for manufacturing a semiconductor memory device, the method comprising the following steps: Forming a multifunctional stack including grooves and a gate stack including vertical holes; A memory layer is formed on the side of the vertical hole; When forming the memory layer, an inner insulating layer is formed on the surface of the groove; A vertical semiconductor layer is formed on the memory layer; When forming the vertical semiconductor layer, an inner semiconductor layer is formed on the inner insulating layer; as well as A first electrode and a second electrode are formed in the groove, which are connected to the inner liner semiconductor layer and spaced apart from each other.

33. The method according to claim 32, in, The multifunctional stack and the gate stack are formed on a first doped semiconductor layer and a second doped semiconductor layer that are separated from each other. The multifunctional stack includes a plurality of first interlayer insulating layers and a plurality of first conductive layers alternately stacked on the first doped semiconductor layer, and The gate stack includes a plurality of second interlayer insulating layers and a plurality of second conductive layers alternately stacked on the second doped semiconductor layer.

34. The method according to claim 33, in, One of the plurality of first conductive layers includes an electrode layer extending along the bottom surface of the groove, and The vertical hole passes through the plurality of second interlayer insulating layers and the plurality of second conductive layers to expose the second doped semiconductor layer.

35. The method according to claim 34, wherein, The vertical semiconductor layer is connected to the second doped semiconductor layer.

36. The method according to claim 32, wherein, The vertical hole has a greater depth than the groove.

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