A method for analyzing abnormal sound of a ceiling screen motor

Abstract

The application provides a ceiling screen motor abnormal sound analysis method, which comprises the following steps: S1, driving the motor to realize forward rotation or reverse rotation of the motor according to the corresponding unfolding button or folding button; S2, collecting the abnormal sound emitted by the planetary gear or / and the driving motor when the driving motor rotates forward or reversely. The application controls the rotation of the driving motor through the button to determine whether the structure of the application has abnormal sound.

Description

Technical Field

[0001] This invention relates to the field of ceiling-mounted screen technology, and in particular to a method for analyzing abnormal noise from a ceiling-mounted screen motor. Background Technology

[0002] Traditional gearboxes, with their central shaft passing through the planet carriers of each planetary gear set, are susceptible to noise discontinuity due to the shaft's free-moving nature and the rotation of the planetary gear sets. Furthermore, inter-component noise and other sound distortions can easily occur, amplified through the gearbox, electric sun visor, or car roof cavities, impacting ride comfort. Therefore, a noise analysis method that can reduce noise is urgently needed. Summary of the Invention

[0003] This invention aims to at least solve the technical problems existing in the prior art, and in particular, it innovatively proposes a method for analyzing abnormal noise of ceiling screen motors.

[0004] To achieve the above-mentioned objectives of this invention, this invention provides a method for analyzing abnormal noise from a ceiling-mounted screen motor, comprising the following steps:

[0005] S1, the drive motor rotates forward or reverse according to the unfold or fold button;

[0006] S2, when the drive motor is rotating in both directions, collect abnormal noises emitted by the planetary gears and / or the drive motor.

[0007] In a preferred embodiment of the present invention, step S2 further includes determining whether the abnormal noise emitted by the planetary gear and / or the drive motor is greater than or equal to a preset noise value:

[0008] If the abnormal noise emitted by the planetary gears and / or the drive motor is greater than or equal to the preset noise value, then change the bearing type;

[0009] If the abnormal noise emitted by the planetary gear and / or the drive motor is less than the preset noise value, then the planetary gear meets the factory standard.

[0010] In a preferred embodiment of the present invention, the bearing is a ball bearing.

[0011] In a preferred embodiment of the present invention, step S1 includes the following steps: The method for starting the drive motor in step S1 includes the following steps:

[0012] S11, Controller U6 determines whether its wake-up terminal PTD5 receives a first-level signal or a second-level signal:

[0013] If the wake-up terminal PTD5 of controller U6 receives the first level signal, controller U6 will wake up and proceed to the next step.

[0014] If the wake-up terminal PTD5 of controller U6 receives the second level signal, controller U6 will enter sleep mode and return to step S11;

[0015] S12, the control terminal PTD16 of controller U6 inputs an enable signal to the enable terminal EN of DC-DC buck converter U2; at this time, the power supply +VBATT input to DC-DC buck converter U2 is converted into a stable power supply +3.3VSW for output through DC-DC buck converter U2; proceed to the next step;

[0016] S13, the control terminal PTC2 of controller U6 inputs a conduction level to the base of transistor Q10, and transistor Q10 is in the conduction state. At this time, the base voltage of transistor Q11 is pulled low, and transistor Q11 is in the conduction state. The collector of transistor Q10 outputs power supply PWR_KEY.

[0017] S14, Controller U6 determines whether the unfold or fold button has been pressed:

[0018] If you click the expand button, proceed to the next step;

[0019] If the fold button is pressed, proceed to step S16;

[0020] S15, Determine if the angle of the rotation axis is within the folding angle threshold:

[0021] If the angle of the rotating shaft is within the folding angle threshold, the controller U6 sends a control signal to the three-phase pre-drive module and the motor drive module. After receiving the control signal sent by the controller U6, the three-phase pre-drive module and the motor drive module drive the motor to rotate forward. When the angle of rotation of the rotating shaft reaches the preset rotation unfolding angle threshold, the drive motor stops working; return to step S14.

[0022] If the angle of the rotation axis is not at the folding angle threshold, that is, at the preset rotation unfolding angle threshold, the drive motor will not work; return to step S14;

[0023] S16, Determine whether the angle of the rotation axis is within the preset rotation unfolding angle threshold:

[0024] If the angle of the rotating shaft is within the preset rotation unfolding angle threshold, the controller U6 sends a control signal to the three-phase pre-drive module and the motor drive module. After receiving the control signal sent by the controller U6, the three-phase pre-drive module and the motor drive module drive the motor to rotate forward. When the angle of rotation of the rotating shaft reaches the preset rotation unfolding angle threshold, the drive motor stops working; return to step S14.

[0025] If the angle of the rotation axis is not at the preset rotation unfolding angle threshold, that is, at the folding angle threshold, then the drive motor will not work; return to step S14.

[0026] In summary, by adopting the above technical solution, this invention uses button control to drive the motor to determine whether there is any abnormal noise in the applied structure.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0029] Figure 1 This is a perspective view of the present invention.

[0030] Figure 2 This is a cross-sectional view of the present invention.

[0031] Figure 3 This is a perspective view of the internal gear ring of the present invention.

[0032] Figure 4 This is a perspective view of the rear end cover of the present invention.

[0033] Figure 5 This is a perspective view of the planet carrier of the first-stage planetary gear set of the present invention.

[0034] Figure 6 This is a schematic block diagram illustrating the connection of the present invention.

[0035] Figure 7 This is a schematic block diagram of the power module circuit connection of the present invention.

[0036] Figure 8 This is a schematic diagram of the circuit connection of the wake-up module of the present invention.

[0037] Figure 9 This is a schematic diagram of the circuit connection of the voltage sampling module of the present invention.

[0038] Figure 10 This is a schematic diagram of the circuit connection of the voltage sampling module of the present invention.

[0039] Figure 11 This is a schematic diagram of the circuit connection of the button module of the present invention.

[0040] Figure 12 This is a schematic diagram of the circuit connection of the CAN communication module of the present invention.

[0041] Figure 13This is a schematic diagram of the circuit connection of the deserializer module of the present invention.

[0042] Figure 14 This is a schematic diagram of the circuit connection of the deserializer module of the present invention.

[0043] Figure 15 This is a schematic diagram of the circuit connection of the deserializer module of the present invention.

[0044] Figure 16 This is a schematic diagram of the circuit connection of the J2 module of the TFT screen interface of the present invention.

[0045] Figure 17 This is a schematic diagram of the circuit connection of the controller module of the present invention.

[0046] Figure 18 This is a schematic diagram of the circuit connection of the controller module of the present invention.

[0047] Figure 19 This is a schematic diagram of the circuit connection of the controller module of the present invention.

[0048] Figure 20 This is a schematic diagram of the circuit connection of the screen backlight module of the present invention.

[0049] Figure 21 This is a schematic diagram of the circuit connection of the three-phase pre-drive module of the present invention.

[0050] Figure 22 This is a schematic diagram of the circuit connection of the J1 module of the present invention.

[0051] Figure 23 This is a schematic diagram of the circuit connection of the motor drive module of the present invention.

[0052] Figure 24 This is a schematic diagram of the circuit connection of the current sampling module of the present invention. Figure 25 This is a schematic flowchart of the present invention. Detailed Implementation

[0053] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0054] This invention provides a method for analyzing abnormal noise from a ceiling-mounted screen motor, such as... Figure 25 As shown, it includes the following steps:

[0055] S1, the drive motor rotates forward or reverse according to the unfold or fold button;

[0056] S2, when the drive motor is rotating in both directions, collect abnormal noises emitted by the planetary gears and / or the drive motor.

[0057] In a preferred embodiment of the present invention, step S2 further includes determining whether the abnormal noise emitted by the planetary gear and / or the drive motor is greater than or equal to a preset noise value:

[0058] If the abnormal noise emitted by the planetary gears and / or the drive motor is greater than or equal to the preset noise value, then change the bearing type;

[0059] If the abnormal noise emitted by the planetary gear and / or the drive motor is less than the preset noise value, then the planetary gear meets the factory standard.

[0060] In a preferred embodiment of the present invention, the bearing is a ball bearing.

[0061] In a preferred embodiment of the present invention, step S1 includes the following steps: The method for starting the drive motor in step S1 includes the following steps:

[0062] S11, Controller U6 determines whether its wake-up terminal PTD5 receives a first-level signal or a second-level signal:

[0063] If the wake-up terminal PTD5 of controller U6 receives the first level signal, controller U6 will wake up and proceed to the next step; the calculation method for the first level signal is as follows:

[0064]

[0065] Wherein, P1 represents the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the first level signal;

[0066] This indicates the cutoff voltage of transistor Q1;

[0067] This indicates the preset voltage first adjustment threshold.

[0068] If the wake-up terminal PTD5 of controller U6 receives the second level signal, then controller U6 enters sleep mode and returns to step S11; the calculation method for the second level signal is as follows:

[0069]

[0070] Wherein, P2 represents the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the second level signal;

[0071] V +3.3V_MCU This indicates the voltage of the +3.3V power supply to the MCU.

[0072] This indicates the preset voltage first adjustment threshold.

[0073]

[0074] S12, the control terminal PTD16 of controller U6 inputs an enable signal to the enable terminal EN of DC-DC buck converter U2; at this time, the power supply +VBATT input to DC-DC buck converter U2 is converted into a stable power supply +3.3VSW for output through DC-DC buck converter U2; proceed to the next step;

[0075] S13, the control terminal PTC2 of controller U6 inputs a conduction level to the base of transistor Q10, and transistor Q10 is in the conduction state. At this time, the base voltage of transistor Q11 is pulled low, and transistor Q11 is in the conduction state. The collector of transistor Q10 outputs power supply PWR_KEY.

[0076] S14, Controller U6 determines whether the unfold or fold button has been pressed:

[0077] If you click the expand button, proceed to the next step;

[0078] If the fold button is pressed, proceed to step S16;

[0079] S15, Determine if the angle of the rotation axis is within the folding angle threshold:

[0080] If the angle of the rotating shaft is within the folding angle threshold, the controller U6 sends a control signal to the three-phase pre-drive module and the motor drive module. After receiving the control signal sent by the controller U6, the three-phase pre-drive module and the motor drive module drive the motor to rotate forward. When the angle of rotation of the rotating shaft reaches the preset rotation unfolding angle threshold, the drive motor stops working; return to step S14.

[0081] If the angle of the rotation axis is not at the folding angle threshold, that is, at the preset rotation unfolding angle threshold, the drive motor will not work; return to step S14;

[0082] S16, Determine whether the angle of the rotation axis is within the preset rotation unfolding angle threshold:

[0083] If the angle of the rotating shaft is within the preset rotation unfolding angle threshold, the controller U6 sends a control signal to the three-phase pre-drive module and the motor drive module. After receiving the control signal sent by the controller U6, the three-phase pre-drive module and the motor drive module drive the motor to rotate forward. When the angle of rotation of the rotating shaft reaches the preset rotation unfolding angle threshold, the drive motor stops working; return to step S14.

[0084] If the angle of the rotation axis is not at the preset rotation unfolding angle threshold, that is, at the folding angle threshold, then the drive motor will not work; return to step S14.

[0085] This invention also discloses a ceiling-mounted screen motor noise analysis system, such as... Figures 1-24 As shown, the device includes planetary gears connecting the ceiling-mounted screen and the drive motor. The planetary gears include a sleeve 5, within which, from back to front, are sequentially arranged a first-stage planetary gear set 1, a second-stage planetary gear set 2, a third-stage planetary gear set 3, and an output planetary gear set 4. In adjacent planetary gear sets, the sun gear of the rear planetary gear set meshes with the planet gears of the front planetary gear set, causing the first-stage planetary gear set 1, the second-stage planetary gear set 2, the third-stage planetary gear set 3, and the output planetary gear set 4 to be sequentially connected and drive each other. The ceiling-mounted screen, drive motor, and planetary gears constitute a noise-generating device. This device is installed inside a vehicle or in a laboratory. To facilitate testing, the device is installed in a laboratory to reduce other noises emitted from within the vehicle itself.

[0086] The front end of the sleeve 5 is provided with an output through hole for the output sleeve 4b of the output planetary gear set 4 to extend out. The planet carrier of the second-stage planetary gear set 2 is fixed with a central shaft 8 extending back and forth. The planet carriers of the first-stage planetary gear set 1 and the third-stage planetary gear set 3 are both provided with through holes for the central shaft 8 to pass through. The disc of the planet carrier of the output planetary gear set 4 is provided with a front limiting structure for supporting the front end of the central shaft 8.

[0087] In addition, there is a sound acquisition sensor for collecting abnormal noises. The sound acquisition sensor is placed near the abnormal noise emitting device. The number of sound acquisition sensors is set according to the actual situation, usually one. The abnormal noises at different locations of the abnormal noise emitting device can be detected by changing the placement of the sound acquisition sensor. The data terminal of the sound acquisition sensor is connected to the data terminal of the analysis controller. The analysis controller can be a desktop computer. The desktop computer analyzes the abnormal noises emitted by the abnormal noise emitting device by the sound acquisition sensor.

[0088] The front limiting structure includes a bearing hole on the disc of the planetary carrier of the output planetary gear set 4. A bearing 4a is provided within the bearing hole for mounting the front end of the central shaft 8. The bearing 4a is a sliding bearing or a rolling bearing (ball bearing), preferably a ball bearing, to reduce abnormal noise. This structure can fix the front end of the central shaft 8, further improving the stability of the central shaft 8 and preventing abnormal noise caused by movement of the central shaft 8.

[0089] The sleeve 5 is also provided with an internal gear ring 7 that is sleeved outside the first-stage planetary gear set 1. All the planetary gears of the first-stage planetary gear set 1 mesh with the internal gear ring 7. The rear end of the internal gear ring 7 is open and the front end is closed. A limiting through hole 7a is provided in the center of the front end of the internal gear ring 7. A limiting boss 1a matching the limiting through hole 7a is provided on the front side of the planet carrier disk of the first-stage planetary gear set 1, which constitutes a rear limiting structure that supports the rear end of the central shaft (8). The gap between the planet carrier of the first-stage planetary gear set 1 and the internal gear ring 7 is eliminated by the limiting boss 1a.

[0090] The sleeve 5 has a detachable rear end cover 6, which has an input through hole for the input end of the drive motor to be inserted. The input through hole is coaxial with the first-stage planetary gear set 1. The output shaft of the drive motor uses sliding bearings and rolling bearings (ball bearings), preferably ball bearings, to reduce abnormal noise. The side of the rear end cover 6 has several threaded holes 6b along its circumference. The sleeve 5 has mounting through holes corresponding to the threaded holes 6b, and is installed by bolts. The structure is simple, the installation is convenient, and the installation efficiency is improved.

[0091] The advantages of the above results are as follows: Fixing the middle of the central shaft to the planet carrier of the central planetary gear set ensures stability at the center, preventing the central shaft from being affected by the rotation of other planetary gear sets and the output planetary gear set, thus avoiding discontinuous noise. The front limiting structure further strengthens the fixation of the front end of the central shaft, and combined with the rear limiting structure, both ends of the central shaft are fixed, improving installation stability and further preventing abnormal noise. Since the first-stage planetary gear set rotates at the fastest speed, limiting bosses and limiting through holes are respectively set on the first-stage planetary gear set and the internal gear ring. This reduces the gap between them, improves connection stability, and allows the first-stage planetary gear set to rotate stably within the internal gear ring, improving rotational stability and further preventing abnormal noise.

[0092] The rear end edge of the internal gear ring 7 has several rearwardly extending protruding teeth 7b, and the front side of the rear end cover 6 has a groove 6a for the protruding teeth of the internal gear ring 7 to be inserted. This improves the fixing effect of the internal gear ring 7, prevents the internal gear ring 7 from moving and causing abnormal noise, facilitates installation, and provides good stability.

[0093] In a preferred embodiment of the present invention, the ceiling screen includes a ceiling screen body, a rotating shaft adapted to the toothed sleeve 4b is provided on one side of the ceiling screen, the rotating shaft is inserted into the output through hole in the toothed sleeve 4b to connect the ceiling screen with the planetary gear, and a PCB board fixing mounting seat is provided in the ceiling screen body for fixing and mounting the PCB board, the PCB board is fixedly mounted on the PCB board fixing mounting seat.

[0094] The PCB circuit board includes a power supply module, a wake-up module, a voltage sampling module, a button module, a CAN communication module, a controller module, a deserializer module, a screen backlight module, a three-phase pre-drive module, a motor drive module, and a current sampling module; for example... Figure 6 As shown.

[0095] The power module is connected to one or any combination of the wake-up module, voltage sampling module, button module, CAN communication module, controller module, deserializer module, screen backlight module, three-phase pre-drive module, motor drive module and current sampling module, respectively, to provide appropriate power or voltage signals to one or any combination of the wake-up module, voltage sampling module, button module, CAN communication module, controller module, deserializer module, screen backlight module, three-phase pre-drive module, motor drive module and current sampling module;

[0096] The controller module is connected to one or any combination of the wake-up module, voltage sampling module, button module, CAN communication module, deserializer module, screen backlight module, three-phase pre-drive module and current sampling module;

[0097] The drive terminal of the three-phase pre-drive module is connected to the drive terminal of the motor drive module, and the sampling terminal of the current sampling module is connected to the sampling terminal of the motor drive module.

[0098] The controller module enables signal acquisition and control of one or any combination of the wake-up module, voltage sampling module, button module, CAN communication module, deserializer module, screen backlight module, three-phase pre-drive module, motor drive module, and current sampling module.

[0099] In a preferred embodiment of the present invention, the power supply module includes one or any combination of a first voltage conversion module, a second voltage conversion module, a third voltage conversion module, a fourth voltage conversion module, a fifth voltage conversion module, a sixth voltage conversion module, a seventh voltage conversion module, an eighth voltage conversion module, a ninth voltage conversion module, a tenth voltage conversion module, an eleventh voltage conversion module, a twelfth voltage conversion module, a thirteenth voltage conversion module, a fourteenth voltage conversion module, and a fifteenth voltage conversion module; such as Figure 7 As shown.

[0100] The power input terminal of the first voltage conversion module is connected to the power output terminal of interface J3. The power output terminal of the first voltage conversion module is connected to the power input terminals of the second and twelfth voltage conversion modules respectively. The power output terminal of the second voltage conversion module is connected to the power input terminals of the third and fourth voltage conversion modules respectively. The power output terminal of the fourth voltage conversion module is connected to the power input terminals of the fifth, sixth, seventh, and eighth voltage conversion modules respectively. The power output terminal of the fifth voltage conversion module is connected to the power input terminal of the ninth voltage conversion module. The power output terminal of the sixth voltage conversion module is connected to the power input terminals of the tenth and eleventh voltage conversion modules respectively. The power output terminal of the twelfth voltage conversion module is connected to the power input terminals of the thirteenth and fourteenth voltage conversion modules respectively. The power output terminal of the fourteenth voltage conversion module is connected to the power input terminal of the fifteenth voltage conversion module.

[0101] In a preferred embodiment of the present invention, the first voltage conversion module includes: a power output terminal of interface J3 connected to a first terminal of capacitor C64, a second terminal of capacitor C64 connected to a first terminal of capacitor C65, a second terminal of capacitor C65 connected to power ground, and a power output terminal of interface J3 outputting a battery. The battery power output from interface J3 is connected to the power output terminal of the vehicle battery, and the battery power output from interface J3 is converted into a stable battery power output after passing through capacitors C64 and C65 connected in series.

[0102] In a preferred embodiment of the present invention, the second voltage conversion module includes: the drain of a field-effect transistor Q17 is connected to a power supply BATTERY; the gate of the field-effect transistor Q17 is connected to the first terminal of a resistor R99, the first terminal of a resistor R100, the positive terminal of a diode D8, and the first terminal of a capacitor C91; the second terminal of a resistor R99 is connected to a power supply ground; the source of the field-effect transistor Q17 is connected to the second terminal of a resistor R100, the negative terminal of a diode D8, and the second terminal of a capacitor C91; the source of the field-effect transistor Q17 is also connected to the first terminal of a capacitor C117; the second terminal of a capacitor C117 is connected to a power supply ground; the source of the field-effect transistor Q17 is connected to the first terminal of an inductor L3; the second terminal of an inductor L3 is connected to the first terminals of capacitors C70 and C62; the second terminals of capacitors C70 and C62 are connected to a power supply ground; and the second terminal of an inductor L3 outputs a power supply +VBATT. The power supply BATTERY outputs voltage through the body diode of MOSFET Q17. MOSFET Q17 not only provides reverse connection protection for subsequent circuits but also has virtually no voltage drop, ensuring that its input voltage equals its output voltage. The output voltage is then divided by resistors R99 and R100 to provide the gate of MOSFET Q17 with a conduction level, turning MOSFET Q17 on. At this time, the source of MOSFET Q17 outputs a continuous voltage. This voltage is filtered by a π-type filter circuit consisting of capacitors C117 and C70 and inductor L3, outputting power supply +VBATT. Power supply +VBATT provides power to the screen backlight module, the three-phase pre-drive module, and the motor drive module.

[0103] In a preferred embodiment of the present invention, the third voltage conversion module includes: the emitter of transistor Q11 is connected to power supply +VBATT; the first terminal of capacitor C102 is connected to power supply +VBATT; the first terminal of resistor R140 is connected to power supply +VBATT; the second terminals of capacitor C102 and resistor R140 are both connected to the base of transistor Q11; the collector of transistor Q11 outputs power supply PWR_KEY; the base of transistor Q11 is connected to the first terminal of resistor R139; the second terminal of resistor R139 is connected to the collector of transistor Q10; the emitter of transistor Q10 is connected to power supply ground; the base of transistor Q10 is connected to the first terminal of resistor R136; the second terminal of R136 is connected to power supply ground; the base of transistor Q10 is connected to the first terminal of resistor R137; and the second terminal of resistor R137 is connected to the control terminal PTC2 of controller U6. When the control terminal PTC2 of controller U6 inputs a cutoff level to the base of transistor Q10, transistor Q10 is in the cutoff state. At this time, the base potential of transistor Q11 is equal to that of the emitter potential of transistor Q10, and there is no power output from the collector of transistor Q10. When the control terminal PTC2 of controller U6 inputs a conduction level to the base of transistor Q10, transistor Q10 is in the conduction state. At this time, the base voltage of transistor Q11 is pulled low, and transistor Q11 is in the conduction state. The collector of transistor Q10 outputs power PWR_KEY, which provides power PWR_KEY to the button module.

[0104] In a preferred embodiment of the present invention, the fourth voltage conversion module includes: a first terminal of resistor R115 connected to the power supply +VBATT; a second terminal of resistor R115 connected to the first terminals of capacitors C53, C58, and C54; the second terminals of capacitors C53, C58, and C54 connected to the power supply ground; a second terminal of resistor R115 connected to the power supply terminal VIN of DC-DC buck converter U2; the bootstrap capacitor terminal BOOT of DC-DC buck converter U2 connected to the first terminal of resistor R52; and resistor R52... The second terminal is connected to the first terminal of capacitor C48. The second terminal of capacitor C48 is connected to the output terminal SW of DC-DC buck converter U2. The output terminal SW of DC-DC buck converter U2 is connected to the first terminal of inductor L6. The second terminal of inductor L6 is connected to the first terminals of capacitors C49, C50, C51, and C52. The second terminals of capacitors C49, C50, C51, and C52 are connected to the power supply ground. The second terminal of inductor L6 outputs +3.3VSW. The second terminal is connected to the first terminal of resistor R62. The second terminal of resistor R62 is connected to the first terminal of resistor R61. The second terminal of resistor R61 is connected to the first terminal of resistor R63 and the feedback terminal FB of DC-DC buck converter U2. The second terminal of resistor R63 is connected to the power supply ground. The enable terminal EN of DC-DC buck converter U2 is connected to the control terminal PTD16 of controller U6. The enable terminal EN of DC-DC buck converter U2 is connected to the first terminal of resistor R11. The second terminal of resistor R11 is connected to the power supply ground. The clock frequency terminal RT / CLK of DC-DC buck converter U2 is... The first terminal of resistor R51 is connected to the power supply ground. The second terminal of resistor R51 is connected to the power supply ground. The heat dissipation terminal EPGND of DC-DC buck converter U2 is in contact with the heat dissipation pad of DC-DC buck converter U2. The power supply ground terminal GND of DC-DC buck converter U2 is connected to the power supply ground. The soft start terminal SOFT-START of DC-DC buck converter U2 is connected to the first terminal of capacitor C56 and the first terminal of capacitor C92 respectively. The second terminal of capacitor C92 is connected to the first terminal of resistor R101. The second terminals of resistor R101 and capacitor C56 are connected to the power supply ground respectively.When a +3.3VSW power supply is required, the control terminal PTD16 of controller U6 inputs a high level to the enable terminal EN of DC-DC buck converter U2, enabling DC-DC buck converter U2 to operate and convert the input power supply +VBATT into a stable +3.3VSW power supply for output. Alternatively, a resistor R65 can be connected to the second terminal of inductor L6, with resistor R65 outputting a +3.3V_MCU power supply to power the controller module. To prevent DC-DC buck converter U2 from outputting power, the control terminal PTD16 of controller U6 inputs a low level to the enable terminal EN of DC-DC buck converter U2, disabling it and preventing power output from DC-DC buck converter U2.

[0105] In a preferred embodiment of the present invention, the fifth voltage conversion module includes: a first terminal of capacitor C69 connected to a power supply +3.3VSW, a second terminal of capacitor C69 connected to power supply ground, a first terminal of resistor R74 connected to a power supply +3.3VSW, a second terminal of resistor R74 connected to the enable terminal EN of positive voltage regulator U4, a second terminal of resistor R74 connected to a first terminal of resistor R72, a second terminal of resistor R72 connected to power supply ground, a power input terminal VIN of positive voltage regulator U4 connected to a power supply +3.3VSW, an output terminal VOUT of positive voltage regulator U4 connected to a first terminal of resistor R75, a second terminal of resistor R75 connected to the adjustment terminal ADJ of positive voltage regulator U4, a second terminal of resistor R75 connected to a first terminal of resistor R76, a second terminal of resistor R76 connected to power supply ground, a power output terminal VOUT of positive voltage regulator U4 connected to a first terminal of capacitor C68, a second terminal of capacitor C68 connected to power supply ground, and a power output terminal VOUT of positive voltage regulator U4 outputting a power supply +1.8VSW. The input power supply +3.3VSW is converted into a stable power supply +1.8VSW by the positive voltage regulator U4 for output.

[0106] In a preferred embodiment of the present invention, the sixth voltage conversion module includes: as follows Figure 6As shown, the first terminal of capacitor C24 is connected to the +3.3VSW power supply, and the second terminal of capacitor C24 is connected to the power supply ground. The first terminal of resistor R26 is connected to the +3.3VSW power supply, and the second terminal of resistor R26 is connected to the enable terminal EN of positive voltage regulator U10. The second terminal of resistor R26 is connected to the first terminal of resistor R31, and the second terminal of resistor R31 is connected to the power supply ground. The power input terminal VIN of positive voltage regulator U10 is connected to the +3.3VSW power supply. The power output terminal VOUT of positive voltage regulator U10 is connected to the first terminal of resistor R30, and the second terminal of resistor R30 is connected to the adjustment terminal ADJ of positive voltage regulator U10. The second terminal of resistor R30 is connected to the first terminal of resistor R27, and the second terminal of resistor R27 is connected to the power supply ground. The power output terminal VOUT of positive voltage regulator U10 is connected to the first terminal of capacitor C29, and the second terminal of capacitor C29 is connected to the power supply ground. The power output terminal VOUT of positive voltage regulator U10 outputs +1.0VSW power supply. The input power supply +3.3VSW is converted into a stable power supply +1.0VSW by the positive voltage regulator U10 for output.

[0107] In a preferred embodiment of the present invention, the seventh voltage conversion module includes: a first terminal of inductor L8 connected to a power supply +3.3VSW; a second terminal of inductor L8 connected to the first terminals of capacitors C36, C37, C38, and C35; and the second terminals of capacitors C36, C37, C38, and C35 connected to power ground. The second terminal of inductor L8 outputs power supply VDDIO. The input power supply +3.3VSW is filtered by an L-shaped filter circuit composed of capacitor C38 and inductor L8, outputting a stable power supply VDDIO to power the deserializer module.

[0108] In a preferred embodiment of the present invention, the eighth voltage conversion module includes: the source of field-effect transistor Q5 is connected to the power supply +3.3VSW; the drain of field-effect transistor Q5 is connected to the first terminal of resistor R81; the second terminal of resistor R81 is connected to the power supply ground; the drain of field-effect transistor Q5 outputs power supply +3.3V_TFT; the first terminal of capacitor C45 and the first terminal of resistor R80 are connected to the power supply +3.3VSW; the second terminal of capacitor C45 and the second terminal of resistor R80 are connected to the gate of field-effect transistor Q5; the gate of field-effect transistor Q5 is connected to the first terminal of resistor R79; the second terminal of resistor R79 is connected to the collector of transistor Q4; the emitter of transistor Q4 is connected to the power supply ground; the base of transistor Q4 is connected to the first terminal of resistor R78; the second terminal of resistor R78 is connected to the power supply ground; the base of transistor Q4 is connected to the first terminal of resistor R77; and the second terminal of resistor R77 is connected to the control terminal PTC15 of controller U6. When the control terminal PTC15 of controller U6 inputs a cutoff level to the base of transistor Q4, transistor Q4 is in the cutoff state. At this time, the gate potential of MOSFET Q5 is equal to that of the source potential of MOSFET Q5, and there is no power output from the drain of MOSFET Q5. When the control terminal PTC15 of controller U6 inputs a conduction level to the base of transistor Q4, transistor Q4 is in the conduction state. At this time, the gate voltage of MOSFET Q5 is pulled low, and MOSFET Q5 is in the conduction state. The drain of MOSFET Q5 outputs power PWR_KEY, which provides power +3.3V_TFT to the TFT screen interface J2 module.

[0109] In a preferred embodiment of the present invention, the ninth voltage conversion module includes: a first terminal of inductor L1 connected to a power supply +1.8VSW; a second terminal of inductor L1 connected to the first terminals of capacitors C19, C20, C21, C22, C27, and C28; and the second terminals of capacitors C19, C20, C21, C22, C27, and C28 connected to power ground. The second terminal of inductor L1 outputs power supply VDD18. The input power supply +1.8VSW is filtered by an L-shaped filter circuit composed of inductor L1 and capacitor C61, outputting a stable power supply VDD18 to power the deserializer module.

[0110] In a preferred embodiment of the present invention, the tenth voltage conversion module includes: a first terminal of inductor L2 connected to a power supply +1.0VSW; a second terminal of inductor L2 connected to the first terminals of capacitors C23, C26, C97, and C25; and the second terminals of capacitors C23, C26, C97, and C25 connected to power ground. The second terminal of inductor L2 outputs power supply VDDA. The input power supply +1.0VSW is filtered by an L-shaped filter circuit composed of inductor L2 and capacitor C23, outputting a stable power supply VDDA to provide analog power to the controller module.

[0111] In a preferred embodiment of the present invention, the eleventh voltage conversion module includes: a first terminal of inductor L14 connected to a power supply +1.0VSW; a second terminal of inductor L14 connected to the first terminals of capacitors C13, C14, C15, and C18; and the second terminals of capacitors C13, C14, C15, and C18 connected to power ground. The second terminal of inductor L14 outputs power supply VDDD. The input power supply +1.0VSW is filtered by an L-shaped filter circuit composed of inductor L14 and capacitor C18, outputting a stable power supply VDDD to provide digital power to the controller module. The digital power supply terminal VDDD of controller U6 is connected to the power supply VDDD.

[0112] In a preferred embodiment of the present invention, the twelfth voltage conversion module includes: the positive terminal of diode D13 is connected to the power supply BATTERY; the negative terminal of diode D13 is connected to the first terminal of capacitor C113 and the first terminal of capacitor C114; the second terminals of capacitor C113 and the second terminal of capacitor C114 are connected to the power supply ground; and the negative terminal of diode D13 outputs power supply +VBAT2. After passing through diode D13, the power supply BATTERY is filtered by capacitors C113 and C114 to obtain a stable power supply +VBAT2 output. Diode D13 serves to prevent reverse connection, protecting the safety of subsequent circuits.

[0113] In a preferred embodiment of the present invention, the thirteenth voltage conversion module includes: the power supply terminal VIN of the linear regulator U5 is connected to the power supply +VBAT2; the power supply output terminal VOUT of the linear regulator U5 is connected to the first terminal of capacitor C115; the second terminal of capacitor C115 is connected to the power supply ground; the power supply output terminal VOUT of the linear regulator U5 outputs a power supply +3.3V_MCU; the power supply terminal VIN of the linear regulator U5 is connected to the first terminal of resistor R33; the second terminal of resistor R33 is connected to the enable terminal EN of the linear regulator U5; and the power supply ground terminal GND of the linear regulator U5 is connected to the power supply ground. The input power supply +VBAT2 is converted into a stable power supply +3.3V_MCU using the linear regulator U5, providing power to the controller module and a wake-up signal to the wake-up module.

[0114] The thirteenth voltage conversion module can also be connected as follows: the power supply terminal VIN of the linear regulator U5 is connected to the power supply +VBAT2; the power output terminal VOUT of the linear regulator U5 is connected to the first terminal of capacitor C115; the second terminal of capacitor C115 is connected to the power supply ground; the power output terminal VOUT of the linear regulator U5 outputs power supply +3.3V_MCU; the enable terminal EN of the linear regulator U5 is connected to the first terminal of resistor R143, the first terminal of resistor R165, and the first terminal of capacitor C116; the second terminal of resistor R165 and the second terminal of capacitor C116 are connected to the power supply ground; the second terminal of resistor R143 is connected to the negative terminal of diode D3; and the power supply ground terminal GND of the linear regulator U5 is connected to the power supply ground. The wake-up level signal is output through the negative terminal of diode D3, which makes the enable terminal EN of linear regulator U5 high. Linear regulator U5 works and converts the input power supply +VBAT2 into a stable power supply +3.3V_MCU, providing power to the controller module and a wake-up signal to the wake-up module.

[0115] In a preferred embodiment of the present invention, the fourteenth voltage conversion module includes: a first terminal of capacitor C123 connected to power supply +VBAT2, a second terminal of capacitor C123 connected to power ground, a power supply terminal VIN and an enable terminal EN of linear regulator U9 connected to power supply +VBAT2, a power output terminal VOUT of linear regulator U9 outputting power supply VCC_5V, a power output terminal VOUT of linear regulator U9 connected to the first terminal of capacitor C124, a second terminal of capacitor C124 connected to power ground, and a power ground terminal GND of linear regulator U9 connected to power ground. The input power supply +VBAT2 is converted into a stable power supply VCC_5V by linear regulator U9 to provide power to the CAN communication module.

[0116] In a preferred embodiment of the present invention, the fifteenth voltage conversion module includes: the emitter of transistor Q7 is connected to power supply VCC_5V; the first end of resistor R145 is connected to power supply VCC_5V; the second end of R145 is connected to the base of transistor Q7; the collector of transistor Q7 outputs power supply PWR_SOR; the base of transistor Q7 is connected to the first end of resistor R144; the second end of resistor R144 is connected to the collector of transistor Q6; the emitter of transistor Q6 is connected to power supply ground; the base of transistor Q6 is connected to the first end of resistor R141; the second end of resistor R141 is connected to power supply ground; the base of transistor Q6 is connected to the first end of resistor R142; and the second end of resistor R142 is connected to the control terminal PTB4 of controller U6. When the control terminal PTB4 of controller U6 inputs a cutoff level to the base of transistor Q6, transistor Q6 is in the cutoff state. At this time, the emitter potential of transistor Q7 is equal to that of transistor Q7, and there is no power output from the collector of transistor Q7. When the control terminal PTB4 of controller U6 inputs a conduction level to the base of transistor Q6, transistor Q6 is in the conduction state. At this time, the base voltage of transistor Q7 is pulled low, and transistor Q7 is in the conduction state. The collector of transistor Q7 outputs power PWR_SOR, which provides sampling power to the current sampling module.

[0117] In a preferred embodiment of the present invention, the wake-up module includes: as follows Figure 8As shown, the first terminal of resistor R58 is connected to the +3.3V power supply (MCU), the second terminal of resistor R58 is connected to the collector of transistor Q1, the collector of transistor Q1 is connected to the first terminal of resistor R132, the second terminal of resistor R132 is connected to the wake-up terminal PTD5 of controller U6, the emitter of transistor Q1 is connected to the power supply ground, the base of transistor Q1 is connected to the first terminal of capacitor C61 and the first terminal of resistor R56, the second terminals of capacitor C61 and resistor R56 are both connected to the power supply ground, and the base of transistor Q1 is connected to the first terminal of resistor R73. The resistor R73 is connected to the cathode of diode D3, the diode D3 is connected to the wake-up terminal of interface J3, the diode D3 is connected to the first terminal of capacitor C66, the capacitor C66 is connected to the power supply ground, the resistor R73 is connected to the first terminal of resistor R59, the resistor R59 is connected to the first terminals of resistor R60 and capacitor C59, the resistor R60 and capacitor C59 are both connected to the power supply ground, and the resistor R59 is connected to the wake-up signal monitoring terminal PTC1 of controller U6. The wake-up signal is output through the wake-up terminal of interface J3 (this wake-up signal can be the ignition signal or other wake-up signals, such as the wake-up signal sent from the vehicle control). When it is the ignition signal, the voltage is divided by resistors R73 and R56 to provide a conduction level for transistor Q1. At this time, transistor Q1 conducts, and the level of the wake-up terminal PTD5 of the input controller U6 is low, thus waking up the controller U6. When the base of transistor Q1 is at the cutoff level, transistor Q1 is in the cutoff state, and the level of the wake-up terminal PTD5 of the input controller U6 is high. In addition, after the wake-up signal is output from the wake-up terminal of interface J3, the wake-up signal can be protected against reverse connection by diode D3. Then, the voltage is divided by resistors R59 and R60, and the wake-up signal monitoring terminal PTC1 of the controller U6 collects whether the ignition signal is abnormal.

[0118] In a preferred embodiment of the present invention, the voltage sampling module includes: as follows Figure 9 and 10As shown, the emitter of transistor Q2 is connected to the power supply BATTERY, the collector of transistor Q2 is connected to the first terminal of resistor R67, the second terminal of resistor R67 is connected to the first terminal of resistor R68 and the first terminal of capacitor C67, the second terminal of resistor R68 and the second terminal of capacitor C67 are both connected to the power supply ground, the second terminal of resistor R68 is connected to the voltage sampling terminal PTC0 of controller U6, the first terminal of resistor R71 is connected to the power supply BATTERY, the second terminal of resistor R71 is connected to the base of transistor Q2, the second terminal of resistor R71 is connected to the first terminal of resistor R66, the second terminal of resistor R66 is connected to the collector of transistor Q3, the emitter of transistor Q3 is connected to the power supply ground, the base of transistor Q3 is connected to the first terminal of resistor R70, the second terminal of resistor R70 is connected to the power supply ground, the base of transistor Q3 is connected to the first terminal of resistor R69, and the second terminal of resistor R69 is connected to the voltage sampling control terminal PTC16 of controller U6.

[0119] The emitter of transistor Q16 is connected to the power supply +VBATT. The collector of transistor Q16 is connected to the first terminal of resistor R217. The second terminal of resistor R217 is connected to the first terminal of resistor R216 and the first terminal of capacitor C141. The second terminals of resistor R216 and capacitor C141 are both connected to the power supply ground. The second terminal of resistor R217 is connected to the voltage sampling terminal PTB3 of controller U6. The first terminal of resistor R218 is connected to the power supply +VBATT. The second terminal of resistor R218 is connected to the base of transistor Q16. The second terminal of resistor R218 is connected to the first terminal of resistor R215. The second terminal of resistor R215 is connected to the second terminal of resistor R66. When the voltage sampling control terminal PTC16 of controller U6 inputs a cutoff level to the base of transistor Q3, transistor Q3 is in the cutoff state. At this time, the base potential of transistor Q2 is equal to the emitter potential of transistor Q2, and there is no voltage output from the collector of transistor Q2. Similarly, the base potential of transistor Q16 is equal to the emitter potential of transistor Q16, and there is no voltage output from the collector of transistor Q16. When it is necessary to sample the voltages of power supply BATTERY and power supply +VBATT, the voltage sampling control terminal PTC16 of controller U6 inputs a conduction level to the base of transistor Q3. When transistor Q3 is in the conducting state, the voltage of transistor Q2 is pulled low. The collector output voltage of transistor Q2, through the voltage divider circuit composed of resistors R67 and R68, ensures the voltage safety of the voltage sampling terminal PTC0 of the input controller U6, thus realizing the voltage acquisition of the power supply BATTERY. At the same time, the voltage of transistor Q16 is pulled low. The collector output voltage of transistor Q16, through the voltage divider circuit composed of resistors R217 and R216, ensures the voltage safety of the voltage sampling terminal PTB3 of the input controller U6, thus realizing the voltage acquisition of the power supply +VBATT.

[0120] In a preferred embodiment of the present invention, the button module includes: as follows Figure 11 As shown, the first end of resistor R131 is connected to the power supply PWR_KEY; the second end of resistor R131 is connected to the folding signal terminal of interface J3; the second end of resistor R131 is connected to the first end of electrostatic discharge protection diode TVS1; the second end of electrostatic discharge protection diode TVS1 is connected to the first end of electrostatic discharge protection diode TVS2; the second end of electrostatic discharge protection diode TVS2 is connected to the unfolding signal terminal of interface J3; the first end of electrostatic discharge protection diode TVS2 is connected to the power supply ground; the second end of resistor R131 is connected to the first end of capacitor C98; the second end of capacitor C98 is connected to the power supply ground; the second end of resistor R131 is connected to the first end of resistor R133; the second end of resistor R133 is connected to the first end of resistor R151; the second end of resistor R151 is connected to the power supply ground; the second end of resistor R133 is connected to the first end of capacitor C101; the second end of capacitor C101 is connected to the power supply ground; and the second end of resistor R133 is connected to the folding signal acquisition terminal PTD7 of controller U6.

[0121] The first terminal of resistor R135 is connected to the power supply PWR_KEY. The second terminal of resistor R135 is connected to the first terminal of capacitor C99, and the second terminal of capacitor C99 is connected to the power supply ground. The second terminal of resistor R135 is connected to the unfold signal terminal of interface J3. The second terminal of resistor R135 is connected to the first terminal of resistor R134. The second terminal of resistor R134 is connected to the first terminals of resistor R150 and capacitor C100, respectively. The second terminals of resistor R150 and capacitor C100 are both connected to the power supply ground. The second terminal of resistor R134 is connected to the unfold signal acquisition terminal PTD6 of controller U6. The folding signal terminal of interface J3 is connected to the folding button, inputting a folding signal to the folding signal acquisition terminal PTD7 of controller U6; similarly, the unfolding signal terminal of interface J3 is connected to the unfolding button, inputting an unfolding signal to the unfolding signal acquisition terminal PTD6 of controller U6. Generally, the other terminals of the folding and unfolding buttons are connected to the power supply ground.

[0122] In a preferred embodiment of the present invention, the CAN communication module includes: as follows Figure 12 As shown, the NC terminal of the communication chip U3 is connected to the +3.3V_MCU power supply, the first terminal of capacitor C142 is connected to the +3.3V_MCU power supply, the second terminal of capacitor C142 is connected to the power supply ground, the first terminals of capacitors C107 and C108 are connected to the VCC_5V power supply, the second terminals of capacitors C107 and C108 are connected to the power supply ground, and the VCC terminal of the communication chip U3 is connected to the VCC_5V power supply.

[0123] The data terminal CANH of communication chip U3 is connected to the first terminal of resistor R148, the second terminal of resistor R148 is connected to the first terminal of capacitor C63, the data terminal CANH of communication chip U3 is connected to the first terminal of resistor R152, the second terminal of resistor R152 is connected to the first terminal of capacitor C10, the second terminal of capacitor C10 is connected to power ground, the second terminal of resistor R152 is connected to the high-level data terminal of interface J3, and the second terminal of resistor R152 is connected to the first terminal of electrostatic protection diode D1.

[0124] The data terminal CANL of communication chip U3 is connected to the first terminal of resistor R149. The second terminal of resistor R149 is connected to the first terminal of capacitor C63. The second terminal of capacitor C63 is connected to the power supply ground. The data terminal CANL of communication chip U3 is connected to the first terminal of resistor R153. The second terminal of resistor R153 is connected to the first terminal of capacitor C60. The second terminal of capacitor C60 is connected to the power supply ground. The second terminal of resistor R153 is connected to the low-level data terminal of interface J3. The second terminal of resistor R153 is connected to the second terminal of electrostatic discharge protection diode D1. The common terminal of electrostatic discharge protection diode D1 is connected to the power supply ground.

[0125] The standby mode selection terminal STB-IN of communication chip U3 is connected to the control terminal PTE10 of controller U6. The data transmission terminal TXD-IN of communication chip U3 is connected to the first terminal of resistor R154, and the second terminal of resistor R154 is connected to the data receiving terminal PTE5 of controller U6. The data receiving terminal RXD-OUT of communication chip U3 is connected to the first terminal of resistor R155, and the second terminal of resistor R155 is connected to the data transmission terminal PTE4 of controller U6. It connects to the vehicle controller module or other modules via interface J3, enabling communication between controller U6 and the vehicle controller module or other modules using communication chip U3.

[0126] In a preferred embodiment of the present invention, the deserializer module includes: as follows Figures 13-16 As shown, the negative differential signal terminal SIOB- of the deserialization chip U1 is connected to the first terminal of capacitor C7. The second terminal of capacitor C7 is connected to the first terminal of resistor R161, and the second terminal of resistor R161 is connected to the power supply ground. The positive differential signal terminal SIOB+ of the deserialization chip U1 is connected to the first terminal of capacitor C12. The second terminal of capacitor C12 is connected to the first terminal of resistor R47, and the second terminal of resistor R47 is connected to the power supply ground. The first terminal of resistor R47 is connected to the first terminal of electrostatic discharge protection diode ESD5, and the second terminal of electrostatic discharge protection diode ESD5 is connected to the power supply ground. The first terminal of electrostatic discharge protection diode ESD5 is connected to the video signal data terminal RF of interface J4. The power supply ground terminal GND of interface J4 is connected to the power supply ground. By connecting interface J4 to the video cable, video data transmitted from interface J4 can be played on the screen.

[0127] The power supply terminal VDD18 of the deserializer chip U1 is connected to power supply VDD18. The first terminal of resistor R28 is connected to power supply VDDIO, and the second terminal of resistor R28 is connected to the data terminal SDA_RX of the deserializer chip U1. The first terminal of resistor R29 is connected to power supply VDDIO, and the second terminal of resistor R29 is connected to the serial clock signal terminal SCL_TX of the deserializer chip U1. The first terminal of resistor R123 is connected to the first terminal of resistor R7, and the second terminal of resistor R7 is connected to the clock terminal PTA0 of controller U6. The first terminal of resistor R121 is connected to the power supply +3.3V_MCU, and the second terminal of resistor R123 is connected to the serial clock signal terminal SCL_TX of the deserializer chip U1. TX is connected; the first end of resistor R122 is connected to the first end of resistor R8; the second end of resistor R8 is connected to the data terminal PTA1 of controller U6 and the first end of resistor R120; the second end of resistor R120 is connected to the power supply +3.3V_MCU; the second end of resistor R122 is connected to the data terminal SDA_RX of deserialization chip U1; the first end of resistor R116 is connected to the data terminal PTA2 of controller U6; the second end of resistor R116 is connected to the data terminal SDA_RX of deserialization chip U1; the first end of resistor R117 is connected to the serial clock signal terminal PTA3 of controller U6; the second end of resistor R117 is connected to the serial clock signal terminal SCL_TX of deserialization chip U1.

[0128] The power supply terminal VDDA of the deserializer chip U1 is connected to the power supply VDDA. The first terminal of the resistor R102 is connected to the power supply VDDIO. The second terminal of the resistor R102 is connected to the twisted pair / coaxial cable mode selection terminal CXTP / GPIO09 of the deserializer chip U1. The twisted pair / coaxial cable mode selection terminal CXTP / GPIO09 of the deserializer chip U1 is connected to the first terminal of the resistor R96. The second terminal of the resistor R96 is connected to the power supply ground.

[0129] The first end of resistor R35 is connected to the power supply VDDIO, and the second end of resistor R35 is connected to the LOCK terminal of deserialization chip U1. The first end of resistor R32 is connected to the PTE9 terminal of controller U6, and the second end of resistor R32 is connected to the LOCK terminal of deserialization chip U1. The first end of resistor R40 is connected to the PTD15 terminal of controller U6, and the second end of resistor R40 is connected to the ERRORB terminal of deserialization chip U1. The first end of resistor R34 is connected to the power supply VDDIO, and the second end of resistor R34 is connected to the ERRORB terminal of deserialization chip U1.

[0130] The first terminal X1 / SOC of the crystal oscillator of the deserializer chip U1 is connected to the first terminal of capacitor C16, and the second terminal of capacitor C16 is connected to the power supply ground. The first terminal X1 / SOC of the crystal oscillator of the deserializer chip U1 is connected to the first terminal of crystal oscillator Y2, and the ground terminal GND of crystal oscillator Y2 is connected to the power supply ground. The second terminal of crystal oscillator Y2 is connected to the second terminal X2 of the crystal oscillator of the deserializer chip U1 and the first terminal of capacitor C17, and the second terminal of capacitor C17 is connected to the power supply ground; thus providing a clock oscillation signal for the deserializer chip U1.

[0131] The transmit reset terminal TXRES of the deserializer chip U1 is connected to the first terminal of resistor R49, and the second terminal of resistor R49 is connected to the power supply ground. The I2C mode selection terminal GPIO01 / I2CSEL of the deserializer chip U1 is connected to the first terminal of resistor R46, and the second terminal of resistor R46 is connected to the power supply VDDIO. The differential signal terminal SIOA+ of the deserializer chip U1 is connected to the first terminal of capacitor C8, and the second terminal of capacitor C8 is connected to the first terminal of resistor R44, and the second terminal of resistor R44 is connected to the power supply ground. The differential signal terminal SIOA- of the deserializer chip U1 is connected to the first terminal of capacitor C11, and the second terminal of capacitor C11 is connected to the first terminal of resistor R43, and the second terminal of resistor R43 is connected to the power supply ground. The power-off mode selection terminal PWDNB of the deserializer chip U1 is connected to the first terminal of resistor R21, and the second terminal of resistor R21 is connected to the power supply ground. The power-off mode selection terminal PWDNB of the deserializer chip U1 is connected to the first terminal of resistor R48, and the second terminal of resistor R48 is connected to the control terminal PTC9 of controller U6.

[0132] The address pins SD / ADD0 / GPIO11 of the deserializer chip U1 are connected to the power supply VDDIO. The address pins SD / ADD0 / GPIO11 of the deserializer chip U1 are also connected to the first terminal of resistor R23, and the second terminal of resistor R23 is connected to ground. The address pins SCK / ADD1 / GPIO12 of the deserializer chip U1 are connected to the power supply VDDIO. The address pins SCK / ADD1 / GPIO12 of the deserializer chip U1 are also connected to the first terminal of resistor R24, and the second terminal of resistor R24 ​​is connected to ground. The address pins WS / ADD2 / GPIO13 of the deserializer chip U1 are connected to the first terminal of resistor R42, and the second terminal of resistor R42 is connected to ground. The address pins WS / ADD2 / GPIO13 of the deserializer chip U1 are connected to the power supply VDDIO; the interrupt signal pins SDIR / GPIO06 of the deserializer chip U1 are connected to the first end of resistor R118, and the second end of resistor R118 is connected to the interrupt signal pin PTC5 of the controller U6; or the interrupt signal pins SDIR / GPIO06 of the deserializer chip U1 are connected to the first end of resistor R124, the second end of resistor R124 is connected to the interrupt signal pin of the TFT screen interface J2 and the first end of resistor R15, and the second end of resistor R15 is connected to the +3.3V_TFT power supply; providing the address code for the deserializer chip U1.

[0133] The data terminal TXOUT_B0- of the deserialization chip U1 is connected to the first negative data terminal of the TFT screen interface J2; the data terminal TXOUT_B0+ of the deserialization chip U1 is connected to the first positive data terminal of the TFT screen interface J2; the data terminal TXOUT_B1- of the deserialization chip U1 is connected to the second negative data terminal of the TFT screen interface J2; the data terminal TXOUT_B0+ of the deserialization chip U1 is connected to the second positive data terminal of the TFT screen interface J2; and the clock terminal TXCLK_OUTB- of the deserialization chip U1 is connected to the first negative clock terminal of the TFT screen interface J2. The clock terminal TXCLK_OUTB+ of the deserialization chip U1 is connected to the first positive clock terminal of the TFT screen interface J2; the data terminal TXOUT_B2- of the deserialization chip U1 is connected to the third negative data terminal of the TFT screen interface J2; the data terminal TXOUT_B2+ of the deserialization chip U1 is connected to the third positive data terminal of the TFT screen interface J2; the data terminal TXOUT_B3- of the deserialization chip U1 is connected to the fourth negative data terminal of the TFT screen interface J2; and the data terminal TXOUT_B3+ of the deserialization chip U1 is connected to the fourth positive data terminal of the TFT screen interface J2.

[0134] The data terminal TXOUT_A0- of the deserializer chip U1 is connected to the fifth negative data terminal of the TFT screen interface J2; the data terminal TXOUT_A0+ of the deserializer chip U1 is connected to the fifth positive data terminal of the TFT screen interface J2; the data terminal TXOUT_A1- of the deserializer chip U1 is connected to the sixth negative data terminal of the TFT screen interface J2; the data terminal TXOUT_A1+ of the deserializer chip U1 is connected to the sixth positive data terminal of the TFT screen interface J2; and the clock terminal TXCLK_OUTA- of the deserializer chip U1 is connected to the second negative clock terminal of the TFT screen interface J2. The clock terminal TXCLK_OUTA+ of the deserialization chip U1 is connected to the second clock positive terminal of the TFT screen interface J2; the data terminal TXOUT_A2- of the deserialization chip U1 is connected to the seventh data negative terminal of the TFT screen interface J2; the data terminal TXOUT_A2+ of the deserialization chip U1 is connected to the seventh data positive terminal of the TFT screen interface J2; the data terminal TXOUT_A3- of the deserialization chip U1 is connected to the eighth data negative terminal of the TFT screen interface J2; and the data terminal TXOUT_A3+ of the deserialization chip U1 is connected to the eighth data positive terminal of the TFT screen interface J2.

[0135] The TFT screen enable control terminal GPIO02 of the deserialization chip U1 is connected to the first terminal of resistor R36, the second terminal of resistor R36 is connected to the TFT screen enable detection terminal PTE7 of controller U6, the TFT screen enable control terminal GPIO02 of the deserialization chip U1 is connected to the first terminal of resistor R37, the second terminal of resistor R37 is connected to the first terminal of resistor R130, and the second terminal of resistor R130 is connected to the backlight enable control terminal PTC8 of controller U6.

[0136] The PWM adjustment terminal WSIR / GPIO08 of the deserialization chip U1 is connected to the first terminal of resistor R38, the second terminal of resistor R38 is connected to the PWM detection terminal PTC3 of controller U6, the PWM adjustment terminal WSIR / GPIO08 of the deserialization chip U1 is connected to the first terminal of resistor R39, the second terminal of resistor R39 is connected to the first terminal of resistor R129, the second terminal of resistor R129 is connected to the backlight adjustment terminal PTB2 of controller U6, the first terminal of resistor R129 is connected to the first terminal of capacitor C93, and the second terminal of capacitor C93 is connected to the power supply ground.

[0137] The power supply terminal VDDD of the deserialization chip U1 is connected to the power supply VDDD, and the power supply terminal EPGND of the deserialization chip U1 is connected to the power ground. It is connected to the TFT screen via the TFT screen interface J2 to display data on the screen.

[0138] In a preferred embodiment of the present invention, the screen backlight module includes: as follows Figure 20As shown, the power supply terminal VCC of the backlight chip U7 is connected to the first terminal of capacitor C87, and the second terminal of capacitor C87 is connected to the power supply ground. The power supply terminal VCC of the backlight chip U7 is connected to the first terminal of resistor R98, and the second terminal of resistor R98 is connected to the power supply VBATT. The second terminal of resistor R98 is connected to the first terminal of capacitor C71, and the second terminal of capacitor C71 is connected to the power supply ground. The first terminal of capacitor C71 is connected to the first terminals of capacitors C81, C82, and C83. The second terminals of capacitors C81, C82, and C83 are all connected to the power supply ground. The first terminal of capacitor C71 is connected to the first terminal of inductor L4, and the second terminal of inductor L4 is connected to the anode of diode D5. The cathode of diode D5 is connected to the first terminal of resistor R86, and the second terminal of resistor R86 is connected to the voltage protection terminal OVP of backlight chip U7. The second terminal of resistor R86 is connected to the first terminal of resistor R87, and the second terminal of resistor R87 is connected to the power supply ground. The cathode of diode D5... The first terminal of capacitor C85, capacitor C84, capacitor C86, and capacitor C80 are connected to the first terminal of the diode. The second terminals of capacitors C85, C84, C86, and C80 are all connected to the power supply ground. The cathode of diode D5 is connected to the first terminal of resistor R9. The second terminal of resistor R9 outputs the power supply TFT_BL+. The second terminal of inductor L4 is connected to the drain of MOSFET Q18. The gate of MOSFET Q18 is connected to the first terminal of resistor R89. The two ends of resistor R89 ​​are connected to the driving voltage terminal DRV of backlight chip U7. The source of field-effect transistor Q18 is connected to the first end of resistor R88. The second end of resistor R88 is connected to the current sampling terminal SEN of backlight chip U7. The source of field-effect transistor Q18 is connected to the first end of resistor R97. The second end of resistor R97 is connected to the power supply ground. The second end of resistor R97 is connected to the first end of capacitor C88. The second end of capacitor C88 is connected to the current sampling terminal SEN of backlight chip U7.

[0139] The backlight adjustment terminal PWM of the backlight chip U7 is connected to the first terminal of resistor R90. The second terminal of resistor R90 is connected to the first terminal of resistor R129. The second terminal of resistor R129 is connected to the backlight adjustment terminal PTB2 of controller U6. The backlight enable terminal EN of the backlight chip U7 is connected to the first terminal of resistor R91. The second terminal of resistor R91 is connected to the first terminal of resistor R130. The second terminal of resistor R130 is connected to the backlight enable terminal PTC8 of controller U6. The compensation terminal VC of the backlight chip U7 is connected to the first terminal of resistor R93. The second terminal of resistor R93 is connected to the first terminal of capacitor C89. The second terminal of capacitor C89 is connected to the power supply ground.

[0140] The STATUS pin of the backlight chip U7 is connected to the PTA13 pin of the controller U6. The STATUS pin of the backlight chip U7 is connected to the first terminal of the resistor R94. The second terminal of the resistor R94 is connected to the +3.3VSW power supply. The RISET pin of the backlight chip U7 is connected to the first terminal of the resistor R92. The second terminal of the resistor R92 is connected to the power supply ground. The RT pin of the backlight chip U7 is connected to the first terminal of the resistor R95. The second terminal of the resistor R95 is connected to the power supply ground. The GREG pin of the backlight chip U7 is connected to the first terminal of the capacitor C90. The second terminal of the capacitor C90 is connected to the power supply ground. The GND pin of the backlight chip U7 is connected to the power supply ground.

[0141] The first backlight activation terminal LED1 of backlight chip U7 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first backlight activation terminal of TFT screen interface J2. The first backlight activation terminal of TFT screen interface J2 is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is connected to the power supply TFT_BL+. The second backlight activation terminal LED2 of backlight chip U7 is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the second backlight activation terminal of TFT screen interface J2. The second backlight activation terminal of TFT screen interface J2 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the power supply TFT_BL+. The third backlight activation terminal LED3 of backlight chip U7 is connected to the first terminal of resistor R4. One end of the resistor R4 is connected to the third backlight activation terminal of the TFT screen interface J2. The third backlight activation terminal of the TFT screen interface J2 is connected to the first end of the capacitor C3, and the second end of the capacitor C3 is connected to the power supply TFT_BL+. The fourth backlight activation terminal LED4 of the backlight chip U7 is connected to the first end of the resistor R5. The second end of the resistor R5 is connected to the fourth backlight activation terminal of the TFT screen interface J2. The fourth backlight activation terminal of the TFT screen interface J2 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is connected to the power supply TFT_BL+. The second ends of capacitors C1, C2, C3, and C4 are connected to the power supply terminal of the TFT screen interface J2. The input power supply VBATT is converted to power the LEDs via the LED beads connected to the TFT screen interface J2, providing backlight.

[0142] In a preferred embodiment of the present invention, the three-phase pre-drive module includes: as follows Figure 21 and 22As shown, the power supply terminal VIN of the pre-driver chip U8 is connected to the power supply +VBATT. The power supply terminal VIN of the pre-driver chip U8 is connected to the first terminal of capacitor C129. The second terminal of capacitor C129 is connected to the power supply ground. The power supply terminal VIN of the pre-driver chip U8 is connected to the first terminal of capacitor C40. The second terminal of capacitor C40 is connected to the power supply ground. The charge pump capacitor terminal CPA of the pre-driver chip U8 is connected to the first terminal of capacitor C30. The second terminal of capacitor C30 is connected to the charge pump capacitor terminal CPB of the pre-driver chip U8. The power supply source terminal VREG of the pre-driver chip U8 is connected to the first terminal of capacitor C31. The second terminal of capacitor C31 is connected to the power supply ground.

[0143] The high-level drive terminal GHA of phase A of pre-driver chip U8 is connected to the first terminal of resistor R57 and the negative terminal of diode D6; the low-level drive terminal GLA of phase A of pre-driver chip U8 is connected to the first terminal of resistor R158 and the negative terminal of diode D12; the high-level drive terminal GHB of phase B of pre-driver chip U8 is connected to the first terminal of resistor R82 and the negative terminal of diode D10; the low-level drive terminal GLB of phase B of pre-driver chip U8 is connected to the first terminal of resistor R159 and the negative terminal of diode D14; the high-level drive terminal GHC of phase C of pre-driver chip U8 is connected to the first terminal of resistor R157 and the negative terminal of diode D11; and the low-level drive terminal GLC of phase C of pre-driver chip U8 is connected to the first terminal of resistor R160 and the negative terminal of diode D15.

[0144] The overcurrent protection terminal LSS of the pre-driver chip U8 is connected to the overcurrent protection terminal OCP. The high-level A-phase terminal HA of the pre-driver chip U8 is connected to the first terminal of resistor R178, and the second terminal of resistor R178 is connected to the high-level A-phase terminal PTD2 of controller U6. The high-level B-phase terminal HB of the pre-driver chip U8 is connected to the first terminal of resistor R180, and the second terminal of resistor R180 is connected to the high-level B-phase terminal PTC6 of controller U6. The high-level C-phase terminal HC of the pre-driver chip U8 is connected to the first terminal of resistor R182, and the second terminal of resistor R182 is connected to controller U6. The high-level C-phase terminal PTE2 is connected; the low-level A-phase terminal LA of the pre-driver chip U8 is connected to the first terminal of resistor R179; the second terminal of resistor R179 is connected to the low-level A-phase terminal PTD3 of controller U6; the low-level B-phase terminal LB of the pre-driver chip U8 is connected to the first terminal of resistor R181; the second terminal of resistor R181 is connected to the low-level B-phase terminal PTC7 of controller U6; the low-level C-phase terminal LC of the pre-driver chip U8 is connected to the first terminal of resistor R183; and the second terminal of resistor R183 is connected to the low-level C-phase terminal PTE6 of controller U6.

[0145] The heat dissipation terminal GND of the pre-driver chip U8 is in contact with the heat dissipation pad of the pre-driver chip. The dead time terminal DT of the pre-driver chip U8 is connected to the first terminal of resistor R54. The second terminal of resistor R54 is connected to the power supply ground. The overcurrent input protection terminal OC_REF of the pre-driver chip U8 is connected to the first terminal of resistor R185. The second terminal of resistor R185 is connected to the power supply PWR_SOR. The first terminal of resistor R185 is connected to the first terminal of resistor R186. The second terminal of resistor R186 is connected to the power supply ground. The sleep mode terminal NSLEEP of the pre-driver chip U8 is connected to the sleep control terminal PTE8 of the controller U6. The fault indication terminal NFAULT of the pre-driver chip U8 is connected to the acquisition terminal PTB5 of the controller U6.

[0146] The capacitor terminal BSTA of the pre-driver chip U8 is connected to the first terminal of capacitor C32. The second terminal of capacitor C32 is connected to the A-phase terminal of the drive motor in interface J1. The second terminal of capacitor C32 is also connected to the capacitor terminal SHA of pre-driver chip U8. The capacitor terminal BSTB of pre-driver chip U8 is connected to the first terminal of capacitor C33. The second terminal of capacitor C33 is connected to the B-phase terminal of the drive motor in interface J1. The second terminal of capacitor C33 is also connected to the capacitor terminal SHB of pre-driver chip U8. The capacitor terminal BSTC of pre-driver chip U8 is connected to the first terminal of capacitor C34. The second terminal of capacitor C34 is connected to the C-phase terminal of the drive motor in interface J1. The second terminal of capacitor C34 is also connected to the capacitor terminal SHC of pre-driver chip U8. This connection between the drive motor and interface J1 provides pre-drive power and short-circuit protection, overcurrent protection, etc., for the three-phase drive motor.

[0147] In a preferred embodiment of the present invention, the motor drive module includes: as follows Figure 23 As shown, the first terminal of resistor R57 is connected to the high-level drive terminal GHA of phase A of pre-driver chip U8, the second terminal of resistor R57 is connected to the first terminal of resistor R172, the cathode of diode D6 is connected to the high-level drive terminal GHA of phase A of pre-driver chip U8, the anode of diode D6 is connected to the first terminal of resistor R172, the anode of diode D6 is connected to the first terminal of capacitor C122, the anode of diode D6 is connected to the gate of field-effect transistor Q8, the second terminals of resistor R172 and capacitor C122 are both connected to the source of field-effect transistor Q8, the drain of field-effect transistor Q8 is connected to the first terminals of capacitor C39 and capacitor C41, the second terminals of capacitor C39 and capacitor C41 are connected to the power supply ground, and the drain of field-effect transistor Q8 is connected to the power supply +VBATT.

[0148] The first terminal of resistor R82 is connected to the high-level drive terminal GHB of phase B of pre-driver chip U8. The second terminal of resistor R82 is connected to the first terminal of resistor R171 and the first terminal of capacitor C111. The cathode of diode D10 is connected to the high-level drive terminal GHB of phase B of pre-driver chip U8. The anode of diode D10 is connected to the second terminal of resistor R82. The first terminal of resistor R171 and the first terminal of capacitor C111 are connected to the gate of field-effect transistor Q12. The second terminal of resistor R171 and the second terminal of capacitor C111 are connected to the source of field-effect transistor Q12. The drain of field-effect transistor Q12 is connected to the power supply +VBATT.

[0149] The first terminal of resistor R157 is connected to the high-level drive terminal GHC of the C phase of pre-driver chip U8. The second terminal of resistor R157 is connected to the first terminal of resistor R170 and the first terminal of capacitor C112. The cathode of diode D11 is connected to the high-level drive terminal GHC of the C phase of pre-driver chip U8. The anode of diode D11 is connected to the second terminal of resistor R157. The first terminal of resistor R170 and the first terminal of capacitor C112 are connected to the gate of field-effect transistor Q14. The second terminal of resistor R170 and the second terminal of capacitor C112 are connected to the source of field-effect transistor Q14. The drain of field-effect transistor Q14 is connected to the power supply +VBATT.

[0150] The source of MOSFET Q8 is connected to the A-phase terminal of the drive motor of interface J1 and the first terminal of capacitor C138. The second terminal of capacitor C138 is connected to the power supply ground. The source of MOSFET Q12 is connected to the B-phase terminal of the drive motor of interface J1 and the first terminal of capacitor C139. The second terminal of capacitor C139 is connected to the power supply ground. The source of MOSFET Q14 is connected to the C-phase terminal of the drive motor of interface J1 and the first terminal of capacitor C140. The second terminal of capacitor C140 is connected to the power supply ground.

[0151] The cathode of diode D12 and the first terminal of resistor R158 are connected to the low-level drive terminal GLA of phase A of pre-driver chip U8, respectively. The anode of diode D12 and the second terminal of resistor R158 are both connected to the gate of field-effect transistor Q9. The anode of diode D12 is connected to the first terminal of resistor R167 and the first terminal of capacitor C121, respectively. The second terminal of resistor R167 and the second terminal of capacitor C121 are both connected to the source of field-effect transistor Q9. The drain of field-effect transistor Q9 is connected to the source of field-effect transistor Q8.

[0152] The cathode of diode D14 and the first terminal of resistor R159 are connected to the low-level drive terminal GLB of phase B of pre-driver chip U8, respectively. The anode of diode D14 and the second terminal of resistor R159 are both connected to the gate of field-effect transistor Q9. The anode of diode D14 is connected to the first terminal of resistor R168 and the first terminal of capacitor C120, respectively. The second terminal of resistor R168 and the second terminal of capacitor C120 are both connected to the source of field-effect transistor Q13. The drain of field-effect transistor Q13 is connected to the source of field-effect transistor Q12.

[0153] The cathode of diode D15 and the first terminal of resistor R160 are connected to the low-level drive terminal GLC of phase C of pre-driver chip U8, respectively. The anode of diode D15 and the second terminal of resistor R160 are connected to the first terminal of resistor R169 and the first terminal of capacitor C119, respectively. The anode of diode D15 is connected to the gate of field-effect transistor Q15. The second terminals of resistor R169 and capacitor C119 are both connected to the source of field-effect transistor Q15. The drain of field-effect transistor Q15 is connected to the source of field-effect transistor Q14.

[0154] The source of MOSFET Q9 is connected to the first terminal of resistor R192, the source of MOSFET Q9 is connected to the first terminal of resistor R187, the second terminal of resistor R187 is connected to the first terminal of resistor R50, and the second terminal of resistor R50 is connected to the power supply ground; the source of MOSFET Q13 is connected to the first terminal of resistor R199, the source of MOSFET Q13 is connected to the first terminal of resistor R188, and the second terminal of resistor R188 is connected to the first terminal of resistor R50; the source of MOSFET Q15 is connected to the first terminal of resistor R205, the source of MOSFET Q15 is connected to the first terminal of resistor R189, and the second terminal of resistor R189 is connected to the first terminal of resistor R50; the first terminal of capacitor C42 is connected to the first terminal of resistor R50, the second terminal of capacitor C42 is connected to the power supply ground, and the first terminal of capacitor C42 is the overcurrent protection terminal OCP. It may also include: the first terminal of resistor R162 connected to the drain of field-effect transistor Q8, the second terminal of resistor R162 connected to the first terminal of capacitor C46, ​​and the second terminal of capacitor C46 connected to the source of field-effect transistor Q8; the first terminal of resistor R166 connected to the drain of field-effect transistor Q9, the second terminal of resistor R166 connected to the first terminal of capacitor C110, and the second terminal of capacitor C110 connected to the source of field-effect transistor Q9; the first terminal of resistor R53 connected to the drain of field-effect transistor Q12, the second terminal of resistor R53 connected to the first terminal of capacitor C44, and the second terminal of capacitor C44 connected to the source of field-effect transistor Q12. The first terminal of resistor R164 is connected to the drain of MOSFET Q13, and the second terminal of resistor R164 is connected to the first terminal of capacitor C106, which in turn is connected to the source of MOSFET Q13. The first terminal of resistor R45 is connected to the drain of MOSFET Q14, and the second terminal of resistor R45 is connected to the first terminal of capacitor C43, which in turn is connected to the source of MOSFET Q14. The first terminal of resistor R163 is connected to the drain of MOSFET Q15, and the second terminal of resistor R163 is connected to the first terminal of capacitor C47, which in turn is connected to the source of MOSFET Q15. This drive circuit, composed of six MOSFETs (Q8, Q9, Q12, Q13, Q14, and Q15), provides power to the drive motor.

[0155] In a preferred embodiment of the present invention, the current sampling module includes: as follows Figure 24As shown, the A-phase output terminal OUT_A of sampling chip U11 is connected to the first terminal of resistor R190 and the sampling terminal PTB13 of controller U6, respectively. The A-phase input negative terminal -IN_A of sampling chip U11 is connected to the first terminal of resistor R195 and the second terminal of resistor R190, respectively. The second terminal of resistor R195 is connected to the first terminal of resistor R193. The second terminal of resistor R193 is connected to the overcurrent protection terminal OCP. The second terminal of resistor R195 is connected to the first terminal of capacitor C131. The second terminal of capacitor C131 is connected to the power supply ground. The second terminal of capacitor C131 is connected to the first terminal of capacitor C132. The second terminal of capacitor C132 is connected to the first terminal of resistor R192. The second terminal of resistor R192 is connected to the source of effect transistor Q9. The second terminal of capacitor C132 is connected to the first terminal of resistor R196. Resistor R1 The second terminal of 96 is connected to the positive terminal +IN_A of the A-phase input of sampling chip U11. The positive terminal +IN_A of the A-phase input of sampling chip U11 is connected to the first terminal of resistor R194. The second terminal of resistor R194 is connected to the first terminal of resistor R201. The second terminal of resistor R194 is connected to the first terminal of resistor R207. The second terminal of resistor R194 is connected to the positive terminal +IN_B of the B-phase input of sampling chip U11. The second terminal of resistor R194 is connected to the first terminal of resistor R191 and the first terminal of capacitor C133. The second terminals of resistor R191 and capacitor C133 are both connected to the power supply ground. The second terminal of resistor R194 is connected to the first terminal of resistor R197. The second terminal of resistor R197 is connected to the power supply PWR_SOR. The positive terminal V+ of the power supply of sampling chip U11 is connected to the power supply PWR_SOR.

[0156] The negative power supply terminal V- of sampling chip U11 is connected to power ground. The output terminal OUT_D of sampling chip U11 is connected to the sampling terminal PTB12 of controller U6. The output terminal OUT_D of sampling chip U11 is connected to the first terminal of resistor R198. The second terminal of resistor R198 is connected to the negative reference voltage input terminal -IN_D of sampling chip U11. The second terminal of resistor R198 is connected to the first terminal of resistor R202. The second terminal of resistor R202 is connected to the first terminal of capacitor C134. The second terminal of resistor R202 is connected to the first terminal of resistor R200. The second terminal of resistor R200 is connected to the overcurrent protection terminal OCP; the second terminal of capacitor C134 is connected to the power supply ground; the second terminal of capacitor C134 is connected to the first terminal of capacitor C135; the second terminal of capacitor C135 is connected to the first terminal of resistor R203; the second terminal of resistor R203 is connected to the positive input terminal +IN_D of sampling chip U11; the second terminal of resistor R203 is connected to the second terminal of resistor R201; the second terminal of capacitor C135 is connected to the first terminal of resistor R199; and the second terminal of resistor R199 is connected to the source of field-effect transistor Q13.

[0157] The positive terminal (+IN_C) of the C-phase input of sampling chip U11 is connected to the second terminal of resistor R207. The positive terminal (+IN_C) of the C-phase input of sampling chip U11 is connected to the first terminal of resistor R209. The second terminal of resistor R209 is connected to the first terminal of resistor R205. The second terminal of resistor R205 is connected to the source of field-effect transistor Q15. The second terminal of resistor R209 is connected to the first terminal of capacitor C136. The second terminal of capacitor C136 is connected to power ground. The second terminal of capacitor C136 is connected to the first terminal of capacitor C137. The second terminal of capacitor C137 is connected to the first terminal of resistor R206. The second terminal of resistor R206 is connected to the overcurrent protection terminal OCP. The second terminal of capacitor C137 is connected to the first terminal of resistor R208. The second terminal of resistor R208 is connected to the negative input terminal -IN_C of sampling chip U11. The second terminal of resistor R208 is connected to the first terminal of resistor R204. The second terminal of resistor R204 is connected to the output terminal OUT_C ​​of sampling chip U11. The second terminal of resistor R204 is connected to the sampling terminal PTD4 of controller U6. The output terminal OUT_B of sampling chip U11 is connected to the negative input terminal -IN_B of sampling chip U11. Sampling chip U11 is used to collect the current of the drive motor, ensuring the safety of the drive motor.

[0158] In a preferred embodiment of the present invention, the controller module further includes: Figures 17-19 As shown, the power supply terminal VDD of controller U6 is connected to the analog power supply terminal VDDA of controller U6. The power supply terminal VDD of controller U6 is connected to the first terminal of capacitor C79, the first terminal of capacitor C72, and the first terminal of capacitor C78. The second terminals of capacitors C79, C72, and C78 are all connected to the power supply ground. The power supply terminal VDD of controller U6 is connected to the +3.3V_MCU power supply. The reference voltage terminal VREFH of controller U6 is connected to the first terminal of capacitors C74, C75, and C76. The second terminals of capacitors C74, C75, and C76 are all connected to the power supply ground. The reference voltage terminal VREFH of controller U6 is connected to the first terminal of resistor R85. The second terminal of resistor R85 is connected to the +3.3V_MCU power supply.

[0159] The data terminal PTA4 of controller U6 is connected to the data terminal of interface J5. PTA4 is also connected to the first terminal of resistor R113. The second terminal of resistor R113 is connected to the power supply terminal of interface J5. The second terminal of resistor R113 is connected to the first terminal of resistor R111. The first terminal of resistor R111 is connected to the +3.3V power supply (MCU). Resistor R111 is connected to the first terminal of capacitor C94. The second terminal of capacitor C94 is connected to ground. The second terminal of resistor R111 is connected to the reset terminal PTA5 of controller U6. The second terminal of resistor R111 is connected to the first terminal of resistor R110. The second terminal of resistor R110 is connected to the reset terminal of interface J5. The clock terminal of interface J5 is connected to the clock terminal PTC4 of controller U6. The clock terminal of interface J5 is connected to the first terminal of resistor R112. The second terminal of resistor R112 is connected to ground. The ground terminal of interface J5 is connected to ground. The test function is achieved by connecting to interface J5 via a data cable.

[0160] The crystal oscillator terminal PTB7 of controller U6 is connected to the first terminal of resistor R114 and the first terminal of crystal oscillator Y1. The crystal oscillator terminal PTB7 of controller U6 is connected to the first terminal of capacitor C95. The second terminal of capacitor C95 is connected to the power supply ground. The second terminal of resistor R114 and the second terminal of crystal oscillator Y1 are both connected to the crystal oscillator terminal PTB6 of controller U6. The second terminal of resistor R114 is connected to the first terminal of capacitor C96. The second terminal of capacitor C96 is connected to the power supply ground.

[0161] The temperature monitoring terminal PTB1 of controller U6 is connected to the first terminal of capacitor C55, the second terminal of capacitor C55 is connected to the power supply ground, the temperature monitoring terminal PTB1 of controller U6 is connected to the first terminal of resistor R19, the second terminal of resistor R19 is connected to the temperature monitoring terminal of TFT screen interface J2, the temperature monitoring terminal of TFT screen interface J2 is connected to the first terminal of resistor R18, and the second terminal of resistor R18 is connected to the power supply +3.3V_TFT.

[0162] The interrupt terminal PTA11 of controller U6 is connected to the first terminal of resistor R6, and the second terminal of resistor R6 is connected to the interrupt signal terminal of TFT screen interface J2.

[0163] The clock terminal PTA0 of controller U6 is connected to the first terminal of resistor R7, and the second terminal of resistor R7 is connected to the clock terminal of TFT screen interface J2.

[0164] The data terminal PTA1 of controller U6 is connected to the first terminal of resistor R8, and the second terminal of resistor R8 is connected to the TFT screen data terminal of TFT screen interface J2.

[0165] The TFT screen reset terminal PTE0 of controller U6 is connected to the first terminal of resistor R20 and the first terminal of resistor R10 respectively. The second terminal of resistor R10 is connected to the first terminal. The second terminal of resistor R20 is connected to the TFT screen reset terminal of TFT screen interface J2.

[0166] The TFT screen read / write protection terminal PTE1 of controller U6 is connected to the first terminal of resistor R22, and the second terminal of resistor R22 is connected to the read / write protection terminal of TFT screen interface J2.

[0167] The TFT screen fault status terminal PTA12 of controller U6 is connected to the first terminal of resistor R16, the second terminal of resistor R16 is connected to the fault status terminal of TFT screen interface J2, the second terminal of resistor R16 is connected to the first terminal of resistor R17, and the second terminal of resistor R17 is connected to the power supply +3.3V_TFT.

[0168] The TFT screen reset terminal PTC17 of controller U6 is connected to the first terminal of resistor R12, the second terminal of resistor R12 is connected to the reset terminal of TFT screen interface J2, the second terminal of resistor R12 is connected to the first terminal of resistor R13, and the second terminal of resistor R13 is connected to the power ground.

[0169] The A-phase position detection terminal PTD1 of controller U6 is connected to the first terminal of resistor R103. The second terminal of resistor R103 is connected to the first position detection terminal of interface J1. The second terminal of resistor R103 is connected to the first terminal of resistor R146 and the first terminal of capacitor C104. The second terminal of capacitor C104 is connected to power ground. The second terminal of resistor R146 is connected to power supply PWR_SOR. The first terminal of resistor R103 is connected to the first terminal of resistor R108. The second terminal of resistor R108 is connected to power ground. The B-phase position detection terminal PTD0 of controller U6 is connected to the first terminals of resistor R104 and resistor R107 respectively. The second terminal of resistor R104 is connected to the second position detection terminal of interface J1. The second terminal of resistor 104 is connected to the first terminal of resistor R147 and the first terminal of capacitor C105. The second terminal of capacitor C105 is connected to the power supply ground. The second terminal of resistor R147 is connected to the power supply PWR_SOR. The second terminal of resistor R107 is connected to the power supply ground. The C-phase position detection terminal PTE11 of controller U6 is connected to the first terminal of resistor R105 and the first terminal of resistor R106 respectively. The second terminal of resistor R105 is connected to the third position detection terminal of interface J1. The second terminal of resistor R105 is connected to the first terminal of resistor R83 and the first terminal of capacitor C9. The second terminal of capacitor C9 is connected to the power supply ground. The second terminal of resistor R83 is connected to the power supply PWR_SOR. The second terminal of resistor R106 is connected to the power supply ground.

[0170] The A-phase voltage detection terminal PTA7 of controller U6 is connected to the first terminal of resistor R173, the second terminal of resistor R173 is connected to the A-phase terminal of drive motor of interface J1, the A-phase voltage detection terminal PTA7 of controller U6 is connected to the first terminal of resistor R84, the second terminal of resistor R84 is connected to power ground, the A-phase voltage detection terminal PTA7 of controller U6 is connected to the first terminal of capacitor C128, and the second terminal of capacitor C128 is connected to power ground.

[0171] The B-phase voltage detection terminal PTA6 of controller U6 is connected to the first terminal of resistor R175, the second terminal of resistor R175 is connected to the B-phase terminal of the drive motor of interface J1, the B-phase voltage detection terminal PTA6 of controller U6 is connected to the first terminal of resistor R174, the second terminal of resistor R174 is connected to the power supply ground, the B-phase voltage detection terminal PTA6 of controller U6 is connected to the first terminal of capacitor C127, and the second terminal of capacitor C127 is connected to the power supply ground.

[0172] The C-phase voltage detection terminal PTC14 of controller U6 is connected to the first terminal of resistor R177. The second terminal of resistor R177 is connected to the C-phase terminal of the drive motor of interface J1. The C-phase voltage detection terminal PTC14 of controller U6 is connected to the first terminal of resistor R176. The second terminal of resistor R176 is connected to the power supply ground. The C-phase voltage detection terminal PTC14 of controller U6 is connected to the first terminal of capacitor C73. The second terminal of capacitor C73 is connected to the power supply ground.

[0173] In a preferred embodiment of the present invention, the TFT screen interface module further includes: the first power supply terminal of the TFT screen interface J2 is connected to the first terminal of capacitor C5 and the first terminal of capacitor C6, the second terminals of capacitor C5 and capacitor C6 are connected to the power ground, the second power supply terminal of the TFT screen interface J2 is connected to the first terminal of resistor R14, and the second terminal of resistor R14 is connected to the power supply +3.3V_TFT.

[0174] The third power supply terminal of the TFT screen interface J2 is connected to the first terminal of resistor R184, and the second terminal of resistor R184 is connected to the +3.3V_TFT power supply.

[0175] In a preferred embodiment of the present invention, the motor interface module further includes: the power supply terminal of interface J1 is connected to the power supply PWR_SOR, the power supply terminal of interface J1 is connected to the first terminal of capacitor C109, the second terminal of capacitor C109 is connected to the power supply ground, the power supply terminal of interface J1 is connected to the first terminal of capacitor C103, the second terminal of capacitor C103 is connected to the power supply ground, and the power supply terminal of interface J1 is connected to the power supply ground.

[0176] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for analyzing abnormal noise from a ceiling-mounted screen motor, characterized in that, The method is implemented by a ceiling-mounted screen motor noise analysis system, which includes a planetary gear connected between the ceiling-mounted screen and the drive motor. The planetary gear includes a sleeve, and a first-stage planetary gear set, a second-stage planetary gear set, a third-stage planetary gear set, and an output planetary gear set are arranged sequentially from back to front inside the sleeve. In two adjacent planetary gear sets, the sun gear of the rear planetary gear set meshes with the planet gear of the front planetary gear set, so that the first-stage planetary gear set, the second-stage planetary gear set, the third-stage planetary gear set, and the output planetary gear set are connected and driven in sequence. The front end of the sleeve is provided with an output through hole for the output gear sleeve of the output planetary gear set to extend out. The planet carrier of the second-stage planetary gear set is fixed with a central shaft extending forward and backward. The planet carriers of the first-stage and third-stage planetary gear sets are both provided with through holes for the central shaft to pass through. The disc of the planet carrier of the output planetary gear set is provided with a front limiting structure for supporting the front end of the central shaft. And a sound sensor for collecting abnormal noises, which is placed near the noise-generating device; The front limiting structure includes a bearing hole on the disc body of the planetary carrier of the output planetary gear set, and a bearing for mounting the front end of the central shaft is provided in the bearing hole; The sleeve also contains an internal gear ring that is sleeved around the first-stage planetary gear set. All planetary gears of the first-stage planetary gear set mesh with the internal gear ring. The internal gear ring has an open rear end and a closed front end, with a limiting through hole centrally located at the front end. A limiting boss matching the limiting through hole is located on the front side of the planet carrier disc of the first-stage planetary gear set, forming a rear limiting structure that supports the rear end of the central shaft. The limiting boss eliminates the gap between the planet carrier and the internal gear ring of the first-stage planetary gear set. The analysis of this ceiling-mounted screen motor noise analysis system includes the following steps: S1, the drive motor rotates forward or reverse according to the unfold or fold button; S2, when the drive motor is rotating in both directions, collect abnormal noises emitted by the planetary gears and the drive motor; S2 also includes determining whether the abnormal noise emitted by the planetary gears and drive motor is greater than or equal to a preset noise value: If the abnormal noise emitted by the planetary gears and drive motor is greater than or equal to the preset noise value, then change the bearing type; If the abnormal noise emitted by the planetary gear and drive motor is less than the preset noise value, then the planetary gear meets the factory standard.

2. The method for analyzing abnormal noise from a ceiling-mounted screen motor according to claim 1, characterized in that, The bearing is a ball bearing.

3. The method for analyzing abnormal noise from a ceiling-mounted screen motor according to claim 1, characterized in that, Step S1 includes the following steps: The method for starting the drive motor in step S1 includes the following steps: S11, Controller U6 determines whether its wake-up terminal PTD5 receives a first-level signal or a second-level signal: If the wake-up terminal PTD5 of controller U6 receives the first level signal, controller U6 will wake up and proceed to the next step. If the wake-up terminal PTD5 of controller U6 receives the second level signal, controller U6 will enter sleep mode and return to step S11; S12, the control terminal PTD16 of controller U6 inputs an enable signal to the enable terminal EN of DC-DC buck converter U2; at this time, the power supply +VBATT input to DC-DC buck converter U2 is converted into a stable power supply +3.3VSW for output through DC-DC buck converter U2; proceed to the next step; S13, the control terminal PTC2 of controller U6 inputs a conduction level to the base of transistor Q10, and transistor Q10 is in the conduction state. At this time, the base voltage of transistor Q11 is pulled low, and transistor Q11 is in the conduction state. The collector of transistor Q10 outputs power supply PWR_KEY. S14, Controller U6 determines whether the unfold or fold button has been pressed: If you click the expand button, proceed to the next step; If the fold button is pressed, proceed to step S16; S15, Determine if the angle of the rotation axis is within the folding angle threshold: If the angle of the rotating shaft is within the folding angle threshold, the controller U6 sends a control signal to the three-phase pre-drive module and the motor drive module. After receiving the control signal sent by the controller U6, the three-phase pre-drive module and the motor drive module drive the motor to rotate forward. When the angle of rotation of the rotating shaft reaches the preset rotation unfolding angle threshold, the drive motor stops working; return to step S14. If the angle of the rotation axis is not at the folding angle threshold, that is, at the preset rotation unfolding angle threshold, the drive motor will not work; return to step S14; S16, Determine whether the angle of the rotation axis is within the preset rotation unfolding angle threshold: If the angle of the rotating shaft is within the preset rotation unfolding angle threshold, the controller U6 sends a control signal to the three-phase pre-drive module and the motor drive module. After receiving the control signal sent by the controller U6, the three-phase pre-drive module and the motor drive module drive the motor to rotate forward. When the angle of rotation of the rotating shaft reaches the preset rotation unfolding angle threshold, the drive motor stops working; return to step S14. If the angle of the rotation axis is not at the preset rotation unfolding angle threshold, that is, at the folding angle threshold, then the drive motor will not work; return to step S14.

Images