Methods, apparatuses, and media for detecting defects on a wafer surface

Abstract

The present disclosure provides a method, device and medium for detecting defects on a wafer surface. The method comprises: obtaining the extinction coefficient and refractive index of the cover layer of the wafer to be measured; constructing a first calibration curve for determining the defect size according to the extinction coefficient and refractive index for DNO channel, DW1O channel and DW2O channel respectively; obtaining the detection size of the detected bright spot of the wafer to be measured in DNO channel, DW1O channel and DW2O channel respectively according to the corresponding radiation intensity of the detected bright spot of the wafer to be measured in DNO channel, DW1O channel and DW2O channel and the first calibration curve corresponding to DNO channel, DW1O channel and DW2O channel respectively; and determining the defect type corresponding to the detected bright spot according to the detection size of the detected bright spot of the wafer to be measured in DNO channel, DW1O channel and DW2O channel respectively.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method, apparatus and medium for detecting defects on the surface of a wafer. Background Technology

[0002] As a method for evaluating defects or foreign objects in semiconductor wafers, the method based on light point defects (LPD) detected by surface inspection equipment is widely used. This method involves incident light onto the surface of the wafer being evaluated and evaluating the presence and size of defects and foreign objects attached to the surface by detecting the emitted light (including scattered and reflected light) from the surface.

[0003] Currently, when the semiconductor wafer being tested is a polished single-crystal wafer or an epitaxial single-crystal wafer, the surface of these types of wafers is smooth and the material is consistent. Therefore, the current LPD-based defect detection scheme can accurately detect and obtain surface defects.

[0004] Depending on the application requirements, polished or epitaxial single-crystal wafers are used as substrates, and a capping layer is formed on the substrate surface through film deposition, ultimately resulting in a wafer with a capping layer. Because the capping layer material is different from the substrate material, the emitted light from the surface of the wafer with the capping layer differs from that of the polished or epitaxial single-crystal wafer during surface defect detection using LPD-based defect detection schemes. Due to this difference, current LPD-based defect detection schemes cannot accurately detect defects present on the surface of wafers with capping layers. Summary of the Invention

[0005] This disclosure provides a method, apparatus, and medium for detecting defects on the surface of a wafer; it can improve the detection accuracy of defects on the surface of a wafer with a covering layer.

[0006] The technical solution disclosed herein is implemented as follows:

[0007] In a first aspect, this disclosure provides a method for detecting defects on the surface of a wafer, the method comprising:

[0008] The extinction coefficient and refractive index of the capping layer of the wafer under test are obtained; wherein, the wafer under test includes a semiconductor wafer having a capping layer on a single-crystal silicon substrate;

[0009] Based on the extinction coefficient and the refractive index, corresponding first calibration curves for determining defect size are constructed for dark field narrow tilted DNO channel, dark field wide 1 tilted DW1O channel, and dark field wide 2 tilted DW2O channel, respectively; wherein, the first calibration curve is used to characterize the correspondence between the radiation intensity and the detection size under the cover layer condition.

[0010] The emission intensity of the detected bright spots on the wafer under test in the DNO, DW1O and DW2O channels is matched with the first calibration curves corresponding to the DNO, DW1O and DW2O channels respectively to obtain the detection size of the detected bright spots on the wafer under test in the DNO, DW1O and DW2O channels respectively.

[0011] The defect type corresponding to the detected bright spot is determined based on the detection size of the bright spot in the DNO channel, DW1O channel, and DW2O channel of the wafer under test.

[0012] Secondly, this disclosure provides an apparatus for detecting defects on the surface of a wafer, the apparatus comprising: an acquisition unit, a construction unit, a matching unit, and a determination unit; wherein,

[0013] The acquisition unit is configured to acquire the extinction coefficient and refractive index of the capping layer of the wafer under test; wherein the wafer under test includes a semiconductor wafer having a capping layer on a single-crystal silicon substrate;

[0014] The construction unit is configured to construct corresponding first calibration curves for determining defect size based on the extinction coefficient and the refractive index for a dark field narrow tilted DNO channel, a dark field wide 1 tilted DW1O channel, and a dark field wide 2 tilted DW2O channel, respectively; wherein, the first calibration curve is used to characterize the correspondence between the radiation intensity and the detection size under the cover layer condition.

[0015] The matching unit is configured to match the emission intensity of the detected bright spots on the wafer under test in the DNO channel, DW1O channel and DW2O channel with the first calibration curves corresponding to the DNO channel, DW1O channel and DW2O channel respectively, to obtain the detection size of the detected bright spots on the wafer under test in the DNO channel, DW1O channel and DW2O channel respectively.

[0016] The determination unit is configured to determine the defect type corresponding to the detected bright spot based on the detection size of the bright spot detected on the wafer under test in the DNO channel, DW1O channel and DW2O channel respectively.

[0017] Thirdly, this disclosure provides a computing device comprising: a processor and a memory; the processor being configured to execute instructions stored in the memory to implement the method for detecting wafer surface defects as described in the first aspect.

[0018] Fourthly, this disclosure provides a computer storage medium storing at least one instruction, which is executed by a processor to implement the method for detecting wafer surface defects as described in the first aspect.

[0019] This disclosure provides a method, apparatus, and medium for detecting defects on the surface of a wafer. The calibration curve is corrected by utilizing the influence of the extinction coefficient and refractive index of the wafer surface under test caused by the capping layer. Defects on the wafer surface and their corresponding dimensions are then detected based on the corrected calibration curve, thereby improving the detection accuracy of defects on the surface of a wafer with a capping layer. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the components of a surface inspection device provided in this disclosure.

[0021] Figure 2 This is a schematic flowchart of a method for detecting defects on the surface of a wafer, as provided in this disclosure.

[0022] Figure 3 This is a schematic diagram of the composition of a wafer to be tested provided in this disclosure.

[0023] Figure 4(a) is a schematic diagram of the first calibration curve of the DNO channel provided in this disclosure.

[0024] Figure 4(b) is a schematic diagram of the first calibration curve of the DW1O channel provided in this disclosure.

[0025] Figure 4(c) is a schematic diagram of the first calibration curve of the DW2O channel provided in this disclosure.

[0026] Figure 5 This is a schematic diagram of a defect detection result provided in this disclosure.

[0027] Figure 6 This is another schematic diagram of defect detection results provided in this disclosure.

[0028] Figure 7 This is a schematic diagram of the device for detecting defects on the surface of a wafer, as provided in this disclosure.

[0029] Figure 8 This is a schematic diagram of the structure of a computing device provided in this disclosure. Detailed Implementation

[0030] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0031] In the method for detecting wafer surface defects mentioned in this disclosure, the wafer to be tested may include a semiconductor wafer having a capping layer on a single-crystal silicon substrate. The single-crystal silicon substrate may include a polished silicon single-crystal wafer, which is obtained by slicing a single-crystal ingot and performing processes such as mirror polishing and cleaning, or an epitaxial silicon single-crystal wafer obtained by forming a single-crystal silicon epitaxial layer on the surface of a polished silicon single-crystal wafer through methods such as chemical vapor deposition. The capping layer present on the single-crystal silicon substrate may be various capping layers formed by film deposition methods. Specifically, the capping layer may include an oxide layer, a nitride layer, a polycrystalline silicon layer, an amorphous silicon layer, a metal layer, etc.

[0032] In some examples, the aforementioned capping layer may be a deposition layer on a monocrystalline silicon substrate containing a film-forming material. Various film-forming methods that can deposit film-forming materials on a monocrystalline silicon substrate using vapor phase growth methods can be listed as methods for forming the deposition layer, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). The thickness of the capping layer may be, for example, in the range of 5 nm to 500 nm, but is not limited to this range. In some examples, the number of capping layers deposited on the monocrystalline silicon substrate may be one, two, or more.

[0033] In the method for detecting wafer surface defects mentioned in this disclosure, exemplarily employing Figure 1 The surface inspection device 10 shown detects surface defects in the aforementioned wafer 1. Figure 1 In the diagram, solid arrows schematically represent incident light, and dashed arrows schematically represent emitted light. In this disclosure, emitted light includes one or both of reflected light and scattered light.

[0034] exist Figure 1 The device 10 includes a first incident system with a low-angle side light source 100 and a second incident system with a high-angle side light source 101a. The second incident system includes the high-angle side light source 101a and a reflector 101b. Light emitted from the high-angle side laser light source 101a is reflected by the reflector 101b, changing its emission direction and incident on the surface of the capping layer (not shown) of the wafer 1 under test.

[0035] In this disclosure, the wavelengths of incident light incident from the first and second incident systems onto the surface of the capping layer of the wafer under test are not particularly limited. In some examples, the incident light may be ultraviolet light, but it may also be visible light or other light. In this disclosure, ultraviolet light refers to light in the wavelength region of less than 400 nm, and visible light refers to light in the wavelength region of 400–600 nm.

[0036] Regarding the two incident systems described above, the high angle (side) / low angle (side) refers to the angle determined relative to the relationship between the two systems, and the specific angle is not limited. In some examples, if all directions horizontal to the surface of the capping layer are set to 0°, and directions perpendicular to the surface of the capping layer are set to 90°, and the incident angle is defined as ranging from a minimum of 0° to a maximum of 90°, then the incident angle of the incident light incident from the first incident system onto the capping layer surface of the wafer under test can be between 0° and 60°, preferably between 0° and 30°. On the other hand, as the incident angle defined similarly above, the incident angle of the incident light incident from the second incident system onto the capping layer surface of the wafer under test being evaluated can be between 60° and 90°, preferably between 80° and 90°.

[0037] See also Figure 1 The device 10 further includes a high-angle side light receiver 201, a low-angle side light receiver 202, and a low-angle side light receiver 203. The low-angle side light receivers 202 and 203 have a structure that receives emitted light around the entire circumference above the stage 11. It is understood that the light-receiving system of the surface inspection device only needs to have a structure capable of receiving emitted light, and is not limited to... Figure 1 The structure shown.

[0038] Regarding the three types of light receivers mentioned above, in this disclosure, the angle (receiving angle) at which the high-angle side light receiver 201 receives emitted light is higher than the angles at which the low-angle side light receivers 202 and 203 receive emitted light. It should be noted that, relative to the receiving angle, the high-angle (side) / low-angle (side) is an angle determined relative to one side and the other, and the specific angle is not limited. In some examples, when the angle is defined with the surface of the cover layer of the wafer under test as a reference, similar to the previously described incident angle, high-angle side light reception may refer to light reception at a receiving angle exceeding 80° and below 90°, and low-angle side light reception may refer to light reception at a receiving angle between 0° and 80°. In some examples, the receiving angle of the low-angle side light receiver 202 is higher than that of the low-angle side light receiver 203.

[0039] Regarding the three types of light receivers mentioned above, in this disclosure, the high-angle side light receiver 201, the low-angle side light receiver 202, and the low-angle side light receiver 203 can selectively receive polarized light with a specific azimuth angle, or they can receive omnidirectional light, that is, they can receive polarized light with all azimuth angles. In some examples, the high-angle side light receiver 201 receives omnidirectional light, the low-angle side light receiver 202 receives polarized light with an azimuth angle of θ1, and the low-angle side light receiver 203 receives polarized light with an azimuth angle of θ2, wherein 0°≤θ1≤90° and 90°≤θ2≤180°.

[0040] Furthermore, the surface inspection apparatus 10, equipped with a rotary motor 12 capable of rotating the stage 11 on which the wafer 1 to be inspected is placed, and a movable unit (not shown) capable of moving in the horizontal direction, can change the irradiation position of the light incident from each of the aforementioned laser light sources. Thus, the inspectable area or the entire surface area of ​​the cover layer of the wafer 1 to be inspected can be sequentially irradiated (i.e., scanned) with light, and defect detection can be performed on the inspectable area or the entire surface area.

[0041] Furthermore, the surface inspection apparatus 10 includes: a control unit 13 that controls the rotation and horizontal movement of the stage 11; and a calculation unit 14 that calculates the detection size of the detected defect type based on the information of the emitted light received by each of the aforementioned light receivers. Additionally, the calculation device 15 receives position information of the illuminated locations from the control unit 13 and sends a signal to move the stage 11 in order to illuminate unilluminated locations. Furthermore, the calculation device 15 can receive information related to the detection size of the detected defect type from the calculation unit 14 and generate various measurement results, which will be described in detail later.

[0042] according to Figure 1 The surface inspection apparatus 10 shown in this disclosure, by combining a first incident system and a high-angle side photodetector 201, can obtain a first detection result of the cover layer surface of the wafer under test in a dark-field narrow oblique (DNO) channel. By combining the first incident system and a low-angle side photodetector 202, a second detection result of the cover layer surface of the wafer under test in a dark-field wide oblique (DW1O) channel can be obtained. By combining the first incident system and a low-angle side photodetector 203, a third detection result of the cover layer surface of the wafer under test in a dark-field wide oblique (DW2O) channel can be obtained. All three detection results can include, under the corresponding channel conditions, the bright spots detected on the cover layer surface of the wafer under test and the detection dimensions corresponding to the bright spots.

[0043] During the inspection of the wafer surface by the surface inspection apparatus 10, light is incident from an incident system onto the capping layer surface of the wafer and emitted from the capping layer surface. Defects on the surface of the wafer are detected as bright spots (light points) in the high-angle side light receiver 201, the low-angle side light receiver 202, and the low-angle side light receiver 203. In some examples, the calculation unit 14 uses the emission intensity and size of a standard particle (e.g., SiO2 particle) as a reference, and obtains the size of the detected bright spot by the emission intensity of the bright spot, thereby calculating the size of the defect causing the bright spot (detection size). In some examples, related schemes construct a correspondence between emission intensity and detection size based on the emission intensity of the standard particle and the detection size. This correspondence can be characterized using a calibration curve. After obtaining the emission intensity of the detected bright spot, the detection size of the detected bright spot can be obtained through the correspondence characterized by the calibration curve. Understandably, for the aforementioned three channels DNO, DW1O, and DW2O, a calibration curve is provided for each channel to characterize the relationship between the intensity of the emitted light and the detection size under the corresponding channel conditions.

[0044] It should be noted that the calibration curves of the relevant schemes are only for polished or epitaxial silicon single-crystal wafers, whose surfaces are relatively smooth. However, when performing defect detection on the wafer under test proposed in this disclosure, the presence of the capping layer makes the surface roughness of the wafer under test significantly higher than that of the silicon single-crystal wafer. That is, the surface haze value of the wafer under test is higher than that of the silicon single-crystal wafer. Therefore, if the calibration curves of the relevant schemes are still used to perform defect detection on the wafer under test, the capping layer will affect light scattering, thereby reducing the intensity of emitted light, which may lead to missed defects or false detections of defect size.

[0045] To improve the accuracy of defect detection on the surface of a wafer under test, this disclosure aims to correct the calibration curve by utilizing the influence of the extinction coefficient and refractive index of the wafer surface under test caused by the capping layer, and to detect defects on the surface of the wafer under test and the corresponding detection dimensions based on the corrected calibration curve, thereby improving the detection accuracy of defects on the surface of a wafer under test with a capping layer.

[0046] Based on this, the present disclosure provides a method for detecting defects on the surface of a wafer, which can be applied to... Figure 1 The computing device 15 shown is as follows. Figure 2 As shown, the method may include steps S201 to S204.

[0047] In step S201, the extinction coefficient and refractive index of the capping layer of the wafer to be tested are obtained.

[0048] In this disclosure, the wafer under test, which is the object of testing, may have a capping layer that includes an oxide layer, a nitride layer, a polycrystalline silicon layer, an amorphous silicon layer, a metal layer, etc., and the number of capping layers may be one, two, or more. Taking wafer 1 under test having two capping layers as an example, such as... Figure 3 As shown, the capping layer closest to the monocrystalline silicon substrate 31 can also be called the protective film layer 32. Specifically, the protective film layer 32 has good chemical and thermal stability, enabling it to protect the monocrystalline silicon substrate 31 and prevent its surface from oxidation, corrosion, and contamination. Optionally, the protective film layer 102 may include any one or a combination of silicon dioxide, silicon nitride, tantalum oxide, or polyimide, and its thickness can be [missing information]. to The specific layer can be selected according to actual needs, and no restrictions are imposed here. The cover layer above the protective film layer 32, away from the single-crystal silicon substrate 31, can also be called the process film layer 33. The process film layer 33 covers the protective film layer 32, which can improve the electrical performance and mechanical strength of the wafer under test, and can also be used in subsequent semiconductor manufacturing processes as optical thin films, insulating layers, photomask layers, etc. Optionally, the thickness of the process film layer 33 can be [missing information]. to The process film 33 includes any one or a combination of silicon dioxide, silicon nitride, tantalum oxide or polyimide, and the specific selection is based on actual needs and is not limited here.

[0049] for Figure 3 The protective film 32 and the process film 33 shown have a higher ion density than the silicon atom ion density in the single-crystal silicon substrate 31. Therefore, their extinction coefficient and refractive index will differ significantly from those of silicon atoms. Figure 1 Taking the surface inspection apparatus 10 shown as an example, when incident light is incident on the surface of the capping layer, the intensity of the emitted light generated by the reflection or scattering of the incident light by the capping layer surface will be reduced compared to the single-crystal silicon substrate 31 due to its extinction coefficient and refractive index. That is, the extinction coefficient and refractive index of the capping layer are factors that need to be considered in order to reduce the intensity of emitted light.

[0050] In some examples, the extinction coefficient represents the proportion of energy absorbed per unit length of light passing through an object. In practice, the extinction coefficient of the capping layer surface of the wafer under test can be determined using transmission methods, for example, by measuring the light transmitted through the capping layer.

[0051] In some examples, refractive index represents the ratio of the speed of light in a vacuum to the speed of light in a medium. In practice, an ellipsometer can be used to determine the refractive index of the capping layer surface of the wafer under test. Specifically, when elliptically polarized light is reflected from the capping layer surface of the wafer under test, its polarization state changes. The angle values ​​of the polarizer and analyzer can be pre-input, and appropriate upper and lower limits of the refractive index and accuracy values ​​can be selected. By utilizing the fitting characteristics, the refractive index of the capping layer surface of the wafer under test can be accurately measured.

[0052] In step S202, a first calibration curve for determining defect size is constructed based on the extinction coefficient and refractive index of the DNO channel, DW1O channel, and DW2O channel, respectively.

[0053] In this disclosure, combined with Figure 1 The relationship between the intensity of the emitted light and the size of the inspection in the surface inspection device 10 shown can be characterized by a calibration curve.

[0054] In related solutions, since the surface inspection device 10 is typically most widely used for detecting surface defects only on polished or epitaxial silicon single-crystal wafers, and the surfaces of these silicon single-crystal wafers are relatively smooth, default second calibration curves are usually provided for the three channels (DNO channel, DW1O channel, and DW2O channel) of the surface inspection device 10 to obtain the detection size corresponding to the detected bright spots in each channel. However, based on the difference between the surface of the capping layer and the surface of the silicon single-crystal wafer described in step S201 above, namely the difference caused by the extinction coefficient and refractive index of the capping layer, if the second calibration curve is still used to detect the bright spots and their corresponding detection sizes of the wafer under test in each channel, the reduced radiation intensity caused by the capping layer will lead to missed or false detections of surface defects in the capping layer.

[0055] Based on this, in response to the difference in radiated light intensity between the extinction coefficient and refractive index of the capping layer and the silicon single crystal wafer surface, this disclosure constructs corresponding first calibration curves using the extinction coefficient and refractive index of the DNO channel, DW1O channel, and DW2O channel, respectively. These first calibration curves characterize the relationship between the radiated light intensity of each corresponding channel and the detection size under capping layer conditions. During defect detection, the default second calibration curve is replaced with the first calibration curve, and the defect size at the bright spot is then detected using the first calibration curve. This improves the adaptability of the calibration curve used in the detection process, thereby avoiding or reducing the occurrence of missed or false detections of defects on the capping layer surface.

[0056] In step S203, the emission intensity of the detected bright spots on the wafer under test in the DNO channel, DW1O channel, and DW2O channel is matched with the first calibration curves corresponding to the DNO channel, DW1O channel, and DW2O channel, respectively, to obtain the detection size of the detected bright spots on the wafer under test in the DNO channel, DW1O channel, and DW2O channel, respectively.

[0057] In this disclosure, through Figure 1 The surface inspection apparatus 10 shown detects bright spots on the wafer under test in the DNO, DW1O, and DW2O channels, respectively. For each bright spot, the corresponding emission intensity in the DNO, DW1O, and DW2O channels can be obtained. The emission intensity corresponding to each of the three channels can be matched with the first calibration curve corresponding to each channel. By using the correspondence between emission intensity and detection size under the capping layer condition represented by the first calibration curve corresponding to each channel, the detection size of the bright spot in each channel can be obtained.

[0058] In step S204, the defect type corresponding to the detected bright spot is determined based on the detection size of the bright spot detected in the DNO channel, DW1O channel and DW2O channel of the wafer under test.

[0059] In this disclosure, taking a bright spot detected by the wafer under test according to the aforementioned scheme as an example, after obtaining the detection size of the bright spot in the three channels through step S203, the detection sizes of two channels can be randomly selected from the detection sizes of the three channels, and the ratio between the detection sizes of the two channels can be calculated. Subsequently, the defect type corresponding to the bright spot can be determined according to the set determination strategy using at least one of the detection sizes of the bright spot in the three channels, or the ratio between the detection sizes of the randomly selected two channels. For example, if at least one of the detection sizes of the bright spot in the three channels exceeds the set upper limit detection size (200nm), the defect type corresponding to the bright spot can be determined to be an attachment. For example, if the ratio of the detection size of the DW2O channel to the detection size of the DW1O channel, or the ratio of the detection size of the DNO channel to the detection size of the DW1O channel, is greater than 1.5, it indicates that the defect type corresponding to the bright spot is a defect that cannot be eliminated by cleaning, such as scratch defects, pit defects, and various concave defects caused by the crystal quality of semiconductor wafers (such as COP (Crystal Originated Particles), dislocations, etc.).

[0060] Understandably, since the first calibration curve is more suitable for the cover layer of the wafer under test than the second calibration curve, the defects in the cover layer of the wafer under test detected by the first calibration curve are more accurate than those detected by the second calibration curve, thus avoiding or reducing the occurrence of false detections or missed detections of defects.

[0061] for Figure 2 In some possible implementations of the technical solution shown, the step of constructing a first calibration curve for determining defect size based on the extinction coefficient and the refractive index for the dark field narrow tilted DNO channel, the dark field wide 1 tilted DW1O channel, and the dark field wide 2 tilted DW2O channel, respectively, includes:

[0062] The emission intensity of standard particles in the DNO channel, DW1O channel, and DW2O channel was obtained.

[0063] Based on the extinction coefficient and the refractive index, the radiation intensity of the standard particle in the DNO channel, DW1O channel and DW2O channel respectively is converted into the reference radiation intensity of the DNO channel, DW1O channel and DW2O channel under the capping layer condition.

[0064] Based on the reference emission intensity and the size of the standard particle, the first calibration curves corresponding to the DNO channel, DW1O channel and DW2O channel are obtained respectively.

[0065] Specifically, the process of obtaining the calibration curve requires the participation of standard particles. Taking SiO2 particles as an example, the emission intensity of the bright spots presented by the SiO2 particles in the DNO, DW1O, and DW2O channels is different, but all are positively correlated with the size of the SiO2 particles, even linearly. For example, the larger the size of the bright spot presented by the SiO2 particles, the greater the emission intensity of the SiO2 particles in the DNO, DW1O, and DW2O channels. However, the extinction coefficient and refractive index of the capping layer cannot usually be characterized by SiO2 particles. Therefore, the emission intensity of the SiO2 particles in the DNO, DW1O, and DW2O channels can be calculated using the extinction coefficient and refractive index of the capping layer, thereby obtaining the emission intensity of bright spots with the same size as the SiO2 particles in the DNO, DW1O, and DW2O channels under the capping layer conditions. This can be referred to as the reference emission intensity in this disclosure. Next, by combining the linear relationship between the bright spot size and the intensity of the emitted light, the detection size of the bright spot corresponding to different intensities of emitted light under the conditions of the capping layer can be obtained by using the reference intensity of emitted light and the bright spot size of the SiO2 particle. This is the first calibration curve.

[0066] for Figure 2In some possible implementations of the technical solution shown, the step of constructing a first calibration curve for determining defect size based on the extinction coefficient and the refractive index for the dark field narrow tilted DNO channel, the dark field wide 1 tilted DW1O channel, and the dark field wide 2 tilted DW2O channel, respectively, includes:

[0067] The conversion relationship between the radiation intensity of the first calibration curve and the radiation intensity of the second calibration curve is obtained based on the extinction coefficient and the refractive index.

[0068] Based on the corresponding conversion relationship, the first calibration curve is obtained using the second calibration curves of the DNO channel, DW1O channel, and DW2O channel.

[0069] Regarding the above implementation, it should be noted that since the extinction coefficient and refractive index depend on the material of the object being inspected, the difference in extinction coefficient and refractive index caused by the material difference between the capping layer and the silicon single-crystal wafer surface can be used to convert the second calibration curves provided by default with the surface inspection device 10 in the DNO, DW1O, and DW2O channels described in the aforementioned scheme into the first calibration curves for the DNO, DW1O, and DW2O channels, respectively. Since the extinction coefficient and refractive index affect the intensity of emitted light, the intensity of emitted light corresponding to the first and second calibration curves is converted for the same inspection size.

[0070] In some examples, taking two overlay layers as an example, based on the material of the overlay layers, the corresponding conversion relationship described in the above implementation includes:

[0071] For the DNO channel, the first correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula:

[0072] Y = 0.177X - 0.089;

[0073] For the DW1O channel, the second correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula:

[0074] Y = 1.2164X - 1.0208;

[0075] For the DW2O channel, the third correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula:

[0076] Y = 3.2473X - 0.5327.

[0077] Based on the two implementation methods mentioned above, the first calibration curves of the DNO channel, DW1O channel and DW2O channel can be obtained respectively, as shown in Figure 4(a), Figure 4(b) and Figure 4(c). In the first calibration curve of each DNO channel, the horizontal axis represents the detection size and the vertical axis represents the light intensity.

[0078] To illustrate the defect detection effect of the first calibration curve proposed in this disclosure, three pieces are used as follows: Figure 3 Taking the wafer under test with two capping layers (labeled Slot 1, Slot 2, and Slot 3 respectively) as an example, the defects detected using the default second calibration curve are as follows: Figure 5 As shown in Figures 4(a), 4(b), and 4(c), the defects detected using the first calibration curves are as follows: Figure 6 As shown.

[0079] By Figure 5 The detection results of Slot 1, Slot 2, and Slot 3 are respectively compared with... Figure 6 A comparison of the detection results from Slot 1, Slot 2, and Slot 3 shows that the number of defects detected using the first calibration curve is significantly greater than the number detected using the second calibration curve. In other words, the detection results using the first calibration curve more accurately reflect the defect situation on the surface of the wafer under test, and the defect detection results of the first calibration curve are more accurate compared to the second calibration curve.

[0080] Based on the same inventive concept as the aforementioned technical solution, see [link to inventive concept]. Figure 7 The document illustrates an apparatus 70 for detecting defects on the surface of a wafer. The apparatus 70 includes: an acquisition unit 701, a construction unit 702, a matching unit 703, and a determination unit 704; wherein,

[0081] The acquisition unit 701 is configured to acquire the extinction coefficient and refractive index of the capping layer of the wafer under test; wherein the wafer under test includes a semiconductor wafer having a capping layer on a single-crystal silicon substrate;

[0082] The construction unit 702 is configured to construct corresponding first calibration curves for determining defect size based on the extinction coefficient and the refractive index for a dark field narrow tilted DNO channel, a dark field wide 1 tilted DW1O channel, and a dark field wide 2 tilted DW2O channel, respectively; wherein, the first calibration curve is used to characterize the correspondence between the radiation intensity and the detection size under the cover layer condition.

[0083] The matching unit 703 is configured to match the emission intensity of the detected bright spots on the wafer under test in the DNO channel, DW1O channel and DW2O channel with the first calibration curves corresponding to the DNO channel, DW1O channel and DW2O channel respectively, to obtain the detection size of the detected bright spots on the wafer under test in the DNO channel, DW1O channel and DW2O channel respectively.

[0084] The determination unit 704 is configured to determine the defect type corresponding to the detected bright spot based on the detection size of the bright spot detected on the wafer under test in the DNO channel, DW1O channel and DW2O channel respectively.

[0085] In some examples, the construction unit 702 is configured to:

[0086] The emission intensity of standard particles in the DNO channel, DW1O channel, and DW2O channel was obtained.

[0087] Based on the extinction coefficient and the refractive index, the radiation intensity of the standard particle in the DNO channel, DW1O channel and DW2O channel respectively is converted into the reference radiation intensity of the DNO channel, DW1O channel and DW2O channel under the capping layer condition.

[0088] Based on the reference emission intensity and the size of the standard particle, the first calibration curves corresponding to the DNO channel, DW1O channel and DW2O channel are obtained respectively.

[0089] In some examples, the construction unit 702 is configured to:

[0090] The conversion relationship between the radiation intensity of the first calibration curve and the radiation intensity of the second calibration curve is obtained based on the extinction coefficient and the refractive index.

[0091] Based on the corresponding conversion relationship, the first calibration curve is obtained using the second calibration curves of the DNO channel, DW1O channel, and DW2O channel.

[0092] In some examples, the corresponding conversion relationship includes:

[0093] For the DNO channel, the first correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula:

[0094] Y = 0.177X - 0.089;

[0095] For the DW1O channel, the second correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula:

[0096] Y = 1.2164X - 1.0208;

[0097] For the DW2O channel, the third correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula:

[0098] Y = 3.2473X - 0.5327.

[0099] In some examples, the extinction coefficient represents the proportion of energy absorbed per unit length as light passes through the capping layer of the wafer under test; the refractive index represents the ratio of the speed of light in a vacuum to the speed of light in the capping layer of the wafer under test.

[0100] In some examples, the acquisition unit 701 is configured to:

[0101] The extinction coefficient is determined by measuring the light transmission intensity of the cover layer of the wafer under test using the transmission method.

[0102] The refractive index is determined by measuring the change in polarization state after ellipsometric light is reflected from the surface of the capping layer of the wafer under test using an ellipsometer.

[0103] In some examples, the determination unit 704 is configured to:

[0104] The detected bright spots are selected from the detection sizes of two channels: DNO channel, DW1O channel, and DW2O channel.

[0105] Calculate the ratio between the detection sizes corresponding to the two selected channels;

[0106] The defect type corresponding to the detected bright spot is determined according to the set judgment strategy by using the detection size of the detected bright spot in the DNO channel, DW1O channel and DW2O channel respectively, or the ratio between the detection sizes of the two selected channels.

[0107] Please refer to Figure 8 It shows the aforementioned Figure 1The diagram illustrates a schematic structural block diagram of the computing device 15. In some examples, the computing device 15 may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The computing device 15 has communication capabilities and can access wired or wireless networks. The computing device 15 may refer to one of a plurality of terminals, and those skilled in the art will understand that the number of such terminals may be more or less. In some examples, the computing device 15 may receive data based on the accessed wired or wireless network. It is understood that the computing device 15 undertakes the calculation and processing work of the technical solution of this disclosure, and this disclosure does not limit it in this respect.

[0108] like Figure 8 As shown, the computing device in this disclosure may include one or more of the following components: processor 810 and memory 820.

[0109] Optionally, the processor 810 connects various parts within the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 820, and by calling data stored in the memory 820. Optionally, the processor 810 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 810 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used for wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 810, but may be implemented using a separate chip.

[0110] The memory 820 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 820 may include a non-transitory computer-readable storage medium. The memory 820 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 820 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0111] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0112] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the method for detecting wafer surface defects as described in the various embodiments above.

[0113] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the method for detecting wafer surface defects as described in the various embodiments above.

[0114] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0115] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0116] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for detecting defects on the surface of a wafer, characterized in that, The method includes: The extinction coefficient and refractive index of the capping layer of the wafer under test are obtained; wherein, the wafer under test includes a semiconductor wafer having a capping layer on a single-crystal silicon substrate; The emission intensity of standard particles in the dark field narrow tilted DNO channel, the dark field wide 1 tilted DW1O channel, and the dark field wide 2 tilted DW2O channel was obtained respectively. Based on the extinction coefficient and the refractive index, the corresponding conversion relationship between the radiation intensity of the first calibration curve and the radiation intensity of the second calibration curve is obtained. The first calibration curve is used to characterize the correspondence between radiation intensity and detection size under the cover layer condition. The second calibration curve is the standard calibration curve provided by default. Based on the corresponding conversion relationship, the radiation intensity of the standard particle in the DNO channel, DW1O channel and DW2O channel is converted into the reference radiation intensity of the DNO channel, DW1O channel and DW2O channel under the cover layer condition. Based on the reference radiation intensity and the size of the standard particle, the first calibration curves corresponding to the DNO channel, DW1O channel and DW2O channel are obtained respectively. The emission intensity of the detected bright spots on the wafer under test in the DNO, DW1O and DW2O channels is matched with the first calibration curves corresponding to the DNO, DW1O and DW2O channels respectively to obtain the detection size of the detected bright spots on the wafer under test in the DNO, DW1O and DW2O channels respectively. The defect type corresponding to the detected bright spot is determined based on the detection size of the bright spot in the DNO channel, DW1O channel, and DW2O channel of the wafer under test.

2. The method according to claim 1, characterized in that, The corresponding conversion relationship includes: For the DNO channel, the first correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula: Y = 0.177X - 0.089; For the DW1O channel, the second correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula: Y = 1.2164X - 1.0208; For the DW2O channel, the third correspondence between the emitted light intensity X corresponding to the second calibration curve and the emitted light intensity Y corresponding to the first calibration curve for the same detection size is shown in the following formula: Y = 3.2473X - 0.5327.

3. The method according to claim 1, characterized in that, The extinction coefficient represents the proportion of energy absorbed per unit length when light passes through the capping layer of the wafer under test; the refractive index represents the ratio of the speed of light in a vacuum to the speed of light in the capping layer of the wafer under test.

4. The method according to claim 1, characterized in that, The process of obtaining the extinction coefficient and refractive index of the capping layer of the wafer under test includes: The extinction coefficient is determined by measuring the light transmission intensity of the cover layer of the wafer under test using the transmission method. The refractive index is determined by measuring the change in polarization state after ellipsometric light is reflected from the surface of the capping layer of the wafer under test using an ellipsometer.

5. The method according to claim 1, characterized in that, The step of determining the defect type corresponding to the detected bright spots based on the detection dimensions of the bright spots detected on the wafer under test in the DNO channel, DW1O channel, and DW2O channel respectively includes: The detected bright spots are selected from the detection sizes of two channels: DNO channel, DW1O channel, and DW2O channel. Calculate the ratio between the detection sizes corresponding to the two selected channels; The defect type corresponding to the detected bright spot is determined according to the set judgment strategy by using the detection size of the detected bright spot in the DNO channel, DW1O channel and DW2O channel respectively, or the ratio between the detection sizes of the two selected channels.

6. An apparatus for detecting defects on the surface of a wafer, characterized in that, The device includes: an acquisition unit, a construction unit, a matching unit, and a determination unit; wherein... The acquisition unit is configured to acquire the extinction coefficient and refractive index of the capping layer of the wafer under test; wherein the wafer under test includes a semiconductor wafer having a capping layer on a single-crystal silicon substrate; The construction unit is configured to acquire the emission intensity of standard particles in the dark field narrow tilted DNO channel, the dark field wide 1 tilted DW1O channel, and the dark field wide 2 tilted DW2O channel, respectively; based on the extinction coefficient and the refractive index, acquire the corresponding conversion relationship between the emission intensity of the first calibration curve and the emission intensity of the second calibration curve, wherein the first calibration curve is used to characterize the correspondence between emission intensity and detection size under the capping layer condition, and the second calibration curve is a default standard calibration curve; based on the corresponding conversion relationship, convert the emission intensity of the standard particles in the DNO channel, DW1O channel, and DW2O channel, respectively, into the reference emission intensity of the DNO channel, DW1O channel, and DW2O channel under the capping layer condition; and acquire the first calibration curve corresponding to the DNO channel, DW1O channel, and DW2O channel, respectively, based on the reference emission intensity and the size of the standard particles. The matching unit is configured to match the emission intensity of the detected bright spots on the wafer under test in the DNO channel, DW1O channel and DW2O channel with the first calibration curves corresponding to the DNO channel, DW1O channel and DW2O channel respectively, to obtain the detection size of the detected bright spots on the wafer under test in the DNO channel, DW1O channel and DW2O channel respectively. The determination unit is configured to determine the defect type corresponding to the detected bright spot based on the detection size of the bright spot detected on the wafer under test in the DNO channel, DW1O channel and DW2O channel respectively.

7. A computing device, characterized in that, The computing device includes a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the method for detecting wafer surface defects as described in any one of claims 1 to 5.

8. A computer storage medium, characterized in that, The storage medium stores at least one instruction, which is executed by a processor to implement the method for detecting wafer surface defects as described in any one of claims 1 to 5.

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